Integrated chip and method of forming the same

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure over a substrate and a channel structure over the gate structure. A first source / drain contact and a second source / drain contact are disposed over the channel structure and the gate structure. The first source / drain contact is laterally separated from the second source / drain contact along a first direction. A capacitor is electrically coupled to the first source / drain contact. The first source / drain contact has a first length and the second source / drain contact has a second length measured along a second direction that is substantially perpendicular to the first direction. The first length is different than the second length.

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