Fabrication process method for increasing an oxide thickness at trench bottom and an u-metal-oxide-semiconductor field-effect transistor formed by using the same

Abstract

A fabrication process method for increasing an oxide thickness at trench bottom and an u-metal-oxide-semiconductor field-effect transistor formed by using the same are provided, wherein a transistor structure involved with a lithography process is employed to define a trench region therein. A pad oxide layer is deposited along the trench and a silicate glass is subsequently formed covering the pad oxide layer on two opposite sides of the trench. As such, two silicate glass spacers are formed, retaining a spacing there in between. An annealing process is carried out such that the silicate glass reflows and fills the spacing at the trench bottom. As a result, a thick oxide layer is formed at the trench bottom. By employing the present invention, it is effective in increasing an oxide thickness at the trench bottom, increasing the corner curvature radius of the gate bottom edge, and reducing a parasitic gate-drain capacitance.

Description

[Technical Field]

[0001] This invention relates to a process method for increasing the thickness of the oxide layer at the bottom of a trench, particularly a process method that utilizes silica glass dopants, after high-temperature annealing, to flow back from the trench sidewall to the bottom of the trench, thereby filling the bottom of the trench and forming a thick oxide layer. This invention also discloses a trench-type gate power metal-oxide-semiconductor field-effect transistor formed using this process method. [Previous Technology]

[0002] It is known that the trench gate power metal-oxide-semiconductor field-effect transistor (UMOSFET) is the transistor structure with the smallest cell pitch among high-power devices. Therefore, it is also the device with the lowest on-resistance per unit area and the lowest specific on-resistance (R on, sp). Please refer to Figure 1, which is a schematic diagram of the basic structure of a prior art N-type trench gate power MOSFET. As shown in the figure, when a gate voltage is applied to the gate 10, sufficient to generate an inversion layer at the interface between the P-type substrate region (shown as P-body) 12 and the trench oxide layer 13, that is, when the gate voltage is greater than the threshold voltage for operation of this trench gate power MOSFET, electrons will flow from the upper source region (shown as N+) 14 into the inversion layer channel, then into the drift region (shown as N-) 15, and finally reach the drain region (shown as N+) 16 on the back side. Generally speaking, in order to form a complete channel, the depth of this trench gate 10 must exceed the P-type substrate region 12 and extend into the drift region 15 (N-).

[0003] Based on the current technological development trend, silicon carbide (SiC) materials have a wider bandgap and a higher breakdown voltage than silicon (Si) substrates. In comparison, the breakdown strength of trench gate power metal-oxide-semiconductor (MOSFET) transistors made of silicon carbide can reach 10 times that of silicon substrates. Therefore, high withstand voltage can be achieved with low impedance and thin drift layer. However, it is worth noting that in the traditional trench gate power metal-oxide-semiconductor structure, when the voltage at the drain of the transistor is increased, the gate oxide layer deep in the N-drift region 15 has to withstand the drain voltage. The two corners at the bottom of the trench have a small radius of curvature, which generates a stronger electric field. In addition, the electric field concentration effect occurs, which reduces the breakdown voltage. In addition, for semiconductor devices made of silicon carbide materials, the commonly used front side of the wafer is the (0001) crystal plane, and its trench sidewalls are the (11-20) or (1-100) crystal planes. Generally speaking, the electron mobility along the (11-20) or (1-100) crystal planes is much higher than that along the (0001) crystal plane, which allows the transistor to have a lower on-resistance. However, the thermal oxidation rate of the (0001) crystal plane is much lower than that of the (11-20) or (1-100) crystal planes. If the gate oxide layer of the transistor is made by thermal oxidation, the thickness of the bottom of the trench will be thinner than that of the sidewalls. If the electric field enhancement effect at the corners on both sides of the bottom of the trench is added, the transistor will fail due to the collapse of the gate oxide layer. It is known that, in order to improve these problems, existing technologies have proposed processes that utilize controlled chemical vapor deposition (CVD) process parameters to make the sidewall coverage lower than the bottom coverage, allowing the bottom oxide layer to be slightly thicker than the sidewall. However, even with this process, the problem of electric field enhancement at the corners on both sides of the bottom of the trench cannot be avoided, so the voltage withstand capability of the transistor is still limited by the gate oxide layer collapse mechanism. Therefore, other protection strategies are still needed.

[0004] In view of this, there is a prior art, as shown in Figure 2, which utilizes an additional P-type region 31 near the bottom of the N-drift region 30 close to the gate 32, and utilizes the depletion effect of the pn junction at the bottom of the adjacent trench to shield the bottom of the trench, thereby reducing the electric field of the gate oxide layer. However, when the transistor is turned on, the depletion area formed by these pn junctions also blocks the current from passing through, generating a junction gate field-effect transistor (JFET) effect, which in turn increases the on-resistance of the device, and still has its unavoidable shortcomings. In addition, existing literature discloses that after the trench is etched, the trench can be filled with silicon dioxide first, and then the silicon dioxide outside the trench can be removed by chemical mechanical planarization (CMP). Then, the silicon dioxide in the trench can be etched by dry etching, leaving only silicon dioxide of the required thickness. However, this method must be combined with the high-cost chemical mechanical planarization process, which has the problem of excessively high process cost. In addition, the thickness of the oxide layer at the bottom of the trench is difficult to control precisely, so it cannot be applied to actual mass production.

[0005] Compared to Figure 2, Figure 3 discloses another technique for protecting the gate oxide layer at the bottom of the protective trench. As shown in Figure 3, the transistor structure has a bottom metal layer 151, followed by a silicon carbide substrate 153 and a silicon carbide drift region 155 stacked on top of it. The method disclosed in Figure 3 involves fabricating protective trenches with the same or greater depth as the channel trench on both sides. Then, the fabricated protective trenches are covered by heavily doped P-type regions (P+ shown in the figure) 157. The electric field shielding effect generated by adjacent P+ regions reduces the electric field strength at the bottom of the trench. Disadvantages of this approach include: the junction field-effect transistor (JFET) effect is known to occur between adjacent P+ regions, increasing the on-resistance. In addition, fabricating deeper protective trenches also increases the difficulty of the fabrication process and affects the reduction of cell pitch.

[0006] On the other hand, please refer to Figure 4, which discloses another technique for protecting the gate oxide layer at the bottom of the trench. From the structure shown in Figure 4, it can be seen that this method uses a P-type heavily doped region (P+ shown in the figure) 167 that is deeper than the trench depth to cover the right half of the trench. The shielding effect achieved by the adjacent P-type heavily doped regions reduces the electric field strength at the bottom of the left half of the trench. As mentioned earlier, this method also increases the on-resistance due to the JFET effect between adjacent P+ regions. Furthermore, only half of each trench can conduct, making the on-resistance of the transistor even greater, which is also a drawback of this method.

[0007] In addition, existing literature has proposed using ion implantation to amorphize the silicon carbide at the bottom of the trench, increasing its oxidation rate, in order to grow a thicker oxide layer through thermal oxidation. However, it is worth noting that the oxidation temperature in this method is lower than the temperature required for silicon carbide recrystallization, which may leave defects in the device structure, thus affecting device performance. Therefore, it has not yet reached the level of practical application.

[0008] Furthermore, it is known that the bottom of the trench gate of a trench-type gate-to-power MOSFET overlaps with the drain, forming a parasitic gate-to-drain capacitance (CGD), also known as feedback capacitance or reverse switching capacitance (Crss). This gate-to-drain capacitance is a key factor affecting the switching speed and power consumption of the transistor. Among the various gate oxide layer protection technologies mentioned above, even adding a shielding layer or increasing the thickness of the oxide layer at the bottom of the trench can reduce this gate-to-drain capacitance. However, a lower gate-to-drain capacitance remains a goal that current trench-type gate-to-power MOSFETs still need to achieve.

[0009] Therefore, considering the numerous problems listed above, it is essential to adopt a multi-faceted approach. Thus, the inventor of this invention, recognizing the potential for improvement in the aforementioned deficiencies, and drawing upon years of experience in this field, has carefully observed and researched the subject, applying theoretical principles to propose a novel design that effectively addresses these deficiencies. This invention discloses a novel manufacturing process that effectively increases the thickness of the oxide layer at the bottom of the gate of a trench-type gate power metal-oxide-semiconductor field-effect transistor. Simultaneously, it effectively reduces the electric field strength of the oxide layer at the bottom of the trench, increases the radius of curvature at the bottom edge of the gate, and reduces the parasitic capacitance between the gate and drain, thereby avoiding many long-standing deficiencies of previous technologies. The applicant will provide a detailed description of the specific architecture and implementation methods below. [Summary of the Invention]

[0010] In order to effectively address the long-standing deficiencies of many prior art, one objective of the present invention is to provide a gate fabrication method suitable for trench gate power metal-oxide-semiconductor field-effect transistors. Through the gate fabrication method disclosed in the present invention, the thickness of the oxide layer at the bottom of the trench can be effectively increased and the curvature of the trench corner can be reduced by utilizing the thermal reflow characteristics of the provided silicon glass dopant. Under the same transistor operating voltage, the electric field strength in the oxide layer can be effectively reduced, thereby effectively improving the voltage withstand capability of the device.

[0011] Another object of the present invention is to provide a process method suitable for increasing the thickness of the oxide layer at the bottom of a trench-type gate power metal-oxide-semiconductor (MOSFET), and a trench-type gate power MOSFET structure formed by using this process method. The present invention utilizes two opposing silicon glass doped sidewall layers with a gap between them. After a heat treatment process, the silicon glass doped sidewall layers flow towards the gap and fill the bottom of the trench, thereby forming a thick oxide layer at the bottom of the trench. By using the process method disclosed in this invention, not only can the thickness of the oxide layer at the bottom of the trench be effectively increased, achieving the purpose of increasing the radius of curvature of the gate bottom edge, but also the effect of reducing the gate-drain capacitance in the transistor structure can be achieved.

[0012] To achieve the above-mentioned objective, the present invention first provides a process method for increasing the thickness of the oxide layer at the bottom of the trench, comprising the following steps:

[0013] (a): A semiconductor substrate is provided, and a drift region is formed on the semiconductor substrate.

[0014] (b): Subsequently, a first heavily doped region is formed in the drift region. According to an embodiment of the present invention, in the step of forming the first heavily doped region, for example, a source ion implantation process can be used to form the first heavily doped region in the drift region.

[0015] (c): Subsequently, a second doped region and a third doped region are formed on opposite sides of the first doped region, and a substrate region is formed between the first doped region, the second doped region, the third doped region and the drift region.

[0016] (d): Next, a hard mask layer is deposited on the first heavily doped region, the second heavily doped region, and the third heavily doped region, and a trench is formed by a photolithography process. According to an embodiment of the present invention, the trench extends through the first heavily doped region and the substrate region, and the bottom of the trench terminates in the drift region.

[0017] In one embodiment, the material of the hard masking layer used in the present invention may be, for example, silicon dioxide.

[0018] (e): Subsequently, the present invention removes the hard masking layer in the previous step and deposits a cushion oxide layer along the trench, such that the cushion oxide layer covers at least two opposite sidewalls and a bottom of the trench.

[0019] According to embodiments of the present invention, in the step of depositing the pad oxide layer, the present invention may, for example, employ a process method such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) to deposit the desired pad oxide layer. For example, in one embodiment of the present invention, the thickness of the formed pad oxide layer covering the two opposite sidewalls of the trench may be, for example, between 30 nanometers and 200 nanometers. Conversely, the thickness of the pad oxide layer covering the bottom of the trench may be, for example, between approximately 30 nanometers and 300 nanometers.

[0020] (f): Subsequently, after the deposition of the underlay oxide layer is completed, the present invention may deposit silicon glass dopants on the two opposite sidewalls of the trench covered with the underlay oxide layer, such that the silicon glass dopants can form opposite sidewall layers on the two opposite sidewalls of the trench, and there is a gap between the two sidewall layers.

[0021] Specifically, one of the sidewall layers (silicone glass dopants) is disposed opposite to one of the opposite sidewalls of the trench, such that the spacing is provided between the two sidewall layers (silicone glass dopants).

[0022] According to an embodiment of the present invention, in the step of depositing the silica dopant, the thickness of the deposited silica dopant may, for example, be between 100 nanometers and 200 nanometers. Furthermore, according to an embodiment of the present invention, in the step of forming the two opposing sidewall layers from the deposited silica dopant, for example, the silica dopant may be etched using an anisotropic etching process to form the two sidewall layers with the gap therein.

[0023] According to one embodiment of the present invention, the thickness of one of the sidewall layers may be, for example, between 50 nanometers and 200 nanometers. Furthermore, the height of one of the sidewall layers may be, for example, between 0.5 micrometers and 2 micrometers.

[0024] (g): After forming the silica glass dopant sidewall layer, the present invention performs a heat treatment process, the purpose of which is to enable the silica glass dopant sidewall layer to flow into the gaps therein through the heat treatment process and fill the bottom of the trench, thereby forming a thick oxide layer (TBOX) at the bottom of the trench.

[0025] In accordance with embodiments of the present invention, in order to enable the silicon glass dopant sidewall layer to have flowable properties, the silicon glass dopant material used in the present invention may include (but is not limited to): borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), and arsenic silicate glass (AsSG).

[0026] Preferably, according to a preferred embodiment of the present invention, the concentration of boron, phosphorus, or arsenic dopants in the silicon glass dopant may be, for example, between 1% and 5%.

[0027] Furthermore, the heat treatment process performed in step (g) above is a high-temperature annealing process. The process temperature of the high-temperature annealing process can be, for example, but is not limited to, between 900°C and 1300°C, and the process time can be, for example, but is not limited to, between 5 minutes and 120 minutes. Generally speaking, those skilled in the art and possessing ordinary knowledge can make appropriate modifications or variations to the technical solutions disclosed in this invention without departing from the spirit of the invention, but such modifications or variations should still fall within the scope of this invention. This invention is not limited to the various parameters and conditions disclosed above.

[0028] Therefore, by employing the process method disclosed in this invention, the thick oxide layer formed by this invention has a side thickness on each of its two sides, and a central thickness in its center. This results in the side thickness of the thick oxide layer being greater than its central thickness, giving the surface of the thick oxide layer an upward-curved shape. In view of this technical feature, this invention can effectively increase the oxide layer thickness at the bottom of the trench, and reduce the electric field strength of the oxide layer at the bottom of the trench, increase the radius of curvature of the gate bottom edge, thereby improving the breakdown voltage of the device and enhancing the device's withstand voltage capability.

[0029] In addition, the present invention can also simultaneously achieve the objective of reducing parasitic gate-drain capacitance (CGD) in transistor structures. Overall, the process method disclosed in this invention for effectively increasing the oxide layer thickness at the bottom of trenches not only has the advantages of simple process and easy control, but also has unique innovation and practical value compared to prior art.

[0030] On the other hand, the present invention also provides a trench gate power metal-oxide-semiconductor formed by a process method of increasing the thickness of the oxide layer at the bottom of the trench. The trench gate power metal-oxide-semiconductor mainly includes the semiconductor substrate, a drift region formed on the semiconductor substrate, a substrate region formed on the drift region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a pad oxide layer, and the thick oxide layer.

[0031] The second doped region and the third doped region are each formed on opposite sides of the first doped region. The first doped region, the second doped region and the third doped region are disposed on the substrate region. A trench is formed by using a photolithography process to separate the first doped region and the substrate region.

[0032] The cushion oxide layer covers at least two opposite sidewalls and the bottom of the trench. The thick oxide layer is formed on the cushion oxide layer and fills and forms the bottom of the trench. The material of the thick oxide layer includes silica glass dopant. The thick oxide layer has a side thickness on each side and a central thickness in its center. The side thickness of the thick oxide layer is greater than its central thickness, so that the surface of the thick oxide layer has an upward curved shape.

[0033] Preferably, according to embodiments of the present invention, the semiconductor substrate used in the present invention may be, for example, a silicon carbide (SiC) substrate. However, the process method disclosed in the present invention and the application of the trench gate power metal-oxide-semiconductor field-effect transistor formed therefrom are not limited to the silicon carbide material mentioned above. Based on the same principle, the technical solution disclosed in the present invention can also be widely applied to other semiconductor materials. For example, the semiconductor substrate material may also be silicon (Si), gallium oxide (Ga₂O₃), aluminum nitride (AlN), and diamond, etc. In addition, the types of transistors that can be applied in the present invention are not limited to N-channel transistors, but may also be transistor elements used for P-channel transistors. In other words, according to the process method disclosed in this invention and the trench gate power metal-oxide-semiconductor field-effect transistor formed therein, the semiconductor substrate, the drift region, and the first heavily doped region have a first semiconductor conductivity type, and the second heavily doped region, the third heavily doped region, and the substrate region have a second semiconductor conductivity type, wherein the first semiconductor conductivity type and the second semiconductor conductivity type are different conductivity types.

[0034] Furthermore, the types of transistor elements are not limited to general trench gate power metal-oxide-semiconductor field-effect transistors (UMOSFETs). In other embodiments of the present invention, for example, they can also be applied to other power elements having the trench gate power metal-oxide-semiconductor field-effect transistor structure, such as insulated gate bipolar transistors (IGBTs), etc. It is evident that the process method for increasing the thickness of the oxide layer at the bottom of the trench disclosed in the present invention, and the resulting trench gate power metal-oxide-semiconductor field-effect transistor, possess extremely high industrial applicability and technical compatibility.

[0035] In summary, it can be confirmed that the present invention mainly discloses a gate fabrication method for a trench-type gate power metal-oxide-semiconductor (MOSFET) and a process method for increasing the thickness of the oxide layer at the bottom of the trench. According to the process technology disclosed in the present invention, a pad oxide layer is deposited on the sidewalls and bottom of the trench. Then, silicon glass doped sidewall layers are formed on the two opposite sidewalls of the trench covered with the pad oxide layer, leaving a gap between them. Subsequently, a heat treatment process (e.g., high-temperature annealing) is used to cause the silicon glass doped sidewall layers to flow and flow into the gap therein, thereby filling the bottom of the trench to form a thick oxide layer at the bottom of the trench.

[0036] Subsequently, after the thick oxide layer is successfully formed in this invention, those skilled in the art can selectively remove the silicon dioxide or silicon glass dopants on the trench sidewalls using a wet etching process. Then, following the conventional process of existing trench gate power metal-oxide-semiconductor (UMOSFET), the following steps can be performed: fabricating the gate oxide layer, depositing and etching back the poly-silicon gate, depositing the inter-layer dielectric (ILD), forming the contact window through a photolithography process, depositing metal, etching and forming a metal pattern, depositing a passivation layer, thinning the back of the crystal by grinding, and performing a metallization process, thereby completing the fabrication of the trench gate power metal-oxide-semiconductor. Given that the subsequent process steps are technical processes familiar to those with ordinary technical background and expertise in the field, the applicant of this invention will not elaborate on this existing process in this application.

[0037] In one feasible embodiment of the present invention, the depth of the trench used may be, for example, between 1 micrometer and 2 micrometers, and the width of the trench used may be, for example, between 0.5 micrometers and 2 micrometers.

[0038] Therefore, as can be seen from the above, by adopting the process technology disclosed in this invention, this invention can not only effectively reduce the overlap area of ​​conventional gate electrode and drain electrode, but also achieve the inventive effect of reducing gate-drain capacitance (CGD).

[0039] On the other hand, the process technology disclosed in this invention also achieves the purpose of increasing the thickness of the oxide layer at the bottom of the gate and reducing the curvature at the corner of the trench, thereby improving the breakdown voltage of the device and enhancing the withstand voltage of the device.

[0040] It is worth noting that the embodiments disclosed in this invention are illustrated using silicon carbide as an example, and their purpose is to enable those skilled in the art to fully understand the technical concept of this invention, rather than to limit the application of this invention. In other words, the process method disclosed in this invention can be applied not only to silicon carbide substrates, but also to various semiconductor materials.

[0041] The following detailed description, with reference to specific embodiments and accompanying drawings, will make it easier to understand the purpose, technical content, features and effects of the present invention.

Implementation Method

[0042] The foregoing description of the present invention, along with the following embodiments, are intended to demonstrate and explain the spirit and principles of the invention, and to provide a further explanation of the scope of the patent application. Please refer in detail to the preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Furthermore, where possible, the same reference numerals will be used in the drawings and description to refer to the same or similar elements. It should be understood that, for clarity and convenience, the shapes and thicknesses may be enlarged in the drawings, and elements not specifically shown or described may take various forms known to those skilled in the art. Once disclosed in this disclosure, such alternatives and modifications will be apparent to those skilled in the art.

[0043] To illustrate the technical content and features of the present invention and to enable those skilled in the art to understand, make, and use the present invention, the following application provides examples through numerous embodiments. However, it should be noted that these embodiments are not intended to limit the scope of the invention. Therefore, all equivalent modifications or variations made in accordance with the spirit of the present invention should be included within the scope of protection of the present invention.

[0044] Unless otherwise stated, certain conditional phrases or words, such as “may” or “possibly,” are generally used to express that embodiments of the invention “have,” but may also be interpreted as unnecessary features, elements, or steps. In other embodiments, these features, elements, or steps may not be required.

[0045] In the embodiments described in this application, the reference to "one embodiment" or "in one embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, "one embodiment" or "in one embodiment" appearing in various places in this application's specification do not necessarily refer to the same embodiment.

[0046] In the embodiments and claims of this application, specific terms are used to refer to specific elements. Those skilled in the art should understand that the same element can be called by different names. This application does not distinguish between elements with different names but the same function. In this application specification and claims, "comprising" is used in an open-ended manner and should therefore be interpreted as "including but not limited to". "Coupled with" is intended to cover any indirect or direct connection. In other words, if this application discloses a first device coupled to a second device, it means that the first device can be connected to the second device directly or indirectly through other intermediate devices or connection methods via electrical connection, wireless communication, optical communication, or other signal connection, with or without signal connection.

[0047] The present invention is described in detail through the following embodiments, which are merely illustrative examples. Those skilled in the art can readily make appropriate modifications and variations to the apparatus and methods while retaining the teachings of the present invention. Therefore, the following disclosure of the present invention should be interpreted as being limited only by the scope of the appended claims. Throughout the patent application and claims, except where explicitly described, the meaning of "a" and "the" includes "one or at least one" of an element or component. Furthermore, throughout the patent application and claims, the singular includes descriptions of multiple elements or components, except where the context clearly excludes multiples. Throughout the specification and claims, unless the meaning of certain words is explicitly defined, the meaning of the word "wherein" includes "among" or "on top of". Generally, the meaning of each term used in these claims and specification refers to its ordinary meaning known to those skilled in the art, unless otherwise noted. Some terms used to describe the invention and to guide those skilled in the art in understanding the invention may be discussed. Each illustrative example in this specification should not be used to limit the scope of the invention.

[0048] The terms “basically,” “approximately,” “about,” and “probably” can refer to a value within 20% of a given value or range, preferably within 10%. In addition, quantities or figures provided in this application can be approximate values, and unless otherwise specified, can be described using the terms mentioned above. When a quantity, density, or other parameter includes a specified range, preferred range, or listed ideal value, its value can be considered as any number within that given range.

[0049] Please refer to Figure 5. This invention discloses a process method for increasing the thickness of the oxide layer at the bottom of a trench, including steps S302, S304, S306, S308, S310, S312, and S314. By adopting the process method disclosed in this invention, it can be effectively used for trench gate power metal-oxide-semiconductor (MOSFETs), increasing the oxide layer thickness at the bottom of the trench gate of the trench MOSFET, and simultaneously reducing the curvature of its trench corner. For further details regarding the process method disclosed in this invention, please refer to Figures 6 to 13, which are schematic cross-sectional views of the structure of a trench gate power MOSFET using the process method disclosed in this invention.

[0050] First, referring to step S302 in Figure 5, as shown in Figure 6, the present invention first provides a semiconductor substrate 40, and forms a drift region 42 on the semiconductor substrate 40. According to a preferred embodiment of the present invention, in this step, the present invention uses N-type silicon carbide as the material of the semiconductor substrate 40, and in Figure 6, it is represented as an N-type heavily doped substrate (shown as "N+ sub" in the figure). Then, an N-type silicon carbide epitaxial layer with a concentration of 1x10 16 cm⁻³ and a thickness of 5.5 μm can be grown epitaxially on the front side of the N-type heavily doped substrate (N+ sub) as the N-drift region (shown as "N-drift") 42 shown in the figure, forming the structure disclosed in Figure 6 of the present invention.

[0051] Following this, referring to step S304 in Figure 5 and as shown in Figure 7, the present invention then forms a first heavily doped region 44 in the drift region 42. Specifically, after completing the previous step, the present invention first undergoes RCA cleaning, then deposits silicon dioxide as a barrier layer, defines the N+ source window using a photolithography process, performs source ion implantation, and removes the barrier layer, thereby forming the first heavily doped region 44 as shown in Figure 7. In other words, according to the embodiment of the present invention, the step of forming the first heavily doped region 44 in the drift region 42 includes forming the first heavily doped region 44 by employing a source ion implantation process. Since this embodiment uses N-type silicon carbide as an example, the first heavily doped region 44 is represented as an N-type heavily doped region (shown as "N+" in the figures) in the relevant figures.

[0052] Following this, referring to step S306 in Figure 5 and as shown in Figure 8, the present invention continues to repeat the RCA cleaning steps and begins to define and implant P+ regions, thereby forming a second heavily doped region (shown as "P+" in the figure) 46 and a third heavily doped region (shown as "P+" in the figure) 48 on opposite sides of the first heavily doped region (N+) 44. Then, silicon dioxide is used again as a barrier layer, and a P-type substrate region window is defined by a photolithography process for substrate ion implantation. Afterwards, the barrier layer is removed, so that a substrate region (shown as "P-body" in the figure) 47 is formed between the first heavily doped region 44, the second heavily doped region 46, the third heavily doped region 48, and the drift region 42, thus forming the structure disclosed in Figure 8 of the present invention.

[0053] Subsequently, as described in step S308 of Figure 5, the present invention then deposits a hard mask layer on the aforementioned first heavily doped region (N+) 44, second heavily doped region (P+) 46, and third heavily doped region (P+) 48, and forms a trench by a photolithography process. Specifically, please refer to Figure 9 of the present invention. The present invention first deposits a hard mask layer 50, which is represented by a diagonal line area in Figure 9. The material of the hard mask layer 50 can be, for example, silicon dioxide (SiO2), to serve as an etch barrier layer for the gate region of the transistor trench. Furthermore, the hard mask layer 50 is deposited on the first heavily doped region (N-type heavily doped region) 44, the second heavily doped region (P-type heavily doped region) 46, and the third heavily doped region (P-type heavily doped region) 48. Then, as shown in Figure 10 of the present invention, a trench region in the transistor is defined by using a lithography process to form a trench 52 as shown in Figure 10.

[0054] In an embodiment of the present invention, the depth of the trench 52 may be controlled, for example, between 1 micrometer and 2 micrometers, and the width of the trench 52 may be between 0.5 micrometers and 2 micrometers. The depth of the trench 52 extends through the first heavily doped region (N-type heavily doped region) 44 and the substrate region (P-body) 47, and terminates at its bottom in the drift region (N-drift) 42.

[0055] Subsequently, as described in step S310 of Figure 5, the present invention then removes the aforementioned hard masking layer 50, and then deposits a cushion oxide layer along the trench 52, such that the cushion oxide layer at least covers two opposite sidewalls and a bottom of the trench 52, as disclosed in Figure 11 of the present invention, the coverage area of ​​the cushion oxide layer 90 is at least covering the two opposite sidewalls and the bottom of the trench 52. In practice, the step of depositing the cushion oxide layer 90 may include depositing the cushion oxide layer 90 by using a low-pressure chemical vapor deposition (LPCVD) or a plasma-enhanced chemical vapor deposition (PECVD). For example, according to one embodiment of the present invention, when the pad oxide layer 90 is deposited by the aforementioned chemical vapor deposition (CVD) method, if low-pressure chemical vapor deposition (LPCVD) is used, the bottom thickness of the pad oxide layer 90 will be close to the sidewall thickness. However, the present invention is not limited to this process method. For example, the thickness of the pad oxide layer 90 covering the bottom of the trench 52 may be between 30 nanometers and 300 nanometers, preferably, the thickness of the pad oxide layer 90 covering the bottom of the trench 52 may be, for example, 100 nanometers, and the thickness of the pad oxide layer 90 covering the two opposite sidewalls of the trench 52 may be, for example, between 30 nanometers and 200 nanometers.

[0056] Therefore, after the deposition of the pad oxide layer 90 is completed, the present invention can continue as described in step S312 of Figure 5: depositing a silicon glass dopant, wherein the silicon glass dopant covers the pad oxide layer 90 on the two opposite sidewalls of the trench 52, thereby forming two opposite sidewall layers 100 (see Figure 12 of the present invention), and as shown in Figure 12 of the present invention, there is a gap S1 between the two sidewall layers 100 formed. In detail, please refer to Figure 12 of the present invention. Specifically, the two sidewall layers 100 formed by silica glass dopants are each disposed on two opposite sidewalls of the trench 52 covering the pad oxide layer 90, such that one of the sidewall layers 100 is disposed corresponding to one of the opposite sidewalls of the trench 52. At the same time, the two sidewall layers 100 are disposed together on the pad oxide layer 90 at the bottom of the trench 52. It is worth noting that, according to an embodiment of the present invention, the gap S1 is left between the two opposite sidewall layers 100.

[0057] Specifically, in forming the sidewall layer 100 in step S312, the present invention can first deposit a silica dopant using a low-pressure chemical vapor deposition (LPCVD) process, and then etch the silica dopant using an anisotropic etching process to form two opposing (silica dopant) sidewall layers 100 having the gap S1 therein. In practice, the above-mentioned anisotropic etching process is also optional and can be selectively adopted by those skilled in the art according to the actual situation. Generally speaking, according to embodiments of the present invention, in the step of depositing the silica dopant, the thickness of the silica dopant can be, for example, between 100 nanometers and 200 nanometers. Therefore, when the silica glass dopant is etched by anisotropic etching to form the sidewall layer 100, the present invention can form a sidewall layer 100 with a thickness of about 50 nanometers to 200 nanometers and a height of about 0.5 micrometers to 2 micrometers.

[0058] In a feasible embodiment of the present invention, the material of the silica glass dopant used in the present invention may include, but is not limited to: borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), and arsenic silica glass (AsSG). Furthermore, the silica glass dopant may have a boron, phosphorus, or arsenic dopant concentration between 1% and 5%, so that the sidewall layer 100 formed by the silica glass dopant has reflowable characteristics in subsequent steps.

[0059] Subsequently, based on this structure, finally, as described in step S314 of Figure 5, the present invention can then perform a heat treatment process to allow the silica glass dopant to flow into the gap S1 and fill the bottom of the trench 52, thereby forming a thick oxide layer (Trench Bottom Oxide, TBOX) 110 at the bottom of the trench 52, as shown in Figure 13 of the present invention.

[0060] In an embodiment of the present invention, the heat treatment process used in the present invention may be, for example, a high-temperature annealing process, and the process temperature of the high-temperature annealing process may be controlled, for example, between 900°C and 1300°C, and the process time may be between 5 minutes and 120 minutes. It is understood that when this high-temperature annealing process is performed, since the sidewall layer 100 formed by the silica glass dopant flows from the aforementioned trench sidewall to the bottom of the trench, it is expected that the thickness of the bottom edge of the formed thick oxide layer 110 will be thicker than that in the center, forming a smiling shape as shown in Figure 13. Specifically, by using the process method disclosed in the present invention, the thick oxide layer 110 formed in the present invention has a side edge thickness on both sides, and the thick oxide layer 110 has a central thickness in its center. The side edge thickness is greater than the central thickness, so that the surface of the thick oxide layer 110 will form and have an upward curved shape, as shown in Figure 13.

[0061] Generally, the thickness of the generated thick oxide layer 110 is subject to the conditions of the high-temperature annealing process, such as process temperature and process time, and thus has a certain degree of process flexibility. It is worth noting that this invention is not limited to the thickness, dimensions, or process parameters disclosed in the embodiments herein, including process temperature and process time. Those skilled in the art can modify the embodiments without departing from the spirit of this invention; however, such modifications should still fall within the scope of this invention. For example, according to one feasible embodiment of the present invention, when the trench width is 1 micrometer and 50 nanometers of silicon dioxide are formed on the trench sidewall by LPCVD, if the borosilicate glass sidewall layer has a gap height of 1 micrometer and a thickness of 100 nanometers, then the thickness of the borosilicate glass flowing to the bottom of the trench will be 222 nanometers. Adding this to the original 100 nanometers of LPCVD silicon dioxide, the oxide layer at the bottom of the trench can then be 322 nanometers. According to other embodiments of the present invention, if different thicknesses are required, they can be easily adjusted and achieved by varying the sidewall gap thickness and height of the borosilicate glass.

[0062] In view of this, it is certain that the present application proposes a process method that can effectively increase the thickness of the oxide layer at the bottom of the trench. It utilizes silicon glass dopants to form a sidewall layer, and then, through a high-temperature annealing process, the silicon glass dopant sidewall layer flows towards the central gap, thereby filling the bottom of the trench to form a thick oxide layer at the bottom of the trench. This effectively increases the thickness of the oxide layer at the bottom of the gate, thereby achieving the purpose of reducing the curvature of the trench corner. When applied to any type of power device with a trench gate power metal-oxide-semiconductor field-effect transistor structure, the withstand voltage capability of the power device can be further improved and optimized. It is worth noting that when applying the process technology claimed in this invention and the process method for increasing the thickness of the oxide layer at the bottom of the trench, the types of transistor elements that can be applied are not limited to general trench gate power metal-oxide-semiconductor field-effect transistors (UMOSFETs). Optionally, in other embodiments of this invention, other power elements with the same trench gate power metal-oxide-semiconductor field-effect transistor structure, such as insulated gate bipolar transistors (IGBTs), can also be widely used. Therefore, this invention clearly possesses superior industrial compatibility and wider applicability compared to the prior art.

[0063] In addition, according to the technical solution provided by the applicant, the types of transistors applicable to this invention are not limited to the N-channel mentioned in the above embodiments, but can also be transistor elements used in P-channels. Generally speaking, the semiconductor substrate, the drift region, and the first heavily doped region disclosed in this invention have a first semiconductor conductivity type, and the second heavily doped region, the third heavily doped region, and the substrate region have a second semiconductor conductivity type. The first semiconductor conductivity type and the second semiconductor conductivity type are different conductivity types. That is, according to one embodiment of this invention, when the first semiconductor conductivity type is an N-type semiconductor, the second semiconductor conductivity type is a P-type semiconductor; in another embodiment of this invention, when the first semiconductor conductivity type is a P-type semiconductor, the second semiconductor conductivity type is an N-type semiconductor. This invention is not limited to the semiconductor conductivity type of the transistor elements used, nor is it limited to the several process layouts (N-channel or P-channel) disclosed above. In other words, those skilled in the art can make equivalent modifications and changes based on their actual product specifications, and on the inventive intent and spirit of this invention, but such modified embodiments should still fall within the scope of this invention.

[0064] In view of the above, it is evident that the present invention not only discloses a process method that can effectively increase the thickness of the oxide layer at the bottom of the trench, but also discloses a trench gate power metal-oxide-semiconductor (MOSFET) formed by using this process method. As shown in Figure 13 of the present invention, the trench gate power MOSFET formed using the process method disclosed in the present invention includes at least: the semiconductor substrate (N+ sub) 40, the drift region (N- drift) 42, the substrate region (P-body) 47, the first heavily doped region (N+) 44, the second heavily doped region (P+) 46, the third heavily doped region (P+) 48, the pad oxide layer 90, and the thick oxide layer 110. The pad oxide layer 90 covers at least two opposite sidewalls and the bottom of the trench. A thick oxide layer 110 is formed on the pad oxide layer 90, and the thick oxide layer 110 fills and forms at the bottom of the trench. The thick oxide layer 110 includes silica glass dopants, and the thick oxide layer 110 has a side thickness on each side and a central thickness in its center. The side thickness is greater than the central thickness, so that the surface of the thick oxide layer 110 has and presents an upward curved shape.

[0065] As for the trench gate power metal-oxide-semiconductor (MOSFET) fabricated according to the present invention, those skilled in the art can continue to perform subsequent back-end processes based on the gate structure of the present invention, including: depositing a dielectric layer on the gate metal layer (performing dielectric layer deposition), defining at least one contact metal window region, contact window etching, metal deposition, and metal etching. Since the technology of these back-end processes is generally the same as that of the existing trench gate power MOSFET process, the present invention will not elaborate on it here. The reason for this invention is that the purpose of this invention is to form a thicker gate oxide layer at the bottom of the trench in a trench-type gate power MOSFET. Simultaneously, by utilizing the technical characteristic that the trench is not completely filled with polycrystalline silicon, the parasitic gate-drain capacitance (CGD) can be effectively reduced, thus achieving the invention's objective of reducing parasitic gate-drain capacitance (CGD). Therefore, the process method disclosed in this invention not only increases the oxide layer thickness at the bottom of the gate, further eliminating the common effect of electric field concentration at the trench corner and its various derivative problems, but also enables the parasitic gate-drain capacitance (CGD) of the trench-type gate power MOSFET to be significantly reduced compared to a completely filled gate structure, according to a certain area ratio.

[0066] In summary, it is evident that by adopting the technical solution and technical features disclosed by the applicant, the present invention discloses a structure and process method that can effectively increase the thickness of the oxide layer at the bottom of the trench, and simultaneously achieves the triple effects of increasing the thickness of the oxide layer at the bottom of the trench, reducing the curvature of the trench corner, and reducing the parasitic gate-drain capacitance (CGD).

[0067] Therefore, in view of the above, compared with the prior art, it is certain that through the embodiments and process methods disclosed in this invention, the electric field strength in the oxide layer can be effectively reduced under the same voltage, the device withstand voltage can be enhanced, and the gate-drain capacitance of the transistor can be further reduced, which is highly innovative and practical. In addition, this invention can also effectively solve the electric field enhancement effect at the corners on both sides of the bottom of the trench, thereby avoiding the shortcomings still existing in the prior art. Furthermore, since this invention can be effectively applied to silicon carbide substrates, and can also be widely applied to various semiconductor materials, including silicon, silicon carbide, gallium oxide, aluminum nitride, and diamond; it is evident that the technical solution claimed by the applicant in this case has excellent industrial applicability and competitiveness. The technical features, methods and effects disclosed in this invention are significantly different from the existing solutions, and cannot be easily completed by those skilled in the art, and should meet the requirements for patent.

[0068] The above-described embodiments are only for illustrating the technical ideas and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered within the patent scope of the present invention. [Simplified Explanation of the Diagram]

[0069] Figure 1 is a schematic diagram of the basic structure of a prior art N-type trench gate power metal-oxide-semiconductor (MOSFET). Figure 2 is a schematic diagram of a prior art structure in which a P-type region is formed at the bottom of the gate of a trench gate power MOSFET. Figure 3 is a schematic diagram of a prior art structure in which a P-type heavily doped region is used to protect the gate oxide layer at the bottom of the trench in a trench gate power MOSFET. Figure 4 is a schematic diagram of another prior art structure in which a P-type heavily doped region is used to protect the gate oxide layer at the bottom of the trench in a trench gate power MOSFET. Figure 5 is a flowchart of a process method adapted to increase the thickness of the bottom oxide layer of the trench according to an embodiment of the present invention. Figure 6 is a schematic diagram of a structure in which an N-type drift region is formed on an N-type semiconductor substrate according to an embodiment of the present invention. Figure 7 is a schematic diagram of a structure in which an N-type heavily doped region is formed after source ion implantation according to the structure in Figure 6. Figure 8 is a schematic diagram of the structure forming the P-type heavily doped region and the P-type substrate region according to the structure in Figure 7. Figure 9 is a schematic diagram of the structure in Figure 8, where silicon dioxide is deposited as a hard masking layer. Figure 10 is a schematic diagram of the structure in Figure 9, where the trench region is defined by a photolithography process. Figure 11 is a schematic diagram of the structure in Figure 10, where a pad oxide layer is deposited after removing the hard masking layer. Figure 12 is a schematic diagram of the structure in Figure 11, where silicon glass dopants are deposited to form two opposing sidewall layers. Figure 13 is a schematic diagram of the structure in Figure 12, where a heat treatment process is performed to allow the silicon glass dopants to flow into the gaps and fill the bottom of the trench, thereby forming a thick oxide layer at the bottom of the trench.

Claims

1. A process method for increasing the thickness of the oxide layer at the bottom of a trench, comprising the following steps: providing a semiconductor substrate and forming a drift region on the semiconductor substrate; forming a first heavily doped region in the drift region; forming a second heavily doped region and a third heavily doped region on opposite sides of the first heavily doped region, and forming a substrate system between the first heavily doped region, the second heavily doped region, the third heavily doped region and the drift region; depositing a hard mask layer on the first heavily doped region, the second heavily doped region and the third heavily doped region, and forming a trench by a photolithography process; removing the hard mask layer and depositing a pad oxide layer, wherein... The pad oxide layer covers at least two opposite sidewalls and a bottom of the trench; a silica glass dopant is deposited, wherein the silica glass dopant covers the pad oxide layer on the two opposite sidewalls of the trench, thereby forming two opposite sidewall layers, and a gap is formed between the two sidewall layers; and a heat treatment process is performed to allow the silica glass dopant to flow into the gap and fill the bottom of the trench, thereby forming a thick oxide layer at the bottom of the trench.

2. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The depth of the trench is between 1 micrometer and 2 micrometers, and the width of the trench is between 0.5 micrometers and 2 micrometers.

3. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The oxide layer of this pad is made of silicon dioxide.

4. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The step of depositing the oxide layer of the padding includes depositing the oxide layer of the padding by employing a low-pressure chemical vapor deposition (LPCVD) or a plasma-enhanced chemical vapor deposition (PECVD).

5. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The thickness of the oxide layer covering the two opposite sidewalls of the trench is between 30 nanometers and 200 nanometers.

6. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The thickness of the oxide layer covering the bottom of the trench is between 30 nanometers and 300 nanometers.

7. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, In the step of depositing the silica glass dopant, the thickness of the silica glass dopant is between 100 nanometers and 200 nanometers.

8. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The step of forming the opposing two sidewall layers from the silica glass dopant further includes: etching the silica glass dopant using an anisotropic etching process to form the two sidewall layers having the gap therein.

9. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 8, wherein, Each of the two sidewall layers has a thickness between 50 nanometers and 200 nanometers.

10. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 8, wherein, Each of the two sidewall layers has a height between 0.5 micrometers and 2 micrometers.

11. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The materials of the silica glass dopant include: borosilicate silica glass, borosilicate silica glass, phosphor silica glass, and arsenic silica glass.

12. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 11, wherein, The silica glass dopant contains between 1% and 5% boron, phosphorus, or arsenic dopants.

13. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The heat treatment process is a high-temperature annealing process.

14. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 13, wherein, The process temperature for this high-temperature annealing process is between 900°C and 1300°C.

15. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 13, wherein, The process time for this high-temperature annealing process is between 5 minutes and 120 minutes.

16. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The formed thick oxide layer has a side thickness on both sides and a central thickness in its center. The side thickness is greater than the central thickness, so that the surface of the thick oxide layer has an upward curved shape.

17. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The semiconductor substrate, the drift region, and the first heavily doped region have a first semiconductor conductivity type, and the second heavily doped region, the third heavily doped region, and the substrate region have a second semiconductor conductivity type. The first semiconductor conductivity type and the second semiconductor conductivity type are different conductivity types.

18. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The semiconductor substrate is made of materials including silicon, silicon carbide, gallium oxide, aluminum nitride, and diamond.

19. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The step of forming the first heavily doped region in the drift region further includes forming the first heavily doped region by a source ion implantation process.

20. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The material of this hard masking layer is silicon dioxide.

21. The process method for increasing the thickness of the oxide layer at the bottom of the trench as described in claim 1, wherein, The trench extends through the first heavily doped region and the substrate region, and the bottom of the trench terminates in the drift region.

22. A trench gate power metal-oxide-semiconductor (MOSFET) formed using a process method for increasing the thickness of the oxide layer at the bottom of a trench as described in claim 1, comprising: The semiconductor substrate; The drift region is formed on the semiconductor substrate; This matrix region is formed on this drift region; The first, second, and third heavily doped regions are respectively formed on opposite sides of the first heavily doped region. The first, second, and third heavily doped regions are disposed on the substrate region. The trench is formed by the photolithography process, thereby separating the first heavily doped region and the substrate region. The pad oxide layer at least covers the two opposite sidewalls and the bottom of the trench. A thick oxide layer is formed on the pad oxide layer, filling and forming the bottom of the trench. The thick oxide layer includes the silica glass dopant. The thick oxide layer has a side thickness on each side and a central thickness at its center. The side thickness is greater than the central thickness, giving the surface of the thick oxide layer an upward-curved shape.

23. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 22, wherein, The materials of the silica glass dopant include: borosilicate silica glass, borosilicate silica glass, phosphor silica glass, and arsenic silica glass.

24. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 23, wherein, The silica glass dopant contains between 1% and 5% boron, phosphorus, or arsenic dopants.

25. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 22, wherein, The thickness of the silica glass dopant is between 100 nanometers and 200 nanometers.

26. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 22, wherein, The semiconductor substrate is made of materials including silicon, silicon carbide, gallium oxide, aluminum nitride, and diamond.

27. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 22, wherein, The semiconductor substrate, the drift region, and the first heavily doped region have a first semiconductor conductivity type, and the second heavily doped region, the third heavily doped region, and the substrate region have a second semiconductor conductivity type. The first semiconductor conductivity type and the second semiconductor conductivity type are different conductivity types.

28. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 22, wherein, The oxide layer of this pad is made of silicon dioxide.

29. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 22, wherein, The depth of the trench is between 1 micrometer and 2 micrometers, and the width of the trench is between 0.5 micrometers and 2 micrometers.

30. The trench gate power metal-oxide-semiconductor field-effect transistor as described in claim 22, wherein, The heat treatment process is a high-temperature annealing process, the process temperature of which is between 900°C and 1300°C, and the process time of which is between 5 minutes and 120 minutes.

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