Semiconductor device and fabrication method thereof

Abstract

A semiconductor device includes a substrate having an active area and an isolation region surrounding the active area; a source region and a drain region disposed in the active area, defining a channel region therebetween; a gate disposed over the channel region; a gate dielectric layer disposed between the gate and the channel region; and a ring-shaped salicidie block layer disposed along a perimeter of the active area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Prior Technology

[0002] Embedded flash memory is a type of non-volatile memory that is directly integrated into an integrated circuit (IC) chip.

[0003] Existing medium voltage (MV) components in embedded flash memory devices suffer from poor breakdown voltage uniformity, thus requiring further improvement. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor device and its manufacturing method to overcome the shortcomings or disadvantages of the prior art.

[0005] The present invention provides a semiconductor device comprising: a substrate having an active region and an isolation region surrounding the active region; a source region and a drain region disposed in the active region and defining a channel region therebetween; a gate disposed above the channel region; a gate dielectric layer disposed between the gate and the channel region; and an annular silica barrier layer disposed along the periphery of the active region.

[0006] According to an embodiment of the present invention, an annular groove is formed at the boundary between the isolation region and the active region, wherein the annular silicate barrier layer overlaps with the annular groove.

[0007] According to an embodiment of the present invention, the annular silicate barrier layer completely covers the annular groove and extends to the peripheral portion of the active region adjacent to the annular groove.

[0008] According to an embodiment of the present invention, the width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

[0009] According to an embodiment of the present invention, the width of the annular silica barrier layer ranges from 0.2 to 0.4 micrometers.

[0010] According to an embodiment of the present invention, the annular silica barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

[0011] According to an embodiment of the present invention, the semiconductor device further includes: a source silicide layer disposed on the source region not covered by the annular silicide barrier layer; a drain silicide layer disposed on the drain region not covered by the annular silicide barrier layer; and a gate silicide layer disposed on the gate not covered by the annular silicide barrier layer.

[0012] According to an embodiment of the present invention, the source silicide layer and the drain silicide layer are not in direct contact with the isolation region.

[0013] According to an embodiment of the present invention, the semiconductor device further includes: a sidewall disposed on the sidewall of the gate, wherein the annular silica barrier layer extends to the sidewall and the gate.

[0014] According to an embodiment of the present invention, the sidewall component comprises silicon nitride.

[0015] Another aspect of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate having an active region and an isolation region surrounding the active region; forming a source region and a drain region in the active region and defining a channel region therebetween; forming a gate over the channel region; forming a gate dielectric layer between the gate and the channel region; and forming an annular silicon barrier layer along the periphery of the active region.

[0016] According to an embodiment of the present invention, an annular groove is formed at the boundary between the isolation region and the active region, wherein the annular silicate barrier layer overlaps with the annular groove.

[0017] According to an embodiment of the present invention, the annular silicate barrier layer completely covers the annular groove and extends to the peripheral portion of the active region adjacent to the annular groove.

[0018] According to an embodiment of the present invention, the width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

[0019] According to an embodiment of the present invention, the width of the annular silica barrier layer ranges from 0.2 to 0.4 micrometers.

[0020] According to an embodiment of the present invention, the annular silica barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

[0021] According to an embodiment of the present invention, the method further includes: forming a source silicide layer on the source region not covered by the annular silicide barrier layer; forming a drain silicide layer on the drain region not covered by the annular silicide barrier layer; and forming a gate silicide layer on the gate not covered by the annular silicide barrier layer.

[0022] According to an embodiment of the present invention, the source silicide layer and the drain silicide layer are not in direct contact with the isolation region.

[0023] According to an embodiment of the present invention, the method further includes: forming a sidewall on the sidewall of the gate, wherein the annular silica barrier layer extends to the sidewall and the gate.

[0024] According to an embodiment of the present invention, the sidewall component comprises silicon nitride. Simple Explanation of the Diagram

[0025] Figure 1 is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 is a schematic cross-sectional view along the tangent line I-I'. Figure 3 is a schematic cross-section along tangent II-II'. Figure 4 illustrates the process of manufacturing a semiconductor device. Implementation

[0026] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments can be implemented. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0027] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0028] Please refer to Figures 1 through 3, wherein Figure 1 is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention, Figure 2 is a cross-sectional schematic diagram along tangent I-I', and Figure 3 is a cross-sectional schematic diagram along tangent II-II'. As shown in Figures 1 through 3, the semiconductor device 1 includes a substrate 100 having an active region AA and an isolation region ST surrounding the active region AA. According to an embodiment of the present invention, for example, the substrate 100 may be a P-type silicon substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the isolation region ST may be a shallow trench insulating region. According to an embodiment of the present invention, the semiconductor device 1 may further include a high-voltage P-type well 110 disposed in the substrate 100.

[0029] According to an embodiment of the present invention, the semiconductor device 1 further includes a gate 101 extending along a reference y-axis direction in the first figure, which spans the active region AA. According to an embodiment of the present invention, the gate 101 is, for example, a polysilicon gate, but is not limited thereto.

[0030] According to an embodiment of the present invention, the semiconductor device 1 further includes a source region 102 and a drain region 103 disposed in the active region AA, and defining a channel region CH therebetween. According to an embodiment of the present invention, a gate 101 is disposed above the channel region CH. According to an embodiment of the present invention, the semiconductor device 1 further includes a gate dielectric layer GD disposed between the gate 101 and the channel region CH. According to an embodiment of the present invention, the gate dielectric layer GD is, for example, a silicon dioxide layer, but is not limited thereto.

[0031] According to an embodiment of the present invention, the semiconductor device 1 further includes an annular silica barrier layer 200 disposed along the periphery of the active region AA. According to an embodiment of the present invention, as shown in Figures 2 and 3, an annular groove D is formed at the boundary between the isolation region ST and the active region AA, wherein the annular silica barrier layer 200 overlaps with the annular groove D.

[0032] According to embodiments of the present invention, the width w of the annular silicate barrier layer 200 ranges, for example, from 0.2 to 0.4 micrometers. According to embodiments of the present invention, the annular silicate barrier layer 200 comprises, for example, silicon oxide, silicon nitride, or a combination thereof.

[0033] According to an embodiment of the present invention, the annular silicate barrier layer 200 completely covers the annular groove D and extends to the peripheral portion of the active region AA adjacent to the annular groove D. According to an embodiment of the present invention, the width s of the peripheral portion of the active region AA overlapping with the annular silicate barrier layer 200 ranges from 0 to 0.1 micrometers.

[0034] According to an embodiment of the present invention, as shown in Figure 3, the semiconductor device 1 further includes a source silicide layer 202 disposed on the source region 102 not covered by the annular silicide barrier layer 200, a drain silicide layer 203 disposed on the drain region 103 not covered by the annular silicide barrier layer 200, and a gate silicide layer 201 disposed on the gate 101 not covered by the annular silicide barrier layer 200.

[0035] According to an embodiment of the present invention, the source silicide layer 202 and the drain silicide layer 203 are in direct contact with the annular silicide barrier layer 200, but not in direct contact with the isolation region ST. This can effectively improve the uniformity of the breakdown voltage of the medium voltage (MV) components embedded in the flash memory device.

[0036] According to an embodiment of the present invention, as shown in Figures 2 and 3, the semiconductor device 1 further includes a sidewall sub-SP disposed on the sidewall of the gate 101, wherein, as shown in Figure 2, an annular silica barrier layer 200 extends to the sidewall sub-SP and the gate 101. According to an embodiment of the present invention, the sidewall sub-SP may, for example, comprise silicon nitride, but is not limited thereto.

[0037] Please also refer to Figure 4, which illustrates a process flow for fabricating a semiconductor device. As shown in Figures 1 to 4, firstly, step S1 is performed, providing a substrate 100 having an active region AA and an isolation region ST surrounding the active region AA. According to an embodiment of the present invention, for example, the substrate 100 may be a P-type silicon substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the isolation region ST may be formed using a shallow trench insulation process.

[0038] According to an embodiment of the present invention, the semiconductor device 1 may further include a high-voltage P-type well 110 disposed in the substrate 100. According to an embodiment of the present invention, as shown in Figures 2 and 3, an annular groove D is formed at the boundary between the isolation region ST and the active region AA.

[0039] Next, step S2 in Figure 4 is performed, involving an oxidation or deposition process to form a gate dielectric layer GD on the active region AA. According to embodiments of the present invention, the gate dielectric layer GD is, for example, a silicon dioxide layer, but is not limited thereto.

[0040] Next, step S3 in Figure 4 is performed, forming a gate 101 above the gate dielectric layer GD. According to an embodiment of the present invention, as shown in Figure 1, the gate 101 extends along the reference y-axis direction in Figure 1, spanning the active region AA. According to an embodiment of the present invention, the gate 101 is, for example, a polycrystalline silicon gate, but is not limited thereto. According to an embodiment of the present invention, as shown in Figures 2 and 3, sidewall sub-SPs are formed on the sidewalls of the gate 101. According to an embodiment of the present invention, the sidewall sub-SPs, for example, comprise silicon nitride.

[0041] Next, step S4 in Figure 4 is performed, in which a source region 102 and a drain region 103 are formed in the active region AA using a photolithography process and an ion implantation process, and a channel region CH is defined therebetween.

[0042] Next, step S5 in Figure 4 is performed, using deposition, lithography, and etching processes to form an annular silica barrier layer 200 along the periphery of the active region AA. According to an embodiment of the present invention, as shown in Figures 2 and 3, the annular silica barrier layer 200 is formed along an annular groove D at the boundary between the isolation region ST and the active region AA, wherein the annular silica barrier layer 200 overlaps with the annular groove D.

[0043] According to an embodiment of the present invention, as shown in Figures 2 and 3, the annular silicate barrier layer 200 completely covers the annular groove D and extends to the peripheral portion of the active region AA adjacent to the annular groove D. According to an embodiment of the present invention, the annular silicate barrier layer 200 may comprise, for example, silicon oxide, silicon nitride, or a combination thereof.

[0044] According to an embodiment of the present invention, the width s of the peripheral portion of the active region AA overlapping with the annular silicate barrier layer 200 ranges from 0 to 0.1 micrometers. According to an embodiment of the present invention, the width w of the annular silicate barrier layer 200 ranges from 0.2 to 0.4 micrometers.

[0045] Next, step S6 in Figure 4 is performed to carry out the metal silicide process, forming a source silicide layer 202 on the source region 102 not covered by the annular silicide barrier layer 200; forming a drain silicide layer 203 on the drain region 103 not covered by the annular silicide barrier layer 200; and forming a gate silicide layer 201 on the gate 101 not covered by the annular silicide barrier layer 200.

[0046] According to an embodiment of the present invention, as shown in Figure 3, the source silicide layer 202 and the drain silicide layer 203 are not in direct contact with the isolation region ST. According to an embodiment of the present invention, as shown in Figure 2, the annular silicide barrier layer 200 extends onto the sidewall sub-SP and the gate 101. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0047] 1: Semiconductor devices 100:Substrate 101: Gate 102: Source Region 103: Drainage Zone 110: High-pressure P-type well 200: Ring-shaped silica barrier layer 201: Gate silicon layer 202: Source silicon layer 203: Drain silica layer AA: Active Zone ST: Quarantine Zone CH: Passage Area GD: Gate Dielectric Layer SP: Sidewall D: Annular groove w: width s: width S1-S6: Steps

Claims

1. A semiconductor device comprising: a substrate having an active region and an isolation region surrounding the active region; a source region and a drain region disposed in the active region and defining a channel region therebetween; a gate disposed above the channel region; a gate dielectric layer disposed between the gate and the channel region; and an annular silica barrier layer disposed along the periphery of the active region, wherein... An annular groove is formed at the boundary between the isolation zone and the active zone, wherein the annular silicate barrier layer overlaps with the annular groove.

2. The semiconductor device as claimed in claim 1, wherein, The annular silica barrier layer completely covers the annular groove and extends to the periphery of the active region adjacent to the annular groove.

3. The semiconductor device as claimed in claim 2, wherein, The width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

4. The semiconductor device as claimed in claim 1, wherein, The width of the annular silica barrier layer ranges from 0.2 to 0.4 micrometers.

5. The semiconductor device as claimed in claim 1, wherein, The annular silica barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

6. The semiconductor device of claim 1, further comprising: a source silicide layer disposed on the source region not covered by the annular silicide barrier layer; a drain silicide layer disposed on the drain region not covered by the annular silicide barrier layer; and a gate silicide layer disposed on the gate not covered by the annular silicide barrier layer.

7. The semiconductor device as claimed in claim 6, wherein, The source silicon layer and the drain silicon layer are not in direct contact with the isolation zone.

8. The semiconductor device of claim 1, further comprising: a sidewall disposed on the sidewall of the gate, wherein, The annular silica barrier layer extends to the sidewall and the gate.

9. The semiconductor device as claimed in claim 8, wherein, The sidewall contains silicon nitride.

10. A method of forming a semiconductor device, comprising: providing a substrate having an active region and an isolation region surrounding the active region; forming a source region and a drain region in the active region, and defining a channel region therebetween; forming a gate over the channel region; forming a gate dielectric layer between the gate and the channel region; and forming an annular silicon barrier layer along the periphery of the active region, wherein... An annular groove is formed at the boundary between the isolation zone and the active zone, wherein the annular silicate barrier layer overlaps with the annular groove.

11. The method as described in claim 10, wherein, The annular silica barrier layer completely covers the annular groove and extends to the periphery of the active region adjacent to the annular groove.

12. The method as described in claim 11, wherein, The width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

13. The method as described in claim 10, wherein, The width of the annular silica barrier layer ranges from 0.2 to 0.4 micrometers.

14. The method as described in claim 10, wherein, The annular silica barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

15. The method of claim 10, further comprising: forming a source silicide layer on the source region not covered by the annular silicide barrier layer; forming a drain silicide layer on the drain region not covered by the annular silicide barrier layer; and forming a gate silicide layer on the gate not covered by the annular silicide barrier layer.

16. The method as described in claim 15, wherein, The source silicon layer and the drain silicon layer are not in direct contact with the isolation zone.

17. The method of claim 10, further comprising: forming a sidewall on the sidewall of the gate, wherein, The annular silica barrier layer extends to the sidewall and the gate.

18. The method as described in claim 17, wherein, The sidewall contains silicon nitride.

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