Semiconductor devices

TW202641102APending Publication Date: 2026-10-01NUVOTON TECH CORP JAPAN
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Patent Information

Application Number
TW115102311
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-01-23
Filing Date
2026-01-21
Publication Date
2026-10-01

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  • Figure TWG2TA001079126_001
    Figure TWG2TA001079126_001
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    Figure TWG2TA001079126_002
  • Figure TWG2TA001079126_003
    Figure TWG2TA001079126_003
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Abstract

A semiconductor device (1) comprises: a low-concentration impurity layer (33) of a first conductivity type formed on a semiconductor substrate (32) of the first conductivity type; a main region (18) of a second conductivity type formed on the low-concentration impurity layer (33); a plurality of gate trenches (17) extending in a first direction parallel to and parallel to the upper surface of the semiconductor substrate (32) and formed at equal intervals in a second direction orthogonal to the first direction; and a plurality of source regions (14) of the first conductivity type sandwiched in the second direction. In each of the plurality of gate trench portions (20) of the plurality of gate trenches (17), they are alternately formed in the first direction at the first period. The plurality of source regions (14) of the plurality of conductivity types and the plurality of main contact regions (13) of the second conductivity type are formed. The upper surface of each of the plurality of mesa (20) is recessed in the first direction at the second period n (n is an integer greater than or equal to 1) times the first period, and at least a portion of the lower surface has a plurality of first recesses (71) that contact the main contact region (13) or the main region (18).
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