Integrated circuit device and method of manufacturing the same

Abstract

Some embodiments relate to a method of fabricating an integrated circuit (IC) device, including forming, on a first substrate of a first IC die having one or more first dielectric layers disposed on a first side of the first substrate, a second dielectric layer on a second side of the first substrate, where one or more first conductive structures are disposed in the one or more first dielectric layers; performing a high-density-plasma (HDP) chemical vapor deposition (CVD) operation employing a combination of silane gas and oxygen gas to form a third dielectric layer on the second dielectric layer; forming a second conductive structure that extends from a side of the first IC die and through the first substrate; and bonding the first IC die to a second IC die to electrically couple one or more third conductive structures of the second IC die to the second conductive structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to integrated circuit devices and methods of manufacturing the same. Prior Technology

[0002] In the increasing use of integrated circuit (IC) devices, the use of multi-die integrated circuit devices is becoming increasingly important to provide reduced device footprint, higher operating speeds, and other benefits. Furthermore, when this technology is implemented in certain image integrated circuit devices (e.g., complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) devices), by bonding multiple IC chips into a single IC device, it can positively influence various image-related characteristics, such as image resolution and refresh rate. Summary of the Invention

[0003] In some embodiments, this disclosure relates to a method. The method includes forming a second dielectric layer on a first substrate having one or more first dielectric layers disposed on a first side of a first substrate, the second dielectric layer being formed on a second side of the first substrate opposite to the first side of the first substrate, wherein one or more first conductive structures are disposed in the one or more first dielectric layers, and the one or more first dielectric layers encompass the first side of the first integrated circuit die; performing a high-density plasma (HDP) chemical vapor deposition (CVD) operation to form a third dielectric layer on the second dielectric layer, the HDP... The CVD operation employs a combination of silane (SiO₄) gas and oxygen (O₂) gas; at least one fourth dielectric layer is formed on the third dielectric layer, the at least one fourth dielectric layer including a second side of the first integrated circuit die opposite to a first side of the first integrated circuit die; a second conductive structure is formed in at least one of the at least one fourth dielectric layer, the third dielectric layer, the second dielectric layer, the first substrate, and at least one of one or more first dielectric layers, the second conductive structure extending from the second side of the first integrated circuit die to at least one of one or more first conductive structures; on the first side of the second substrate of the second integrated circuit die, one or more third conductive structures are formed in one or more fifth dielectric layers disposed on the second substrate; and the first integrated circuit die is bonded to the second integrated circuit die to electrically couple one or more third conductive structures to the second conductive structure.

[0004] In other embodiments, this disclosure relates to another method. The method includes forming one or more first dielectric layers on a first side of a first substrate and one or more first conductive structures disposed within the one or more first dielectric layers to form a first portion of a first integrated circuit die having a first side opposite to the first substrate; inverting the first portion of the first integrated circuit die; forming a second dielectric layer on a second side of the first substrate; and performing a high-density plasma (HDP) chemical vapor deposition (CVD) operation to form a third dielectric layer on the second dielectric layer. The CVD operation employs a combination of silane (SiO₄) and oxygen (O₂) gases, performed at a temperature of approximately 300 degrees Celsius. At least one fourth dielectric layer is formed on the third dielectric layer, the at least one fourth dielectric layer comprising a second side of the first integrated circuit die. A second conductive structure is formed in each of the at least one fourth dielectric layer, the third dielectric layer, the second dielectric layer, the first substrate, and at least one of one or more first dielectric layers, the second conductive structure extending from the second side of the first integrated circuit die to at least one of the one or more first conductive structures. The first integrated circuit die is inverted. On the first side of the second substrate of the second integrated circuit die, one or more third conductive structures are formed in one or more fifth dielectric layers disposed on the second substrate, the one or more third conductive junctions... At least one of the structures extends to a first side of the second integrated circuit die opposite to the second substrate; a second side of the first integrated circuit die is bonded to a first side of the second integrated circuit die to electrically couple one or more third conductive structures to the second conductive structure; on a first side of the third substrate of the third integrated circuit die, one or more fourth conductive structures are formed in one or more sixth dielectric layers disposed on the third substrate, at least one of the one or more fourth conductive structures extends to a first side of the third integrated circuit die opposite to the third substrate; the third integrated circuit die is reversed; and a first side of the third integrated circuit die is bonded to a first side of the first integrated circuit die to electrically couple at least one of the one or more fourth conductive structures to at least one of the one or more first conductive structures.

[0005] In other embodiments, this disclosure relates to an integrated circuit device. The integrated circuit device includes a first integrated circuit die comprising: a first substrate; one or more first dielectric layers disposed on an upper side of the first substrate; one or more first conductive structures disposed in the one or more first dielectric layers; a second dielectric layer disposed on a lower side of the first substrate; a third dielectric layer disposed on a lower side of the second dielectric layer, the third dielectric layer having a nitrogen concentration less than five percent of the nitrogen concentration of at least one of the one or more first dielectric layers; at least one fourth dielectric layer disposed on a lower side of the third dielectric layer, the at least one fourth dielectric layer comprising a lower side of the first integrated circuit die; and a second conductive structure extending upward from the lower side of the first integrated circuit die through the first substrate to at least one of the one or more first conductive structures; and a second integrated circuit die comprising: a second substrate; one or more fifth dielectric layers disposed on an upper side of the second substrate; and one or more third conductive structures disposed in the one or more fifth dielectric layers, wherein at least one of the one or more third conductive structures is electrically coupled to a second conductive structure on an upper side of the second integrated circuit die. Simple Explanation of the Diagram

[0006] The aspects of this disclosure are most readily understood from the following detailed description when reading the accompanying drawings. These drawings are drawn to clearly illustrate relevant aspects of the embodiments. These drawings may illustrate the relationships between various structures and / or elements within the embodiments. It should be noted that these drawings are not necessarily drawn to scale. In some cases, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 shows a cross-sectional view of some embodiments of an integrated circuit imaging device comprising multiple integrated circuit chips bonded together. Figure 2 shows a cross-sectional view of some embodiments of a magnified portion of the cross-sectional view of Figure 1, including a multilayer dielectric structure disposed on the underside of the substrate. Figure 3 shows a cross-sectional view depicting the thickness of some embodiments of the dielectric layer subset shown in Figure 2. Figures 4A to 4X show cross-sectional views of some embodiments of the polydiode integrated circuit imaging device associated with Figure 1 at various stages of manufacturing, according to this disclosure. Figures 5 and 6 illustrate methods for forming polycrystalline integrated circuit devices according to some embodiments of the present disclosure. Implementation

[0007] This disclosure provides numerous different embodiments or examples to achieve the various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, embodiments in which a first feature is formed on or over a second feature may include instances where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] In addition, spatial relative terms such as "below," "under," "lower," "above," "above," etc., may be used herein for descriptive convenience to describe the relationship between one element or feature and another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. In some embodiments, the terms "about" and / or "about" may be interpreted as meaning + / - 10% or + / - 5%, while in other embodiments, the terms "about" and / or "about" may be interpreted as within the normal manufacturing tolerances of a given wafer fabrication process.

[0009] In some complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) integrated circuit (IC) devices, multiple IC chips (e.g., three or more IC chips) may be coupled together to support several different circuits, components, or functions associated with an electronic device (e.g., a digital camera). For example, multiple IC chips may include a photodetector array, timing and readout circuitry that converts the charge stored in the photodetector into image data, data storage and / or processing circuitry for storing and / or processing the image data for use by other parts of the electronic device, etc.

[0010] In such integrated circuit devices employing three or more integrated circuit dies, one or more internal dies may be bonded to two other integrated circuit dies on opposite sides of the internal die: one on a first side of the internal die, where multiple conductive (e.g., metal) layers within several dielectric layers are disposed on the upper side of the substrate, and the other on a second side of the internal die, closer to the lower side of the coupling substrate. While die bonding of the dielectric layer of the first side of the internal die to the dielectric layer of another integrated circuit die is generally considered to form a stable connection between dies, bonding of the lower side of the substrate of the second side of the internal die to the dielectric layer of another integrated circuit die can sometimes result in a less stable integrated circuit device structure.

[0011] As described in more detail below, depending on the specific chemical properties of one or more dielectric materials disposed under the substrate, at least a portion of the structure of the substrate and the dielectric layer disposed under the substrate may eventually peel off. For example, the dielectric layer disposed under the substrate may separate from the substrate itself. In some cases, it is suspected that one or more dielectric layers may release water vapor, causing water vapor to accumulate under the substrate, thereby causing peeling and thus damaging the integrated circuit device.

[0012] To address this issue, this disclosure provides embodiments of several integrated circuit devices in which the water content and / or nitrogen content in one or more dielectric layers disposed on the underside of a substrate is low. In some instances, nitrogen may act as a water repellent, potentially causing at least some of the present water to move toward the underside of the substrate, thereby potentially facilitating peeling. In some embodiments, the amount of water present near or at the substrate (e.g., near or at one or more dielectric layers disposed on the underside of the substrate) is less than or equal to about 2 x 10⁻⁹ parts per million (ppm). Furthermore, in some embodiments, the amount of nitrogen present may be less than five percent of the nitrogen content in other dielectric layers typically used in integrated circuit grains, such as inter-metal dielectric (IMD) layers deposited on the substrate, or dielectric layers used to bond the substrate of an integrated circuit grain to another integrated circuit grain.

[0013] For example, an undoped silicate glass (USG) layer deposited on an intermediate dielectric layer (e.g., a high dielectric constant or high-κ dielectric layer) disposed on a substrate may result in the presence of significant amounts of water and nitrogen, potentially leading to separation of the intermediate dielectric layer from the substrate. In some instances, the USG may be formed using a combination of silane (SiH4) gas and nitrous oxide (N2O) gas (e.g., at a temperature of approximately 400 degrees Celsius) via high-density-plasma (HDP) chemical vapor deposition (CVD) operations.

[0014] In contrast, using an HDP oxide layer on an intermediate dielectric layer (e.g., a high-κ dielectric layer) disposed on a substrate can result in a significant reduction in the presence of water (e.g., approximately 2 x 10⁻⁹ ppm) and nitrogen (e.g., nitrogen concentrations less than five percent as provided in the USG case described above, or less than five percent of the dielectric layer used for intergranular bonding or disposed on the substrate as an IMD layer), thereby reducing or eliminating potential delamination at the substrate / intermediate dielectric layer boundary. In some instances, the HDP oxide may be formed via HDP CVD operation using a combination of silane gas (SiH₄) and oxygen (O₂) at relatively lower temperatures (e.g., approximately 300 degrees Celsius) compared to the USG case described above.

[0015] In other embodiments, similar reductions in water and nitrogen content can be achieved through other means. For example, the amount of water produced can be reduced by decreasing the amount of the thin film deposition precursor (e.g., by reducing the amount or flow rate of silane gas and / or nitrous oxide gas used for depositing the dielectric thin film). In other embodiments, the amount of nitrogen present can be reduced by extending the exposure time or reducing the power used for the radio frequency (RF) energy to create the high-density plasma from the precursor used to create the thin film, which may result in a reduction of nitrogen impurities introduced into the deposited thin film.

[0016] Therefore, in some embodiments, reducing the presence of water and / or nitrogen may result in the formation of low-stress, high-adhesion dielectric films by reducing the likelihood of peeling (e.g., between the substrate and adjacent dielectric layers), which may lead to higher film stack quality and increased circuit probe (CP) test yield.

[0017] Figure 1 illustrates a cross-sectional view of an integrated circuit imaging device (or more generally, an integrated circuit device) 100 comprising multiple integrated circuit dies (and / or wafers) 101, 102, and 103 bonded together in some embodiments. In the various embodiments described herein, integrated circuit die 102 is sometimes referred to as the first integrated circuit die, integrated circuit die 103 as the second integrated circuit die, and integrated circuit die 101 as the third integrated circuit die. Despite these designations, integrated circuit dies 101, 102, and 103 may be manufactured individually and subsequently bonded to another of integrated circuit dies 101, 102, and 103 in any order (including simultaneously). Furthermore, while three integrated circuit dies 101, 102, and 103 are depicted in Figure 1, in other embodiments, the integrated circuit device 100 may include two or more additional dies.

[0018] As shown in Figure 1, the integrated circuit die 101 includes a substrate 110A (e.g., a semiconductor substrate, such as a silicon (Si) substrate) in which a plurality of photosensitive regions 114 are disposed (e.g., doped or implanted within the substrate 101A). In some embodiments, the substrate 110A may be a p-type substrate, and the photosensitive regions 114 may be n-doped regions, or vice versa. In some embodiments, each photosensitive region 114 may form part of a photodetector (e.g., a PN photodiode, a PIN photodiode, or the like) with the surrounding area of ​​the substrate 110A. Although eight photosensitive regions 114 are depicted in Figure 1, other embodiments may include any other number of photosensitive regions 114.

[0019] In some embodiments, the photosensitive area 114 may be at least partially surrounded laterally by one or more vertically oriented optical isolation structures 116, which may extend at least partially from the upper side of the substrate 110A into the substrate 110A. The optical isolation structure 116 (e.g., fabricated as a deep trench isolation (DTI) structure) may include a light-reflective material, which may include one or more metals and / or one or more oxides (e.g., silicon oxide (SiOx), such as silicon dioxide (SiO2), or another oxide) or other dielectric materials.

[0020] Furthermore, in some embodiments, the dielectric isolation structure 111 may be disposed in the substrate 110A and may be used to electrically isolate a portion of the corresponding upper bonding structure 124 from the substrate 110A. In some embodiments, the upper bonding structure 124 may facilitate bonding with other integrated circuit device-related structures located on the integrated circuit die 101.

[0021] Furthermore, in some embodiments, one or more dielectric layers 117 and 112A may be disposed on the substrate 110A, which may include, but are not limited to, silicon dioxide (SiO2), another silicon oxide (SiOx), or another dielectric material. In some embodiments, dielectric layers 117 and 112A may be used as passivation layers and / or anti-reflective coating (ARC) layers. Dielectric layers 117 and 112A may include one or more of silicon-oxide-aluminum (SiOAl), aluminum oxide (AlO), hafnium oxide (HfO), tantalum-oxide-silicon (TaOSi) (e.g., for anti-reflection), and / or silicon oxide (SiOx) (e.g., for passivation).

[0022] Furthermore, in some embodiments, a mesh structure including one or more reflective segments 118 may be configured on and / or within the dielectric layer 117. The reflective segments 118 constituting the mesh structure may define multiple openings through which light from above may be guided by the reflective segments 118 toward the photosensitive area 114. In some embodiments, the reflective segments 118 may comprise one or more materials, such as metals (e.g., tungsten (W)), barrier materials (e.g., titanium nitride (TiN)), and / or dielectric materials (e.g., silicon oxide (SiOx)).

[0023] In some embodiments, an optical filter layer having a plurality of filter elements 120 (e.g., each filter element 120 may be disposed over a corresponding photosensitive area 114) may be disposed over a dielectric layer 112A. Each filter element 120 may include a dielectric material that filters light of one or more wavelength bands to allow specific wavelength bands (e.g., including red, green, or blue bands) to pass through. In some embodiments, each filter element 120 may include a pigment, dye, or other light-transmitting material for filtering light of one or more wavelength bands.

[0024] Above the filter element 120, a plurality of corresponding lenses (e.g., microlenses) 122 may be disposed. Each lens 122 may be associated with a corresponding photosensitive area 114. In some embodiments, each lens 122 may guide at least some light through the corresponding filter element 120 and dielectric layers 112A and 117 into the corresponding photosensitive area 114 below it. In some embodiments, the lens 122 may be made of a polymer, oxide (e.g., silicon dioxide (SiO2)) or other substantially transparent material.

[0025] In the view provided in FIG1, a plurality of gate structures 128 (e.g., one gate structure for each photosensitive region 114) may be configured on the underside of the substrate 110A to serve as gate terminals of a transfer transistor that transfers charge from the photosensitive region 114 to a floating diffusion region (not explicitly shown in FIG1) for signal amplification, readout, etc. In some embodiments, the gate structure 128 may comprise polysilicon or another conductive material disposed on an oxide or other dielectric material.

[0026] Also disposed beneath the substrate 110A is one or more dielectric layers 126A, wherein one or more conductive structures 130 are disposed to facilitate electrical connections between circuit portions within the integrated circuit die 101 and with adjacent integrated circuit dies 102. In some embodiments, the dielectric layer 126A may include, but is not limited to, silicon oxide (SiOx) (e.g., silicon dioxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, or the like. The conductive structures 130 may be arranged as layers of conductive elements (as shown in FIG1) and selectively interconnected through conductive via structures (not explicitly shown in FIG1). In some embodiments, the conductive structures 130 may comprise one or more metals (e.g., copper (Cu)), alloys, or another conductive material (e.g., polycrystalline silicon (poly-Si)). One or more such conductive structures 130 may be electrically connected to one or more gate structures 128.

[0027] To facilitate bonding and electrical connection with the integrated circuit die 102, one or more dielectric layers 138 may be disposed on dielectric layer 126A, wherein one or more conductive bonding structures 132 are disposed. In some embodiments, the conductive bonding structure 132 may include bonding elements 134 disposed on the underside of the integrated circuit die 101. Furthermore, in some embodiments, the conductive bonding structure 132 may further include bonding via elements 133, which electrically couple the bonding elements 134 to one or more conductive structures 130 of the integrated circuit die 101.

[0028] In some embodiments, one or more etch stop layers 136 may be configured between dielectric layer 126A, dielectric layer 138, and other dielectric layers disclosed herein. Some examples of these etch stop layers 136 are depicted in Figure 2, which is discussed below. The etch stop layer 136 may comprise one or more of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), and / or another dielectric material.

[0029] Referring again to FIG1, the integrated circuit die 102 may include a semiconductor substrate 110B (e.g., including silicon (Si) or another semiconductor material) comprising a plurality of well regions 140. For example, well regions 140 may be n-type or p-type well regions by ion doping or implantation. Furthermore, in some embodiments, one or more well regions 140 may include source-drain regions 129 disposed within well regions 140. For example, an n-type well region 140 may include a p-type source-drain region 129, and vice versa. As used herein, the term "source-drain region" or similar terms may refer to the individual or collective source or drain regions depending on the context.

[0030] In some embodiments, substrate 110B may include one or more shallow trench isolation (STI) structures 142 extending downward from the upper side of substrate 110B. In some embodiments, STI structures 142 may substantially isolate adjacent well regions 140. Furthermore, in some embodiments, STI structures 142 may include silicon oxide (e.g., silicon dioxide (SiO₂)) or other dielectric materials.

[0031] Each well region 140 disposed on the upper side of the substrate 110B may have a gate structure 128. In some embodiments, the gate structure 128 may comprise a layer of oxide or other dielectric material on which conductive elements may be disposed. In these cases, the gate structure 128 may operate as a gate transistor, forming together with the source-drain region 129 and the well region 140 as a transistor that may be used in circuitry for reading out or processing image data from the integrated circuit die 101.

[0032] One or more dielectric layers 126B may also be disposed on the upper side of the substrate 110B, wherein one or more conductive structures 130 are disposed, in a manner similar to that described above for the integration of the integrated circuit die 101. In some embodiments, the conductive structures 130 may be electrically connected to the gate structure 128, the source-drain region 129, or other structures or elements within the integrated circuit die 102.

[0033] Furthermore, in some embodiments, one or more dielectric layers 138, possibly including one or more etch stop layers 136, may be disposed above dielectric layer 126B. Further, one or more conductive bonding structures 132 may be disposed in dielectric layer 138, similar to those described above for bonding integrated circuit dies 101. In some embodiments, one or more conductive bonding structures 132 may be coupled to one or more conductive structures 130 of integrated circuit die 102 and / or bonding structures 132 of integrated circuit die 101, thereby facilitating electrical connection between integrated circuit dies 101 and 102 in bonding region 104A.

[0034] In some embodiments, a plurality of dielectric layers 154, 152, and / or 150 may be disposed under the substrate 110B of the integrated circuit die 102 (e.g., to provide a stable base, on which dielectric layer 138 and an accompanying conductive bonding structure 132 may be disposed for bonding with the integrated circuit die 103 in bonding region 104B). The various characteristics of these dielectric layers 154, 152, and 150, and the manner in which they are used in conjunction with the conductive bonding structure 132, are described in more detail below with reference to FIG. 2 (an enlarged cross-sectional view of region 200 indicated in FIG. 1).

[0035] Furthermore, in the integrated circuit die 102, a through-substrate via (TSV) structure 141 may be configured, extending from one or more of the plurality of dielectric layers disposed under the substrate 110B, through the substrate 110B, and to at least one conductive structure 130 located in the dielectric layer 126B. Further, in some embodiments, the lower end of the TSV structure 141 may be electrically connected to one or more conductive bonding structures 132, thereby facilitating electrical connections between one or more conductive structures 130 of the integrated circuit die 102 and the integrated circuit die 103.

[0036] As described in Figure 1, in some embodiments, the integrated circuit die 103 may include a semiconductor substrate 110C, in which well regions 140, source-drain regions 129, and STI structures 142 may be configured, as discussed above regarding integrated circuit die 102. Furthermore, a gate structure 128 may be configured on the well region 140 of the substrate 110C, and a conductive structure 130 may be configured within a dielectric layer 126C, which may be configured on top of the substrate 110C, corresponding to the configuration described above for integrated circuit die 102. Additionally, a bonding structure 132 may be configured in a dielectric layer 138, which may be configured on the dielectric layer 126C. In some embodiments, one or more etch stop layers 136 may be configured between the dielectric layers 138.

[0037] Figure 2 shows an enlarged cross-sectional view of region 200 of the cross-sectional view of Figure 1 in some embodiments, including a multilayer dielectric structure having dielectric layers 154, 152, and 150 disposed on the underside of substrate 110B. For example, Figure 2 depicts an STI structure 142 disposed within substrate 110B, an etch stop layer 210 disposed on the upper side of substrate 110B, and a dielectric layer 126B disposed on etch stop layer 210.

[0038] Furthermore, dielectric layers 154, 152, and 150 are disposed on the underside of substrate 110B, and etch stop layer 136 and dielectric layer 138 are disposed on dielectric layer 152 in an alternating manner. In some embodiments, dielectric layer 154 disposed on substrate 110B may comprise a high dielectric constant dielectric layer, although other types of dielectric materials may be used in other embodiments. Dielectric layer 150 disposed on dielectric layer 152 may be a passivation layer or isolation barrier, and may include, but is not limited to, silicon nitride (SiN).

[0039] The dielectric layer 152 may generate less water vapor and nitrogen during fabrication than at least some other dielectric layers disposed within the integrated circuit die. For example, the dielectric layer 152 may be a high-density-plasma (HDP) oxide (e.g., a form of silicon dioxide (SiO2)). In some embodiments, the HDP oxide may be deposited using an HPD CVD process employing a combination of silane (SiH4) gas and oxygen (O2) gas (e.g., at about 300 degrees Celsius, or in the range of 275 to 325 degrees Celsius). Furthermore, argon (Ar) gas may be included as a carrier gas to create the high-density plasma, which, through chemical reaction with silane and oxygen, facilitates the deposition of a thin film onto the dielectric layer 154.

[0040] In some instances, the use of oxygen may result in a significantly lower generation of nitrogen molecules or ions 202 within dielectric layer 152 compared to other dielectric layers (e.g., those typically deployed in IMD layers or inter-die bonding layers). Furthermore, in some instances, HPD CVD processes (e.g., particularly at temperatures around 300 degrees Celsius) may result in a significantly reduced amount of water vapor (H2O) molecules 204 generated during the creation of HDP oxides compared to the creation of other dielectric layers using other processes (e.g., undoped silica glass or low-deposition-rate resistor protection oxide (LRPO)). Additionally, in some instances, the reduced amount of nitrogen molecules or ions 202 may limit the repulsion of water vapor molecules 204 towards the substrate 110B, thereby reducing the likelihood of separation or peeling between the substrate 110B and dielectric layer 154, potentially improving the quality and reliability of the integrated circuit device 100.

[0041] In contrast, using an alternative material (e.g., undoped silica glass (USG)) as dielectric layer 152 may facilitate this stripping. For example, in another embodiment, USG may be deposited on dielectric layer 154 using an HPD CVD process employing a combination of silane (SiH4) gas (e.g., at various concentrations) and nitrous oxide (N2O) gas (e.g., at approximately 400 degrees Celsius). In some embodiments, argon (Ar) may be included as a carrier gas to create a high-density plasma that, through chemical reaction with silane and nitrous oxide, facilitates film deposition onto dielectric layer 154. In some instances, the use of nitrous oxide may result in the generation of a large number of nitrogen molecules or ions 202 (e.g., in the form of SiN- ions) configured within dielectric layer 152. Furthermore, such an HPD CVD process (e.g., particularly at a temperature of 400 degrees Celsius) may result in the presence of a large number of water vapor (H2O) molecules 204. Furthermore, in some instances, the presence of a relatively large number of nitrogen molecules or ions 202 may, in turn, repel water vapor molecules 204 toward the substrate 110B (e.g., due to heating during subsequent processing of the integrated circuit device 100). Some of these may eventually remain at one or more portions of the interface between the substrate 110B and the dielectric layer 154, which could further lead to separation or peeling between the substrate 110B and the dielectric layer 154. Such peeling will result in a reduction in the quality and reliability of the integrated circuit device 100.

[0042] In a further embodiment, referring to FIG1, one or more dielectric layers 126A, 126B, 126C, 138 of integrated circuit dies 101, 102, 103 may comprise one or more individual dielectric layers of a first dielectric material (e.g., silicon dioxide, USG, etc.) doped or implanted with nitrogen. The at least one individual dielectric layer may be, for example, an inter-layer dielectric (ILD) layer, an inter-metal dielectric (IMD) layer, a bonding dielectric layer, or a similar layer. In various embodiments, the percentage of first nitrogen atoms in the one or more individual dielectric layers is in the range of about 15 at% to 30 at%, or other suitable values. In a further embodiment, the at least one individual dielectric layer may be formed by an HPD CVD process employing a combination of silane (SiH4) gas and nitrous oxide (N2O) gas (e.g., at about 400 degrees Celsius). In some embodiments, dielectric layer 152 comprises a first dielectric material (e.g., silicon dioxide). In various embodiments, dielectric layer 152 is doped or implanted with nitrogen and has a second nitrogen atom percentage that is lower than the first nitrogen atom percentage of one or more individual dielectric layers (e.g., about 0.5 at% or lower, less than about 1.0 at% etc.). In a further embodiment, the nitrogen concentration in dielectric layer 152 is less than five percent of the nitrogen concentration in one or more individual dielectric layers. The relatively low nitrogen concentration of dielectric layer 152 (e.g., less than five percent of the nitrogen concentration in one or more individual dielectric layers) reduces or prevents separation or peeling between substrate 110B and dielectric layer 152, thereby improving the quality and reliability of integrated circuit device 100.

[0043] Figure 3 shows a cross-sectional view depicting the thicknesses of some embodiments of the subset of dielectric layers shown in Figure 2. More specifically, dielectric layer 154 is shown to have a thickness D1, dielectric layer 152 is shown to have a thickness D2, dielectric layer 150 is shown to have a thickness D3, and etch stop layer 136 is shown to have a thickness D4. In some embodiments, etch stop layer 136 may be the narrowest of the four dielectric layers shown (e.g., D4 < D3, D2, and D1). Furthermore, in some embodiments, the thickness of dielectric layer 154 (e.g., when containing a high dielectric constant dielectric material) may be significantly smaller than the thicknesses of dielectric layers 152 and 150 (e.g., D1 < D2 and D3). Furthermore, in some embodiments, the thickness of dielectric layer 152 (e.g., HDP oxide) may be significantly larger than the thickness of dielectric layer 150 (e.g., D2 > D3). In some embodiments, the thickness D1 of dielectric layer 154 is in the range of about 500 Å to 700 Å, or other suitable values. In some embodiments, the thickness D2 of dielectric layer 152 is in the range of about 2000 Å to 7500 Å, or other suitable values. In some embodiments, the thickness D3 of dielectric layer 150 is in the range of about 1500 Å to 2000 Å, or other suitable values.

[0044] Figures 4A to 4X illustrate cross-sectional views of a polycrystalline integrated circuit device (e.g., integrated circuit device 100 of Figure 1) at various stages of manufacturing, according to this disclosure. While Figures 4A to 4X are depicted as a series of actions, it should be understood that these actions are not limiting, as the order of actions in each series may change in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some actions described and / or illustrated may be omitted in whole or in part.

[0045] For example, Figure 4A shows at least one well region 140 formed (e.g., by doping, implantation or similar means) in the substrate 110B of the integrated circuit die 102. In addition, one or more source-drain regions 129 may be formed in each or more of the at least one well region 140.

[0046] Figure 4B illustrates the removal (e.g., by lithography and etching) of portions of substrate 110B to form one or more trenches 404 (e.g., between adjacent well regions 140 and / or at other locations on the upper side of substrate 110B). Figure 4C illustrates the formation (e.g., deposition) of dielectric material in the trenches 404 to form shallow trench isolation (STI) structures 142. In some embodiments, the STI structure 142 may include, but is not limited to, silicon oxide (e.g., silicon dioxide (SiO2)) or other dielectric materials. In some embodiments, a chemical-mechanical planarization (CMP) operation may be performed after the formation of the STI structure 142.

[0047] Figure 4D illustrates the formation (e.g., deposition and subsequent lithography and etching) of gate structures 128 on substrate 110B (e.g., one gate structure 128 per well region 140). In some embodiments, gate structures 128 may include, but are not limited to, polycrystalline silicon (poly-Si) or other conductive materials.

[0048] Figure 4E illustrates the formation of one or more conductive structures 130 in at least one dielectric layer 126B formed on a substrate 110B. In some embodiments, this formation may include depositing one or more dielectric layers 126B, interspersed with lithography and etching of the dielectric layers 126B, and subsequently depositing conductive material to form portions of the conductive structures 130, which may include conductive elements interconnected with conductive via structures (not explicitly shown in Figure 4E). In some embodiments, the dielectric material may include, but is not limited to, silicon oxide (SiOx) (e.g., silicon dioxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, or the like. Furthermore, in some embodiments, the conductive material may include copper (Cu) or other metals, alloys, and / or other conductive materials. Additionally, in some embodiments, one or more etch stop layers (not shown in FIG4E) may be formed between some dielectric layers 126B.

[0049] Figure 4F illustrates an etch stop layer 136 formed (e.g., deposited) on dielectric layer 126B and possibly on one or more conductive elements of conductive structure 130. In some embodiments, etch stop layer 136 may include, but is not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), and / or other dielectric materials.

[0050] Figure 4G illustrates the formation (e.g., deposition) of a dielectric layer 138 on an etch stop layer 136. In some embodiments, the dielectric layer 138 may comprise one or more of the dielectric materials described above.

[0051] Figure 4H illustrates the removal (e.g., by lithography and etching) of a portion of the dielectric layer 138 to form one or more trenches 406. Subsequently, Figure 4I illustrates the formation (e.g., deposition) of one or more conductive bonding structures 132 (e.g., including bonding elements 134 and possible bonding via elements 133, each bonding via element 133 connecting a corresponding bonding element 134 to one or more conductive structures 130). In some embodiments, the conductive bonding structure 132 may comprise copper (Cu) or other metals, alloys, and / or other conductive materials. Furthermore, in some embodiments, CMP operations may be performed on the resulting surfaces of the dielectric layer 138 and the conductive bonding structure 132.

[0052] Figure 4J shows a reversal or "flip" of the structure of Figure 4I to facilitate the formation of a structure on the underside of the substrate 110B, such as the various dielectric structures discussed above in relation to Figure 2.

[0053] Figure 4K illustrates the formation (e.g., deposition) of a dielectric layer 154 on a substrate 110B. In some embodiments, the dielectric layer 154 may include, but is not limited to, a high dielectric constant dielectric layer or other dielectric materials.

[0054] Figure 4L illustrates the formation (e.g., deposition) of dielectric layer 152 on dielectric layer 154. In some embodiments, dielectric layer 152 may comprise HDP oxide. More specifically, in some embodiments, dielectric layer 152 may be formed using an HDP CVD process employing a combination of silane gas and oxygen (e.g., at approximately 300 degrees Celsius, or in the range between 275 and 325 degrees Celsius).

[0055] Figure 4M illustrates the formation (e.g., deposition) of dielectric layer 150 on dielectric layer 152. In some embodiments, dielectric layer 150 may be a passivation layer and / or an isolation barrier, and may include, but is not limited to, silicon nitride (SiN).

[0056] Figure 4N illustrates the removal (e.g., by lithography and etching) of material to form one or more trenches 408 that pass through dielectric layers 150, 152, and 154, through substrate 110B, and into dielectric layer 126B, terminating at conductive structure 130. Subsequently, Figure 4O illustrates the formation (e.g., deposition) of conductive material (e.g., copper (Cu) or other metals, alloys, or other conductive materials) to form one or more TSV structures 141.

[0057] Figure 4P shows the formation (e.g., deposition) of an etch stop layer 136 on dielectric layer 150 and TSV structure 141. Figure 4Q shows the subsequent formation (e.g., deposition) of a dielectric layer 138 on etch stop layer 136.

[0058] Figure 4R illustrates the removal (e.g., by lithography and etching) of one or more portions of dielectric material to form one or more trenches 410 (e.g., at least partially entering dielectric layer 138 and possibly penetrating through dielectric layer 138 and etch stop layer 136 to reach TSV structure 141). Figure 4S illustrates the formation (e.g., deposition) of conductive material to provide conductive bonding structure 132 in a manner similar to that described above in relation to Figure 4I, resulting in the formation of integrated circuit die 102. Furthermore, in some embodiments, CMP operations may be performed on the resulting surface of dielectric layer 138 and conductive bonding structure 132.

[0059] Figure 4T illustrates the inversion of integrated circuit die 102 in preparation for bonding with integrated circuit die 103. In some embodiments, the various layers and structures of integrated circuit die 103 are configured as described above in relation to Figure 1. Figure 4U then illustrates the bonding of integrated circuit dies 102 and 103, creating an electrical connection between them via bonding structures 132 in bonding region 104B. In some embodiments, the bonding may be a thermally based bonding, wherein integrated circuit dies 102 and 103 are contacted with each other (e.g., at room temperature) to bond opposing dielectric layers 138. The assembly can then be heated to induce opposing conductive bonding structures 132 located in bonding region 104B to bond with each other.

[0060] Figure 4V shows the positioning of integrated circuit die 101, with the dielectric layer 138 and conductive bonding structure 132 of integrated circuit dies 101 and 102 facing each other. Then, Figure 4W shows the bonding of integrated circuit dies 102 and 103, with an electrical connection created between them through the bonding structure 132 in bonding region 104A. In some embodiments, the bonding may be a thermally based bonding, as described above in relation to Figure 4U.

[0061] Figure 4X illustrates further processing of the integrated circuit die 101 to create the integrated circuit device 100. In some embodiments, such processing may include forming trenches extending downward from the upper side of the integrated circuit die 101 to at least one conductive structure 130 (e.g., by lithography and etching), forming an upper bonding structure 124 in the trenches (e.g., by conformal deposition), and forming a lens 122 on the filter element 120 (e.g., by deposition and etching).

[0062] Figures 5 and 6 illustrate methods 500 and 600, respectively, for forming a polycrystalline integrated circuit device (e.g., integrated circuit device 100), according to some embodiments of this disclosure. While these methods and other methods described and / or illustrated herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the illustrated sequence or actions. Therefore, in some embodiments, actions may be performed in a different sequence than illustrated, and / or simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other undescribed actions or events may be included.

[0063] In action 502, one or more first dielectric layers (e.g., dielectric layer 126B of FIG. 1) are disposed on a first substrate (e.g., substrate 110B of FIG. 1) of the first integrated circuit die (e.g., integrated circuit die 102 of FIG. 1), and a second dielectric layer (e.g., dielectric layer 154 of FIG. 1 and 2) is formed on a second side of the first substrate opposite to the first side, wherein one or more first conductive structures (e.g., conductive structure 130 of FIG. 1) are disposed in one or more first dielectric layers. FIG. 4K shows a cross-sectional view corresponding to some embodiments of action 502.

[0064] In action 504, a high-density-plasma (HDP) chemical vapor deposition (CVD) operation is performed to form a third dielectric layer (e.g., dielectric layer 152 in Figures 1 and 2) on the second dielectric layer. The HDP CVD operation employs a combination of silane gas and oxygen. Figure 4L shows a cross-sectional view corresponding to some embodiments of action 504.

[0065] In action 506, at least one fourth dielectric layer (e.g., dielectric layers 150 and 138 of Figures 1 and 2) is formed on the third dielectric layer. The at least one fourth dielectric layer comprises a second side of the first integrated circuit die. Figure 4M shows a cross-sectional view corresponding to some embodiments of action 506.

[0066] In action 508, a second conductive structure (e.g., TSV structure 141 and conductive bonding structure 132 of Figures 1 and 2) is formed in each of at least one fourth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate, and at least one of one or more first dielectric layers. The second conductive structure extends from a second side of the first integrated circuit die to at least one of the one or more first conductive structures. Figures 4N to 4S show cross-sectional views corresponding to some embodiments of action 508.

[0067] In action 510, on the first side of the second substrate of the second integrated circuit die, one or more third conductive structures (e.g., conductive structure 130 and conductive bonding structure 132 of FIG. 1) are formed on the second substrate in one or more fifth dielectric layers (e.g., dielectric layers 126C and 138 of FIG. 1). FIG. 4T shows a cross-sectional view corresponding to some embodiments of action 510.

[0068] In action 512, the first integrated circuit die is joined with the second integrated circuit die to electrically couple one or more third conductive structures to the second conductive structure. Figure 4U shows a cross-sectional view corresponding to some embodiments of action 512.

[0069] Regarding method 600 of FIG. 6, in action 602, one or more first dielectric layers (e.g., dielectric layers 126B and 138 of FIG. 1), and one or more first conductive structures (e.g., conductive structure 130 and conductive bonding structure 132 of FIG. 1) disposed in one or more first dielectric layers, are formed on a first side of a first substrate (e.g., substrate 110B of FIG. 1) to form a first portion of a first integrated circuit die (e.g., integrated circuit die 102) having a first side opposite to the first substrate. FIG. 4E to 4I show cross-sectional views corresponding to some embodiments of action 602.

[0070] In action 604, a first portion of the first integrated circuit die is inverted. Figure 4J shows a cross-sectional view corresponding to some embodiments of action 604.

[0071] In action 606, a second dielectric layer (e.g., dielectric layer 154 of Figures 1 and 2) is formed on the second side of the first substrate. Figure 4K shows a cross-sectional view corresponding to some embodiments of action 606.

[0072] In action 608, a high-density-plasma (HDP) chemical vapor deposition (CVD) operation is performed to form a third dielectric layer (e.g., dielectric layer 152 in Figures 1 and 2) on the second dielectric layer. The HDP CVD operation may employ a combination of silane gas and oxygen, performed at a temperature of approximately 300 degrees Celsius. Figure 4L shows a cross-sectional view corresponding to some embodiments of action 608.

[0073] In action 610, at least one fourth dielectric layer (e.g., dielectric layers 150 and 138 of Figures 1 and 2) is formed on the third dielectric layer. The at least one fourth dielectric layer may comprise a second side of the first integrated circuit die. Figures 4M to 4Q show cross-sectional views corresponding to some embodiments of action 610.

[0074] In action 612, a second conductive structure (e.g., TSV structure 141 and conductive bonding structure 132 of Figures 1 and 2) is formed in each of at least one fourth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate, and at least one of one or more first dielectric layers. The second conductive structure may extend from a second side of the first integrated circuit die to at least one of one or more first conductive structures. Figures 4N to 4S show cross-sectional views corresponding to some embodiments of action 612.

[0075] In action 614, the first integrated circuit die is inverted. Figure 4T shows a cross-sectional view corresponding to some embodiments of action 614.

[0076] In action 616, on the first side of the second substrate (e.g., substrate 110C of FIG. 1) of the second integrated circuit die (e.g., integrated circuit die 103 of FIG. 1), one or more third conductive structures (e.g., conductive structure 130 and conductive bonding structure 132 of FIG. 1) are formed on the second substrate, disposed in one or more fifth dielectric layers (e.g., dielectric layers 126C and 138 of FIG. 1). At least one of the one or more third conductive structures may extend to the first side of the second integrated circuit die opposite the second substrate. FIG. 4T shows a cross-sectional view corresponding to some embodiments of action 616.

[0077] In action 618, the second side of the first integrated circuit die is joined to the first side of the second integrated circuit die to electrically couple one or more third conductive structures to the second conductive structure. Figure 4U shows a cross-sectional view corresponding to some embodiments of action 618.

[0078] In action 620, on the first side of the third substrate (e.g., substrate 110A of FIG. 1) of the third integrated circuit die (e.g., integrated circuit die 101 of FIG. 1), one or more fourth conductive structures (e.g., conductive structure 130 and conductive bonding structure 132 of FIG. 1) are formed on the third substrate and disposed in one or more sixth dielectric layers (e.g., dielectric layers 126A and 138 of FIG. 1). At least one of the one or more fourth conductive structures may extend to the first side of the third integrated circuit die opposite to the third substrate. FIG. 4V shows a cross-sectional view corresponding to some embodiments of action 620.

[0079] In action 622, the third integrated circuit die is inverted. Figure 4V shows a cross-sectional view corresponding to some embodiments of action 622.

[0080] In action 624, the first side of the third integrated circuit die is joined to the first side of the first integrated circuit die to electrically couple at least one of one or more fourth conductive structures to at least one of one or more first conductive structures. Figure 4W shows a cross-sectional view corresponding to some embodiments of action 624.

[0081] Therefore, in some embodiments, this disclosure relates to a method. The method includes forming a second dielectric layer on a first substrate having one or more first dielectric layers disposed on a first side of a first substrate, the second dielectric layer being formed on a second side of the first substrate opposite to the first side of the first substrate, wherein one or more first conductive structures are disposed in the one or more first dielectric layers, and the one or more first dielectric layers encompass the first side of the first integrated circuit die; performing a high-density plasma (HDP) chemical vapor deposition (CVD) operation to form a third dielectric layer on the second dielectric layer, the HDP... The CVD operation employs a combination of silane (SiO₄) gas and oxygen (O₂) gas; at least one fourth dielectric layer is formed on a third dielectric layer, the at least one fourth dielectric layer including a second side of the first integrated circuit die opposite to a first side of the first integrated circuit die; a second conductive structure is formed in at least one fourth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate, and at least one of one or more first dielectric layers, the second conductive structure extending from the second side of the first integrated circuit die to at least one of one or more first conductive structures; on the first side of the second substrate of the second integrated circuit die, one or more third conductive structures are formed in one or more fifth dielectric layers disposed on the second substrate; and the first integrated circuit die is bonded to the second integrated circuit die to electrically couple one or more third conductive structures to the second conductive structure. In some embodiments, the high-density plasma chemical vapor deposition operation is performed at a temperature of about 300 degrees Celsius. In some embodiments, the second dielectric layer comprises a high dielectric constant dielectric material. In some embodiments, the third dielectric layer comprises silicon dioxide. In some embodiments, the second conductive structure includes: a conductive through-substrate via extending through the first substrate to at least one of the one or more first conductive structures; and a first conductive bonding structure disposed on the conductive through-substrate via and extending to a second side of the first integrated circuit die. In some embodiments, the one or more third conductive structures include a second conductive bonding structure forming a portion of a first side of the second integrated circuit die; bonding the first integrated circuit die to the second integrated circuit die includes electrically coupling the second conductive bonding structure to the first conductive bonding structure.

[0082] In other embodiments, this disclosure relates to another method. The method includes forming one or more first dielectric layers on a first side of a first substrate and one or more first conductive structures disposed within the one or more first dielectric layers to form a first portion of a first integrated circuit die having a first side opposite to the first substrate; inverting the first portion of the first integrated circuit die; forming a second dielectric layer on a second side of the first substrate; and performing a high-density plasma (HDP) chemical vapor deposition (CVD) operation to form a third dielectric layer on the second dielectric layer. The CVD operation employs a combination of silane (SiO₄) and oxygen (O₂) gases, performed at a temperature of approximately 300 degrees Celsius. At least one fourth dielectric layer is formed on the third dielectric layer, the at least one fourth dielectric layer comprising a second side of the first integrated circuit die. A second conductive structure is formed in each of the at least one fourth dielectric layer, the third dielectric layer, the second dielectric layer, the first substrate, and at least one of one or more first dielectric layers, the second conductive structure extending from the second side of the first integrated circuit die to at least one of the one or more first conductive structures. The first integrated circuit die is inverted. On the first side of the second substrate of the second integrated circuit die, one or more third conductive structures are formed in one or more fifth dielectric layers disposed on the second substrate, the one or more third conductive junctions... At least one of the structures extends to a first side of a second integrated circuit die opposite to a second substrate; a second side of a first integrated circuit die is bonded to a first side of a second integrated circuit die to electrically couple one or more third conductive structures to a second conductive structure; on a first side of a third substrate of a third integrated circuit die, one or more fourth conductive structures disposed on a third substrate are formed, at least one of the one or more sixth dielectric layers, at least one of the one or more fourth conductive structures extending to a first side of a third integrated circuit die opposite to a third substrate; the third integrated circuit die is reversed; and a first side of a third integrated circuit die is bonded to a first side of a first integrated circuit die to electrically couple at least one of the one or more fourth conductive structures to at least one of the one or more first conductive structures. In some embodiments, a photosensitive region is formed in the third substrate; a gate structure is formed on the first side of the third substrate near the photosensitive region, wherein at least one of the one or more fourth conductive structures is formed to be electrically connected to the gate structure. In some embodiments, an optical filter layer is formed on the first side of the third substrate; a lens structure is formed on the optical filter layer. In some embodiments, a portion of the third substrate is removed through a second side of the third substrate to form a trench extending to one of the one or more fourth conductive structures; an upper bonding structure electrically coupled to one of the one or more fourth conductive structures is conventionally formed in the trench.

[0083] In other embodiments, this disclosure relates to an integrated circuit device. The integrated circuit device includes a first integrated circuit die comprising: a first substrate; one or more first dielectric layers disposed on an upper side of the first substrate; one or more first conductive structures disposed in the one or more first dielectric layers; a second dielectric layer disposed on a lower side of the first substrate; a third dielectric layer disposed on a lower side of the second dielectric layer, the third dielectric layer having a nitrogen concentration less than five percent of the nitrogen concentration of at least one of the one or more first dielectric layers; at least one fourth dielectric layer disposed on a lower side of the third dielectric layer, the at least one fourth dielectric layer comprising a lower side of the first integrated circuit die; and a second conductive structure extending upward from the lower side of the first integrated circuit die through the first substrate to at least one of the one or more first conductive structures; and a second integrated circuit die comprising: a second substrate; one or more fifth dielectric layers disposed on an upper side of the second substrate; and one or more third conductive structures disposed in the one or more fifth dielectric layers, wherein at least one of the one or more third conductive structures is electrically coupled to a second conductive structure on an upper side of the second integrated circuit die. In some embodiments, the third dielectric layer comprises a high-density plasma oxide formed using a high-density plasma chemical vapor deposition (HDCVD) operation using a combination of silane gas and oxygen. In some embodiments, the HDCVD operation is performed at a temperature of approximately 300 degrees Celsius. In some embodiments, the second dielectric layer comprises a high-dielectric-constant dielectric material. In some embodiments, the second conductive structure comprises: a conductive through-substrate via extending upward through the first substrate to at least one of the one or more first conductive structures; and a first conductive bonding structure disposed at the lower end of the conductive through-substrate via and extending downward to the lower side of the first integrated circuit die. In some embodiments, at least one of the one or more first conductive structures includes a conductive element having an electrical coupling to the lower side of the upper end of the conductive through-substrate via. In some embodiments, at least one of the one or more third conductive structures further includes a second conductive bonding structure on the upper side of the second integrated circuit die; and the second conductive bonding structure is electrically coupled to the first conductive bonding structure. In some embodiments, a third integrated circuit die includes: a third substrate; one or more sixth dielectric layers disposed on the underside of the third substrate; and one or more fourth conductive structures disposed in the one or more sixth dielectric layers, wherein at least one of the one or more fourth conductive structures is electrically coupled to at least one of the one or more first conductive structures.In some embodiments, at least one of the one or more first conductive structures includes a first conductive bonding structure on the upper side of the first integrated circuit die; at least one of the one or more fourth conductive structures includes a second conductive bonding structure on the lower side of the third integrated circuit die; the second conductive bonding structure is electrically coupled to the first conductive bonding structure. In some embodiments, the third substrate includes a photosensitive region; at least one of the one or more fourth conductive structures is electrically coupled to a gate structure disposed on the third substrate near the photosensitive region.

[0084] It should be understood that in this written description and the claims below, the terms "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish different elements of a figure or series of figures. These terms themselves do not imply any temporal order or structural proximity of these elements, nor are they intended to describe corresponding elements in different illustrative embodiments and / or unillustrative embodiments. For example, "first dielectric layer" described in relation to a first figure does not necessarily correspond to "first dielectric layer" described in relation to another figure, nor does it necessarily correspond to "first dielectric layer" in unillustrative embodiments.

[0085] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other programs and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0086] 100: Integrated Circuit Imaging Device 101, 102, 103: Integrated circuit chips 104A, 104B: Joint area 110A, 110B, 110C: Substrate / Semiconductor Substrate 111: Dielectric isolation structure 112A, 117, 126A, 126B, 126C, 138, 150, 152, 154: Dielectric layers 114: Photosensitive area 116: Optical isolation structure 118: Reflection segment 120: Filter element 122: Lens 124: Upper joint structure 128: Gate Structure 129: Source-Drain Region 130: Conductive structure 132: Conductive bonding structure / bonding structure 133: Connecting through-hole element 134: Connecting element 136,210: Etching stop layer 140: Well Area 141: Through-substrate via structure / TSV structure 142: Shallow trench isolation structure / STI structure 200: Area 202: Nitrogen molecules or ions 404, 406, 408, 410: Trench 502, 504, 506, 508, 510, 512, 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624: Actions D1, D2, D3, D4: Thickness

Claims

1. A method for manufacturing an integrated circuit device, comprising: On a first substrate having one or more first dielectric layers disposed on a first side of a first substrate, a second dielectric layer is formed on a second side of the first substrate opposite to the first side of the first substrate, wherein one or more first conductive structures are disposed in the one or more first dielectric layers, and the one or more first dielectric layers encompass the first side of the first integrated circuit die; a high-density plasma chemical vapor deposition (PDCVD) operation is performed to form a third dielectric layer on the second dielectric layer, the PDCVD operation employing a combination of silane gas and oxygen; at least one fourth dielectric layer is formed on the third dielectric layer, the at least one fourth dielectric layer encompassing the second side of the first integrated circuit die opposite to the first side of the first integrated circuit die; a second conductive structure is formed in each of the at least one fourth dielectric layer, the third dielectric layer, the second dielectric layer, the first substrate, and at least one of the one or more first dielectric layers, the second conductive structure extending from the second side of the first integrated circuit die to at least one of the one or more first conductive structures; On a first side of the second substrate of the second integrated circuit die, one or more third conductive structures are formed in one or more fifth dielectric layers disposed on the second substrate; and the first integrated circuit die is bonded to the second integrated circuit die to electrically couple the one or more third conductive structures to the second conductive structure.

2. The method of claim 1, wherein the second conductive structure comprises: a conductive through-substrate via structure extending through the first substrate to at least one of the one or more first conductive structures; and a first conductive bonding structure disposed on the conductive through-substrate via structure and extending to the second side of the first integrated circuit die.

3. A method of manufacturing an integrated circuit device, comprising: forming one or more first dielectric layers and one or more first conductive structures disposed in the one or more first dielectric layers on a first side of a first substrate to form a first portion of a first integrated circuit die opposite to the first side of the first substrate; reversing the first portion of the first integrated circuit die; forming a second dielectric layer on a second side of the first substrate; performing a high-density plasma chemical vapor deposition (PDCVD) operation to form a third dielectric layer on the second dielectric layer, the PDCVD operation employing a combination of silane gas and oxygen at a temperature of about 300 degrees Celsius; forming at least one fourth dielectric layer on the third dielectric layer, the at least one fourth dielectric layer including a second side of the first integrated circuit die; forming a second conductive structure in each of the at least one fourth dielectric layer, the third dielectric layer, the second dielectric layer, the first substrate, and at least one of the one or more first dielectric layers, the second conductive structure extending from the second side of the first integrated circuit die to at least one of the one or more first conductive structures; and reversing the first integrated circuit die. On a first side of a second substrate of a second integrated circuit die, one or more third conductive structures are formed in one or more fifth dielectric layers disposed on the second substrate, at least one of the one or more third conductive structures extending to the first side of the second integrated circuit die opposite to the second substrate; the second side of the first integrated circuit die is joined to the first side of the second integrated circuit die to electrically couple the one or more third conductive structures to the second conductive structure; on a first side of a third substrate of a third integrated circuit die, one or more fourth conductive structures are formed in one or more sixth dielectric layers disposed on the third substrate, at least one of the one or more fourth conductive structures extending to the first side of the third integrated circuit die opposite to the third substrate; the third integrated circuit die is reversed; and the first side of the third integrated circuit die is joined to the first side of the first integrated circuit die to electrically couple at least one of the one or more fourth conductive structures to at least one of the one or more first conductive structures.

4. The method as described in claim 3, further comprising: A photosensitive area is formed in the third substrate; A gate structure is formed on the first side of the third substrate near the photosensitive area, wherein at least one of the one or more fourth conductive structures is formed to be electrically connected to the gate structure.

5. The method as described in claim 3, further comprising: An optical filter layer is formed on the first side of the third substrate; And a lens structure is formed on the optical filter layer.

6. The method as described in claim 3, further comprising: A portion of the third substrate is removed through a second side of the third substrate to form a trench extending into one of the one or more fourth conductive structures; And an upper bonding structure that is electrically coupled to one of the one or more fourth conductive structures is formed in the trench.

7. An integrated circuit device, comprising: A first integrated circuit die includes: a first substrate; one or more first dielectric layers disposed on an upper side of the first substrate; one or more first conductive structures disposed in the one or more first dielectric layers; a second dielectric layer disposed on a lower side of the first substrate; a third dielectric layer disposed on a lower side of the second dielectric layer, the third dielectric layer having a nitrogen concentration less than five percent of the nitrogen concentration of at least one of the one or more first dielectric layers; at least one fourth dielectric layer disposed on a lower side of the third dielectric layer, the at least one fourth dielectric layer including a lower side of the first integrated circuit die; and a second conductive structure extending upward from the lower side of the first integrated circuit die through the first substrate to at least one of the one or more first conductive structures; and a second integrated circuit die includes: a second substrate; one or more fifth dielectric layers disposed on an upper side of the second substrate; and one or more third conductive structures disposed in the one or more fifth dielectric layers, wherein at least one of the one or more third conductive structures is electrically coupled to the second conductive structure on an upper side of the second integrated circuit die.

8. The integrated circuit arrangement as claimed in claim 7, wherein the second conductive structure comprises: The conductive through-substrate via structure extends upward through the first substrate to at least one of the one or more first conductive structures; The first conductive bonding structure is disposed at the lower end of the conductive through-substrate via structure and extends downward to the lower side of the first integrated circuit die.

9. The integrated circuit device as claimed in claim 7, further comprising a third integrated circuit die, including: Third base; One or more sixth dielectric layers are disposed on the underside of the third substrate; And one or more fourth conductive structures are disposed in one or more sixth dielectric layers, wherein at least one of the one or more fourth conductive structures is electrically coupled to at least one of the one or more first conductive structures.

10. The integrated circuit arrangement as claimed in claim 9, wherein: The third substrate includes a photosensitive region; and at least one of the one or more fourth conductive structures is electrically coupled to a gate structure disposed on the third substrate near the photosensitive region.

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