Imaging integrated circuit device and method of fabricating the same

Abstract

An integrated circuit (IC) device includes a substrate having a plurality of first photosensitive regions and a plurality of second photosensitive regions. Each of a plurality of first photosensitive region groups includes one or more first photosensitive regions and is associated with one of a plurality of image pixels, and each second photosensitive region group includes one or more second photosensitive regions and is associated with one of a plurality of phase detection pixels. The IC device also includes an isolation structure extending toward a first side of the substrate from a second side of the substrate. The isolation structure circumscribes each of the first photosensitive regions in a plan view of the IC device. The isolation structure includes a first configuration for each image pixel and a second configuration different from the first configuration for each phase detection pixel in the plan view.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit device and a method for manufacturing the same, and more specifically, to an image integrated circuit device and a method for manufacturing the same. Prior Technology

[0002] Some integrated circuit (IC) manufacturers have integrated various aspects of phase detection autofocus (PDAF) technology into complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) devices. In such devices, the speed associated with PDAF technology can be higher than that associated with other autofocus technologies because the device can continuously provide the phase detection data required for autofocus while simultaneously acquiring image data with very little delay. Summary of the Invention

[0003] According to some embodiments, an integrated circuit device includes a substrate, an isolation structure extending at least partially from a second side of the substrate toward a first side of the substrate, and a mesh structure disposed above the first side of the substrate. The substrate includes a plurality of first photosensitive areas and a plurality of second photosensitive areas. Each of the plurality of groups of first photosensitive areas includes one or more corresponding first photosensitive areas, and each of the plurality of groups of first photosensitive areas is associated with a corresponding one of a plurality of image pixels. Each of the plurality of groups of second photosensitive areas includes one or more corresponding second photosensitive areas, and each of the plurality of groups of second photosensitive areas is associated with a plurality of image pixels. The phase-detection pixels are associated with a corresponding one. In the plan view of the integrated circuit device, the isolation structure is tangent to each of the plurality of first photosensitive areas, and the isolation structure includes a first configuration for each of the plurality of image pixels and a second configuration for each of the plurality of phase-detection pixels, the second configuration being different from the first configuration. The mesh structure is tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups. The mesh structure includes a plurality of masking members, each of the plurality of masking members being disposed above a portion of a corresponding one of the plurality of second photosensitive area groups.

[0004] According to some embodiments, a method of manufacturing an integrated circuit device includes: forming a plurality of first photosensitive regions and a plurality of second photosensitive regions in a substrate, each of a plurality of first photosensitive region groups including one or more corresponding first photosensitive regions, and each of a plurality of second photosensitive region groups including one or more corresponding second photosensitive regions; forming at least one dielectric layer on a first side of the substrate, the at least one dielectric layer including at least one conductive structure electrically coupled to the first side of the substrate; removing a portion of the substrate to form at least one trench, the at least one trench extending at least partially from a second side of the substrate toward the first side of the substrate; and filling the at least one trench with at least one dielectric material to form an isolation junction. In the plan view of the integrated circuit device, the isolation structure is tangent to each of the plurality of first photosensitive areas. In the plan view of the integrated circuit device, the isolation structure includes a first configuration within each of the plurality of first photosensitive area groups and a second configuration for each of the plurality of second photosensitive area groups, the second configuration being different from the first configuration; and a mesh structure is formed above the second side of the substrate, the mesh structure being tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups, the mesh structure including a plurality of blocking members, each of the plurality of blocking members being disposed above a portion of a corresponding one of the plurality of second photosensitive area groups.

[0005] According to some embodiments, a method of manufacturing an integrated circuit device includes: forming a plurality of first photosensitive areas and a plurality of second photosensitive areas in a substrate, each of a plurality of groups of first photosensitive areas including one or more corresponding first photosensitive areas, and a plurality of groups of second photosensitive areas including one or more corresponding second photosensitive areas; etching the substrate to form at least one trench, the at least one trench extending at least partially from a second side of the substrate toward a first side of the substrate; filling the at least one trench with at least one dielectric material to form an isolation structure; forming a mesh structure above the second side of the substrate, the mesh structure including a plurality of shielding members, each of the plurality of shielding members disposed above a portion of a corresponding one of the plurality of groups of second photosensitive areas; and forming an optical lens layer above the substrate, the optical lens layer including a plurality of lens portions and a plurality of additional lens portions, each of the plurality of lens portions disposed above a corresponding one of the plurality of groups of first photosensitive areas, and at least two of the plurality of additional lens portions disposed above a corresponding one of the plurality of groups of second photosensitive areas. Simple Explanation of the Diagram

[0006] The best understanding of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1A through 1D show plan views, cross-sectional views, alternative cross-sectional views, and additional cross-sectional views of some embodiments of an integrated circuit (IC) device employing an isolation structure to reduce crosstalk of a partially shielded PDAF, according to the present disclosure. Figures 2 through 12 show plan views of some additional embodiments of an IC device employing an isolation structure to provide reduced crosstalk for a partially shielded PDAF according to this disclosure. Figures 13A through 13C show plan views, cross-sectional views, and alternative cross-sectional views of some embodiments of an IC device employing an optical lens layer to provide reduced crosstalk for a partially obscured PDAF, according to the present disclosure. Figure 13D shows a cross-sectional view of some embodiments of an IC device employing an isolation structure and optical lens layer to reduce crosstalk of a partially obscured PDAF, according to this disclosure. Figures 14 to 16 show plan views of some additional embodiments of an IC device employing an optical lens layer to provide reduced crosstalk for a partially obscured PDAF according to this disclosure. Figures 17A to 17L show cross-sectional views of some embodiments of the manufacturing process of an IC device according to this disclosure, which employs an isolation structure to provide reduced crosstalk for a partially shielded PDAF, as shown in Figure 1C. Figure 18 shows a flowchart of some embodiments of a method for forming an IC device according to the present disclosure, wherein the IC device employs an isolation structure that provides reduced crosstalk for a partially shielded PDAF. Figures 19A and 19B show cross-sectional views of some embodiments of the manufacturing process of an IC device according to this disclosure, which employs an optical lens layer to provide reduced crosstalk for a partially obscured PDAF, as shown in Figure 13C. Figure 20 shows a flowchart of some embodiments of a method for forming an IC device according to the present disclosure, wherein the IC device employs an optical lens layer that provides reduced crosstalk for a partially obscured PDAF. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. Devices may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly. In some embodiments, the terms "about" and / or "approximately" may be interpreted as + / - 10% or + / - 5%, while in other embodiments, the terms "about" and / or "approximately" may be interpreted as within the normal manufacturing tolerances of a given wafer fab manufacturing process.

[0009] In some cases, phase detection autofocus (PDAF) functionality can be integrated into a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) integrated circuit (IC) device using a half-shield phase detection (HSPD) pixel design. In such a design, some pixel positions in the image pixel array are occupied by special-purpose phase detection pixels, which include "half-occluders" positioned over a portion of the associated pixel (e.g., the left, right, lower, or upper half), effectively blocking half of the light from one or more photodetectors associated with that pixel. Processing data from such phase detection pixels can generate indications (e.g., amplitude and direction) that can be used to adjust the relative distance between an external lens (e.g., a camera lens) and the CIS IC device to focus an object onto the CIS IC device. In some cases, the HSPD pixel arrangement can serve as the primary phase detection mechanism for a CIS IC device, while in other examples, the HSPD pixel arrangement can be used during periods when another phase detection mechanism (such as a quadrature phase detection (QPD) PDAF circuit using image pixels) is unavailable (e.g., during QPD quad-cell (4C) merging).

[0010] However, in some HSPD designs, a portion of the light encountering an HSPD pixel may be misdirected to adjacent image pixels, for example, by one or more isolation structures (e.g., backside deep trench isolation, BDTI) surrounding each of the multiple photosensitive regions of a phase-detection pixel. More specifically, the bottom side or bottom surface of such an isolation structure may cause light scattering, redirecting the received light to adjacent image pixels, potentially increasing the amount of light detected by the image pixel beyond what is actually relevant to that pixel.

[0011] In some cases, this crosstalk between HSPD pixels and image pixels can be optimized using an overlay mesh structure (e.g., a metal grid (MG) structure) in which the width of each segment has a critical dimension (CD). This critical dimension allows the HSPD pixels and image pixels to maintain the same sensitivity when the isolation structure causes scattering, as described above. However, this sensitivity balance may lead to a shift in the spectral response or quantum efficiency (QE) (e.g., the portion of photon flux that may contribute to the photocurrent associated with the pixel) relative to the wavelength of light received by the HSPD pixel relative to the image pixel. Therefore, the combination of the isolation structure and the mesh structure may result in a decrease in QE at lower wavelengths (e.g., due to the CD of the width of each segment of the mesh structure) and an increase in QE at higher wavelengths (e.g., due to BDTI light scattering).

[0012] To address these issues, this disclosure provides embodiments of an IC device that employs either or both of an isolation structure and / or an optical lens layer to reduce light scattering from the HSPD pixel to adjacent image pixels. In some embodiments, the isolation structure, while surrounding each photosensitive area of ​​an image pixel, may have a different (e.g., reduced) structure in one or more phase-detection pixels. For example, in some embodiments, the configuration of the isolation structure in the phase-detection pixels may differ from its configuration in the image pixels in a plan view of the IC device. In other embodiments, the optical lens layer may include a lens portion (e.g., a spherical lens portion) located above each group of photosensitive areas associated with an image pixel and may also include at least two lens portions (e.g., multiple elliptical lens portions, or multiple spherical lens portions smaller than the lens portions associated with the image pixel) located above each group of photosensitive areas associated with an HSPD pixel. Using such an isolation structure and / or optical lens layer reduces the amount of light redirected from the HSPD pixel to adjacent image pixels. Therefore, potential problems caused by this crosstalk can be mitigated, such as undesirable flares related to image pixels and QE shift within HSPD pixels due to uneven light sensitivity between image pixels and HSPD pixels.

[0013] Figures 1A through 1D illustrate plan views, cross-sectional views, alternative cross-sectional views, and additional cross-sectional views of some embodiments of an integrated circuit (IC) device 100A employing an isolation structure 140 to reduce crosstalk of partially obscured PDAF, according to this disclosure. More specifically, Figure 1A (including lines 1B-1B and 1D-1D) is a plan view of the IC device 100A corresponding to the cross-sectional view of Figure 1B, where the layers of components of the IC device 100A associated with each pixel in Figure 1B are vertically stacked. However, in other embodiments, these same components may be laterally tilted between layers, as shown in the cross-sectional view of Figure 1C. For example, in some embodiments, the chief ray angle (CRA) associated with each pixel may vary depending on the pixel position within the pixel array in the IC device 100A. More specifically, pixels located at or near the center of the array may have a chief ray angle of approximately zero degrees, resulting in the pixel components being substantially vertically stacked, as shown in Figures 1A and 1B. Conversely, pixels near the edges or corners of the array may have significant principal ray angles, requiring the components of these pixels to be tilted toward the center of the array, as shown in Figure 1C. In some examples, this component misalignment can exacerbate potential crosstalk between phase-detection pixels and image pixels. While the various embodiments shown in Figures 2 through 12, 13A and 13B, and 14 through 16 depict the case of vertical alignment, the same embodiments discussed below are also applicable to tilted cases (e.g., the cases shown in Figures 13C, 13D, 17A through 17L, and 19A and 19B).

[0014] As shown in the cross-sectional views of Figures 1B, 1C, and 1D, the substrate 102 may include a plurality of photosensitive regions 104 (e.g., photodiodes or the like) forming photodetectors (PDs). The photosensitive regions 104 may be formed (e.g., doped or implanted) in the substrate 102. In some embodiments, as shown in Figures 1A through 1D, each pixel includes four photosensitive regions 104. However, in other embodiments, one or more photosensitive regions 104 may be used in each pixel.

[0015] In some embodiments, one or more photosensitive areas 104 may be arranged to form corresponding photosensitive area groups. Furthermore, each photosensitive area group may be associated with a phase-detection (e.g., HSPD) pixel 120A or an image pixel 122. In the embodiments shown in Figures 1A to 1D and other figures discussed below, each phase-detection pixel 120A and image pixel 122 may be associated with a photosensitive area group comprising four photosensitive areas 104 (e.g., arranged in a 2x2 configuration). As shown in Figure 1A, the image pixels 122 may be arranged in a specific pattern (e.g., arranged in a larger 2x2 configuration) to facilitate accurate color imaging. Furthermore, the phase-detection pixels 120A may be periodically distributed within the image pixels 122. In some embodiments, the phase-detection pixels 120A may be arranged in pairs. For example, the first phase-detection pixel 120A may correspond to a half-shield (HS) 130, which covers a first pair (e.g., the left or lower half) of the photosensitive area 104 associated with the first phase-detection pixel 120A (as shown in FIG. 1A). Furthermore, the second phase-detection pixel 120A may correspond to the half-shield 130, which covers a second pair (e.g., the right or upper half) of the photosensitive area 104 associated with the second phase-detection pixel 120A. However, image pixels 122 and phase-detection pixels 120A may also have other arrangements besides those shown in FIG. 1A.

[0016] The circuit dielectric layer 112 may be adjacent to the substrate 102 (e.g., on the first side of the substrate 102), and the circuit dielectric layer 112 includes a conductive structure 114 (e.g., a metal (copper (Cu)), alloy or other conductive material) to form a sensing circuit coupled to the photosensitive area 104 of the substrate 102 (e.g., transmitting the charge generated by photons hitting the photosensitive area 104, resetting the associated photodetector, etc.). The circuit dielectric layer 112 may include one or more dielectric materials, including but not limited to silicon oxide (SiOx) (e.g., silicon oxide (SiO2)), silicon nitride (SiN), silicate carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, etc. In some embodiments, additional layers (e.g., additional substrates, circuit dielectric layers, and / or the like) may be disposed below the circuit dielectric layer 112, but for the sake of simplicity in the following discussion, such layers will not be discussed further herein.

[0017] As shown in Figures 1A to 1D, an isolation structure 140 may be disposed within a substrate 102. In some embodiments, the isolation structure 140 includes a portion (e.g., a wall) extending at least partially from a second side of the substrate 102 toward a first side of the substrate 102. In some embodiments, the isolation structure 140 is configured to laterally isolate each photosensitive area 104 in each image pixel 122 from adjacent other photosensitive areas 104 (e.g., in a plan view), as shown in the plan view of Figure 1A.

[0018] Additionally, in some embodiments, in the plan view of the IC device 100A, the configuration of the isolation structure 140 in each of the one or more phase detection pixels 120A differs from its configuration in each of the image pixels 122. An example of this configuration is that there are no walls of the isolation structure 140 in the photosensitive area group of the phase detection pixels 120A. In some embodiments, this configuration of the isolation structure 140 of the phase detection pixels 120A represents a distinguishing feature between the various embodiments of Figures 1A to 1D and Figures 2 to 12, as described in detail below.

[0019] In some embodiments, as shown in Figures 1A to 1D, the isolation structure 140 may include a first (e.g., outer) dielectric layer 144 and a second (e.g., inner) dielectric layer 142. In some embodiments, the first dielectric layer 144 may include, but is not limited to, alumina silicon oxide (SiOAl), alumina (AlO), hafnium oxide (HfO), silicon tantalum oxide (TaOSi), doped polycrystalline silicon, another dielectric material, and / or the like. Furthermore, in some embodiments, the second dielectric layer 142 may include, but is not limited to, silicon oxide (SiOx) (e.g., silicon dioxide (SiO2)), another dielectric material, and / or the like. Additionally, in some embodiments, an additional air gap layer may be disposed in the second dielectric layer 142. For example, in some embodiments, both the first dielectric layer 144 and the second dielectric layer 142 may be conformally deposited on the substrate 102 and deposited in one or more trenches of the substrate 102, thereby leaving an air gap defined by the second dielectric layer 142 within one or more trenches. In some embodiments, a subsequent dielectric layer (e.g., at least a portion of the sensor dielectric layer 106) may cover the upper end of the air gap.

[0020] In other embodiments, the isolation structure 140 may employ different materials and numbers of layers. Furthermore, in some embodiments, the isolation structure 140 may be designed as a back-side deep trench isolation (BDTI) structure, as shown in Figures 1B to 1D. Additionally, in some embodiments (not explicitly shown in Figures 1B to 1D), such a BDTI structure may be complementary to a front-side DTI (FDTI) structure extending from a first (e.g., lower) side of the substrate 102 and toward the lower end of the BDTI structure.

[0021] In some embodiments, a sensor dielectric layer 106 may be disposed on a substrate 102. In some embodiments, the sensor dielectric layer 106 may include one or more dielectric materials, such as those listed above with the circuit dielectric layer 112 or the isolation structure 140. For example, the sensor dielectric layer 106 may include a first dielectric layer 144 and a second dielectric layer 142 (e.g., discussed above in conjunction with the isolation structure 140), or in other embodiments, it may include one or more other dielectric materials (e.g., materials contained in the circuit dielectric layer 112). In some embodiments, the sensor dielectric layer 106 may extend continuously from the substrate 102 as part of the isolation structure 140 within a trench within the substrate 102. Furthermore, in some embodiments, the sensor dielectric layer 106 may include or serve as a passivation layer and / or an anti-reflective coating. For example, the first dielectric layer 144 may serve as an anti-reflective coating, while the second dielectric layer 142 may serve as a passivation layer.

[0022] Referring again to Figures 1A through 1D, a mesh structure 132 may be disposed on the sensor dielectric layer 106. In some embodiments, the mesh structure 132 may include a plurality of mesh segments 133 extending laterally onto the sensor dielectric layer 106. Additionally, in some embodiments, the mesh structure 132 may be tangent to the photosensitive area groups of the phase detection pixels 120A and the image pixels 122, as best shown in Figure 1A. Therefore, the mesh structure 132 may be provided with openings 131 through which light can be received by the photosensitive area 104 of each phase detection pixel 120A and the image pixel 122. In some embodiments, the mesh structure 132 may include, but is not limited to, metallic materials (e.g., tungsten (W)) or other conductive materials (e.g., titanium nitride (TiN), which may be used as a barrier layer), dielectric materials (e.g., silicon oxide (SiOx)), etc. Furthermore, in some embodiments, the mesh structure 132 may be covered or sealed with the same or similar material as the sensor dielectric layer 106 (e.g., silicon dioxide (SiO2)). In some embodiments, the mesh structure 132 may be a material that substantially reflects light.

[0023] In some embodiments, the semi-occluder 130 may also be disposed above the sensor dielectric layer 106 in each phase detection pixel 120A (e.g., aligned with the mesh structure 132 in the cross-sectional view of FIG. 1D), as described above. In some embodiments, the semi-occluder 130 may cover approximately half, slightly less than half, or slightly more than half of the phase detection pixel 120A, thus covering approximately half (e.g., two) of the photosensitive area 104 of the phase detection pixel 120A for phase detection. While FIG. 1A shows the semi-occluder 130 covering the left half of the phase detection pixel 120A, in other embodiments, the semi-occluder 130 may cover the right half, the lower half, or the upper half. In some embodiments, the semi-occluder 130 may be adjacent to at least some of the mesh segments 133 of the mesh structure 132. Additionally, in some embodiments, the semi-occluder 130 may comprise the same material as the mesh structure 132, as described above, or may comprise other materials such as conductive or dielectric materials.

[0024] In some embodiments, a filter element 134 may be disposed above the photosensitive area 104 of each image pixel 122 (e.g., on the sensor dielectric layer 106). More specifically, each filter element 134 may be an element that allows light of a specific bandwidth (e.g., color) to pass through the photosensitive area 104 below, while blocking light of other bandwidths. In some embodiments, the bandwidth or color passed may be red, blue, or green. More specifically, the image pixels 122 may typically be arranged in a 2x2 array with one red, one blue, and two green filter elements 134. Furthermore, in some embodiments, a filter element 134 may not be disposed above each phase detection pixel 120A (e.g., as shown in Figures 1B to 1D), or a transparent filter element 134 may be disposed above each phase detection pixel 120A, such as an element that allows most light frequencies to pass through, an element that allows radiation with wavelengths between about 380 nanometers (nm) and about 780 nm to pass through, etc. In some embodiments, each filter element 134 may include, but is not limited to, pigment material, dye material or the like disposed on the sensor dielectric layer 106.

[0025] Furthermore, as shown in Figures 1B to 1D, an optical lens layer 110 (e.g., comprising multiple lens portions 111, such as microlenses) may be disposed above the filter element 134 and the sensor dielectric layer 106. More specifically, in some embodiments, the optical lens layer 110 may be disposed on the filter element 134 of each image pixel 122 and may further extend toward the substrate 102 onto the sensor dielectric layer 106 corresponding to each phase detection pixel 120A. Additionally, in some embodiments, each lens portion 111 may be disposed above the photosensitive area 104 of the corresponding image pixel 122 or phase detection pixel 120A. In some embodiments, the optical lens layer 110 may include, but is not limited to, silicon dioxide (SiO2) or silicon-based glass, another type of glass, another substantially transparent material, or the like. Furthermore, while each lens portion 111 of the optical lens layer 110 is presented as a microlens in Figures 1B to 1D, other types of lenses (e.g., Fresnel lenses) may be used in other embodiments, but are not specifically discussed herein.

[0026] Furthermore, in some embodiments, an anti-reflective coating (ARC) 113 may be disposed above the optical lens layer 110. In some embodiments, the ARC 113 may be manufactured using titanium nitride (TiN), silicon nitride (SiN), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), and / or other anti-reflective materials that allow light to pass through.

[0027] As shown in Figure 1C, in some embodiments, light rays 152 passing through the ARC 113 of the phase detection pixel 120A, the optical lens layer 110, and the sensor dielectric layer 106 may not hit the walls or other elements of the isolation structure 140 before being absorbed by the photosensitive area 104, thereby reducing the likelihood that at least some light rays 152 will be redirected to adjacent image pixels 122.

[0028] As described above, the embodiments of Figures 1A to 1D include an isolation structure 140 that provides a reduced or modified configuration for a group of photosensitive areas of one or more phase-detection pixels 120A. In some embodiments, the modified structure, in a plan view of the IC device 100A, has no walls or other elements of the isolation structure 140 within the grid structure 132. Similarly, Figures 2 to 12 show plan views of some additional embodiments of an IC device employing an isolation structure 140 to provide reduced crosstalk for a partially occluded PDAF according to this disclosure. Other portions of the IC device shown in Figures 2 to 12 may have the same or similar structures or elements as described above in conjunction with the IC device 100A of Figures 1A to 1D.

[0029] For example, Figure 2 depicts an IC device 100B having a group of photosensitive areas of phase-detecting pixels 120B, wherein an isolation structure 140 includes a single wall 252 spanning the group of photosensitive areas, the single wall 252 separating at least one photosensitive area 104 from another photosensitive area 104 in the group of photosensitive areas. More specifically, the single wall 252 may extend across the central region of the phase-detecting pixels 120B (e.g., below and along the edge of the semi-occluder 130). In some embodiments, the single wall 252 may be spaced substantially equal distances from the opposite sides of the phase-detecting pixels 120B.

[0030] Similarly, FIG3 depicts an IC device 100C having a group of photosensitive areas of phase detection pixels 120C, wherein the isolation structure 140 includes a single linear wall 352 spanning the group of photosensitive areas, the single linear wall 352 separating at least one photosensitive area 104 from another photosensitive area 104 in the group of photosensitive areas. More specifically, in the plan view of FIG3, the single linear wall 352 may extend across the central region of the semi-obscured member 130. In such embodiments, the width of one or more photosensitive areas 104 may be increased or decreased (as shown in FIG3) such that the single linear wall 352 may not intersect with the photosensitive areas 104 of the group of photosensitive areas. In some embodiments, the distance between the single wall 252 and a first side of the phase detection pixel 120C may be greater than the distance between the single wall 252 and the opposite second side of the phase detection pixel 120C.

[0031] Figure 4 depicts an IC device 100D with a group of photosensitive areas having phase-detection pixels 120D, wherein the isolation structure 140 includes intersecting first and second linear walls 452. More specifically, the first linear wall 452 crosses the group of photosensitive areas in a first lateral direction in a plan view of the IC device 100D, and the second linear wall 452 crosses the group of photosensitive areas in a second lateral direction perpendicular to the first lateral direction in a plan view of the IC device 100D. In some embodiments, the first and second linear walls 452 may intersect in a quadrant region (e.g., the lower left region in the example of Figure 4) in a plan view of the IC device 100D. Additionally, in some embodiments, the quadrant region where the first and second linear walls 452 intersect may be located below the semi-obscuring member 130, as shown in Figure 4. Furthermore, in some embodiments, the width of one or more photosensitive areas 104 may be increased or decreased (as shown in Figure 3) such that the first and second linear walls 452 may not intersect with the photosensitive areas 104 of the group of photosensitive areas.

[0032] Figure 5 depicts an IC device 100E with a group of photosensitive areas having phase-detection pixels 120E, wherein the isolation structure 140 includes intersecting first linear walls 552A and second linear walls 552B. More specifically, the first linear wall 552A spans the group of photosensitive areas in a first lateral direction in a plan view of the IC device 100E, and the second linear wall 552B extends from the first linear wall 552A in a second lateral direction perpendicular to the first lateral direction in a plan view of the IC device 100E to the periphery of the group of photosensitive areas. In some embodiments, the first linear wall 552A and the second linear wall 552B may separate two of the photosensitive areas 104 of the group of photosensitive areas from each other and separate the other photosensitive areas 104 of the group of photosensitive areas from each other in a plan view of the IC device 100E. Additionally, in some embodiments (as shown in Figure 5), the first linear wall 552A and the second linear wall 552B may be completely disposed below the semi-obscuring member 130.

[0033] Figure 6 illustrates an IC device 100F with a group of photosensitive areas containing phase-detection pixels 120F. The isolation structure 140 includes four individual walls 652. In a plan view of the IC device 100F, each individual wall 652 extends from a corresponding wall of the isolation structure 140 at the periphery of the photosensitive area group toward the central region of the photosensitive area group. In some embodiments (as shown in Figure 6), three individual walls 652 may be completely disposed below the semi-occluder 130, and one individual wall 652 may be completely exposed by the semi-occluder 130. Additionally, in some embodiments, in a plan view of the IC device 100F, the length of each individual wall 652 may be the same as or different from the lengths of the other individual walls 652.

[0034] Although the plan views of the embodiments shown in Figures 1A to 1D and Figures 2 to 6 depict the left half of the semi-occluder 130, these same embodiments may also employ the right half of the semi-occluder 130, wherein each such embodiment may be presented as a left-right mirror or 180-degree rotated image as shown in Figures 1A to 1D and Figures 2 to 6. Such mirror or rotated image embodiments may be presented on the same IC device because the HSPD mechanism may employ multiple pairs of phase-detection pixels 120A to 120F, wherein each pair may include phase-detection pixels 120A to 120F with the left half of the semi-occluder 130 and phase-detection pixels 120A to 120F with the right half of the semi-occluder 130.

[0035] Furthermore, Figures 7 to 12 illustrate some embodiments related to Figures 1A to 1D and Figures 2 to 6, but with the upper half of the half-blocking member 130 replacing the left half. More specifically, the embodiments of Figures 7 (IC device 100G with phase detection pixels 120G), 8 (IC device 100H with phase detection pixels 120H), 9 (IC device 100I with phase detection pixels 120I), 10 (IC device 100J with phase detection pixels 120J), 11 (IC device 100K with phase detection pixels 120K), and 12 (IC device 100L with phase detection pixels 120L) correspond to the embodiments of Figures 1A to 1D, 2, 3, 4, 5, and 6, respectively. Furthermore, each portion of the isolation structure 140 associated with phase detection pixels 120G to 120L in Figures 7 to 12 is rotated 90 degrees clockwise relative to the portions in Figures 1A to 1D, 2, 3, 4, 5, and 6 to align with the semi-masking member 130 of the upper portion therein.

[0036] Furthermore, while the embodiments shown in Figures 7 through 12 use the upper half of the semi-occluder 130 in the provided plan view, the same embodiments may also employ the lower half of the semi-occluder 130, wherein each such embodiment may be presented as a vertically mirrored or 180-degree rotated image as shown in Figures 7 through 12. Such mirrored or rotated image embodiments may be presented on the same IC device because the HSPD mechanism may employ multiple pairs of phase-detecting pixels 120G to 120L, wherein each pair may include a phase-detecting pixel with the upper half of the semi-occluder 130 and a phase-detecting pixel with the lower half of the semi-occluder 130. Furthermore, in some embodiments, depending on the principal ray angle (CRA) of the respective phase-detecting pixels 120G to 120L, a mixture of upper and lower half semi-occluders 130 and left and right half semi-occluders 130 may be suitable (e.g., to minimize crosstalk caused by the associated phase-detecting pixels).

[0037] In addition to the various embodiments of Figures 1A to 1D and Figures 2 to 12 (where a reduced or modified portion of the isolation structure 140 is incorporated into phase detection pixels 120A to 120L), the portion of the optical lens layer 110 relative to the phase detection pixels can be modified to reduce crosstalk while maintaining an acceptable QE distribution. For example, Figures 13A (including lines 13B-13B) to 13C respectively show plan views, cross-sectional views, and alternative cross-sectional views of some embodiments of an IC device 100M employing an optical lens layer to provide reduced crosstalk for a partially obscured PDAF according to this disclosure. In some embodiments, in the cross-sectional view, the optical lens layer 110 may include a first curved surface disposed directly above image pixel 122 and a second curved surface disposed above phase detection pixel 120. The arc length of the first curved surface is greater than the arc length of the second curved surface. More specifically, while individual lens portions 111 of the optical lens layer 110 disposed above the corresponding image pixel 122 may remain spherical (as shown in Figures 1 to 12), each phase detection pixel 120 may be associated with two elliptical lens portions 111A. Furthermore, in some embodiments, each elliptical lens portion 111A may be disposed above a corresponding pair of photosensitive areas 104 of the phase detection pixel 120. Additionally, in some embodiments, each elliptical lens portion 111A may extend perpendicularly to the semi-obscured member 130, such that approximately half of each elliptical lens portion 111A is disposed above the left half of the semi-obscured member 130. Therefore, as shown in Figure 13C, light 152 may be guided by each elliptical lens portion 111A, such that reflections on the side of the substrate 102 adjacent to the circuit dielectric layer 112 can be guided in a manner that reduces or minimizes crosstalk with adjacent image pixels 122.

[0038] Figure 13D shows a cross-sectional view of some embodiments of an IC device 100N employing an isolation structure 140 and an optical lens layer 110 to reduce crosstalk of a partially obscured PDAF according to this disclosure. For example, the isolation structure 140 may be as shown in Figure 1C, wherein the walls of the isolation structure 140 are not located within the phase detection pixel 120, and the optical lens layer 110 may include a spherical lens portion 111 and an elliptical lens portion 111A. Furthermore, in some embodiments, any of the isolation structures 140 in Figures 1A to 1C and Figures 2 to 12 may be used in conjunction with the optical lens layers 110 in Figures 13A to 13C and Figures 14 to 16 of the same IC device.

[0039] While Figures 13A through 13D depict the use of the left half of the semi-obscuring member 130, Figure 14 shows a plan view of some additional embodiments of an IC device 100O employing an optical lens layer 110, wherein a pair of elliptical lens portions 111A are disposed above the upper half of the semi-obscuring member 130, with each elliptical lens portion 111A disposed above a corresponding pair of photosensitive areas 104. In some embodiments, in the plan view of Figure 14, the elliptical lens portions 111A are rotated 90 degrees clockwise relative to the portion shown in Figure 13A. Furthermore, in some embodiments, the elliptical lens portions 111A may be used in conjunction with the lower half of the semi-obscuring member 130; in some embodiments, both the upper and lower halves of the semi-obscuring member 130 may be used simultaneously in the IC device.

[0040] Figure 15 illustrates an embodiment of IC device 100P, wherein four spherical lens portions 111B are disposed above the corresponding photosensitive areas 104 of the phase detection pixel 120. In some embodiments, the diameter of each spherical lens portion 111B may be approximately half the diameter of each spherical lens portion 111 associated with the image pixel 122. Furthermore, in some embodiments, the phase detection pixel 120 may have two separate left-half semi-occluders 130 associated with it, with one left-half semi-occluder 130 associated with each pair of spherical lens portions 111B. Similarly, Figure 16 illustrates an embodiment of IC device 100Q, wherein two upper-half semi-occluders 130 and four spherical lens portions 111B are employed in a manner similar to that shown in Figure 15. Furthermore, in some embodiments, the spherical lens portions 111B may be used in conjunction with two lower-half semi-occluders 130; in some embodiments, both upper and lower semi-occluders 130 are used simultaneously in the IC device. In some embodiments, a combination of upper, lower, left and right half-blocking members 130 and associated spherical lens portions 111B may be used within the same IC device.

[0041] Figures 17A to 17L show cross-sectional views of various stages of the manufacture of an IC device according to this disclosure (IC device 100A as shown in Figure 1C), which employs an isolation structure (isolation structure 140 as shown in Figure 1C) to provide reduced crosstalk for a partially obscured PDAF. While Figures 17A to 17L are described as a series of actions, it should be understood that these actions are not limiting, as the order of actions in each series may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0042] For example, Figure 17A shows a substrate 102 (e.g., a semiconductor substrate, such as a silicon (Si) substrate or the like). In some embodiments, substrate 102 may serve as the substrate for a back-side portion of an IC device 100A, which includes a sensor dielectric layer 106, a mesh structure 132, and so on. Furthermore, substrate 102 may also serve as the substrate for a front-side portion of the IC device 100A, such as the circuit dielectric layer 112 and associated conductive structure 114 in Figure 1C.

[0043] Figure 17B illustrates a photosensitive region 104 formed (e.g., implanted, doped, or similar) on the front surface of substrate 102 to combine with the surrounding region of substrate 102 to form a corresponding photodetector (e.g., a PN photodiode, a PIN photodiode, or similar). In some embodiments, substrate 102 may be a p-type substrate and photosensitive region 104 may be an n-type doped region. In other embodiments, photosensitive region 104 may be combined with substrate 102 to form other types of photodetectors.

[0044] Figure 17C illustrates the formation (e.g., by iterative lithography, etching, and deposition) of one or more circuit dielectric layers 112, each comprising a plurality of conductive structures 114 to form a circuit electrically coupled to a photosensitive region 104. The conductive structures 114 may include, but are not limited to, metals (e.g., copper (Cu)), alloys, another conductive material, or the like. In some embodiments, the circuit dielectric layer 112 may include, but is not limited to, silicon oxide (SiOx) (such as silicon oxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, or the like, as described above.

[0045] Figure 17D shows the inversion (e.g., flipping) of the sub-component of Figure 17C to facilitate access to the back side of the substrate 102 opposite to the front side of the substrate 102, thereby enabling subsequent processing as described below with respect to Figures 17E to 17L.

[0046] Figure 17E illustrates a portion of the substrate 102 removed (e.g., by lithography and etching) to form a trench 1710, in which an isolation structure 140 will be formed. In some embodiments, the trench 1710 may extend substantially to the front side of the substrate 102. Furthermore, the trench 1710 may laterally surround each photosensitive area 104 of the photosensitive area group of each image pixel 122, while providing a reduced or modified configuration for the trench 1710 within the photosensitive area group associated with the phase detection pixel 120A (e.g., by omitting the trench 1710 associated with the phase detection pixel 120A), as described above.

[0047] Figure 17F illustrates a first dielectric layer 144 of an isolation structure 140 conformally formed (e.g., conformally deposited) in trench 1710 and on substrate 102. As described above, in some embodiments, the first dielectric layer 144 may include, but is not limited to, silicon alumina (SiOAl), aluminum oxide (AlO), hafnium oxide (HfO), tantalum silicon oxide (TaOSi), doped polycrystalline silicon, another high dielectric constant dielectric material, another dielectric material, or the like.

[0048] Figure 17G illustrates the formation (e.g., deposition) of a second dielectric layer 142 in trench 1710 and over the first dielectric layer 144. As described above, in some embodiments, the second dielectric layer 142 may include, but is not limited to, silicon oxide (SiOx) (e.g., silicon dioxide (SiO2)), another dielectric material, and / or the like. Furthermore, in some embodiments, the second dielectric layer 142 (which may be bonded to the first dielectric layer 144) may be formed over the sensor dielectric layer 106 on the substrate 102. Subsequently, in some embodiments, the upper surface of the sensor dielectric layer 106 may be planarized (e.g., by chemical-mechanical planarization, CMP).

[0049] Figure 17H ​​illustrates a mesh structure 132 formed (e.g., by deposition, photolithography, and etching) on ​​the sensor dielectric layer 106 to surround the photosensitive area group of each phase detection pixel 120 and image pixel 122 in a planar view. Therefore, the mesh structure 132 may be provided with openings 131 through which light can be received by the photosensitive area 104 of each phase detection pixel 120 and image pixel 122. In some embodiments, as previously described, the mesh structure 132 may include, but is not limited to, metallic materials (e.g., tungsten (W)) or other conductive materials (e.g., titanium nitride (TiN) which can serve as a barrier layer), dielectric materials (e.g., silicon oxide (SiOx)), or the like.

[0050] Figure 17I illustrates the formation (e.g., conformal deposition) of additional dielectric material (e.g., the same material as the sensor dielectric layer 106, such as silicon dioxide (SiO2) or another dielectric material) to cover or seal the mesh structure 132.

[0051] Figure 17J illustrates the formation of filter elements 134 over the mesh structure 132 and the sensor dielectric layer 106. In some embodiments, each filter element 134 may have a specific color associated with a corresponding image pixel 122. As described above, in some embodiments, each filter element 134 may allow light associated with a specific color (e.g., red, green, or blue) to pass through, thereby filtering other colors. In some embodiments, the formation of the filter elements 134 may include: applying a color combination layer for each type or color of filter element 134, selectively patterning the color combination layer (e.g., exposing it to ultraviolet light), and removing unexposed areas of the color combination layer to form a pattern of filter element 134 with the desired color.

[0052] Figure 17K illustrates an optical lens layer 110 formed (e.g., by deposition, patterning, and reflow) on a filter element 134 (e.g., for image pixel 122) and a sensor dielectric layer 106 (e.g., for phase detection pixel 120), wherein the optical lens layer 110 provides a lens portion 111 (e.g., a spherical microlens or the like) for each corresponding image pixel 122 and phase detection pixel 120 to focus received light onto a photosensitive area 104 corresponding to the relevant pixel. In some embodiments, the formation of the lens portion 111 may include: forming a photosensitive layer made of a substantially transparent material (e.g., a polymer, an oxide (such as SiO2), or other substantially transparent material), patterning the photosensitive layer, and then reflowing the patterned photosensitive layer (e.g., at some predetermined temperature) to form the lens portion 111.

[0053] Figure 17L illustrates the formation (e.g., deposition) of ARC 113 on optical lens layer 110. In some embodiments, ARC 113 may include, but is not limited to, titanium nitride (TiN), silicon nitride (SiN), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), and / or another antireflective material that allows light to pass through, as described above.

[0054] Figure 18 illustrates flowcharts of some embodiments of a method 1800 for forming an IC device (e.g., IC device 100A of Figure 1C) according to this disclosure, wherein the IC device employs an isolation structure to provide reduced crosstalk for a partially obscured PDAF. While the methods described herein and / or other methods shown and / or described herein are shown as a series of actions or events, it should be understood that this disclosure is not limited to the order or actions shown. Therefore, in some embodiments, actions may be performed in a different order than shown and / or may be performed simultaneously. Furthermore, in some embodiments, the actions or events shown may be subdivided into multiple actions or events that may occur at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0055] For example, in action 1802, a plurality of first photosensitive areas (e.g., photosensitive area 104 of FIG. 17B) are formed in a substrate (e.g., substrate 102 of FIG. 17A and FIG. 17B) via a first side of the substrate. In some embodiments, each of the plurality of groups of first photosensitive areas includes one or more of the plurality of first photosensitive areas. Additionally, a plurality of second photosensitive areas (e.g., photosensitive area 104 of FIG. 17B) are formed in the substrate via a first side of the substrate. In some embodiments, each of the plurality of groups of second photosensitive areas includes one or more of the plurality of second photosensitive areas. In some embodiments, each of the plurality of groups of first photosensitive areas may be associated with a corresponding one of a plurality of image pixels (e.g., photosensitive area 104 of each image pixel 122 in FIG. 1A to FIG. 1D), and each of the plurality of groups of second photosensitive areas may be associated with a corresponding one of a plurality of phase-detection pixels (e.g., photosensitive area 104 of each phase-detection pixel 120 in FIG. 1A to FIG. 1D). Figures 17A and 17B show cross-sectional views of some embodiments corresponding to action 1802.

[0056] In action 1804, at least one dielectric layer (e.g., circuit dielectric layer 112 in FIG. 17C) is formed on a first side of the substrate. In some embodiments, the at least one dielectric layer may include at least one conductive structure (e.g., conductive structure 114 in FIG. 17C) electrically coupled to the first side of the substrate. FIG. 17C shows a cross-sectional view corresponding to some embodiments of action 1804.

[0057] In action 1806, a portion of the substrate is removed to form at least one trench (e.g., trench 1710 in FIG. 17E), said at least one trench extending at least partially from a second side of the substrate toward a first side of the substrate. FIG. 17D and FIG. 17E show cross-sectional views corresponding to some embodiments of action 1806.

[0058] In action 1808, the at least one trench is filled with at least one dielectric material (e.g., the first dielectric layer 144 of FIG. 17F and the second dielectric layer 142 of FIG. 17G) to form an isolation structure (e.g., isolation structure 140 of FIG. 17G). In some embodiments, in a plan view of the IC device, the isolation structure may be tangent to each of the plurality of first photosensitive areas. Furthermore, in some embodiments, in a plan view of the IC device, the isolation structure may include a first configuration for each of the plurality of first photosensitive area groups and a second configuration different from the first configuration for each of the plurality of second photosensitive area groups (e.g., a lack of walls between photosensitive areas 104 of phase detection pixel 120A of FIG. 17G). FIG. 17F and FIG. 17G show cross-sectional views corresponding to some embodiments of action 1808.

[0059] In action 1810, a mesh structure (e.g., mesh structure 132 in FIG. 17H) is formed above the second side of the substrate. In some embodiments, the mesh structure may be tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups. Furthermore, the mesh structure may include a plurality of blocking elements (e.g., half-blocking elements 130 in FIG. 1A and FIG. 1D). Additionally, each of the plurality of blocking elements may be disposed above a portion of a corresponding one of the plurality of second photosensitive area groups. FIG. 17H shows a cross-sectional view corresponding to some embodiments of action 1810.

[0060] Figures 19A and 19B show cross-sectional views of some embodiments of an IC device (e.g., IC device 100M, as shown in the cross-sectional view of Figure 13C) employing optical lens layers (e.g., optical lens layer 110 of Figure 13C) at various stages of manufacturing according to this disclosure. While Figures 19A and 19B are described as a series of actions, it should be understood that these actions are not limiting, as the order of actions in each series may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0061] For example, Figure 19A illustrates a sub-assembly including a substrate 102 for photosensitive areas 104 of image pixels 122 and phase detection pixels 120, a circuit dielectric layer 112 with conductive structures 114, an isolation structure 140 comprising a first dielectric layer 144 and a second dielectric layer 142 in the substrate 102, a sensor dielectric layer 106, a mesh structure 132 defining a plurality of openings 131, and a filter element 134 for image pixels 122. The fabrication of this sub-assembly is at least similar to that described above in conjunction with Figures 17A to 17J, except that the configuration of the isolation structure 140 within the phase detection pixels 120 may correspond to the configuration of the isolation structure 140 within the image pixels 122. More specifically, in some embodiments, as shown in Figure 19A, the isolation structure 140 surrounds each photosensitive area 104 within the phase detection pixels 120 and the image pixels 122.

[0062] Figure 19B illustrates an optical lens layer 110 formed (e.g., by deposition, patterning, and reflow) on a filter element 134 (e.g., for image pixel 122) and a sensor dielectric layer 106 (e.g., for phase detection pixel 120), wherein the optical lens layer 110 provides a lens portion 111 (e.g., a spherical microlens or the like) for each corresponding image pixel 122 and a plurality of lens portions 111A (e.g., elliptical microlenses or the like) for each corresponding phase detection pixel 120 to focus received light onto a photosensitive area 104 corresponding to the relevant pixel. In some embodiments, the lens portions 111 and 111A may be formed as described above in conjunction with Figure 17K. Subsequently, in some embodiments, an ARC 113 is formed on the optical lens layer 110, as described in detail above in conjunction with Figure 17L.

[0063] Figure 20 shows a flowchart of some embodiments of a method 2000 for forming an IC device (e.g., IC device 100M of Figure 13C) according to this disclosure, wherein the IC device employs an optical lens layer that provides reduced crosstalk for a partially obscured PDAF.

[0064] For example, in action 2002, a plurality of first photosensitive areas (e.g., photosensitive area 104 of FIG. 17B) are formed in a substrate (e.g., substrate 102 of FIG. 17A and FIG. 17B) via a first side of the substrate. In some embodiments, each of the plurality of groups of first photosensitive areas includes one or more corresponding first photosensitive areas. Additionally, a plurality of second photosensitive areas (e.g., photosensitive area 104 of FIG. 17B) are formed in the substrate via a first side of the substrate. In some embodiments, the plurality of groups of second photosensitive areas includes one or more corresponding second photosensitive areas. Each of the plurality of groups of first photosensitive areas may be associated with a corresponding one of a plurality of image pixels (e.g., photosensitive area 104 of each image pixel 122 of FIG. 13A to FIG. 13C), and each of the plurality of groups of second photosensitive areas may be associated with a corresponding one of a plurality of phase-detection pixels (e.g., photosensitive area 104 of each phase-detection pixel 120 of FIG. 13A to FIG. 13C). Figures 17A and 17B show cross-sectional views corresponding to some embodiments of action 2002.

[0065] In action 2004, the substrate is etched to form at least one trench (e.g., trench 1710 in FIG. 17E), said at least one trench extending at least partially from a second side of the substrate toward a first side of the substrate. FIG. 17D and FIG. 17E show cross-sectional views corresponding to some embodiments of action 2004.

[0066] In action 2006, the at least one trench is filled with at least one dielectric material (e.g., the first dielectric layer 144 of FIG. 17F and the second dielectric layer 142 of FIG. 17G) to form an isolation structure (e.g., isolation structure 140 of FIG. 17G). In some embodiments, in a plan view of the IC device, the isolation structure may be tangent to each of the plurality of first photosensitive areas and each of the plurality of second photosensitive areas. FIG. 17F and FIG. 17G are enhanced by the isolation structure 140 in FIG. 19A to show cross-sectional views of some embodiments corresponding to action 2006.

[0067] In action 2008, a mesh structure (e.g., mesh structure 132 of FIG. 17H) is formed above the second side of the substrate. In some embodiments, the mesh structure may be tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups. Furthermore, the mesh structure may include a plurality of blocking elements (e.g., half-blocking element 130 of FIG. 13A). Additionally, each of the plurality of blocking elements may be disposed above a portion of a corresponding one of the plurality of second photosensitive area groups. FIG. 17H, enhanced by the isolation structure 140 of FIG. 19A, shows a cross-sectional view corresponding to some embodiments of action 2008.

[0068] In action 2010, an optical lens layer (e.g., optical lens layer 110 of FIG. 19B) is formed over the plurality of filter elements and the substrate. In some embodiments, the optical lens layer may include a plurality of lens portions (e.g., lens portion 111 of FIG. 19B) and a plurality of additional lens portions (e.g., lens portion 111A of FIG. 19B). In some embodiments, each of the plurality of lens portions may be disposed over a corresponding one of the plurality of first photosensitive area groups. Furthermore, in some embodiments, at least two of the plurality of additional lens portions may be disposed over a corresponding one of the plurality of second photosensitive area groups. FIG. 19B shows a cross-sectional view corresponding to some embodiments of action 2010.

[0069] In some embodiments, this disclosure provides an IC device comprising: a substrate including: a plurality of first photosensitive areas, wherein each of a plurality of groups of first photosensitive areas includes one or more corresponding first photosensitive areas, and wherein each of the plurality of groups of first photosensitive areas is associated with a corresponding one of a plurality of image pixels; and a plurality of second photosensitive areas, wherein each of a plurality of groups of second photosensitive areas includes one or more corresponding second photosensitive areas, and wherein each of the plurality of groups of second photosensitive areas is associated with a corresponding one of a plurality of phase-detecting pixels; and an isolation structure, at least partially extending from a second side of the substrate toward a first side of the substrate. Extending further, in the plan view of the IC device, the isolation structure is tangent to each of the plurality of first photosensitive areas. In the plan view of the IC device, the isolation structure includes a first configuration for each of the plurality of image pixels and a second configuration different from the first configuration for each of the plurality of phase-detection pixels; and a mesh structure disposed above a first side of the substrate. The mesh structure is tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups. The mesh structure includes a plurality of blocking members, each of the plurality of blocking members being disposed above a portion of a corresponding one of the plurality of second photosensitive area groups.

[0070] In some embodiments, in the plan view of the integrated circuit device, for each of the plurality of phase-detecting pixels, the isolation structure includes an opening above the entire phase-detecting pixel. In some embodiments, in the plan view of the integrated circuit device, for each of the plurality of phase-detecting pixels, the isolation structure includes a single linear wall spanning the phase-detecting pixel, the single linear wall separating at least one of the plurality of second photosensitive areas of the phase-detecting pixel from another of the plurality of second photosensitive areas of the phase-detecting pixel. In some embodiments, in the plan view of the integrated circuit device, the single linear wall is disposed at the central region of the occlusion of the phase-detecting pixel. In some embodiments, in the plan view of the integrated circuit device, the single linear wall is disposed along the edge of the occlusion of the phase-detecting pixel. In some embodiments, for a phase-detecting pixel among the plurality of phase-detecting pixels, the isolation structure includes a first linear wall and a second linear wall. The first linear wall crosses the phase-detecting pixel in a first lateral direction in the plan view of the integrated circuit device, and the second linear wall crosses the phase-detecting pixel in a second lateral direction in the plan view of the integrated circuit device, the second lateral direction being perpendicular to the first lateral direction. In the plan view of the integrated circuit device, the first linear wall and the second linear wall intersect in a quadrant region of the phase-detecting pixel. In some embodiments, the quadrant region is located below the occlusion member of the phase-detecting pixel. In some embodiments, for a phase-detecting pixel among the plurality of phase-detecting pixels, the isolation structure includes a first linear wall and a second linear wall. The first linear wall crosses the phase-detecting pixel in a first lateral direction in the plan view of the integrated circuit device, and the second linear wall extends from the first linear wall to the periphery of the phase-detecting pixel in a second lateral direction perpendicular to the first lateral direction in the plan view of the integrated circuit device. In the plan view of the integrated circuit device, the first linear wall and the second linear wall separate two of the plurality of second photosensitive areas in the phase-detecting pixel from each other and separate the other plurality of second photosensitive areas in the phase-detecting pixel from each other. In some embodiments, the first linear wall and the second linear wall are completely disposed below the shielding member of the phase-detecting pixel. In some embodiments, for a phase-detecting pixel among the plurality of phase-detecting pixels, the isolation structure includes four separate walls. In the plan view of the integrated circuit device, each of the four separate walls extends partially from a corresponding wall of the isolation structure at the periphery of the phase-detecting pixel toward the central region of the phase-detecting pixel.In some embodiments, the integrated circuit device further includes a plurality of filter elements and an optical lens layer. The plurality of filter elements are disposed above the grid structure, each of the plurality of filter elements being disposed above a corresponding one of the plurality of image pixels. The optical lens layer is disposed above the plurality of filter elements and the substrate, and the optical lens layer includes a plurality of spherical lens portions and a plurality of elliptical lens portions. Each of the plurality of spherical lens portions is disposed above a corresponding one of the plurality of image pixels, and each of the plurality of elliptical lens portions is disposed on a corresponding half of the plurality of phase-detecting pixels. In some embodiments, the integrated circuit device further includes a plurality of filter elements and an optical lens layer. The plurality of filter elements are disposed above the grid structure, each of the plurality of filter elements being disposed above a corresponding one of the plurality of image pixels. The optical lens layer is disposed above the plurality of filter elements and the substrate, and the optical lens layer includes a plurality of first spherical lens portions and a plurality of second spherical lens portions. Each of the plurality of first spherical lens portions is disposed above a corresponding one of the plurality of image pixels, and each of the plurality of second spherical lens portions is disposed above a corresponding one of the plurality of second photosensitive areas of the plurality of phase-detecting pixels. .

[0071] In some embodiments, this disclosure provides a method for manufacturing an IC device. The method includes: forming a plurality of first photosensitive regions and a plurality of second photosensitive regions in a substrate, each of a plurality of first photosensitive region groups including one or more corresponding first photosensitive regions, and a plurality of second photosensitive region groups including one or more corresponding second photosensitive regions; forming at least one dielectric layer on a first side of the substrate, the at least one dielectric layer including at least one conductive structure electrically coupled to the first side of the substrate; removing a portion of the substrate to form at least one trench, the at least one trench extending at least partially from a second side of the substrate toward the first side of the substrate; filling the at least one trench with at least one dielectric material to form an isolation structure, in I In the plan view of the IC device, the isolation structure is tangent to each of the plurality of first photosensitive areas. In the plan view of the IC device, the isolation structure includes a first configuration for each of the plurality of first photosensitive area groups and a second configuration different from the first configuration for each of the plurality of second photosensitive area groups; and a mesh structure is formed above a second side of the substrate, the mesh structure being tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups, the mesh structure including a plurality of blocking members, each of the plurality of blocking members being disposed above a portion of a corresponding one of the plurality of second photosensitive area groups.

[0072] In some embodiments, for a second photosensitive area group among the plurality of second photosensitive area groups, in the plan view of the integrated circuit device, the isolation structure includes an opening over the entirety of the second photosensitive area group. In some embodiments, for a second photosensitive area group among the plurality of second photosensitive area groups, in the plan view of the integrated circuit device, the isolation structure includes a single linear wall spanning the second photosensitive area group, the single linear wall separating at least one of the plurality of second photosensitive areas in the second photosensitive area group from another of the plurality of second photosensitive areas in the second photosensitive area group. In some embodiments, for a second photosensitive area group among the plurality of second photosensitive area groups, in the plan view of the integrated circuit device, the isolation structure includes two intersecting linear walls that separate the plurality of second photosensitive areas in the second photosensitive area group from each other. In some embodiments, the method further includes: forming a plurality of filter elements above the grid structure, wherein each of the plurality of filter elements is disposed above a corresponding one of the plurality of first photosensitive area groups; and forming an optical lens layer above the plurality of filter elements and the substrate, the optical lens layer including a plurality of spherical lens portions, each of the plurality of spherical lens portions being disposed above a corresponding one of the plurality of first photosensitive area groups or above a corresponding one of the plurality of second photosensitive area groups.

[0073] In some embodiments, this disclosure provides another method of manufacturing an IC device. The method includes: forming a plurality of first photosensitive areas and a plurality of second photosensitive areas in a substrate, each of a plurality of groups of first photosensitive areas including one or more corresponding first photosensitive areas, and each of a plurality of groups of second photosensitive areas including one or more corresponding second photosensitive areas; etching the substrate to form at least one trench extending at least partially from a second side of the substrate toward a first side of the substrate; filling the at least one trench with at least one dielectric material to form an isolation structure; forming a mesh structure above the second side of the substrate, the mesh structure including a plurality of shielding members, each of the plurality of shielding members disposed above a portion of a corresponding member of the plurality of groups of second photosensitive areas; and forming an optical lens layer above the substrate, the optical lens layer including a plurality of lens portions and a plurality of additional lens portions, wherein each of the plurality of lens portions is disposed above a corresponding member of the plurality of groups of first photosensitive areas, and at least two of the plurality of additional lens portions are disposed above a corresponding member of the plurality of groups of second photosensitive areas.

[0074] In some embodiments, the plurality of lens portions include spherical lens portions and at least two of the plurality of additional lens portions include two elliptical lens portions, each of the two elliptical lens portions being disposed above a corresponding half of the corresponding one of the plurality of second photosensitive area groups. In some embodiments, the plurality of additional lens portions include four spherical lens portions, each of the four spherical lens portions being disposed above a corresponding quarter of the corresponding one of the plurality of second photosensitive area groups.

[0075] It should be understood that in this specification and the claims, the terms "first," "second," "third," etc., are merely general designations used for ease of description to distinguish different elements in a single figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0076] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0077] 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M, 100N, 100O, 100P, 100Q: Integrated Circuit (IC) Devices 102: Base 104: Photosensitive area 106: Sensor dielectric layer 110: Optical lens layer 111: Lens section 111A: Lens Section / Elliptical Lens Section 111B: Spherical lens section 112: Circuit dielectric layer 113: Anti-reflective coating (ARC) 114: Conductive Structure 120, 120A, 120B, 120C, 120D, 120E, 120F, 120H, 120I, 120J, 120K, 120L: Phase-detection pixels 122:Image pixel 130: Partial cover 131: Opening 132: Grid Structure 133: Grid segment 134: Filter element 140: Isolation Structure 142: Second dielectric layer 144: First dielectric layer 152: Light 252: Single-walled 352: Single linear wall 452, 552B: Second linear wall 552A: First linear wall 652: Individual wall 1710: Ditch 1800, 2000: Methods 1802, 1804, 1806, 1808, 1810, 2002, 2004, 2006, 2008, 2010: Actions 1B-1B, 1D-1D, 13B-13B: Lines

Claims

1. An integrated circuit device, comprising: a substrate The method includes: a plurality of first photosensitive areas, wherein each of the plurality of groups of first photosensitive areas includes one or more corresponding first photosensitive areas, and each of the plurality of groups of first photosensitive areas is associated with one corresponding image pixel; and a plurality of second photosensitive areas, wherein each of the plurality of groups of second photosensitive areas includes one or more corresponding second photosensitive areas, and each of the plurality of groups of second photosensitive areas is associated with one corresponding phase detection pixel; An isolation structure, extending at least partially from a second side of the substrate toward a first side of the substrate, is tangent to each of the plurality of first photosensitive areas in a plan view of the integrated circuit device. The isolation structure includes a first configuration for each of the plurality of image pixels and a second configuration for each of the plurality of phase-detection pixels, the second configuration being different from the first configuration. A grid structure is disposed above the first side of the substrate, tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups. The grid structure includes a plurality of blocking members, each of which is disposed directly above a corresponding member of the plurality of second photosensitive area groups and covers a portion of the plurality of second photosensitive areas.

2. The integrated circuit device as claimed in claim 1, wherein in the plan view of the integrated circuit device, for the phase detection pixels among the plurality of phase detection pixels, the isolation structure includes an opening above the overall phase detection pixel.

3. The integrated circuit device of claim 1, wherein, in the plan view of the integrated circuit device, for each of the plurality of phase-detecting pixels, the isolation structure includes a single linear wall spanning the phase-detecting pixels, the single linear wall separating at least one of the plurality of second photosensitive areas of the phase-detecting pixels from another of the plurality of second photosensitive areas of the phase-detecting pixels.

4. The integrated circuit arrangement as claimed in claim 1, wherein the isolation structure comprises, for the phase detection pixels among the plurality of phase detection pixels: A first linear wall crosses the phase detection pixel in a first lateral direction in the plan view of the integrated circuit device; And a second linear wall that crosses the phase detection pixel in a second lateral direction in the plan view of the integrated circuit device, the second lateral direction being perpendicular to the first lateral direction, wherein the first linear wall and the second linear wall intersect in the quadrant region of the phase detection pixel in the plan view of the integrated circuit device.

5. The integrated circuit arrangement of claim 1, wherein, for the phase detection pixels among the plurality of phase detection pixels, the isolation structure comprises: A first linear wall crosses the phase detection pixel in a first lateral direction in the plan view of the integrated circuit device; And a second linear wall, extending from the first linear wall to the periphery of the phase-detecting pixel in the plan view of the integrated circuit device along a second lateral direction perpendicular to the first lateral direction, wherein in the plan view of the integrated circuit device, the first linear wall and the second linear wall separate two of the plurality of second photosensitive areas in the phase-detecting pixel from each other, and separate the other plurality of second photosensitive areas in the phase-detecting pixel from each other.

6. The integrated circuit arrangement of claim 1, wherein the isolation structure comprises, for the phase detection pixels of the plurality of phase detection pixels: In the plan view of the integrated circuit device, each of the four separate walls extends partially from a corresponding wall of the isolation structure on the outer periphery of the phase-detecting pixel toward the central region of the phase-detecting pixel.

7. The integrated circuit arrangement as claimed in claim 1, further comprising: Multiple filter elements are disposed above the grid structure, and each of the multiple filter elements is disposed above a corresponding one of the multiple image pixels; An optical lens layer is disposed above the plurality of filter elements and the substrate, the optical lens layer comprising: a plurality of spherical lens portions, each of the plurality of spherical lens portions being disposed above a corresponding one of the plurality of image pixels; And a plurality of elliptical lens portions, each of which is disposed on a corresponding half of the plurality of phase detection pixels.

8. The integrated circuit arrangement as claimed in claim 1, further comprising: Multiple filter elements are disposed above the grid structure, and each of the multiple filter elements is disposed above a corresponding one of the multiple image pixels; An optical lens layer is disposed above the plurality of filter elements and the substrate, the optical lens layer comprising: a plurality of first spherical lens portions, each of the plurality of first spherical lens portions being disposed above a corresponding one of the plurality of image pixels; And a plurality of second spherical lens portions, each of the plurality of second spherical lens portions being disposed above a corresponding one of the plurality of second photosensitive areas in the plurality of phase detection pixels.

9. A method of manufacturing an integrated circuit device, comprising: A plurality of first photosensitive areas and a plurality of second photosensitive areas are formed in a substrate, each of the plurality of first photosensitive area groups including one or more corresponding first photosensitive areas, and each of the plurality of second photosensitive area groups including one or more corresponding second photosensitive areas; at least one dielectric layer is formed on a first side of the substrate, the at least one dielectric layer including at least one conductive structure electrically coupled to the first side of the substrate; A portion of the substrate is removed to form at least one trench extending at least partially from a second side of the substrate toward a first side of the substrate; the at least one trench is filled with at least one dielectric material to form an isolation structure tangent to each of the plurality of first photosensitive areas in a plan view of the integrated circuit device; the isolation structure includes a first configuration within each of the plurality of first photosensitive area groups and a second configuration for each of the plurality of second photosensitive area groups, the second configuration being different from the first configuration; and a mesh structure is formed above the second side of the substrate, the mesh structure being tangent to each of the plurality of first photosensitive area groups and each of the plurality of second photosensitive area groups, the mesh structure including a plurality of shielding members, each of the plurality of shielding members being disposed directly above a corresponding one of the plurality of second photosensitive area groups and covering a portion of the plurality of second photosensitive areas.

10. A method of manufacturing an integrated circuit device, comprising: A plurality of first photosensitive areas and a plurality of second photosensitive areas are formed in a substrate, each of the plurality of first photosensitive area groups including one or more corresponding first photosensitive areas, and the plurality of second photosensitive area groups including one or more corresponding second photosensitive areas; the substrate is etched to form at least one trench, the at least one trench extending at least partially from a second side of the substrate toward a first side of the substrate; the at least one trench is filled with at least one dielectric material to form an isolation structure; A grid structure is formed above the second side of the substrate. The grid structure includes a plurality of shielding members, each of which is positioned directly above a corresponding member of the plurality of second photosensitive area groups and covers a portion of the plurality of second photosensitive areas. An optical lens layer is formed over the substrate, the optical lens layer comprising: a plurality of lens portions, wherein each of the plurality of lens portions is disposed over a corresponding one of the plurality of first photosensitive area groups; And a plurality of additional lens portions, wherein at least two of the plurality of additional lens portions are disposed above a corresponding one of the plurality of second photosensitive area groups.

Images