Semiconductor structure and method for forming the same

Abstract

A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes the following steps. A first deposition process is performed to form a first cladding layer over a substrate. A second deposition process is performed to form a second cladding layer directly on the first cladding layer. The first cladding layer and the second cladding layer are made of the same material, but with different film densities.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor structure and a method for forming the same. More specifically, this disclosure relates to a semiconductor structure having two cladding layers made of the same material but with different thin film densities, and a method for manufacturing the same. [Previous Technology]

[0002] Controlling the etching process is often a challenge in the manufacturing of semiconductor devices, especially when thin layers are still retained in the structure. The challenge mainly stems from the lack of selectivity for layers made of the same material during the etching process. In the prior art, etching in areas with different pattern loads may lead to over-etching, resulting in unintended damage or performance problems.

[0003] Therefore, there is still a need for a novel semiconductor manufacturing method that can provide good process control while retaining a thinner layer. [Summary of the Invention]

[0004] This disclosure addresses the challenge of controlling the etching process in structures with residual thin layers by configuring two coating layers made of the same material but with different film densities. The coating layers can be formed through different deposition processes, or process parameters (e.g., oxygen flow rate or plasma power) can be adjusted during formation to retain a thinner coating layer without causing unintended damage or performance issues.

[0005] The embodiments disclosed herein provide a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes the following steps: performing a first deposition process to form a first cladding layer over a substrate; performing a second deposition process to form a second cladding layer directly over the first cladding layer. The first cladding layer and the second cladding layer are made of the same material but have different film densities.

[0006] In some embodiments, the first deposition process is different from the second deposition process.

[0007] In some embodiments, the first deposition process is selected from one of the group consisting of chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma vapor deposition, electron beam evaporation and physical vapor deposition, while the second deposition process is selected from another of the group consisting of chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma vapor deposition, electron beam evaporation and physical vapor deposition.

[0008] In some embodiments, the thickness of the first coating layer is in the range of 5 nanometers to 100 nanometers, or in the range of 20 nanometers to 50 nanometers.

[0009] In some embodiments, the first deposition process and the second deposition process have different deposition rates.

[0010] In some embodiments, the deposition rate of the first deposition process is lower than the deposition rate of the second deposition process.

[0011] In some embodiments, the power level used in the first deposition process is different from that used in the second deposition process.

[0012] In some embodiments, the power level used in the first deposition process is higher than that used in the second deposition process.

[0013] In some embodiments, the method of forming a semiconductor structure further includes the following step: performing an ion implantation process on the first or second cladding layer.

[0014] In some embodiments, the first deposition process is the same as the second deposition process.

[0015] In some embodiments, the first and second coating layers comprise silicon dioxide, and the ion implantation process uses nitrogen ions.

[0016] In some embodiments, the method of forming the semiconductor structure further includes the following steps: patterning a second cladding layer to form at least one trench. The trench exposes a portion of the first cladding layer.

[0017] In some embodiments, the method of forming a semiconductor structure further includes the following step: forming a waveguide between a substrate and a first cladding layer.

[0018] In some embodiments, the thickness of the first cladding layer is less than or equal to the evanescent wave region of the waveguide.

[0019] In some embodiments, the method of forming the semiconductor structure further includes the following step: forming a third cladding layer between the substrate and the waveguide.

[0020] The embodiments disclosed herein provide a semiconductor structure. The semiconductor structure includes a substrate and a first cladding layer, the first cladding layer being disposed above the substrate. The semiconductor structure further includes a second cladding layer, the second cladding layer being disposed above the first cladding layer and in direct contact with the first cladding layer. The first cladding layer and the second cladding layer are made of the same material, but have different film densities.

[0021] In some embodiments, the first or second coating layer contains doped ions, thereby producing different film densities.

[0022] In some embodiments, the second covering layer has at least one groove that exposes a portion of the first covering layer.

[0023] In some embodiments, the semiconductor structure further includes a waveguide disposed between the substrate and the first cladding layer.

[0024] In some embodiments, the first coating layer and the second coating layer comprise silicon dioxide or silicon nitride.

Implementation Method

[0025] The following disclosure provides many different embodiments or examples to implement different features of this invention. Specific examples of the various components and their arrangements described below are provided to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, if it is stated that a first feature is formed on or above a second feature, it may include embodiments where the first and second feature are in direct contact, or embodiments where other feature is formed between the first and second feature, so that the first and second feature may not be in direct contact.

[0026] It should be understood that other operational steps may be performed before, between, or after the method, and in other embodiments of the method, some operational steps may be replaced or omitted.

[0027] In addition, spatial terms such as "below," "under," "down," "above," "above," and similar terms may be used herein to facilitate the description of the relationship between one element or feature and other elements or features in the diagram. These spatial terms encompass different orientations of the device in use or operation, as well as the orientations described in the diagram. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial adjectives used herein will be interpreted in accordance with the orientation after the turn.

[0028] In this disclosure, the terms "about," "approximately," and "substantially" generally mean within 20% of a given value, or within 10% of a given value, or within 5% of a given value, or within 3% of a given value, or within 2% of a given value, or within 1% of a given value, or even within 0.5% of a given value. The given values ​​in this disclosure are approximate values. That is, even without a specific description of "about," "approximately," or "substantially," the given value may still contain the meaning of "about," "approximately," or "substantially."

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted in a meaning consistent with the context of the relevant art and will not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0030] The same reference numerals and / or markings may be used repeatedly in the following embodiments. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the various embodiments and / or structures discussed.

[0031] Figure 1 is a partial cross-sectional view of semiconductor 100 according to some embodiments of the present disclosure. It should be noted that, for the sake of brevity, some components of semiconductor 100 have been omitted in Figure 1.

[0032] Referring to Figure 1, in some embodiments, semiconductor 100 includes substrate 10. For example, substrate 10 may include elemental semiconductors (e.g., silicon or germanium), compound semiconductors (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)), alloy semiconductors (e.g., silicon germanium (SiGe), silicon germanium carbon (SiGeC), gallium arsenide phosphide (GaAsP), or indium gallium phosphide (GaInP)), any other suitable semiconductors, or combinations thereof. Furthermore, substrate 10 may be a semiconductor-on-insulator (SOI) substrate, comprising a bottom substrate, a buried oxide layer disposed on the bottom substrate, and a semiconductor layer disposed on the buried oxide layer. In some examples, substrate 10 may be a semiconductor wafer (e.g., a silicon wafer or any other suitable semiconductor wafer).

[0033] The substrate 10 may include various p-type doped regions and / or n-type doped regions formed by ion implantation and / or diffusion processes. For example, the doped regions may be configured to form transistors, photodiodes, and / or light-emitting diodes, but this disclosure is not limited thereto. Furthermore, the substrate 10 may include various isolation components to separate various device regions within the substrate 10. For example, the isolation components may include shallow trench isolation (STI) components, but this disclosure is not limited thereto. The formation of shallow trench isolation (STI) components may involve etching trenches in the substrate 10 and filling the trenches with an insulating material (e.g., silicon dioxide, silicon nitride, or silicon oxynitride). The filled trenches may have a multilayer structure, such as a trench filled with a thermally oxidized silicon nitride liner. A chemical mechanical polishing (CMP) process may be performed to etch back excess insulating material and planarize the top surface of the isolation component. Furthermore, the substrate 10 may include various conductive components (e.g., conductive lines or vias). For example, the conductive components may be made of aluminum (Al), copper (Cu), tungsten (W), alloys thereof, any other suitable conductive material, or combinations thereof.

[0034] Referring to Figure 1, in some embodiments, the semiconductor 100 includes an upper cladding layer 22 and an upper cladding layer 23. The upper cladding layer 22 is disposed above the substrate 10, and the upper cladding layer 23 is disposed above the upper cladding layer 22 and in direct contact with the upper cladding layer 22. In some embodiments, the upper cladding layer 22 and the upper cladding layer 23 are made of the same material but have different film densities. The different film densities mentioned herein refer to the different arrangements of molecules in the upper cladding layer 22 and the upper cladding layer 23. This difference can be achieved through different deposition processes, adjustment of process parameters, or doping with different ions, but the embodiments disclosed herein are not intended to limit the scope of the invention.

[0035] In some embodiments, the upper cladding layer 22 and the upper cladding layer 23 comprise silicon dioxide (SiO2), silicon nitride (SiN), any other suitable material, or a combination thereof. The upper cladding layer 22 and the upper cladding layer 23 may be formed by deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma vapor deposition (HDPVD), electron beam evaporation (E-gun), and physical vapor deposition (e.g., sputtering deposition), but the embodiments disclosed herein are not limited thereto.

[0036] In some embodiments, the upper cladding layer 22 or the upper cladding layer 23 has doped ions, thereby producing different film densities. For example, both the upper cladding layer 22 and the upper cladding layer 23 may be made of silicon dioxide (SiO2), one layer of which is doped with nitrogen ions, but the embodiments disclosed herein are not limited thereto.

[0037] As shown in Figure 1, in some embodiments, the upper cladding layer 23 has at least one trench 23T that exposes a portion of the upper cladding layer 22. For example, an etching process can be performed on the upper cladding layer 23 to form at least one trench 23T. Since the upper cladding layer 22 and the upper cladding layer 23 have different film densities, the upper cladding layer 22 can serve as an etch stop layer in the etching process. More specifically, based on the difference in film density, under the same etching parameters, the etching rate of the upper cladding layer 23 is faster than that of the upper cladding layer 22, with a difference of up to 1.05 times to 5 times. Therefore, the etch stop position can be controlled at the location of the upper cladding layer 22.

[0038] Figures 2A to 2G are partial cross-sectional views illustrating various stages of the method for forming the semiconductor structure 102 according to some embodiments of the present disclosure. It should be noted that, for the sake of brevity, some components of the semiconductor structure 102 have been omitted in Figures 2A to 2G.

[0039] Referring to Figure 2A, in some embodiments, a substrate 10 is provided. Referring to Figure 2B, in some embodiments, a lower cladding layer 21 is formed on the substrate 10. For example, the lower cladding layer 21 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, aluminum oxide, aluminum nitride, similar materials, or combinations thereof, but the embodiments disclosed herein are not limited thereto. Furthermore, the lower cladding layer 21 may be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, spin coating, similar processes, or combinations thereof, but the embodiments disclosed herein are not limited thereto. Next, in some embodiments, a waveguide 30 is formed on the lower cladding layer 21. More specifically, the lower cladding layer 21 is formed between the substrate 10 and the waveguide 30. The waveguide 30 may be formed by a deposition process, examples of which have been described above and will not be repeated here.

[0040] Referring to Figure 2C, in some embodiments, a first deposition process is performed to form an upper cladding layer 22 over the substrate 10. More specifically, a waveguide 30 is formed between the substrate 10 and the upper cladding layer 22. In some embodiments, the first deposition process may be selected from one of the group consisting of chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), high-density plasma vapor deposition (HDPVD), electron beam evaporation (E-gun), and physical vapor deposition (PVD). In some embodiments, physical vapor deposition includes sputtering deposition.

[0041] Referring to Figure 2D, in some embodiments, a second deposition process is performed to form an upper cladding layer 23 directly on the upper cladding layer 22, wherein the upper cladding layer 22 and the upper cladding layer 23 are made of the same material but have different film densities. Here, the thickness of the upper cladding layer 22 is less than the thickness of the upper cladding layer 23. In some embodiments, the thickness of the upper cladding layer 22 is between about 5 nanometers and about 100 nanometers, or between about 20 nanometers and about 50 nanometers. In some embodiments, the thickness of the upper cladding layer 22 is less than or equal to the evanescent wave region of the waveguide 30, which is typically the length at which the electromagnetic wave intensity decays to 1 / e. Furthermore, the thickness of the upper cladding layer 23 may be between about 30 nanometers and about 2000 nanometers, or between about 50 nanometers and about 500 nanometers.

[0042] In some embodiments, the first deposition process is different from the second deposition process. In some embodiments, the second deposition process is another process selected from the group consisting of chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), high-density plasma vapor deposition (HDPVD), electron beam evaporation (E-gun), and physical vapor deposition (PVD).

[0043] In one embodiment, the first deposition process is electron beam evaporation, and the second deposition process is chemical vapor deposition. In another embodiment, the first deposition process is electron beam evaporation, and the second deposition process is physical vapor deposition. In yet another embodiment, the first deposition process is chemical vapor deposition, and the second deposition process is physical vapor deposition. Different deposition processes may result in different film densities for the upper coating layer 22 and the upper coating layer 23, but the embodiments disclosed herein are not intended to be limiting.

[0044] In some embodiments, the first deposition process and the second deposition process have different deposition rates, thereby producing different film densities for the upper coating layer 22 and the upper coating layer 23. In some embodiments, the deposition rate of the first deposition process (forming the upper coating layer 22) is lower than the deposition rate of the second deposition process (forming the upper coating layer 23). For example, when both the upper coating layer 22 and the upper coating layer 23 are made of silicon dioxide, the silicon dioxide flow rate in the first deposition process may be greater than or less than that in the second deposition process.

[0045] In some embodiments, the first deposition process and the second deposition process use different power levels, thereby giving the upper cladding layer 22 and the upper cladding layer 23 different film densities. In some embodiments, the first deposition process uses a higher power level (e.g., plasma power) than the second deposition process.

[0046] In some other embodiments, ion-assisted deposition (IAD) may be used, and may be selectively combined with a higher deposition temperature or a lower deposition rate to increase the density and hardness of the deposited film (e.g., the upper coating layer 22 and / or the upper coating layer 23).

[0047] In some other embodiments, the first deposition process is the same as the second deposition process. In some embodiments, an ion implantation process is performed on the upper cladding layer 22 or the upper cladding layer 23, thereby producing different film densities for the upper cladding layer 22 and the upper cladding layer 23. For example, the ion implantation process can be performed on the upper cladding layer 22 before the second deposition process. Alternatively, the ion implantation process can be performed on the upper cladding layer 23 after the second deposition process. In some embodiments, the upper cladding layer 22 and the upper cladding layer 23 comprise silicon dioxide, and nitrogen ions are used in the ion implantation process, but the embodiments disclosed herein are not intended to limit the scope.

[0048] Referring to Figures 2E to 2G, in some embodiments, the upper cladding layer 23 is patterned to form at least one trench 23T, the trench 23T exposing a portion of the upper cladding layer 22. For example, as shown in Figure 2E, a mask layer 40 having a plurality of openings 40T may be formed over the upper cladding layer 23. Then, as shown in Figure 2F, the mask layer 40 may be used as an etching mask to perform an etching process to etch the upper cladding layer 23. For example, the mask layer 40 may contain a photoresist material, such as positive or negative photoresist. Furthermore, the mask layer 40 may be a hard mask, containing silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), similar materials, or combinations thereof, but the embodiments disclosed herein are not limited thereto. The mask layer 40 may be a single-layer structure or a multi-layer structure. The masking layer 40 may be formed by a deposition process, a photolithography process, other applicable processes or combinations thereof, but the embodiments disclosed herein are not limited thereto.

[0049] For example, deposition processes may include spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), similar processes, or combinations thereof. For example, photolithography processes may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking (PEB), development, rinsing, drying (e.g., hard baking), other applicable processes, or combinations thereof, but the embodiments disclosed herein are not intended to be limiting.

[0050] The etching process may include dry etching, wet etching, or a combination thereof. For example, dry etching may include reactive ion etching (RIE), inductively coupled plasma (ICP), neutron beam etching (NBE), electron cyclotron resonance (ECR) etching, or combinations thereof, but the embodiments disclosed herein are not intended to limit the scope. For example, wet etching may use hydrofluoric acid (HF), ammonium hydroxide (NH4OH), any suitable etchant, or a combination thereof, but the embodiments disclosed herein are not intended to limit the scope.

[0051] In this disclosure, since the upper cladding layer 22 and the upper cladding layer 23 have different film densities, the upper cladding layer 22 can be used as an etch stop layer during the etching process, thereby exposing part of the upper cladding layer 22. Next, as shown in Figure 2G, the mask layer 40 is removed.

[0052] Figure 3 illustrates a portion of the optical emission spectroscopy (OES) signal during etching of the semiconductor structure 102. As shown in Figure 3, in this embodiment, the upper cladding layer 22 and the upper cladding layer 23 have the same material (i.e., silicon dioxide (SiO2)) but different film densities. Therefore, significant signal changes (e.g., greater than 5) occur at the junction of the upper cladding layer 22 and the upper cladding layer 23, or at the location where pre-doped elements appear in the upper cladding layer 22. That is, the film quality changes significantly.

[0053] For example, the difference between the etching rate of the upper cladding layer 22 and the etching rate of the upper cladding layer 23 can be greater than 5%, 10%, or even more than 20%, but the embodiments disclosed herein are not limited thereto. As long as a identifiable signal change occurs (e.g., elemental differences or a distinguishable difference in etching rates), the etching equipment can be set to terminate the etching process manually or automatically. This ensures that the etching stop layer appears in a shallow position of the upper cladding layer 22, thereby achieving precise control over the etching termination position.

[0054] Figure 4 is an actual cross-sectional view of the semiconductor structure 102 under a scanning electron microscope (SEM). In this embodiment, both the upper cladding layer 22 and the upper cladding layer 23 are made of silicon dioxide (SiO2), wherein the upper cladding layer 22 is formed by electron beam evaporation (E-gun), and the upper cladding layer 23 is formed by chemical vapor deposition (CVD). As shown in Figure 4, there is a clear boundary line DL between the upper cladding layer 22 and the upper cladding layer 23, that is, the upper cladding layer 22 and the upper cladding layer 23 are made of the same material, but have different film densities.

[0055] As described above, in the embodiments disclosed herein, by configuring two coating layers made of the same material but with different film densities, the challenge of controlling the etching process in structures with residual thin layers (e.g., the upper coating layer 22) can be solved. The coating layers can be formed by different deposition processes, or process parameters (e.g., oxygen flow rate or plasma power) can be adjusted during formation to retain a thinner coating layer without causing unintended damage or performance problems.

[0056] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Furthermore, although this disclosure has been presented above with reference to several embodiments, it is not intended to limit this disclosure.

[0057] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable using this disclosure should or may be implemented in any single embodiment of this disclosure. Rather, language relating to features and advantages is to be understood as meaning that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Thus, the discussion of features and advantages and similar language throughout this specification may, but does not necessarily, represent the same embodiments.

[0058] Furthermore, in one or more embodiments, the features, advantages, and characteristics described herein may be combined in any suitable manner. Based on the description herein, those skilled in the art will recognize that this disclosure may be implemented without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be identified in some embodiments that may not be present in all embodiments of this disclosure. [Simplified Explanation of the Diagram]

[0059] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, according to industry standard practice, various feature components are not drawn to scale. In fact, the dimensions of various feature components may be enlarged or reduced to clearly show the technical features of the embodiments of this disclosure. Figure 1 is a partial cross-sectional view of a semiconductor according to some embodiments of this disclosure. Figures 2A to 2G are partial cross-sectional views of various stages of the semiconductor structure formation method according to some embodiments of this disclosure. Figure 3 shows a partial optical emission spectrum (OES) signal during etching of the semiconductor structure. Figure 4 is an actual cross-sectional view of the semiconductor structure under a scanning electron microscope (SEM).

Claims

1. A method for forming a semiconductor structure, comprising: Perform a first deposition process to form a first cladding layer over a substrate; And perform a second deposition process to form a second coating layer directly on the first coating layer, wherein the first coating layer and the second coating layer are made of the same material but have different film densities.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the first deposition process is different from the second deposition process, the first deposition process being selected from one of the group consisting of chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma vapor deposition, electron beam evaporation and physical vapor deposition, and the second deposition process being selected from another of the group consisting of chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma vapor deposition, electron beam evaporation and physical vapor deposition.

3. The method for forming a semiconductor structure as described in claim 1, wherein the thickness of the first cladding layer is in the range of 5 nanometers to 100 nanometers, or in the range of 20 nanometers to 50 nanometers.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein the deposition rate of the first deposition process is lower than the deposition rate of the second deposition process, or the power level used in the first deposition process is higher than that in the second deposition process.

5. The method for forming a semiconductor structure as described in claim 1 further includes: An ion implantation process is performed on the first or second coating layer, wherein the first deposition process is the same as the second deposition process, the first and second coating layers comprise silicon dioxide, and the ion implantation process uses nitrogen ions.

6. The method for forming a semiconductor structure as described in claim 1 further includes: The second coating layer is patterned to form at least one groove, wherein the at least one groove exposes a portion of the first coating layer.

7. The method for forming a semiconductor structure as described in claim 1 further includes: A waveguide is formed between the substrate and the first cladding layer; A third cladding layer is formed between the substrate and the waveguide, wherein the thickness of the first cladding layer is less than or equal to an evanescent wave region of the waveguide.

8. A semiconductor structure, comprising: One substrate; A first covering layer is disposed on top of the substrate; And a second coating layer disposed on the first coating layer and in direct contact with the first coating layer, wherein the first coating layer and the second coating layer are made of the same material but have different film densities.

9. The semiconductor structure as claimed in claim 8, wherein the first or second cladding layer includes a doped ion, thereby producing different film densities.

10. The semiconductor structure as described in claim 8, further comprising: A waveguide is disposed between the substrate and the first cladding layer, wherein the second cladding layer has at least one trench that exposes a portion of the first cladding layer, and the first cladding layer and the second cladding layer comprise silicon dioxide or silicon nitride.

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