Self-aligned contact patterning method with use of an Anti-spacer

TW202641204APending Publication Date: 2026-10-01TOKYO ELECTRON LTD
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Patent Information

Application Number
TW114145718
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-26
Filing Date
2025-11-24
Publication Date
2026-10-01

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Abstract

A method for manufacturing semiconductor devices can include forming an anti-spacer pattern including anti-spacer trenches, formed between a first patterned photoresist layer and a patterned overcoat layer, and extending along a first direction, forming a first patterned hard mask layer having first contact trenches extending along the first direction using the anti-spacer pattern, where the first patterned hard mask layer is formed from a first hard mask layer of underlying layers, forming a second patterned photoresist layer, where the second patterned photoresist layer includes contact-edge features and second contact trenches overlapping with the first contact trenches of the first patterned hard mask layer, where the contact-edge features and the second contact trenches extend in a second direction that is non-parallel with the first direction; and self-aligned etching using the second patterned photoresist layer and the first patterned hard mask layer to form third contact trenches.
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