Scalable and dynamic multi-modal chip design hotspot classification

Abstract

Identifying hotspots, or regions on the semiconductor designer substrate that are prone to manufacturing defects or performance issues, requires either error-prone techniques like design rule checking, or resource-intensive techniques such as scanning electron microscopy (SEM) imaging. This disclosure describes training and using a model-based architecture to quickly identify a probability of these hotspots at specific locations. The model is scalable and multi-modal, using inputs of different types (images, tabular, timeseries, etc.) from different sources. Detecting the likelihood of a hotspot can be done very efficiently with this model-based solution and can be used to minimize false positives and negatives before employing more time-intensive inspection techniques.

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