Method for forming stacked semiconductor structure
TW202641299APending Publication Date: 2026-10-01TOKYO ELECTRON LTD
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Patent Information
- Application Number
- TW114144650
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-11-22
- Filing Date
- 2025-11-17
- Publication Date
- 2026-10-01
Smart Images
Figure TWG2TA001078507_001 
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Abstract
A method includes forming a first die in a first wafer. The first die includes first bond pads and one or more first test pads on a first side of the first die and a first capping layer over each of the one or more first test pads. The method further includes contacting at least one first capping layer with one or more first test probes to perform a first test, identifying the first die as a known good die based on a result of the first test, and removing at least a portion of each first capping layer.
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