Semiconductor device and formation method thereof

Abstract

A method of forming a semiconductor device comprises the following steps. A first active region and a second active region are formed over a substrate. An isolation feature is formed over the substrate and between the first active region and the second active region along a direction. A first gate structure is formed over the first active region and a second gate structure over the second active region. A gate isolation feature is formed disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion over the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a k value less than about

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Prior Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor components are generally manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] In some embodiments, a method of forming a semiconductor device includes the following steps: forming a first active region and a second active region over a substrate; forming an isolation feature along a direction over the substrate and between the first active region and the second active region; forming a first gate structure over the first active region and a second gate structure over the second active region; forming a gate isolation feature disposed along this direction between the first gate structure and the second gate structure, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a dielectric constant of less than about 4.

[0005] In some embodiments, a method of forming a semiconductor device includes the following steps: forming a first active region and a second active region over a substrate; forming an isolation feature along a direction over the substrate and between the first active region and the second active region; forming a first gate structure over the first active region and a second gate structure over the second active region; forming a source / drain feature over the substrate; forming a contact etch-stop layer (CESL) extending along the sidewalls of the first gate structure and the second gate structure; forming an inter-dielectric layer (ILD) over the CESL, wherein the CESL between the ILD layer and the source / drain feature includes a non-linear profile; forming a gate isolation feature disposed between the first gate structure and the second gate structure along this direction, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes a SiOC with a dielectric constant of less than about 4.

[0006] In some embodiments, a semiconductor device includes a first channel region and a second channel region, an isolation feature, a first gate stack, a second gate stack, a gate spacer, and a gate isolation feature. The first channel region and the second channel region extend over a substrate. The isolation feature is disposed over the substrate and between the first channel region and the second channel region. The first gate stack is disposed over the first channel region and the isolation feature. The second gate stack is disposed over the second channel region and the isolation feature. The gate spacer is disposed along a sidewall of the first gate stack, wherein the first gate stack includes a gate dielectric layer and a gate electrode above the gate dielectric layer, wherein the bottom surface of the gate spacer is lower than the top surface of the first channel region, and wherein a dielectric constant of the gate spacer is less than a dielectric constant of the gate dielectric layer. The gate isolation feature is disposed between the first gate stack and the second gate stack, wherein the gate isolation feature has a first curved sidewall. Simple Explanation of the Diagram

[0007] The various features disclosed herein are best understood in conjunction with the accompanying drawings from the following detailed description. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of each feature may be increased or decreased arbitrarily for clarity of explanation. Figure 1 illustrates an example of a gate-all-around field-effect transistor (GAA-FET) in a three-dimensional view according to some embodiments. Figures 2 through 5 and Figure 6A show the reference cross section A-A' shown in Figure 1, extending along the longitudinal axis of the gate region through the gate region. Figure 6B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin. Figure 7A shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 7B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin. Figure 8A shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 8B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin. Figure 9A shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 9B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin. Figure 10A shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 10B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 11A shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 11B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 11C shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 12A shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 12B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 12C shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 12D shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 13A shows the reference cross section A-A' shown in Figure 1, extending along the longitudinal axis of the gate region through the gate region. Figure 13B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 13C shows the reference cross section C-C' shown in Figure 1, extending along the longitudinal direction of the gate region through the source / drain region. Figure 14A shows the reference cross section A-A' shown in Figure 1, extending along the longitudinal axis of the gate region through the gate region. Figure 14B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 15A shows the reference cross section A-A' shown in Figure 1, extending along the longitudinal axis of the gate region through the gate region. Figure 15B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 16A shows the reference cross section A-A' shown in Figure 1, extending along the longitudinal axis of the gate region through the gate region. Figure 16B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 17A shows the reference cross section A-A' shown in Figure 1, extending along the longitudinal axis of the gate region through the gate region. Figure 17B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin and passing through the fin. Figure 17C is an enlarged cross-sectional view of the structure shown in Figure 17A. Figure 17D shows a top view of a GAA-FET in a gate cleaving process according to some embodiments of this disclosure. Figures 18A through 18G illustrate the gate cutting steps (i.e., the metal gate cutting steps) according to some embodiments. Figure 19A shows a top view of a GAA-FET in a gate cleaving process according to some embodiments of this disclosure. Figure 19B shows the reference cross section D-D' shown in Figure 19A. Figure 20A shows the reference cross section A-A' shown in Figure 1, extending along the longitudinal axis of the gate region through the gate region. Figure 20B shows the reference cross section B-B' shown in Figure 1, extending along the longitudinal axis of the fin. Implementation

[0008] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features so that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0009] Additionally, for ease of description, this document uses spatially relative terms (such as "below," "under," "lower part," "above," "upper part," and the like) to describe the relationship between one element or feature shown in the figures and another element or feature. Besides the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 230 degrees or in other orientations), and thus the spatially relative descriptive terms used herein can be interpreted in the same way. As used herein, "around," "about," "approximately," or "substantially" should generally mean within 20%, 10%, or 5% of a given value or range. The quantities given herein are approximate, meaning that unless explicitly stated otherwise, the terms "around," "about," "approximately," or "substantially" can be inferred. Those skilled in the art will understand that dimensions can vary according to different technology nodes. Those skilled in the art will recognize that dimensions depend on the specific component type, the technology employed, the minimum feature size, and the like. Therefore, the terminology is intended to be interpreted in light of the technology being evaluated.

[0010] This disclosure generally relates to integrated circuit (IC) structures and methods of forming them, and more specifically to the fabrication of gate-all-around (GAA) transistors. It is also noted that this disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include transistors whose gate structures are formed on at least two sides of a channel region. Such multi-gate elements may include p-type metal-oxide-semiconductor (MOS) elements or n-type MOS elements. Due to their finned structure, specific examples may be presented and referred to herein as FinFETs. Embodiments of a type of multi-gate transistor referred to herein as gate-all-around (GAA) elements are also presented herein. GAA elements include any element whose gate structure or a portion thereof is formed on four sides of a channel region (e.g., around a portion of the channel region). Elements presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, and / or other suitable channel configurations. Embodiments of elements that may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure are presented herein. However, those skilled in the art will recognize that the teachings can be applied to a single channel (e.g., a single nanosheet) or any number of channels. Those skilled in the art will also recognize other instances of semiconductor devices that can benefit from the state of this disclosure.

[0011] In the fabrication of semiconductor devices, metal gates may comprise multiple layers, including a work function metal layer and a fill metal. The fill metal may be a material different from the work function metal layer to provide a suitable threshold voltage or conductivity for the semiconductor device. However, the etchant used to etch the fill metal can etch the work function metal layer at a faster etch rate, resulting in an opening with a recessed profile in the metal gate. Such recessed profiles often lead to void formation during cut metal gate (CMG) refill formation, as CMG refill formation is a conformal deposition process. Since subsequent dry etching processes used for source / drain via formation can easily etch through the voids and further etch the metal gate, resulting in undesirable electrical shorts between the source / drain contacts and the metal gate, or between the source / drain contacts, voids can cause missing metal gates. Other issues, such as chemical mechanical polishing (CMP) load problems and negative impacts on wafer acceptance testing (WAT), yield, and reliability, may unexpectedly arise.

[0012] Furthermore, CMG refill can be achieved using a two-layer process. For example, a silicon nitride pad formed by atomic layer deposition (ALD) and a silicon oxide refill layer formed by ALD can be used to form a CMG refill for metal gate isolation. Oxygen plasma oxidation in plasma-enhanced ALDs (ALDs) used to form silicon oxide can be detrimental to the high-dielectric-constant gate dielectric layer and the metal gate, resulting in a threshold voltage (Vt) shift and affecting device performance.

[0013] Some embodiments disclosed herein provide a method for forming a gate isolation structure as CMG refill using oxidant-free deposition via siloxane precursor activation and plasma polymerization. This mitigates oxidation of the metal gate and reduces threshold voltage (Vt) offset. The oxidant-free deposition can be performed using bottom-up flowable deposition to address porosity issues from the PEALD process and prevent electrical short circuits between the source / drain contacts. The gate isolation structure may include SiOCx with a low dielectric constant (e.g., below about 4) to reduce resistance-capacitance (RC) delay effects by reducing the effective capacitance (Ceff), thus improving ring oscillator (RO) performance.

[0014] Figure 1 illustrates an example of a GAA-FET (e.g., nanowire FET, nanosheet FET, or similar) in a three-dimensional view according to some embodiments. The GAA-FET includes a nanostructure 104 (e.g., nanosheet, nanowire, nanoring, nanoplate, or other structure having a nanometer-scale size (e.g., several nanometers)) above fins 102 on a substrate 100 (e.g., a semiconductor substrate), wherein the nanostructure 104 acts as a channel region for the GAA-FET. The nanostructure 104 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 106 are disposed between adjacent fins 102, which may protrude over and from adjacent isolation regions 106. Although the isolation regions 106 are described / shown as separate from the substrate 100, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and isolation regions. Additionally, although the bottom portion of fin 102 is shown as a single continuous material with substrate 100, the bottom portion of fin 102 and / or substrate 100 may comprise a single material or a plurality of materials. In this context, fin 102 represents a portion extending between adjacent isolation regions 106.

[0015] A gate dielectric layer 110 is located above the top surface of the fin 102 and along the top, sidewalls, and bottom surface of the nanostructure 104. A gate electrode 112 is located above the gate dielectric layer 110. Epitaxial source / drain regions 108 are formed on the fin 102 on opposite sides of the gate dielectric layer 110 and the gate electrode 112.

[0016] Figure 1 further illustrates reference cross sections used in later figures. Cross section A-A' is along the longitudinal axis of the gate electrode 112 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 108 of the GAA-FET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fin 102 of the GAA-FET, and in a direction, for example, between the current flow directions between the epitaxial source / drain regions 108 of the GAA-FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the GAA-FET. For clarity, these reference cross sections are represented in subsequent figures.

[0017] Some embodiments discussed herein are described in the context of using a GAA-FET with the gate formed in a post-processing step. In other embodiments, a gate-first process may be used. Furthermore, some embodiments are contemplated for use in planar devices such as planar FETs or fin field-effect transistors (FinFETs).

[0018] Figures 2 through 20B are cross-sectional and top views of intermediate stages in the manufacture of a GAA-FET according to some embodiments.

[0019] In Figure 2, a substrate 100 is provided. Substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 100 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 100 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide indium phosphide; or combinations thereof.

[0020] Further, in Figure 2, a multilayer stack 201 is formed over the substrate 100. The multilayer stack 201 includes alternating layers of first semiconductor layers 202A to 202C (collectively referred to as first semiconductor layers 202) and second semiconductor layers 204A to 204C (collectively referred to as second semiconductor layers 204). The second semiconductor layer 204 may be referred to as a second semiconductor structure or a second active region. For illustrative purposes and as discussed in more detail below, the first semiconductor layer 202 will be removed, and the second semiconductor layer 204 will be patterned to form the channel region of the GAA-FET.

[0021] For illustrative purposes, the multilayer stack 201 is shown as three layers including each of a first semiconductor layer 202 and a second semiconductor layer 204. In some embodiments, the multilayer stack 201 may include any number of first semiconductor layers 202 and second semiconductor layers 204. Each of the layers in the multilayer stack 201 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the second semiconductor layer 204 may be formed of a semiconductor material suitable for use as a channel region for a GaA-FET, such as silicon, silicon carbon, silicon germanium, or the like.

[0022] The first semiconductor material and the second semiconductor material may be materials that have high etch selectivity to each other. Therefore, the first semiconductor layer 202 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 204 of the second semiconductor material, thereby allowing the second semiconductor layer 204 to be used as a channel region for the GAA-FET.

[0023] Referring now to Figure 3, according to some embodiments, fin structure 206 is formed in substrate 100 and nanostructure 203 is formed in multilayer stack 201. In some embodiments, nanostructure 203 and fin structure 206 may be formed in multilayer stack 201 and substrate 100 respectively by etching trenches in multilayer stack 201 and substrate 100. Each fin structure 206 and the overlying nanostructure 203 may be collectively referred to as a semiconductor fin extending from substrate 100. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. Etching may be anisotropic. The nanostructure 203 is formed by etching a multilayer stack 201. The first nanostructures 202A to 202C (collectively referred to as the first nanostructure 202) are further defined from the first semiconductor layer 202, and the second nanostructures 204A to 204C (collectively referred to as the second nanostructure 204) are defined from the second semiconductor layer 204. The first nanostructure 202 and the second nanostructure 204 can be further collectively referred to as nanostructure 203.

[0024] Fin structure 206 and nanostructure 203 can be patterned by any suitable method. For example, fin structure 206 and nanostructure 203 can be patterned using one or more photolithography processes (including dual-patterning or multi-patterning processes). Typically, dual-patterning or multi-patterning processes combine photolithography and self-aligned processes, thereby allowing the production of patterns with, for example, smaller pitches compared to those that could be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fin structure 206. Although each of fin structure 206 and nanostructure 203 is shown as having a consistently consistent width, in other embodiments, fin structure 206 and / or nanostructure 203 may have tapered sidewalls such that the width of each of fin structure 206 and / or nanostructure 203 continuously increases in the direction toward substrate 100. In such embodiments, each of the nanostructures 203 may have a different width and be trapezoidal in shape.

[0025] In Figure 4, a shallow trench isolation (STI) region 208 is formed adjacent to the fin structure 206. The STI region 208 can be formed by depositing an insulating material over the substrate 100, the fin structure 206, and the nanostructure 203, and between adjacent fin structures 206. The STI region 208 may be referred to as an isolation structure or isolation feature. The insulating material may be an oxide (such as silicon oxide), a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 203. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 100, fin structure 206, and nanostructure 203. Subsequently, a filler material (such as those discussed above) may be formed over the liner.

[0026] The removal process is then applied to the insulating material to remove excess insulating material over the nanostructure 203. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, a combination thereof, or the like, may be used. The planarization process exposes the nanostructure 203 such that, after the planarization process is completed, the top surfaces of the nanostructure 203 and the insulating material are flush.

[0027] The insulating material is then recessed to form the STI region 208. The insulating material is recessed such that the upper portion of the fin structure 206 protrudes between adjacent STI regions 208. Additionally, the top surface of the STI region 208 may, as shown, have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof. The top surface of the STI region 208 may be formed into a flat, raised, and / or recessed state by appropriate etching. The STI region 208 can be recessed using acceptable etching processes, such as processes that are selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate compared to the materials of the fin structure 206 and the nanostructure 203). For example, oxide removal can be used, employing, for example, diluted hydrofluoric (dHF) acid.

[0028] The fabrication process described above with respect to Figures 2 through 4 is merely one example of how the fin structure 206 and nanostructure 203 can be formed. In some embodiments, the fin structure 206 and / or nanostructure 203 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed above the top surface of substrate 100, and trenches can be etched through the dielectric layer to expose the underlying substrate 100. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fin structure 206 and / or nanostructure 203. The epitaxial structure may comprise alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the epitaxially grown material can be doped in situ during growth, which avoids prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0029] Further, in Figure 4, suitable wells (not shown separately) may be formed in fin structure 206 and / or nanostructure 203. In some embodiments with different well types in different device regions (e.g., NFET regions and PFET regions), different placement steps may be implemented using photoresist or other masks (not shown separately). For example, photoresist may be formed over fin structure 206 and STI region 208 in both the NFET and PFET regions. The photoresist is patterned to expose the PFET region. The photoresist may be formed using spin coating techniques and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, placement of a first impurity (e.g., an n-type impurity, such as phosphorus, arsenic, antimony, or the like) is performed in the PFET region, and the photoresist may act as a mask to substantially prevent the placement of the first impurity into the NFET region. After placement, the photoresist is removed, such as by an acceptable ashing process.

[0030] After or before the placement of the PFET region, a photoresist or other mask (not shown separately) is formed over the fin structure 206, nanostructure 203, and STI region 208 in both the NFET and PFET regions. The photoresist is then patterned to expose the NFET region. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, placement of a second impurity (e.g., a p-type impurity, such as boron, boron fluoride, indium, or the like) can be performed in the NFET region, and the photoresist can act as a mask to substantially prevent the placement of the p-type impurity into the PFET region. After placement, the photoresist can be removed, such as by an acceptable ashing process.

[0031] After one or more well implantations in the NFET and PFET regions, annealing can be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, although in-situ and implantation doping can be used together.

[0032] In Figure 5, a dummy dielectric layer 210 is formed on fin structure 206 and / or nanostructure 203. The dummy dielectric layer 210 may be, for example, silicon oxide, silicon nitride, combinations thereof, or similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 212 is formed over the dummy dielectric layer 210, and a masking layer 214 is formed over the dummy gate layer 212. The dummy gate layer 212 may be formed over the dummy dielectric layer 210 and then planarized, such as by CMP. The masking layer 214 may be deposited over the dummy gate layer 212. The dummy gate layer 212 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (polySiGe), metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer 212 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 212 may be made of other materials that have high etch selectivity compared to etching of the isolation region. The masking layer 214 may include, for example, silicon nitride, silicon oxynitride, or the like. Note that, for illustrative purposes only, the dummy dielectric layer 210 is illustrated as covering only the fin structure 206 and the nanostructure 203. In some embodiments, the dummy dielectric layer 210 may be deposited such that the dummy dielectric layer 210 covers the STI region 208, such that the dummy dielectric layer 210 extends between the dummy gate layer 212 and the STI region 208.

[0033] In Figures 6A and 6B, the mask layer 214 (see Figure 5) can be patterned using acceptable photolithography and etching techniques to form a mask 218. The pattern of the mask 218 can then be transferred to the dummy gate layer 212 and the dummy dielectric layer 210 to form dummy gate 216 and dummy gate dielectric layer 211, respectively. The dummy gate 216 covers the corresponding channel region of the fin structure 206. The pattern of the mask 218 can be used to separate each of the dummy gates 216 from the adjacent dummy gate 216 entities. The dummy gate 216 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the corresponding fin structure 206.

[0034] In Figures 7A and 7B, a first spacer layer 220 and a second spacer layer 222 are formed over the structures shown in Figures 6A and 6B, respectively. The first spacer layer 220 and the second spacer layer 222 will then be patterned to serve as spacers for forming self-aligned source / drain regions. In Figures 7A and 7B, the first spacer layer 220 is formed on the top surface of the STI region 208; on the top surface and sidewalls of the fin structure 206, nanostructure 203, and mask 218; and on the sidewalls of the dummy gate 216 and the dummy gate dielectric layer 211. The second spacer layer 222 is deposited over the first spacer layer 220. The first spacer layer 220 can be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 222 may be formed of a material having a different etching rate than the material of the first spacer layer 220 (such as silicon oxide, silicon nitride, silicon oxynitride, or the like), and may be deposited by CVD, ALD, or the like.

[0035] In Figures 8A and 8B, the first spacer layer 220 and the second spacer layer 222 are etched to form the first spacer 221 and the second spacer 223. As will be discussed in more detail below, the first spacer 221 and the second spacer 223 act on the self-aligned, subsequently formed source and drain regions (collectively referred to as the source / drain regions), and protect the sidewalls of the fin structure 206 and / or nanostructure 203 during subsequent processing. The first spacer layer 220 and the second spacer layer 222 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or similar. In some embodiments, the material of the second spacer layer 222 has a different etching rate than the material of the first spacer layer 220, such that when the second spacer layer 222 is patterned, the first spacer layer 220 can act as an etching stop layer, and when the first spacer layer 220 is patterned, the second spacer layer 222 can act as a mask. For example, the second spacer layer 222 can be etched using an anisotropic etching process, wherein the first spacer layer 220 acts as an etching stop layer, and the remaining portion of the second spacer layer 222 forms the second spacer 223 as shown in Figure 8A. Subsequently, the second spacer 223 acts as a mask when etching the exposed portion of the first spacer layer 220, thereby forming the first spacer 221 as shown in Figure 8A.

[0036] As shown in Figure 8A, the first spacer 221 and the second spacer 223 are disposed on the sidewalls of the fin structure 206 and / or the nanostructure 203. In some embodiments, spacers 221 and 223 remain only partially on the sidewalls of the fin structure 206. In some embodiments, no spacers remain on the sidewalls of the fin structure 206. As shown in Figure 8B, in some embodiments, the second spacer layer 222 may be removed over the first spacer layer 220 adjacent to the mask 218, the dummy gate 216, and the dummy gate dielectric layer 211, and the first spacer 221 is disposed on the sidewalls of the mask 218, the dummy gate 216, and the dummy gate dielectric layer 211. In other embodiments, a portion of the second spacer layer 222 may remain over the first spacer layer 220 adjacent to the mask 218, the dummy gate 216, and the dummy gate dielectric layer 211.

[0037] In some embodiments, the first spacer 221 (also referred to as the gate spacer) on the gate sidewall has a small thickness (e.g., in the range of about 1 nm to about 10 nm) to reduce the gate-to-gate spacing without significantly reducing the source / drain region size. In some embodiments, the first spacer 221 on the gate sidewall is formed of a low dielectric constant (low k) material (e.g., porous silicon oxide) having a dielectric constant value of, for example, less than about 3.5. The low dielectric constant material can help reduce, for example, the parasitic capacitance between the subsequently formed metal gate and the source / drain contacts.

[0038] The above disclosure generally describes a process for forming spacers. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different sequence of steps may be used (e.g., the first spacer 221 may be patterned before the deposition of the second spacer layer 222), additional spacers may be formed and removed, and / or the like.

[0039] In Figures 9A and 9B, according to some embodiments, a source / drain groove 226 is formed in the fin structure 206, the nanostructure 203, and the substrate 100. Subsequently, an epitaxial source / drain region is formed in the source / drain groove 226. The source / drain groove 226 may extend through the first nanostructure 202 and the second nanostructure 204 and into the substrate 100. As shown in Figure 9A, the bottom surface of the source / drain groove 226 may be flush with the top surface of the STI region 208, as an example. In some other embodiments, the fin structure 206 may be etched such that the bottom surface of the source / drain groove 226 is disposed below or above the top surface of the STI region 208. The source / drain recess 226 can be formed by etching the fin structure 206, nanostructure 203, and substrate 100 using an anisotropic etching process (such as RIE, NBE, or similar). During the etching process used to form the source / drain recess 226, a first spacer 221, a second spacer 223, and a mask 218 shield portions of the fin structure 206, nanostructure 203, and substrate 100. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 203 and / or the fin structure 206. A timed etching process can be used to terminate the etching of the source / drain recess 226 after the source / drain recess 226 has reached a target depth.

[0040] In Figures 10A and 10B, portions of the sidewalls of the layer of nanostructure 203 formed from the first semiconductor material (e.g., first nanostructure 202) exposed by the source / drain recess 226 are etched to form sidewall recesses 228 between corresponding second nanostructures 204. Although the sidewalls of the first nanostructure 202 in the sidewall recesses 228 are shown as straight as in Figure 10B, the sidewalls may be recessed or raised. The sidewalls may be etched using an isotropic etching process (such as wet etching or the like). In some embodiments, where the first nanostructure 202 comprises, for example, SiGe, and the second nanostructure 204 comprises, for example, Si or SiC, a dry etching process having tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first nanostructure 202.

[0041] In Figures 11A to 11C, internal spacers 230 are formed in sidewall recesses 228. Internal spacers 230 can be formed by depositing an internal spacer layer (not shown separately) over the structure shown in Figures 10A and 10B. Internal spacers 230 serve as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in source / drain recesses 226, and the first nanostructure 202 will be replaced by a corresponding gate structure.

[0042] The internal spacer layer can be deposited using conformal deposition processes (such as CVD, ALD, or similar). The internal spacer layer can comprise materials such as silicon nitride or silicon oxynitride, although any suitable material can be used, such as low-k materials with a dielectric constant value less than about 3.5. The internal spacer layer can then be anisotropically etched to form internal spacers 230. Although the outer walls of the internal spacers 230 are shown as flush with the sidewalls of the second nanostructure 204, the outer walls of the internal spacers 230 may extend beyond or be recessed from the sidewalls of the second nanostructure 204.

[0043] Furthermore, although the outer walls of the internal spacer 230 are shown as straight in Figure 11B, the outer walls of the internal spacer 230 may be recessed or convex. As an example, Figure 11C shows an embodiment in which the sidewalls of the first nanostructure 202 are recessed, the outer walls of the internal spacer 230 are recessed, and the internal spacer is recessed from the sidewalls of the second nanostructure 204. The internal spacer layer may be etched by anisotropic etching processes (such as RIE, NBE, or similar). The internal spacer 230 may be used to prevent subsequent etching processes (such as etching processes for forming gate structures) from damaging the subsequently formed source / drain regions (such as the epitaxial source / drain regions 232 discussed below with respect to Figures 12A to 12D).

[0044] In Figures 12A through 12D, epitaxial source / drain regions 232 are formed in source / drain recesses 226. In some embodiments, the epitaxial source / drain regions 232 may apply stress to the second nanostructure 204, thereby improving device performance. As shown in Figure 12B, the epitaxial source / drain regions 232 are formed in the source / drain recesses 226 such that each dummy gate 216 is disposed between corresponding adjacent pairs of the epitaxial source / drain regions 232. In some embodiments, a first spacer 221 is used to separate the epitaxial source / drain regions 232 from the dummy gate layer 212, and an inner spacer 230 is used to separate the epitaxial source / drain regions 232 from the first nanostructure 202 at an appropriate lateral distance, such that the epitaxial source / drain regions 232 are not short-circuited with the gate of the subsequently formed GAA-FET.

[0045] In some embodiments, the epitaxial source / drain region 232 may include any acceptable material suitable for an n-type GAA-FET. For example, if the second nanostructure 204 is silicon-based, the epitaxial source / drain region 232 may include a material that applies tensile strain to the second nanostructure 204, such as silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. In some embodiments, the epitaxial source / drain region 232 may include any acceptable material suitable for a p-type GAA-FET. For example, if the second nanostructure 204 is silicon-based, the epitaxial source / drain region 232 may contain a material that applies compressive strain to the second nanostructure 204, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 232 may have a surface protruding from the corresponding upper surface of the nanostructure 203 and may have facets.

[0046] The epitaxial source / drain region 232 can be formed by implanting dopants, followed by annealing. The source / drain region can have an impurity concentration between about 1 x 10¹⁷ atoms / cm³ and about 1 x 10²² atoms / cm³. The n-type and / or p-type impurities used for the source / drain region can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain region 232 can be doped in situ during growth.

[0047] As a result of the epitaxial process used to form the epitaxial source / drain regions 232, the upper surface of the epitaxial source / drain regions 232 has facets that extend laterally outward beyond the sidewalls of the nanostructure 203. In some embodiments, these facets cause adjacent epitaxial source / drain regions 232 to merge, as shown in Figure 12A. In some other embodiments, adjacent epitaxial source / drain regions 232 remain separated after the epitaxial process is completed, as shown in Figure 12C. In the embodiments shown in Figures 12A and 12C, a first spacer 221 and a second spacer 223 may be formed to the top surface of the STI region 208, thereby blocking lateral epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 221 and the second spacer 223 may be adjusted to remove spacer material, thereby allowing the epitaxial growth area to extend to the surface of the STI region 208.

[0048] The epitaxial source / drain region 232 may comprise one or more semiconductor material layers. For example, the epitaxial source / drain region 232 may comprise a first semiconductor material layer 232A, a second semiconductor material layer 232B, and a third semiconductor material layer 232C, which are distinguished by dashed lines in Figures 12A and 12B. Any number of semiconductor material layers may be used in the epitaxial source / drain region 232. Each of the first semiconductor material layer 232A, the second semiconductor material layer 232B, and the third semiconductor material layer 232C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 232A may have a dopant concentration lower than that of the second semiconductor material layer 232B and higher than that of the third semiconductor material layer 232C. In an embodiment in which the epitaxial source / drain region 232 comprises three semiconductor material layers, a first semiconductor material layer 232A may be deposited, a second semiconductor material layer 232B may be deposited over the first semiconductor material layer 232A, and a third semiconductor material layer 232C may be deposited over the second semiconductor material layer 232B.

[0049] Figure 12D illustrates an embodiment in which the sidewalls of the first nanostructure 202 are recessed, the outer sidewalls of the internal spacer 230 are recessed, and the internal spacer 230 is recessed from the sidewalls of the second nanostructure 204. As shown in Figure 12D, the epitaxial source / drain region 232 may be formed to contact the internal spacer 230 and may extend through the sidewalls of the second nanostructure 204.

[0050] In Figures 13A through 13C, an interlayer dielectric (ILD) layer 236 is deposited over the structure shown in Figures 12A through 12D. The ILD layer 236 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 234 is disposed between the ILD layer 236 and the epitaxial source / drain region 232, the second spacer 223, and the first spacer 221. CESL 234 may comprise a dielectric material such as SiN, SiOx, SiCN, SiON, SiOCN, Al2O3, HfO2, ZrO2, HfAlOx, and HfSiOx, or similar, which has an etch rate different from that of the overlying ILD layer 236. CESL 234 may extend along the sidewall of the dummy gate 216. In some embodiments, CESL 234 has a portion 235 with a non-linear profile between the ILD layer 236 and the epitaxial source / drain region 232.

[0051] In Figures 14A and 14B, a planarization process (such as chemical mechanical polishing) may be performed to make the top surface of the ILD layer 236 flush with the top surface of the dummy gate 216 or the mask 218. The planarization process may also remove the mask 218 on the dummy gate 216, and a portion of the first spacer 221 along the sidewall of the mask 218. After the planarization process, the dummy gate 216, the first spacer 221, and the top surface of the ILD layer 236 are flush within the process variation. Thus, the top surface of the dummy gate layer 212 is exposed through the ILD layer 236. In some embodiments, the mask 218 may remain, in which case the planarization process makes the top surface of the ILD layer 236 flush with the top surfaces of the mask 218 and the first spacer 221.

[0052] In Figures 15A and 15B, the dummy gate 216 and the mask 218 (if present) are removed in one or more etching steps, forming a gate trench 238 between corresponding gate spacers 221. In some embodiments, a portion of the dummy gate dielectric layer 211 in the gate trench 238 may also be removed. In some embodiments, the dummy gate 216 and the dummy gate dielectric layer 211 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 216 at a faster rate than the first spacer 221. Each gate trench 238 exposes and / or covers a portion of nanostructures 204, which will serve as channel regions in the subsequently completed GAA-FET. The nanostructures 204 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 232. During removal, when the dummy gate 216 is etched, the dummy gate dielectric layer 211 can be used as an etch stop layer. The dummy gate dielectric layer 211 can then be removed after the dummy gate 216 is removed.

[0053] In Figures 16A and 16B, the first nanostructure 202 in the gate trench is removed by an isotropic etching process (such as wet etching or similar) using an etchant selective to the material of the first nanostructure 202. In other words, the first nanostructure 202 is removed by a selective etching process that etches the first nanostructure 202 at a faster rate than it etches the second nanostructure 204, thus creating a space between the second nanostructures 204 (also referred to as a sheet-to-sheet space if the nanostructures 204 are nanosheets). This step can be referred to as a channel release process. At this intermediate processing step, the space between the second nanostructures 204 can be filled using ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the second nanostructure 204 can be referred to as a nanosheet, nanowire, nanoplate, or nanoring having a nanoscale size (e.g., several nanometers), depending on its geometry. For example, in some embodiments, the second nanostructure 204 may be trimmed into a substantially circular shape (i.e., cylindrical) due to the selective etching process used to completely remove the first nanostructure 202. In that case, the resulting second nanostructure 204 may be referred to as a nanoline.

[0054] In embodiments where the first nanostructure 202 comprises, for example, SiGe and the second nanostructure 204 comprises, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructure 202. In some embodiments, both the channel release step and the preceding step of laterally recessing the first nanostructure 202 (i.e., the steps shown in Figures 10A to 10B) employ a selective etching process that etches the first nanostructure 202 (e.g., SiGe) at a faster etch rate than etching the second nanostructure 204 (e.g., Si), and thus in some embodiments, the same etchant chemistry can be used for both steps. In this case, the etching time / duration of the channel release step is longer than the etching time / duration of the preceding step of laterally recessing the first nanostructure 202 in order to completely remove the sacrificial nanostructure 202.

[0055] Figure 17C is an enlarged cross-sectional view of the structure shown in Figure 17A. In Figures 17A through 17C, high-dielectric-constant / metal gate structures 240 are formed in gate trenches 238 to surround each of the nanosheets 204 suspended in the gate trenches 238. The high-dielectric-constant / metal gate structure 240 may be the final gate of a GAA FET. The gate structure 240, epitaxial source / drain regions 232, and channel regions (nanosheets 204) are used as transistors. The final gate structure may be a stack of high-dielectric-constant / metal gates; however, other compositions are also possible. In some embodiments, each of the high-dielectric-constant / metal gate structures 240 forms a gate associated with a multichannel provided by a plurality of nanosheets 204. For example, the high-dielectric-constant / metal gate structure 240 is formed within a sheet-to-sheet space provided by the release of the nanosheets 204. In various embodiments, the high-dielectric-constant / metal gate structure 240 includes an interface layer 242 formed around the nanosheet 204, a high-dielectric-constant gate dielectric layer 244 formed around the interface layer 242, and a gate metal layer 246 formed around the high-dielectric-constant gate dielectric layer 244 and filling the remaining portion of the gate trench 238. The formation of the high-dielectric-constant / metal gate structure 240 may include one or more deposition processes to form various gate materials, followed by a CMP process to remove excess gate material, resulting in the high-dielectric-constant / metal gate structure 240 having a top surface flush with the top surface of the ILD layer 236. As shown in the cross-sectional views of Figures 17A and 17C, the high-dielectric-constant / metal gate structure 240 surrounds each of the nanosheets 204 and is therefore referred to as the gate of a GAA FET. In some embodiments, the dielectric constant of the first spacer 221 is less than the dielectric constant of the high-dielectric-constant gate dielectric layer 244.

[0056] In some embodiments, interface layer 242 is formed by silicon oxide on the exposed surface of the semiconductor material in gate trench 238 using, for example, thermal oxidation, chemical oxidation, wet oxidation, or the like. As a result, the surface portion of the nanosheet 204 exposed in gate trench 238 is oxidized to silicon oxide to form interface layer 242.

[0057] In some embodiments, the high dielectric constant gate dielectric layer 244 includes a dielectric material such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), similar materials, or combinations thereof.

[0058] In some embodiments, the gate metal layer 246 comprises one or more metal layers. For example, the gate metal layer 246 may include one or more work function metal layers stacked on top of another and fill metal filling the remaining portion of the gate trench 238. The one or more work function metal layers in the gate metal layer 246 provide a suitable work function for the high dielectric constant / metal gate structure 240. For an n-type GAA FET, the gate metal layer 246 may include one or more n-type work function metal (N-metal) layers. The n-type work function metal may exemplary include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type GAA FET, the gate metal layer 246 may include one or more p-type work function metal (P-metal) layers. The p-type work function metal may include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the filler metal in the gate metal layer 246 may include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicon, cobalt silicon, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0059] Figures 18A through 18G illustrate a gate dicing step (i.e., a metal gate dicing step) according to some embodiments. In this step, a patterned mask (e.g., a patterned photoresist) is first formed over substrate 100, except for CMG target regions 256a, 256b, 256c, as shown in Figure 17D, and then one or more etching processes are performed on the exposed CMG target regions 256a, 256b, 256c to form gate dicing openings 266 (see Figure 18C). Each gate dicing opening breaks a continuous high-dielectric-constant / metal gate structure 240 into individual gate structures 240a, 240b (see Figure 19B) and breaks a continuous gate refill metal structure 254 into individual gate refill metal structures 254a, 254b. In some embodiments, CMG target regions 256a may be located between the first spacers 221, CMG target regions 256b may extend across the first spacers 221, and CMG target regions 256c may extend across the gate refill metal structures 254a, 254b. Subsequently, a gate isolation structure 268 is formed in the gate cutout 266 to electrically isolate the individual gate structures 240a, 240b and the gate refill metal structures 254a, 254b. The gate isolation structure 268 may then be disposed between and interface with the first spacers 221.

[0060] As shown in Figure 18A, one or more hard masking layers may be formed over the gate metal layer 246 of the high dielectric constant / metal gate structure 240. Two hard masking layers 262 and 264 are shown in this example. In one embodiment, hard masking layer 262 comprises titanium nitride, while hard masking layer 264 comprises silicon nitride. In this embodiment, the material used for hard masking layer 262 is selected to have good adhesion to the gate metal layer 246 but not to react with the gate metal layer 246. Hard masking layers 262 and 264 may be deposited using CVD, PVD, ALD, or other suitable methods.

[0061] Referring to Figure 18B, hard mask layers 262 and 264 are patterned (e.g., etched) to provide openings 266 for exposing the gate metal layer 246. In one example, patterned photoresist is formed over hard mask layers 262 and 264 by photoresist coating, exposure, post-exposure baking, and development. Hard mask layers 262 and 264 can then be etched using the patterned photoresist as an etching mask to form openings 266. The etching process may include wet etching, dry etching, reactive ion etching, or other suitable etching methods. Subsequently, the patterned photoresist is removed, for example, by resist stripping. Note that the sidewalls of the openings 266 at hard mask layers 262 and 264 are vertical or nearly vertical.

[0062] The gate metal layer 246 can then be etched through the opening 266. Patterned hard mask layers 262 and 264 protect the remainder of the gate metal layer 246 from the etching process. Referring to Figure 18C, the opening 266 can extend downward and through the gate metal layer 246 into the STI region 208. In some embodiments, the opening 266 can have a curved bottom surface. Specifically, the etching process is performed such that the opening 266 has a recessed profile. The etching process can use one or more etchants or mixtures of etchants to etch various layers in the gate metal layer 246. The etchant initially used to etch the fill metal can etch the lower volt-function metal layer at a faster rate, resulting in a laterally widened opening 266. For example, the gate metal layer 246 can have an upper sidewall S1, a middle sidewall S2, and a lower sidewall S3. The upper sidewall S1 and the lower sidewall S3 can be inclined relative to the top surface T1 of the gate metal layer 246. In some embodiments, the middle sidewall S2 can be curved and recessed. For example, the intermediate sidewall S2 can be referred to as a curved intermediate sidewall or a curved sidewall. In some embodiments, the opening 266 may have a top width 266T and a bottom width 266B that is smaller than the top width 266T. In other words, the opening 266 becomes narrower in the direction toward the substrate 100.

[0063] A gate isolation structure or gate isolation feature (see 268 in Figure 18G) may then be formed in opening 266. In some embodiments, gate isolation structure 268 may be formed by a flowable CVD (FCVD) process. Refer to Figure 18D. In some embodiments, the FCVD process for forming gate isolation structure 268 may be performed by pulsed first precursor 270, pulsed second precursor 272, and pulsed reactant 274 to opening 266 in a high dielectric constant / metal gate structure 240 above substrate 100. For example, first precursor 270 may include a siloxane precursor or a silicon-containing monomer including Si-OR groups, wherein R may be a hydrocarbon group, such as CH3 or C2H5, and second precursor 272 may include a siloxane precursor or a silicon-containing monomer including Si-H groups. In some embodiments, reactant 274 may include NHx gas, Ar gas, H2 gas, combinations thereof, or the like. The first precursor 270, the second precursor 272, and the reactant 274 can be oxidant-free. This reduces oxidation of the high dielectric constant / metal gate structure 240 and decreases the threshold voltage (Vt) shift.

[0064] In some embodiments, the first precursor 270 and the second precursor 272 can be activated by free radicals and electrons provided, for example, by reactant 274. In some embodiments, the first precursor 270, the second precursor 272, and the reactant 274 can be in the gas phase. The Si-OR group of the first precursor 270 can react with free radicals of the reactant 274, such as NHx*, Ar*, H*, e-, and thereby cleave to form Si-O* groups. The Si-H group of the second precursor 272 can react with free radicals of the reactant 274, such as NHx*, Ar*, H*, e-, and thereby cleave to form Si* groups. Subsequently, the Si-O* groups and the Si* groups can be crosslinked to form a product 275 comprising Si-O-Si groups; the crosslinking reaction between the Si-O* groups and the Si* groups can be referred to as plasma polymerization.

[0065] Referring to Figure 18E. When beginning the deposition of the gate isolation structure 268, due to the bottom-up flowable deposition, the gate isolation structure 268 may be deposited only on the bottom of the opening 266 and not on the top surface of the high-dielectric-constant / metal gate structure 240, as will be discussed in more detail below. In other words, the top surface of the high-dielectric-constant / metal gate structure 240 does not have the gate isolation structure 268. In some embodiments, the gate isolation structure 268 may include carbon. For example, the gate isolation structure 268 may include SiO, SiOC, or a combination thereof. The carbon concentration in the gate isolation structure 268 can be tuned by the materials of the first precursor 270, the second precursor 272, the cleavage of the Si-OR groups of the first precursor 270, and the cleavage of the Si-H groups of the second precursor 272 through the flux and / or density of free radicals (NHx*, Ar*, and H*) or electrons (e-) provided by the reactant 274.

[0066] In some embodiments, the flux and / or density of NHx*, Ar*, H*, and e- can be controlled by the plasma power and flow rate of NHx gas, Ar gas, and H2 gas during the FCVD process to form the gate isolation structure 268. For example, during the FCVD process of forming the gate isolation structure 268, the plasma power can be in the range of about 50 W to about 2000 W, the flow rate of NHx gas can be in the range of about 10 sccm to about 2000 sccm, and the temperature can be in the range of about 25°C to about 400°C. Since the gate isolation structure 268 is formed by oxidant-free deposition through siloxane precursor activation and plasma polymerization, oxidation of the metal gate can be mitigated and threshold voltage (Vt) shift can be reduced.

[0067] In some embodiments, post-plasma treatment may be performed to tune the carbon concentration in the gate isolation structure 268, which will be discussed in more detail below. In some embodiments, the gate isolation structure 268 may have a carbon atom concentration ranging from about 0% to about 60%. In some embodiments, the gate isolation structure 268 may have a dielectric constant value of about 2.5 to about 5, such as 4 or less. In some embodiments, the gate isolation structure 268 may include Si-C bonds, CO bonds, or combinations thereof, which can be observed by X-ray photoelectron spectroscopy (XPS) or Fourier transform infrared spectroscopy (FTIR). In some embodiments, the gate isolation structure 268 may have a dielectric constant value less than that of silicon nitride (e.g., 7) or less than that of silicon oxide (e.g., 4). The gate isolation structure 268 may include SiOCx with a low dielectric constant (such as less than about 4), and thus the resistance-capacitance (RC) delay effect can be reduced by reducing the effective capacitance (Ceff), thereby improving the performance of the ring oscillator (RO).

[0068] In some embodiments, the top width 266T of the opening 266 can be less than about 100 nm, such as in the range from about 1 nm to about 100 nm, making the top width 266T sufficiently narrow to increase the condensation rate of the product 275 used to form the gate isolation structure 268, which is beneficial for growing materials with increased molecular weight (MW). This increased molecular weight can lead to a high boiling point of the gate isolation structure 268. Therefore, bottom-to-top condensation of the gate isolation structure 268 becomes easier, which can promote bottom-up growth of the gate isolation structure 268. In other words, bottom-up growth deposition of the gate isolation structure 268 in the deep opening 266 can be achieved by capillary condensation. Undesirable porosity formation problems in the gate isolation structure 268 that may be caused by the PEALD process can be prevented. Electrical short circuits between the source / drain contacts can also be prevented.

[0069] Refer to Figure 18F. As previously discussed with respect to Figure 18E, due to the bottom-up growth of the gate isolation structure 268, the opening 266 can be filled by the gate isolation structure 268 as seamlessly or without pores.

[0070] After the opening 266 is filled by the gate isolation structure 268, a planarization operation (such as chemical mechanical polishing) can be performed on the structure in Figure 18F until the gate metal layer 246 is exposed, as shown in Figure 18G. Since the gate isolation structure 268 can be inherent to the contour of the opening 266, the gate isolation structure 268 can have a top width 268T and a bottom width 268B smaller than the top width 268T. For example, the gate isolation structure 268 can have a top portion A1, a middle portion A2, and a bottom portion A3, wherein the middle portion A2 is perpendicular between the top portion A1 and the bottom portion A3. In some embodiments, the top portion A1 can have opposing inclined sidewalls A1s, and the bottom portion A3 can have opposing inclined sidewalls A3s. The middle portion A2 can have opposing curved sidewalls A2s, such as protruding sidewalls. In other words, the curved sidewalls A2 can have a curvature greater than the curvature of the inclined sidewalls A1s and A3s. In some embodiments, the middle portion A2 may have a maximum width greater than the bottom width 268B.

[0071] Figure 19A shows a top view of the semiconductor element in Figure 18G after the gate dicing step, according to some embodiments of this disclosure. Figure 19B shows the reference cross-section D-D' shown in Figure 19A. The gate isolation structure 268 can break down the continuous high-dielectric-constant / metal gate structure 240 into individual gate structures 240a, 240b. In some embodiments, the gate isolation structure 268a may be between first spacers 221, the gate isolation structure 268b may extend across the first spacers 221, and the gate isolation structure 268c may extend across the gate refill metal structures 254a, 254b. Subsequently, the gate isolation structure 268a is formed in the gate dicing opening OP1 to electrically isolate the individual gate structures 240a, 240b and the gate refill metal structures 254a, 254b.

[0072] Figure 20A shows a reference cross-section A-A' extending along the longitudinal axis of the gate region through the gate region shown in Figure 1. Figure 20B shows a reference cross-section B-B' extending along the longitudinal axis of the fin through the fin shown in Figure 1. In some embodiments, the interconnect structure 248 may be disposed on the substrate 100. In some embodiments, the interconnect structure 248 of the semiconductor element may include a plurality of dielectric layers 2521, 2522, 2523, etch stop layers 2801, 2802, 2803, metal vias 2821, 2822, wires 257, and gate contacts 2581, source / drain contacts 2582. The metal vias 2821, 2822, wires 257, and / or gate contacts 2581, source / drain contacts 2582 may be routed through the dielectric layers 2521, 2522 and / or etch stop layers 2801, 2802 to connect the transistor to external electronic components. For example, as shown in Figures 20A to 20B, etch-stop layer 2801, dielectric layer 2521, etch-stop layer 2802, dielectric layer 2522, etch-stop layer 2803, and dielectric layer 2523 are arranged and stacked in a bottom-to-top order. Gate contact 2581 is routed through dielectric layer 2521 and / or etch-stop layer 2801 to connect between metal via 2821 and high-dielectric-constant / metal gate structure 240 and / or between conductors 257. Source / drain contact 2582 is routed through dielectric layer 2521, etch-stop layer 2801, CESL 234, and ILD layer 236 to connect between metal via 2822 and epitaxial source / drain region 232. In some embodiments, the wire 257, gate contact 2581, source / drain contact 2582, and metal vias 2821, 2822 may comprise a metal-based material with good electrical conductivity, such as copper (Cu). In some embodiments, a silicate layer 284 is formed at a portion of the epitaxial source / drain region 232 exposed at the bottom of the contact opening. The silicate layer 284 may be formed by depositing a metal (such as Ni, Co, or Ti) on the exposed portion of the epitaxial source / drain region 232, performing an annealing process that causes the metal to selectively react with the exposed portion of the epitaxial source / drain region 232, then removing unreacted portions of the metal, leaving the silicate layer 284 on the epitaxial source / drain region 232. In some embodiments, the conductivity of the silicate layer 284 is greater than the conductivity of the epitaxial source / drain region 232. In some embodiments, the source / drain contact 2582 has a conductivity greater than that of the silica layer 284.

[0073] In some embodiments, the interconnect structure 248 may be formed by a damascene process, a dual damascene process, a combination thereof, or the like. For example, a trench etching process may be performed to form a plurality of trenches. Subsequently, a metallic material such as copper may be provided in the trenches as a medium for electrical transmission. Thus, the interconnect structure 248 may be formed as part of an integrated circuit in a semiconductor device.

[0074] Based on the above discussion, it can be seen that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage necessary for all embodiments. One advantage is that by using oxidant-free deposition through siloxane precursor activation and plasma polymerization to form the gate isolation structure, oxidation of the gate metal layer 246 of the gate structure can be mitigated, and threshold voltage (Vt) offset can be reduced. Oxidant-free deposition can be performed using bottom-up flowable deposition to address porosity issues from the PEALD process and prevent electrical short circuits between the source / drain contacts. The gate isolation structure may include SiOCx with a low dielectric constant (such as below about 4) to reduce resistive-capacitive (RC) delay effects by reducing the effective capacitance (Ceff), thereby improving ring oscillator (RO) performance.

[0075] In some embodiments, a method of forming a semiconductor device includes the following steps: A first active region and a second active region are formed over a substrate. An isolation feature is formed over the substrate along a direction and between the first active region and the second active region. A first gate structure is formed over the first active region and a second gate structure is formed over the second active region. A gate isolation feature is formed, disposed along this direction between the first gate structure and the second gate structure, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a dielectric constant of less than about 4. In some embodiments, forming the gate isolation feature includes forming the gate isolation feature using flowable chemical vapor deposition. In some embodiments, forming the gate isolation feature includes pulsed a first precursor to the substrate, pulsed a second precursor to the substrate, and pulsed a reactant to the substrate to cleave the first precursor and the second precursor. In some embodiments, the first precursor is a siloxane precursor. In some embodiments, the first precursor includes Si-OR groups. In some embodiments, the second precursor is a siloxane precursor. In some embodiments, the second precursor includes Si-H groups. In some embodiments, the reactants comprise NHx gas, Ar gas, H2 gas, or combinations thereof. In some embodiments, the first precursor, the second precursor, and the reactants are oxidant-free.

[0076] In some embodiments, a method of forming a semiconductor device includes the following steps: A first active region and a second active region are formed over a substrate. An isolation feature is formed over the substrate along a direction and between the first active region and the second active region. A first gate structure is formed over the first active region and a second gate structure is formed over the second active region. A source / drain feature is formed over the substrate. A contact etch-stop layer (CESL) extending along the sidewalls of the first gate structure and the sidewalls of the second gate structure is formed. An interlayer dielectric (ILD) layer is formed over the CESL, wherein the CESL between the ILD layer and the source / drain feature includes a non-linear profile. A gate isolation feature is formed along this direction between the first gate structure and the second gate structure, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a dielectric constant of less than about 4. In some embodiments, the gate isolation feature has an upper sidewall, a curved intermediate sidewall, and a lower sidewall, and the curved intermediate sidewall is between the upper and lower sidewalls. In some embodiments, the curved intermediate sidewall is convex. In some embodiments, a curved intermediate sidewall is attached to the gate isolation feature. In some embodiments, the gate isolation feature has a top width different from the bottom width. In some embodiments, the gate isolation feature has a top width greater than the bottom width. In some embodiments, the gate isolation feature contains a carbon concentration ranging from about 0% to about 60%. In some embodiments, forming the gate isolation feature involves bottom-up growth of the gate isolation feature.

[0077] In some embodiments, a semiconductor element includes a first channel region and a second channel region extending above a substrate, an isolation feature disposed above the substrate and between the first channel region and the second channel region, a first gate stack disposed above the first channel region and the isolation feature, a second gate stack disposed above the second channel region and the isolation feature, a gate spacer disposed along the sidewall of the first gate stack, and a gate isolation feature disposed between the first gate stack and the second gate stack. The first gate stack includes a gate dielectric layer and a gate electrode above the gate dielectric layer, wherein the bottom surface of the gate spacer is lower than the top surface of the first channel region, and wherein the dielectric constant of the gate spacer is less than the dielectric constant of the gate dielectric layer. The gate isolation feature has a first curved sidewall. In some embodiments, the gate isolation feature includes a second curved sidewall opposite to the first curved sidewall. In some embodiments, the gate isolation feature is seamless.

[0078] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0079] 100:Substrate 102: Fins 104: Nanostructure 106: Isolation Area 108: Epitaxial Source / Drain Region 110: Gate dielectric layer 112: Gate electrode 201: Multi-layer stacking 202A: First semiconductor layer, first nanostructure 202B: First semiconductor layer, first nanostructure 202C: First semiconductor layer, first nanostructure 203: Nanostructure 204: Second semiconductor layer, nanosheet, second nanostructure 204A: Second semiconductor layer, second nanostructure 204B: Second semiconductor layer, second nanostructure 204C: Second semiconductor layer, second nanostructure 206: Fin Structure 208: STI area 210: Dummy Dielectric Layer 211: Dummy gate dielectric layer 212: Virtual gate layer 214: Masking layer 216: Dummy gate 218: Mask 220: First spacer layer 221: First spacer 222: Second spacer layer 223: Second spacer 226: Source / Drain Groove 228: Sidewall Groove 230: Internal spacers 232: Epitaxial Source / Drain Region 232A: First semiconductor material layer 232B: Second semiconductor material layer 232C: Third semiconductor material layer 234: Contact Etching Termination Layer 235: Part 236: ILD layer 238: Gate trench 240: High dielectric constant / metal gate structure 240a: Gate structure 240b: Gate structure 242: Interface Layer 244: High dielectric constant gate dielectric layer 246: Gate metal layer 248: Interconnection Structure 2521: Dielectric layer 2522: Dielectric layer 2523: Dielectric layer 254a: Gate Refill Metal Structure 254b: Gate Refill Metal Structure 256a: CMG target region 256b: CMG target area 256c: CMG target area 257: Conductor 2581: Gate Contact 262: Hard mask layer 264: Hard mask layer 266: Opening 266B: Bottom width 266T: Top width 268: Gate isolation structure 268a: Gate isolation structure 268B: Bottom width 268b: Gate isolation structure 268c: Gate isolation structure 268T: Top Width 270: First Precursor 272: Second Precursor 274: Pulse Reactant 275: Product 2801: Etching stop layer 2802: Etching stop layer 2803: Etching stop layer 2821: Metal through hole 284: Silicon layer A-A': Reference cross section A1: Top section A1s: Inclined sidewall A2: Middle section A2s: Curved sidewall A3: Bottom section A3s: Sloping sidewall B-B': Reference cross section C-C': Reference cross section D-D': Reference cross section OP1: Gate Cut-off Opening S1: Upper sidewall S2: Middle sidewall S3: Lower sidewall T1: Top surface

[0080] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: forming a first active region and a second active region over a substrate; forming an isolation feature over the substrate along a direction and between the first active region and the second active region; forming a first gate structure over the first active region and forming a second gate structure over the second active region; and forming a gate isolation feature disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes a SiOC with a dielectric constant of less than about 4, wherein forming the gate isolation feature comprises: pulse a first precursor to the substrate; pulse a second precursor to the substrate; and pulse a reactant to the substrate to cleave the first precursor and the second precursor.

2. The method of claim 1, wherein forming the gate isolation feature comprises: forming the gate isolation feature using flowable chemical vapor deposition.

3. The method of claim 1, wherein the second precursor comprises a Si-H group.

4. The method as described in claim 1, wherein the first precursor is a siloxane precursor.

5. A method of forming a semiconductor device, comprising: forming a first active region and a second active region over a substrate; forming an isolation feature over the substrate along a direction and between the first active region and the second active region; forming a first gate structure over the first active region and a second gate structure over the second active region; forming a source / drain feature over the substrate; forming a contact etch stop layer (CESL) extending along a sidewall of the first gate structure and a sidewall of the second gate structure; forming an inter-dielectric layer (ILD) over the CESL, wherein the CESL between the ILD layer and the source / drain feature includes a non-linear profile; and forming a gate isolation feature disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion above the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes a SiOC with a dielectric constant of less than about 4, wherein forming the gate isolation feature includes: pulse a first precursor onto the substrate; A second precursor is pulsed onto the substrate; and a reactant is pulsed onto the substrate to cleave the first and second precursors.

6. The method of claim 5, wherein the gate isolation feature has an upper sidewall, a curved intermediate sidewall, and a lower sidewall, and the curved intermediate sidewall is located between the upper sidewall and the lower sidewall.

7. The method as described in claim 6, wherein the curved intermediate sidewall is convex.

8. A semiconductor device comprising: a first channel region and a second channel region extending over a substrate; an isolation feature disposed over the substrate and between the first channel region and the second channel region; a first gate stack disposed over the first channel region and the isolation feature; a second gate stack disposed over the second channel region and the isolation feature; a gate spacer disposed along a sidewall of the first gate stack, wherein the first gate stack includes a gate dielectric layer and a gate electrode above the gate dielectric layer, wherein a bottom surface of the gate spacer is lower than a top surface of the first channel region, wherein a dielectric constant of the gate spacer is less than a dielectric constant of the gate dielectric layer; and a gate isolation feature disposed between the first gate stack and the second gate stack, wherein a middle portion of the gate isolation feature has a first curved sidewall, and a bottom portion of the gate isolation feature has a sloping sidewall, the curvature of the first curved sidewall being greater than the curvature of the sloping sidewall.

9. The semiconductor element as claimed in claim 8, wherein the gate isolation feature includes a second curved sidewall opposite to the first curved sidewall.

10. The semiconductor element as claimed in claim 8, wherein the gate isolation feature is seamless.

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