Three-dimensional fanout packaging structure for a system-on chip and related methods

Abstract

The present invention relates to a system comprising a pair of System-on-Chip dies that includes through-silicon vias (TSVs) coupling the front side and the back side. A first fanout wafer with first fanout layers is coupled to the front side of the System-on-Chip dies and second fanout wafer with second fanout layers is coupled to the TSVs on the back side of the System-on-Chip dies. A carrier wafer is bonded to the second fanout wafer, collectively forming a 3D double-sided fanout structure that approximately doubles the available die-to-die routing bandwidth.

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