Semiconductor structure and fabrication method thereof

Abstract

A semiconductor structure includes a substrate having a bump pad thereon and a passivation layer disposed on the substrate. The passivation layer covers a perimeter of the bump pad and has a slot-shaped opening exposing a central region of the bump pad. An under bump metal (UBM) layer is disposed on the central region of the bump pad. A solder bump is disposed on the UBM layer. The solder bump has a flat top surface area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an improved semiconductor structure and its fabrication method. Prior Technology

[0002] In semiconductor wafer manufacturing, bumps are an important component connecting the wafer to external circuitry. However, existing bump structures, especially solder bar bumps, present some problems when using probes for electrical testing of the wafer, such as chip testing (CP testing). Solder bar bump designs are often used for high-current components, so during CP testing, each solder bar bump typically contacts multiple probes to distribute the current.

[0003] However, because the surface of the strip-shaped bump structure is arc-shaped, insufficient contact area between the probe and the bump structure during CP testing can easily lead to probe burn-out. This is because the surface of the strip-shaped bump structure is not flat enough, preventing the probe from making effective contact, resulting in excessive resistance and localized overheating. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor structure and its fabrication method to overcome the shortcomings or disadvantages of the prior art.

[0005] The present invention provides a semiconductor structure comprising a substrate having a bump pad thereon; a passivation layer disposed on the substrate, wherein the passivation layer covers a periphery of the bump pad and has a groove-shaped opening exposing a central region of the bump pad; an under-bump metal (UBM) layer disposed on the central region of the bump pad; and a solder bump disposed on the UBM layer, wherein the solder bump includes a flat top surface region.

[0006] According to an embodiment of the present invention, the slot-shaped opening has a length L and a width W, and the L / W ratio is greater than or equal to 1.

[0007] According to an embodiment of the present invention, the solder bump further includes a vertical sidewall.

[0008] According to an embodiment of the invention, the solder bump further includes a rounded corner located between the vertical sidewall and the flat top surface area.

[0009] According to an embodiment of the present invention, the bump pad comprises an aluminum pad.

[0010] Another aspect of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a bump pad thereon; forming a passivation layer on the substrate, wherein the passivation layer covers a periphery of the bump pad and has a groove-shaped opening to expose a central region of the bump pad; forming an under-bump metal (UBM) layer on the central region of the bump pad; forming a solder bump on the UBM layer; performing a reflow process on the solder bump; and after the reflow process, pressing the solder bump with a fixture at a predetermined temperature to form a flat top surface region on the solder bump.

[0011] According to an embodiment of the present invention, the slot-shaped opening has a length L and a width W, and the L / W ratio is greater than or equal to 1.

[0012] According to an embodiment of the present invention, the solder bump further includes a vertical sidewall.

[0013] According to an embodiment of the invention, the solder bump further includes a rounded corner located between the vertical sidewall and the flat top surface area.

[0014] According to an embodiment of the present invention, the bump pad comprises an aluminum pad.

[0015] According to an embodiment of the present invention, the predetermined temperature is between 250 and 280 degrees Celsius.

[0016] In another aspect, the present invention provides a semiconductor structure comprising a substrate having a bump pad thereon; a first passivation layer disposed on the substrate, wherein the first passivation layer covers a periphery of the bump pad and has a first groove opening exposing a central region of the bump pad; a second passivation layer disposed on the first passivation layer, wherein the second passivation layer has a second groove opening overlapping the first groove opening, wherein the size of the second groove opening is larger than the size of the first groove opening; an under-bump metal (UBM) layer disposed on the central region of the bump pad; and a solder bump filling the first groove opening and the second groove opening.

[0017] According to an embodiment of the present invention, the slot-shaped opening has a length L and a width W, and the L / W ratio is greater than or equal to 1.

[0018] According to an embodiment of the present invention, the second groove-shaped opening is concentric with and completely overlaps with the first groove-shaped opening.

[0019] According to an embodiment of the present invention, a stepped structure is provided between the second groove opening and the first groove opening.

[0020] According to an embodiment of the present invention, the second passivation layer has an inclined sidewall around the second groove opening, and wherein the UBM layer covers the inclined sidewall.

[0021] In another aspect, the present invention provides a semiconductor structure comprising a substrate having a bump pad thereon; a passivation layer disposed on the substrate, wherein the passivation layer covers a periphery of the bump pad and has a groove-shaped opening exposing a central region of the bump pad; a first copper layer disposed on the bump pad; an annular second copper layer disposed along the periphery of the bump pad, wherein the annular second copper layer partially overlaps the first copper layer, and wherein the annular second copper layer defines an opening; and a solder bump filled into the opening.

[0022] According to an embodiment of the present invention, the slot-shaped opening has a length L and a width W, and the L / W ratio is greater than or equal to 1.

[0023] According to an embodiment of the present invention, the solder bump extends to a top surface of the annular second copper layer.

[0024] According to an embodiment of the present invention, the thickness of the annular second copper layer is greater than the thickness of the first copper layer. Simple Explanation of the Diagram

[0025] Figure 1 is a top view schematic diagram of a strip-shaped protrusion structure according to an embodiment of the present invention. Figure 2 is a cross-sectional view along the tangent line I-I' in Figure 1. Figure 3 is a top view schematic diagram of a spherical protrusion structure according to another embodiment of the present invention. Figure 4 is a schematic cross-sectional view along the tangent line II-II' in Figure 3. Figures 5 through 8 illustrate the steps involved in forming the strip-shaped bump structure shown in Figure 2. Figure 9 is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. Figure 10 is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. Figures 11 through 20 illustrate the steps involved in forming the bump structure shown in Figure 9. Figure 21 illustrates the steps to form the bump structure in Figure 10. Figure 22 is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. Figure 23 is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. Figures 24 to 34 illustrate the steps involved in forming the bump structure shown in Figure 22. Figure 35 illustrates the steps to form the bump structure in Figure 23. Implementation

[0026] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments can be implemented. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0027] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0028] Please refer to Figures 1 through 4, wherein Figure 1 is a top view of a strip-shaped bump structure according to an embodiment of the present invention, Figure 2 is a cross-sectional view along the tangent I-I' direction in Figure 1, Figure 3 is a top view of a spherical bump structure according to another embodiment of the present invention, and Figure 4 is a cross-sectional view along the tangent II-II' direction in Figure 3. As shown in Figures 1 and 3, bump structures B1 and B2 respectively have a strip-shaped solder bump 240 and a spherical solder bump 240, which have a length L in the y-axis direction and a width W in the x-axis direction. The L / W ratio of the strip-shaped solder bump 240 in Figure 1 is greater than 1, and the L / W ratio of the spherical solder bump 240 in Figure 3 is approximately equal to 1.

[0029] As shown in Figures 1 and 2, a bump structure B1 is disposed on a substrate 100, such as a silicon substrate or a GaN substrate, but not limited thereto. At least one dielectric layer 110, such as a silicon oxide layer, is disposed on the substrate 100, but not limited thereto. Furthermore, bump pads 210 are disposed on the dielectric layer 110. According to an embodiment of the present invention, the bump pads 210 may, for example, comprise aluminum pads. According to an embodiment of the present invention, passivation layers 120 and 130 are further disposed on the substrate 100, wherein passivation layers 120 and 130 cover the periphery of the bump pads 210 and have a groove-shaped opening OP1, which has approximately a length L in the y-axis direction and approximately a width W in the x-axis direction, and the L / W ratio is greater than 1. According to embodiments of the present invention, passivation layer 120 and passivation layer 130 may, for example, contain polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), but are not limited thereto.

[0030] According to an embodiment of the present invention, the slot-shaped opening OP1 exposes the central region of the bump pad 210. According to an embodiment of the present invention, a sputtered layer 220, an under-bump metal (UBM) layer 230, and a solder bump 240 are sequentially formed on the central region of the bump pad 210. According to an embodiment of the present invention, the solder bump 240 is disposed on the UBM layer 230. According to an embodiment of the present invention, the sputtered layer 220 is, for example, TiW / Cu or Ti / Cu. According to an embodiment of the present invention, the UBM layer 230 is, for example, Ni, Cu, or Cu / Ni / Au. According to an embodiment of the present invention, the solder bump 240 may contain tin or any suitable solder material.

[0031] To avoid burn-out of the probes 310 and 320 due to insufficient contact area with the solder bump 240, a flat top surface area R is formed on the solder bump 240 to provide sufficient contact area for the probes 310 and 320 during CP testing. For example, if the dimensions D (width in the y-axis direction) of the probes 310 and 320 are 75µm and the spacing S is 150µm, then the required width of the flat top surface area R in the y-axis direction for the two probes 310 and 320 is 300µm (i.e., R ≥ 2D + S).

[0032] According to an embodiment of the present invention, the solder bump 240 may further include a vertical sidewall 240a. According to an embodiment of the present invention, the solder bump 240 further includes a fillet 240c located between the vertical sidewall 240a and the flat top surface region R.

[0033] As shown in Figures 3 and 4, similarly, bump structure B2 is disposed on substrate 100, such as a silicon substrate or a GaN substrate, but not limited thereto. At least one dielectric layer 110, such as a silicon oxide layer, is disposed on substrate 100, but not limited thereto. Furthermore, bump pads 210 are disposed on dielectric layer 110. According to an embodiment of the invention, bump pads 210 may, for example, comprise aluminum pads. According to an embodiment of the invention, passivation layers 120 and 130 are further disposed on substrate 100, wherein passivation layers 120 and 130 cover the periphery of bump pads 210 and have a groove-shaped opening OP1, which has approximately a length L in the y-axis direction and approximately a width W in the x-axis direction, and the L / W ratio is approximately equal to 1. According to an embodiment of the invention, passivation layers 120 and 130 may, for example, comprise PI, PBO, BCB, but are not limited thereto.

[0034] According to an embodiment of the present invention, the slot-shaped opening OP1 exposes the central region of the bump pad 210. According to an embodiment of the present invention, a sputtered layer 220, a UBM layer 230, and a solder bump 240 are sequentially formed on the central region of the bump pad 210. According to an embodiment of the present invention, the solder bump 240 is disposed on the UBM layer 230. According to an embodiment of the present invention, the sputtered layer 220 is, for example, TiW / Cu or Ti / Cu. According to an embodiment of the present invention, the UBM layer 230 is, for example, Ni, Cu, or Cu / Ni / Au. According to an embodiment of the present invention, the solder bump 240 may contain tin or any suitable solder material.

[0035] The solder bump 240 also has a flat top surface area R, which provides sufficient contact area for probes 310 and 320 during CP testing. For example, if the size D (width in the y-axis direction) of probes 310 and 320 is 75um and the spacing S is 150um, then the required width of the flat top surface area R in the y-axis direction for the two probes 310 and 320 is 300um.

[0036] Please refer to Figures 5 through 8, which illustrate the steps for forming the strip-shaped bump structure shown in Figure 2. As shown in Figure 5, a substrate 100 is first provided, for example, a silicon substrate or a GaN substrate, but not limited thereto. Next, at least one dielectric layer 110, for example, a silicon oxide layer, but not limited thereto, is formed on the substrate 100. Then, bump pads 210 are formed on the dielectric layer 110. According to an embodiment of the invention, the bump pads 210 may, for example, comprise aluminum pads. Then, a passivation layer 120 is formed on the substrate 100, the passivation layer 120 covering the periphery of the bump pads 210 and forming a groove-shaped opening OP.

[0037] Next, as shown in Figure 6, a passivation layer 130 is formed on the substrate 100. The passivation layer 130 covers the periphery of the bump pad 210 and forms a groove-shaped opening OP1, the size of which may be approximately equal to the size of the groove-shaped opening OP. According to embodiments of the present invention, the passivation layer 120 and the passivation layer 130 may, for example, contain poly(PI), poly(PBO), or poly(BCB), but are not limited thereto.

[0038] Next, a bumping process is performed, in which a sputtered layer 220, a UBM layer 230, and a solder bump 240 are sequentially formed on the central region of the bump pad 210. According to an embodiment of the invention, the solder bump 240 is disposed on the UBM layer 230. According to an embodiment of the invention, the sputtered layer 220 is, for example, TiW / Cu or Ti / Cu. According to an embodiment of the invention, the UBM layer 230 is, for example, Ni, Cu, or Cu / Ni / Au. According to an embodiment of the invention, the solder bump 240 may contain tin or any suitable solder material. After the reflow process, the solder bump 240 has a spherical surface 240s. According to an embodiment of the invention, as shown in Figure 1, the solder bump 240 has a length L and a width W, and the L / W ratio is greater than 1.

[0039] As shown in Figure 7, a hot pressing process is performed on the solder bump 240. At a predetermined temperature, a jig 400 presses down on the solder bump 240, softening and pressing it down to form a flat top surface area R on the solder bump 240. As shown in Figure 8, the jig 400 is finally removed, allowing the solder bump 240 to cool. According to an embodiment of the present invention, the jig 400 is, for example, a hot press plate, and the predetermined temperature is, for example, between 250 and 280 degrees Celsius.

[0040] Please refer to Figure 9, which is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. As shown in Figure 9, the bump structure B3 is also disposed on the substrate 100, for example, a silicon substrate or a GaN substrate, but is not limited thereto. The top view of the bump structure B3 can be a strip-shaped bump structure as shown in Figure 1, or a spherical bump structure as shown in Figure 3.

[0041] According to an embodiment of the present invention, at least one dielectric layer 110, such as a silicon oxide layer, is provided on the substrate 100, but is not limited thereto. Furthermore, bump pads 210 are provided on the dielectric layer 110. According to an embodiment of the present invention, the bump pads 210 may, for example, comprise aluminum pads. According to an embodiment of the present invention, a passivation layer 120 and passivation layers 131-134 are further provided on the substrate 100, wherein the passivation layers 120 and 131 cover the periphery of the bump pads 210 and have a groove-shaped opening OP1, which has approximately a length L in the y-axis direction and approximately a width W in the x-axis direction as shown in Figure 1, and the L / W ratio is greater than 1. According to an embodiment of the present invention, the passivation layers 120 and 131-134 may, for example, comprise PI, PBO, BCB, but are not limited thereto. According to an embodiment of the present invention, for example, the thickness of each passivation layer 131-134 may be approximately 20 micrometers.

[0042] Figure 9 illustrates four passivation layers 131-134; however, it should be understood that in other embodiments, there may be two or more passivation layers.

[0043] According to an embodiment of the present invention, a passivation layer 131 covers the periphery of the bump pad 210 and has a groove-shaped opening OP1, exposing the central region of the bump pad 210. According to an embodiment of the present invention, a passivation layer 132 is disposed on the passivation layer 131, wherein the passivation layer 132 has a groove-shaped opening OP2 that completely overlaps with the groove-shaped opening OP1, and wherein the size of the groove-shaped opening OP2 is larger than the size of the groove-shaped opening OP1. According to an embodiment of the present invention, a passivation layer 133 is disposed on the passivation layer 132, wherein the passivation layer 133 has a groove-shaped opening OP3 that completely overlaps with the groove-shaped opening OP2, and wherein the size of the groove-shaped opening OP3 is larger than the size of the groove-shaped opening OP2. According to an embodiment of the present invention, a passivation layer 134 is disposed on the passivation layer 133, wherein the passivation layer 134 has a groove-shaped opening OP4 that completely overlaps with the groove-shaped opening OP3, and wherein the size of the groove-shaped opening OP4 is larger than the size of the groove-shaped opening OP3.

[0044] According to an embodiment of the present invention, the slotted openings OP1-OP4 are concentric and completely overlap each other. According to an embodiment of the present invention, a stepped structure is provided between the slotted openings OP1-OP4. According to an embodiment of the present invention, the passivation layers 131-134 have inclined sidewalls SW1-SW4 around the slotted openings OP1-OP4 respectively.

[0045] According to an embodiment of the present invention, a sputtered layer 220, a UBM layer 230, and a solder bump 240 are sequentially formed on the central region of the bump pad 210 within the slot-shaped openings OP1-OP4. According to an embodiment of the present invention, the solder bump 240 is disposed on the UBM layer 230. According to an embodiment of the present invention, the sputtered layer 220 is, for example, TiW / Cu or Ti / Cu. According to an embodiment of the present invention, the UBM layer 230 is, for example, Ni, Cu, or Cu / Ni / Au. According to an embodiment of the present invention, the solder bump 240 may contain tin or any suitable solder material.

[0046] According to an embodiment of the present invention, the solder bump 240 may have an inverted pyramid-shaped cross-sectional profile. According to an embodiment of the present invention, the sputtering layer 220 and the UBM layer 230 conformally cover the inclined sidewalls SW1-SW4. After the reflow process, the solder bump 240 has a relatively flat upper surface, which can avoid the situation of insufficient contact area between the probe and the solder bump 240, resulting in probe burn-in.

[0047] Please refer to Figure 10, which is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. As shown in Figure 10, the bump structure B3 in Figure 9 can continue to undergo a bump hot pressing process. At a predetermined temperature, the solder bump 240 is pressed with a jig (as shown in Figures 7-8). After the formed solder bump 240 is softened and pressed down, a flat top surface area R is formed on the solder bump 240, thus forming the bump structure B4.

[0048] Please refer to Figures 11-21, where Figures 11 to 20 illustrate the steps for forming the bump structure in Figure 9, and Figure 21 illustrates the steps for forming the bump structure in Figure 10. As shown in Figure 11, a substrate 100 is first provided, for example, a silicon substrate or a GaN substrate, but not limited thereto. Next, at least one dielectric layer 110, for example, a silicon oxide layer, but not limited thereto, is formed on the substrate 100. Then, bump pads 210 are formed on the dielectric layer 110. According to an embodiment of the present invention, the bump pads 210 may include, for example, aluminum pads. Then, a passivation layer 120 is formed on the substrate 100, the passivation layer 120 covering the periphery of the bump pads 210 and forming a groove-shaped opening OP.

[0049] Next, as shown in Figure 12, a passivation layer 131 is formed on the substrate 100. The passivation layer 131 covers the periphery of the bump pad 210 and forms a groove opening OP1, the size of which can be approximately equal to the groove opening OP.

[0050] As shown in Figures 13-15, passivation layers 132-134 are sequentially formed on substrate 100. Passivation layer 132 has a slot-shaped opening OP2 that completely overlaps with slot-shaped opening OP1, passivation layer 133 has a slot-shaped opening OP3 that completely overlaps with slot-shaped opening OP2, and passivation layer 134 has a slot-shaped opening OP4 that completely overlaps with slot-shaped opening OP3. The size of slot-shaped opening OP4 is larger than the size of slot-shaped opening OP3, the size of slot-shaped opening OP3 is larger than the size of slot-shaped opening OP2, and the size of slot-shaped opening OP2 is larger than the size of slot-shaped opening OP1.

[0051] According to an embodiment of the present invention, the slotted openings OP1-OP4 are concentric and completely overlap each other. According to an embodiment of the present invention, there is a stepped structure between the slotted openings OP1-OP4.

[0052] As shown in Figure 16, a sputtered layer 220 is then deposited over the entire substrate 100. According to an embodiment of the invention, the sputtered layer 220 is conformally deposited within the groove-shaped openings OP1-OP4. According to an embodiment of the invention, the sputtered layer 220 is, for example, TiW / Cu or Ti / Cu.

[0053] As shown in Figure 17, a photoresist pattern PR is then formed on the sputtered layer 220, which has an opening PRO to define the position and pattern of the bump to be formed.

[0054] As shown in Figure 18, an electroplating process can then be performed to form a UBM layer 230 and solder bumps 240 within the opening PRO and the slot-shaped openings OP1-OP4. According to an embodiment of the invention, the UBM layer 230 is, for example, Ni, Cu, or Cu / Ni / Au. According to an embodiment of the invention, the solder bumps 240 may contain tin or any suitable solder material.

[0055] As shown in Figure 19, the photoresist pattern PR is then removed. An etching process is then performed to remove the sputtered layer 220 that was originally located directly below the photoresist pattern PR.

[0056] As shown in Figure 20, the next step is to perform a reflow process, which completes the bump structure B3 in Figure 9.

[0057] As shown in Figure 21, the bump structure B3 in Figure 9 can continue to undergo a bump hot pressing process. At a predetermined temperature, the solder bump 240 is pressed with a jig (as shown in Figures 7-8). After the formed solder bump 240 is softened and pressed down, a flat top surface area R is formed on the solder bump 240, thus forming the bump structure B4 in Figure 10.

[0058] Please refer to Figure 22, which is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. As shown in Figure 22, the bump structure B5 is also disposed on the substrate 100, for example, a silicon substrate or a GaN substrate, but is not limited thereto. The top view of the bump structure B5 can be a strip-shaped bump structure as shown in Figure 1, or a spherical bump structure as shown in Figure 3.

[0059] According to an embodiment of the present invention, at least one dielectric layer 110, such as a silicon oxide layer, is provided on the substrate 100, but is not limited thereto. Furthermore, bump pads 210 are provided on the dielectric layer 110. According to an embodiment of the present invention, the bump pads 210 may, for example, comprise aluminum pads. According to an embodiment of the present invention, passivation layers 120 and 130 are further provided on the substrate 100, wherein passivation layers 120 and 130 cover the periphery of the bump pads 210 and have a groove-shaped opening OP1 exposing the central region of the bump pads 210. According to an embodiment of the present invention, passivation layers 120 and 130 may, for example, comprise PI, PBO, or BCB, but are not limited thereto.

[0060] According to an embodiment of the present invention, the slotted opening OP1 has an approximate length L in the y-axis direction as shown in Figure 1, an approximate width W in the x-axis direction, and the L / W ratio is greater than 1.

[0061] According to an embodiment of the present invention, a first copper layer CL1 with a thickness t1 of approximately 4-20 micrometers is provided on the bump pad 210. According to an embodiment of the present invention, an annular second copper layer CL2 with a thickness t2 of approximately 15-135 micrometers is provided around the periphery of the bump pad 210. According to an embodiment of the present invention, the annular second copper layer CL2 partially overlaps the first copper layer CL1. The annular second copper layer CL2 defines an opening CLO, the shape of which is similar to a slotted opening OP1, and solder bumps 240 are filled into the opening.

[0062] According to an embodiment of the present invention, the solder bump 240 extends onto the top surface S1 of the annular second copper layer CL2. According to an embodiment of the present invention, the thickness t2 of the annular second copper layer CL2 is greater than the thickness t1 of the first copper layer CL1.

[0063] Please refer to Figure 23, which is a cross-sectional schematic diagram of a bump structure according to another embodiment of the present invention. As shown in Figure 23, the bump structure B5 in Figure 22 can continue to undergo a bump hot pressing process. At a predetermined temperature, the solder bump 240 is pressed with a jig (as shown in Figures 7-8). After the formed solder bump 240 is softened and pressed down, a flat top surface area R is formed on the solder bump 240, thus forming the bump structure B6.

[0064] Please refer to Figures 24-35, where Figures 24 to 34 illustrate the steps for forming the bump structure in Figure 22, and Figure 35 illustrates the steps for forming the bump structure in Figure 23. As shown in Figure 24, a substrate 100 is first provided, for example, a silicon substrate or a GaN substrate, but not limited thereto. Next, at least one dielectric layer 110, for example, a silicon oxide layer, but not limited thereto, is formed on the substrate 100. Then, bump pads 210 are formed on the dielectric layer 110. According to an embodiment of the present invention, the bump pads 210 may include, for example, aluminum pads. Then, a passivation layer 120 is formed on the substrate 100, the passivation layer 120 covering the periphery of the bump pads 210 and forming a groove-shaped opening OP.

[0065] Next, as shown in Figure 25, a passivation layer 130 is formed on the substrate 100. The passivation layer 130 covers the periphery of the bump pad 210 and forms a groove opening OP1, the size of which can be approximately equal to the groove opening OP.

[0066] As shown in Figure 26, a sputtered layer 220 is then deposited over the entire substrate 100. According to an embodiment of the invention, the sputtered layer 220 is conformally deposited within the groove-shaped opening OP1 and on the passivation layer 130. According to an embodiment of the invention, the sputtered layer 220 is, for example, TiW / Cu or Ti / Cu.

[0067] As shown in Figure 27, a photoresist pattern PR1 is then formed on the sputtered layer 220, which has an opening PRO1 to define the position and pattern of the bump to be formed.

[0068] As shown in Figure 28, an electroplating process can then be performed to form a first copper layer CL1 in the opening PRO1 and the groove opening OP1, with a thickness of, for example, about 4-20 micrometers.

[0069] As shown in Figure 29, the photoresist pattern PR1 is then removed.

[0070] As shown in Figure 30, a photoresist pattern PR2 is formed on the first copper layer CL1 and the sputtered layer 220, which has an opening PRO2 to expose a portion of the first copper layer CL1 and the sputtered layer 220 around the bump pad 210.

[0071] As shown in Figure 31, an electroplating process can then be performed to form an annular second copper layer CL2 within the opening PRO2, with a thickness of, for example, approximately 15-135 micrometers. The annular second copper layer CL2 defines the opening CLO, whose shape is similar to the groove-shaped opening OP1.

[0072] As shown in Figure 32, the photoresist pattern PR2 is then removed.

[0073] As shown in Figure 33, the solder ball SB is then placed into the opening CLO defined by the annular second copper layer CL2.

[0074] As shown in Figure 34, the next step is to perform a reflow process to form a solder bump 240 within the opening CLO defined by the annular second copper layer CL2, thus completing the bump structure B5 in Figure 22.

[0075] As shown in Figure 35, the bump structure B5 in Figure 34 can continue to undergo a bump hot pressing process. At a predetermined temperature, the solder bump 240 is pressed with a jig (as shown in Figures 7-8). After the formed solder bump 240 is softened and pressed down, a flat top surface area R is formed on the solder bump 240, thus forming the bump structure B6 in Figure 23. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0076] 100:Substrate 110: Dielectric layer 120: Passivation layer 130, 131-134: Passivation layer 210: Bump pad 220: Sputtered coating 230: Under-Bump Metallization (UBM) Layer 240: Solder bump 240a: Vertical sidewall 240c: Rounded corners 240s: Spherical surface 310, 320: Probes 400:Jig B1-B6: Bump Structure OP, OP1-OP4: Slotted opening CL1: First copper layer CL2: Annular second copper layer D: Size S: Spacing L: Length W: Width R: Flat top surface area SW1-SW4: Inclined sidewalls t1, t2: thickness PR, PR1, PR2: Photoresist patterns PRO, PRO1, PRO2: Opening SB: Tin Ball

Claims

1. A method of forming a semiconductor structure, comprising: providing a substrate having a bump pad thereon; forming a passivation layer on the substrate, wherein, The passivation layer covers a periphery of the bump pad and has a groove-shaped opening to expose a central region of the bump pad; an under-bump metal (UBM) layer is formed on the central region of the bump pad; a solder bump is formed on the UBM layer; a reflow process is performed on the solder bump; and after the reflow process, the solder bump is pressed with a fixture at a predetermined temperature to form a flat top surface area on the solder bump.

2. The method as described in request item 1, wherein, The slotted opening has a length L and a width W, and the L / W ratio is greater than or equal to 1.

3. The method as described in request item 1, wherein, The solder bump also includes a vertical sidewall.

4. The method as described in request item 3, wherein, The solder bump also includes a rounded corner located between the vertical sidewall and the flat top surface area.

5. The method as described in request item 1, wherein, The bump pad includes an aluminum pad.

6. The method as described in request item 1, wherein, The target temperature is between 250 and 280 degrees Celsius.

7. A semiconductor structure comprising: a substrate having a bump pad thereon; and a first passivation layer disposed on the substrate, wherein... The first passivation layer covers a periphery of the bump pad and has a first slot opening exposing a central region of the bump pad; a second passivation layer is disposed on the first passivation layer, wherein the second passivation layer has a second slot opening overlapping the first slot opening, wherein the size of the second slot opening is larger than the size of the first slot opening; an under-bump metal (UBM) layer is disposed on the central region of the bump pad; and a solder bump fills the first slot opening and the second slot opening, wherein the second passivation layer has an inclined sidewall around the second slot opening, and wherein the UBM layer covers the inclined sidewall.

8. The semiconductor structure as described in claim 7, wherein, The slotted opening has a length L and a width W, and the L / W ratio is greater than or equal to 1.

9. The semiconductor structure as described in claim 7, wherein, The second groove-shaped opening is concentric with and completely overlaps with the first groove-shaped opening.

10. The semiconductor structure as described in claim 7, wherein, There is a stepped structure between the second groove opening and the first groove opening.

Images