Memory chiplet structure and semiconductor package structure using the same

Abstract

Disclosed is a memory chiplet structure, which includes a single bank or a plurality of memory banks. Each memory bank includes an arbiter and a memory, and the memory is addressed. The arbiter of each memory bank is configured to perform arbitration according to the received access command and its own address space to determine to transmit data stored by the memory or control signals, write data into the memory and / or forward an access command. Therefore, the number of memory banks can be adjusted according to different storage capacity requirements. Besides, the memory bank that communicates with the outside of the memory chiplet structure is provided with an input / output interface, so that the memory chiplet structure communicates with an external chip to increase storage capacity and / or bandwidth. In addition, the memory chiplet structure can be applied to a 3D semiconductor package structure or a

Images