Electronic package and manufacturing method thereof

Abstract

An electronic package is made by arranging an electrical bridge die with a wiring portion on one side of a circuit structure, and a plurality of electronic components on another side of the circuit structure. The wiring portion includes at least one magnetic layer and a coil inductor formed on the magnetic layer, so that the electrical bridge die as a power management IC is integrated into the electronic package. Therefore, the distance from power supply to the electronic components can be shortened to effectively improve the performance of the electronic package.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging process, and more particularly to an integrated multi-chip electronic package and its manufacturing method. Prior Technology

[0002] With the evolution of semiconductor packaging technology, different packaging technologies have been developed to improve electrical functionality and save packaging space. For example, in conjunction with the significantly increased number of input / output ports on various chips, integrated circuits with different functions can be integrated into a single package structure. This packaging method can leverage the heterogeneous integration characteristics of System-in-Package (SiP) to integrate electronic components with different functions, such as memory, central processing unit, graphics processor, and image application processor, through stacking design. It is suitable for use in various thin and light electronic products.

[0003] Figure 1 is a perspective view of a conventional semiconductor package 1 applied to a circuit board 6. As shown in Figure 1, the circuit board 6 is equipped with at least one power management IC 60, a capacitor 61 and an inductor 62 to serve as a voltage regulator module (VRM) 6a.

[0004] However, in the conventional semiconductor package 1, its power supply comes from the voltage regulation module 6a, and therefore it is kept at a certain distance from the power management chip 60. This results in the power management chip 60 supplying power (such as circuit 63) to the semiconductor package 1 at a distance that is too far, causing the delay time to be too long. Therefore, it is difficult to improve the performance of the semiconductor package 1.

[0005] Furthermore, some components of the voltage regulation module 6a, such as the power management chip 60, capacitor 61 and inductor 62, are respectively located on the circuit board 6, thus occupying a certain area of ​​the circuit board 6, making it difficult to reduce the size of the circuit board 6, and making it difficult for the final product to meet the miniaturization requirements.

[0006] Therefore, how to overcome the various shortcomings of conventional technology is a technical problem that all sectors urgently need to solve. Summary of the Invention

[0007] In view of the various deficiencies of the prior art, the present invention provides an electronic package comprising: a circuit structure; an electrical bridging element having a wiring portion, which is attached to one side of the circuit structure and electrically connected to the circuit structure, wherein the wiring portion includes at least one magnetic layer and a coil inductor formed on the magnetic layer; and a plurality of electronic components, which are attached to the other side of the circuit structure and electrically connected to the circuit structure, such that the plurality of electronic components are electrically connected to the electrical bridging element through the circuit structure.

[0008] The present invention also provides a method for manufacturing an electronic package, comprising: providing an electrical bridging element having a wiring portion, wherein the wiring portion includes at least one magnetic layer and a coil inductor formed on the magnetic layer; attaching the electrical bridging element to one side of a circuit structure and electrically connecting the circuit structure; and attaching a plurality of electronic components to the other side of the circuit structure and electrically connecting the circuit structure, such that the plurality of electronic components are electrically connected to the electrical bridging element through the circuit structure.

[0009] In the aforementioned electronic package and its manufacturing method, an intermediate element is disposed on one side of the circuit structure, so that the plurality of electronic components are electrically connected to the intermediate element through the circuit structure. For example, the intermediate element has a plurality of through conductive vias.

[0010] In the aforementioned electronic package and its manufacturing method, the coil inductor has a first inductor segment and a second inductor segment respectively disposed on opposite sides of the magnetic layer, such that the first inductor segment and the second inductor segment are interconnected by a plurality of inductor pillars to form the coil inductor around the magnetic layer.

[0011] In the aforementioned electronic package and its manufacturing method, the electrical bridging element further includes a semiconductor substrate having a plurality of conductive vias, so that the wiring portion is formed on the semiconductor substrate and electrically connected to the plurality of conductive vias.

[0012] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly involve forming a magnetic layer in the electrical bridging element, thereby forming a coil-type inductor around the magnetic layer. This allows the electrical bridging element to be integrated into the electronic package as a power management chip or an integrated voltage regulator, thus shortening the distance of power supply to the electronic component. Therefore, compared with the prior art, the electronic package of the present invention requires a shorter power supply distance, thereby reducing the delay time and effectively improving the performance of the electronic package.

[0013] Furthermore, by integrating the electrical bridging element as a power management chip or integrated voltage regulator into the electronic package, the area occupied by the wiring board can be reduced, thereby reducing the size of the wiring board. Therefore, compared with the prior art, the electronic package of the present invention can reduce the size of the circuit board, so that the final product meets the requirements of miniaturization. Simple Explanation of the Diagram

[0014] Figure 1 is a three-dimensional schematic diagram of a conventional semiconductor package applied to a circuit board.

[0015] Figures 2A to 2D are cross-sectional schematic diagrams illustrating the manufacturing method of the electrical bridging element of the present invention.

[0016] Figure 2E is a partial top view of Figure 2D.

[0017] Figures 3A to 3F are cross-sectional schematic diagrams illustrating the manufacturing process of the electronic package of the present invention.

[0018] Figure 4 is a cross-sectional view of the application of Figure 3F. Implementation

[0019] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0020] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0021] Figures 2A to 2D are cross-sectional schematic diagrams illustrating the fabrication method of the electrical bridging element in the semiconductor package of the present invention. In this embodiment, the electrical bridging element (bridge die) 2 is a power management IC or an integrated voltage regulator (IVR).

[0022] As shown in Figure 2A, a semiconductor substrate 20 is provided, which has a first side 20a and a second side 20b opposite to each other, and the semiconductor substrate 20 has a plurality of conductive vias 200, such as through silicon vias (TSVs), connecting the first side 20a and the second side 20b, so that one end face of the conductive via 200 is exposed on the first side 20a, while the other end face is bonded with a conductive bump 27.

[0023] In this embodiment, the conductive bump 27 comprises copper pillars and / or solder balls, which are bonded to the conductive via 200 by an under bump metallurgy (UBM) 270. For example, a protective layer 28 exposing the conductive via 200 can be formed first on the second side 20b of the semiconductor substrate 20, and then the under bump metallurgy 270 can be formed on the end face of the conductive via 200 to form the conductive bump 27 on the under bump metallurgy 270, so that the conductive bump 27 protrudes from the second side 20b of the semiconductor substrate 20.

[0024] As shown in Figure 2B, a first wiring structure 21 electrically connecting the conductive vias 200 is formed on the first side 20a of the semiconductor substrate 20.

[0025] In this embodiment, the first wiring structure 21 includes an insulating layer 210 and a first conductive layer 25 disposed on the insulating layer 210 and electrically connected to the conductive vias 200, such as a redistribution layer (RDL). For example, the material forming the first conductive layer 25 is copper, and the material forming the insulating layer 210 is such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.

[0026] Furthermore, the first conductive layer 25 has a first line segment 250 and a first inductor segment 251.

[0027] As shown in Figure 2C, a second wiring structure 22 electrically connected to the first wiring structure 21 is formed on the first wiring structure 21.

[0028] In this embodiment, the second wiring structure 22 includes a magnetic layer 220 and a second conductive layer 26 disposed on the magnetic layer 220 and electrically connected to the first conductive layer 25. For example, the material forming the second conductive layer 26 is copper, and the material forming the magnetic layer 220 is such as a magnetic epoxy molding compound (EMC), a magnetic polyimide (PI), or other magnetic dielectric materials.

[0029] Furthermore, the second conductive layer 26 has a second line segment 260 electrically connected to the first line segment 250, and a second inductor segment 261 corresponding to the first inductor segment 251. For example, the first inductor segment 251 and the second inductor segment 261 are interconnected by a plurality of inductor pillars 262 to form a coil, so as to form a coil-type inductor 24 around the magnetic layer 220, as shown in FIG2E.

[0030] As shown in Figure 2D, a protective layer 23 is formed on the second wiring structure 22 so that the second line segment 260 of the second conductive layer 26 is exposed on the protective layer 23 for bonding with the conductive bump 29. The first wiring structure 21 and the second wiring structure 22 can be regarded as a wiring part 2a.

[0031] In this embodiment, the conductive bump 29 includes copper pillars and / or solder balls, and it should be understood that the number of layers of the wiring portion 2a can be designed according to requirements and is not limited to the above.

[0032] Figures 3A to 3F are cross-sectional schematic diagrams of the manufacturing method of the electronic package of the present invention.

[0033] As shown in Figure 3A, at least one intermediate element 3a, at least one electrical bridging element 2 as shown in Figure 2D, and a support structure 30 disposed on the support plate 9 are provided, and a plurality of conductive pillars 33 are formed on the support structure 30.

[0034] In this embodiment, the intermediate element 3a includes an intermediate plate 31, a circuit portion 32, a plurality of first conductors 311 formed on the intermediate plate 31, and a plurality of second conductors 312 formed on the circuit portion 32 and electrically connected to the circuit portion 32, and the plurality of first conductors 311 are covered by a protective film 313.

[0035] The intermediate plate 31 is made of silicon substrate and has a plurality of conductive through holes 310, such as through-silicon vias (TSVs), through which the circuit section 32 is electrically connected to the plurality of first conductors 311.

[0036] The circuit portion 32 includes at least one passivation layer 320 and a conductive trace 321 bonded to the passivation layer 320, so that the conductive trace 321 electrically connects the conductive via 310 and the plurality of second conductors 312. It should be understood that there are many different configurations of the intermediate element 3a, and there is no particular limitation.

[0037] The first conductor 311 and the second conductor 312 are metal pillars such as copper pillars, and the protective film 313 is an insulating film or polyimide (PI) material, which does not expose the first conductor 311.

[0038] Furthermore, the supporting structure 30 includes at least one insulating layer 300 and at least one wiring layer 301 disposed on the insulating layer 300. For example, the wiring layer 301 is made of copper, and the insulating layer 300 is made of dielectric materials such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or others.

[0039] Furthermore, the carrier plate 9 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 90 and an adhesive layer 91 are sequentially formed by coating, so that the carrier structure 30 is disposed on the adhesive layer 91.

[0040] In addition, the conductive post 33 is disposed on the wiring layer 301 and electrically connected to the wiring layer 301, and the material forming the conductive post 33 is a metal such as copper or solder.

[0041] As shown in Figure 3B, the electrical bridging element 2 and the intermediate element 3a are disposed on the bearing structure 30.

[0042] In this embodiment, the electrical bridging element 2 is disposed on the carrier structure 30 by its wiring portion 2a, so that the conductive bump 29 is electrically connected to the wiring layer 301, and the intermediary element 3a is connected to the carrier structure 30 by its second conductor 312 by solder material 314, so that the second conductor 312 is electrically connected to the wiring layer 301.

[0043] As shown in Figure 3C, a covering layer 35 is formed on the support structure 30 to cover the electrical bridging element 2, the intermediate element 3a, and the conductive pillars 33. The covering layer 35 has opposing first surfaces 35a and second surfaces 35b, and it is bonded to the support structure 30 via the first surface 35a. Next, a circuit structure 36 is formed on the second surface 35b of the covering layer 35 to electrically connect the conductive pillars 33, the electrical bridging element 2, and the intermediate element 3a.

[0044] In this embodiment, the covering layer 35 is an insulating material, such as an epoxy resin encapsulant, which can be formed on the support structure 30 by lamination or molding.

[0045] Furthermore, a leveling process can be used to make the second surface 35b of the coating layer 35 flush with the end face of the conductive post 33, the surface of the conductive bump 27, the surface of the protective film 313, and the surface of the first conductor 311, so that the conductive post 33, the conductive bump 27, the protective film 313, and the first conductor 311 are exposed on the second surface 35b of the coating layer 35. For example, a grinding process can be used to remove part of the material of the conductive post 33, the conductive bump 27, the protective film 313, the first conductor 311, and the coating layer 35 to perform the leveling process.

[0046] Furthermore, the circuit structure 36 includes multiple dielectric layers 360 and multiple circuit layers 361 disposed on the dielectric layers 360, such as a redistribution layer (RDL) specification, and the outermost dielectric layer 360 can serve as a solder resist layer, so that the outermost circuit layer 361 is exposed to the solder resist layer. Alternatively, the circuit structure 36 may also include only a single dielectric layer 360 and a single circuit layer 361.

[0047] In addition, the material forming the circuit layer 361 is copper, and the material forming the dielectric layer 360 is a dielectric material such as poly(p-diazole)benzene (PBO), polyimide (PI), prepreg (PP) or others.

[0048] As shown in Figure 3D, a plurality of electronic components 34 are connected on the outermost circuit layer 361 of the circuit structure 36. These electronic components 34 can be electrically connected to each other through the circuit structure 36 and the electrical bridging element 2, and then the electronic components 34 are covered by an encapsulation layer 38.

[0049] The electronic component 34 can be an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. For example, the intermediate component 3a can also serve as an electrical bridging component, allowing the electronic components 34 to be electrically connected to each other through the intermediate component 3a.

[0050] In this embodiment, the electronic component 34 is a semiconductor chip, which is disposed on the circuit layer 361 and electrically connected to the circuit layer 361 by means of a plurality of conductive bumps 340, such as solder material, using a flip-chip method, and the conductive bumps 340 are covered with a primer 341; or, the electronic component 34 can be electrically connected to the circuit layer 361 by means of a plurality of bonding wires (not shown); or it can be electrically connected to the circuit layer 361 by means of conductive materials (not shown) such as conductive adhesive or solder. However, the method of electrically connecting the electronic component 34 to the circuit layer 361 is not limited to the above.

[0051] Furthermore, the encapsulation layer 38 is an insulating material, such as polyimide (PI), dry film, or an encapsulating compound such as epoxy resin, which can be formed on the circuit structure 36 by lamination or molding. It should be understood that the material forming the encapsulation layer 38 may be the same as or different from the material of the covering layer 35.

[0052] In addition, the encapsulation layer 38 covers the base adhesive 341, but the base adhesive 341 may not be formed, and the encapsulation layer 38 may be used to directly cover the conductive bump 340.

[0053] As shown in Figure 3E, the support plate 9 and its release layer 90 and adhesive layer 91 are removed to expose the support structure 30.

[0054] In this embodiment, a plurality of conductive elements 37, such as solder balls, are formed on the support structure 30, so that the conductive elements 37 are electrically connected to the wiring layer 301. For example, an insulating protective layer 370, such as a solder resist layer, can be formed on the support structure 30 first, and the insulating protective layer 370 has a plurality of openings so that the wiring layer 301 is exposed through these openings for bonding C4 bump-sized conductive elements 37.

[0055] Furthermore, at least one auxiliary element 39 may be provided on a portion of the conductive element 37 on the support structure 30, so that the auxiliary element 39 is electrically connected to the wiring layer 301 through the conductive element 37. For example, the auxiliary element 39 may be an active element, a passive element, or a combination of both, wherein the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor.

[0056] Alternatively, a leveling process, such as grinding, can be used to remove part of the material of the encapsulation layer 38, so that the upper surface of the encapsulation layer 38 is flush with the upper surface of the electronic component 34, thereby exposing the electronic component 34 to the encapsulation layer 38.

[0057] As shown in Figure 3F, a cutting process is performed along the cutting path S shown in Figure 3E to obtain the electronic package 3.

[0058] In this embodiment, the electronic package 3 can be placed on the upper side of a wiring carrier 4 via conductive elements 37, as shown in FIG4, and then the conductive elements 37 are covered with a base adhesive 43. For example, the wiring carrier 4 is an organic material board (such as a packaging substrate with a core layer and circuitry or a coreless packaging substrate with circuitry) or an inorganic material board (such as a silicon substrate).

[0059] Furthermore, at least one heat sink 41 and / or an electrical functional component 42 can be configured on the upper side of the wiring carrier 4 as needed, and the lower side of the wiring carrier 4 can be connected to an electronic device (not shown) such as a circuit board by a plurality of solder balls 40, so that the wiring carrier 4 is electrically connected to the electronic device.

[0060] Furthermore, the electrical functional element 42 is an active element, a passive element, or a combination thereof, and is electrically connected to the electrical contact 400 of the wiring carrier board 4. The active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor.

[0061] Therefore, the present invention mainly achieves this by forming the magnetic layer 220 in the electrical bridging element 2, so that the first inductor segment 251 and the second inductor segment 261 form a coil inductor 24 around the magnetic layer 220. This allows the electrical bridging element 2 to be integrated into the electronic package 3 as a power management chip (Power Management IC) or an integrated voltage regulator (IVR). As a result, the distance of power supply to the electronic component 34 can be shortened. Therefore, compared with the prior art, the electronic package 3 of the present invention requires a shorter power supply distance, thereby shortening the delay time and effectively improving the performance of the electronic package 3.

[0062] Furthermore, by integrating the electrical bridging element 2 as a power management IC or an integrated voltage regulator (IVR) into the electronic package 3, the area occupied by the wiring carrier 4 is reduced, thereby reducing the size of the wiring carrier 4. Therefore, compared with the prior art, the electronic package 3 of the present invention can reduce the size of the circuit board, so that the final product meets the requirements of miniaturization.

[0063] The present invention provides an electronic package 3, which includes: a circuit structure 36 having opposite sides, an electrical bridging element 2 having a wiring portion 2a, and a plurality of electronic components 34.

[0064] The electrical bridging element 2 is attached to one side of the circuit structure 36 and electrically connected to the circuit structure 36. The wiring portion 2a includes at least one magnetic layer 220 and a coil inductor 24 formed on the magnetic layer 220.

[0065] The electronic component 34 is attached to the other side of the circuit structure 36 and electrically connected to the circuit structure 36, so that the plurality of electronic components 34 are electrically connected to each other through the circuit structure 36 and the electrical bridging element 2.

[0066] In one embodiment, an intermediary element 3a is provided on one side of the circuit structure 36, so that the plurality of electronic components 34 are electrically connected to the intermediary element 3a through the circuit structure 36. For example, the intermediary element 3a has a through conductive via 310.

[0067] In one embodiment, the coil inductor 24 has a first inductor segment 251 and a second inductor segment 261 respectively disposed on opposite sides of the magnetic layer 220, such that the first inductor segment 251 and the second inductor segment 261 are interconnected by a plurality of inductor pillars 262, so as to form the coil inductor 24 around the magnetic layer 220.

[0068] In one embodiment, the electrical bridging element 2 further includes a semiconductor substrate 20 having a plurality of conductive vias 200, so that the wiring portion 2a is formed on the semiconductor substrate 20 and electrically connected to the conductive vias 200.

[0069] In summary, the electronic package and its manufacturing method of the present invention involve forming a magnetic layer in the electrical bridging element, and having the first inductor segment and the second inductor segment form a coil-type inductor around the magnetic layer. This allows the electrical bridging element to be integrated into the electronic package as a power management chip or an integrated voltage regulator, thereby shortening the distance of power supply to the electronic component. Therefore, the electronic package of the present invention requires a shorter power supply distance, thus reducing latency and effectively improving the performance of the electronic package.

[0070] Furthermore, by integrating the electrical bridging element as a power management chip or integrated voltage regulator into the electronic package, the area occupied by the wiring board is reduced, thereby reducing the size of the wiring board. Therefore, the electronic package of the present invention can reduce the size of the circuit board, so that the final product meets the requirements of miniaturization.

[0071] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

[0072] 1: Semiconductor package 2: Electrical bridging components 2a: Wiring section 20: Semiconductor substrate 20a: First side 20b: Second side 200, 310: Conductive vias 21: First wiring structure 210, 300: Insulation layer 22: Second wiring structure 220: Magnetic layer 23: Protective layer 24: Coil Inductor 25: First conductive layer 250: First Line Section 251: First inductor segment 26: Second conductive layer 260: Second Line Section 261: Second inductor segment 262: Inductor Post 27, 29, 340: Conductive bumps 270: Metal layer under the bump 28: Protective layer 3: Electronic packaging components 3a: Intermediate element 30: Load-bearing structure 301: Wiring Layer 31: Intermediary Board 311: First conductor 312: Second conductor 313: Protective film 314: Solder materials 32: Line Department 320: Passivation layer 321: Conductive trace 33: Conductive column 34: Electronic components 341,43: Base rubber 35: Covering layer 35a: First surface 35b: Second surface 36: Circuit Structure 360: Dielectric layer 361: Line Layer 37: Conductive elements 370: Insulating protective layer 38: Encapsulation layer 39: Auxiliary components 4: Wiring carrier board 40: Welding ball 400: Electrical contacts 41: Heat sink 42: Electrical functional components 6a: Voltage regulation module 6: Circuit board 60: Power Management Chip 61: Capacitor 62: Inductor 63: Circuit 9: Support plate 90: Release layer 91: Adhesive layer S: Cutting path

Claims

1. An electronic package, comprising: Line structure; An electrical bridging element having a wiring section is attached to one side of the circuit structure and electrically connected to the circuit structure. The wiring section includes a magnetic layer and a coil inductor formed on the magnetic layer. The coil inductor has a first inductor segment and a second inductor segment respectively disposed on opposite sides of the magnetic layer. The first inductor segment and the second inductor segment are interconnected by a plurality of inductor pillars to form the coil inductor around the magnetic layer. A plurality of electronic components are attached to the other side of the circuit structure and electrically connected to the circuit structure. The plurality of electronic components are electrically connected to the electrical bridging element through the circuit structure.

2. The electronic package as described in claim 1, wherein, An intermediary element is provided on one side of the circuit structure, so that the plurality of electronic components are electrically connected to the intermediary element through the circuit structure.

3. The electronic package as described in claim 2, wherein, The intermediate element has multiple through-holes.

4. The electronic package as described in claim 1, wherein, This electrical bridging element is used as a power management chip or integrated voltage regulator.

5. The electronic package as described in claim 1, wherein, The electrical bridging element further includes a semiconductor substrate having a plurality of conductive vias, such that the wiring portion is formed on the semiconductor substrate and electrically connected to the plurality of conductive vias.

6. A method for manufacturing an electronic package, comprising: An electrical bridging element with a wiring portion is provided, wherein the wiring portion includes a magnetic layer and a coil inductor formed on the magnetic layer, and the coil inductor has a first inductor segment and a second inductor segment respectively disposed on opposite sides of the magnetic layer, such that the first inductor segment and the second inductor segment are interconnected by a plurality of inductor pillars to form the coil inductor around the magnetic layer; the electrical bridging element is combined to one side of a circuit structure and electrically connected to the circuit structure; and a plurality of electronic components are combined to the other side of the circuit structure and electrically connected to the circuit structure, such that the plurality of electronic components are electrically connected to the electrical bridging element through the circuit structure.

7. The method for manufacturing an electronic package as described in claim 6, wherein, An intermediary element is provided on one side of the circuit structure, so that the plurality of electronic components are electrically connected to the intermediary element through the circuit structure.

8. The method for manufacturing an electronic package as described in claim 7, wherein, The intermediate element has multiple through-holes.

9. The method for manufacturing an electronic package as described in claim 6, wherein, This electrical bridging element is used as a power management chip or integrated voltage regulator.

10. A method for manufacturing an electronic package as described in claim 6, wherein, The electrical bridging element further includes a semiconductor substrate having a plurality of conductive vias, such that the wiring portion is formed on the semiconductor substrate and electrically connected to the plurality of conductive vias.

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