Electronic device

Abstract

An electronic device includes an array substrate and a counter substrate disposed opposite to the array substrate. The array substrate includes a base, scan lines, data lines, pixel electrodes, light-shielding metal patterns, and a first common electrode and a second common electrode. The scan lines and the data lines are disposed on the base and extend in the first and second directions, respectively. The first common electrode is disposed on the scan lines and the data lines. The pixel electrodes are disposed on the first common electrode, where a first gap exists between any two adjacent pixel electrodes in the first direction. The light-shielding metal patterns are disposed on the pixel electrodes and correspond to the first gaps, respectively. A second gap exists between any two adjacent light-shielding metal patterns in the second direction. The light-shielding metal patterns and the second gaps overlap the data lines and the scan lines, respectively. The second common electrode covers and is in contact with the light-shielding metal patterns, and the counter substrate has light-transmitting regions overlapping the data lines.

Description

[Technical Field]

[0001] The present invention relates to an electronic device, and more particularly to an electronic device comprising a light-shielding metal pattern overlapping with data lines. [Previous Technology]

[0002] Electronic devices using array substrates with scan lines and data lines are widely used, such as projectors, smartphones, and virtual reality wearable devices, and the demand for high resolution and high transmittance is increasing. However, in order to meet the requirements of high resolution and high transmittance, the light-shielding pattern on the opposite substrate corresponding to the data lines, such as a black matrix, is prone to line breakage due to excessively thin line width, which leads to a decrease in the yield of electronic devices. [Summary of the Invention]

[0003] At least one embodiment of the present invention provides an electronic device that does not require the provision of a light-shielding pattern for the corresponding data lines on the opposing substrate. Therefore, it can avoid the situation where the light-shielding pattern of the corresponding data lines is broken due to the excessively thin line width, thereby improving the yield of the electronic device.

[0004] At least one embodiment of the present invention provides an electronic device comprising an array substrate and a counter substrate. The array substrate comprises a first substrate, a plurality of scan lines, a plurality of data lines, a plurality of switching elements, an insulating layer, a first transparent common electrode, a plurality of pixel electrodes, a plurality of light-shielding metal patterns, and a second transparent common electrode. The scan lines are disposed on the first substrate and extend along a first direction, and the data lines are disposed on the first substrate and extend along a second direction, the first direction being different from the second direction. The switching elements are disposed on the first substrate, and each switching element is electrically connected to one of the scan lines and one of the data lines. The insulating layer is disposed on the first substrate and covers the scan lines, the data lines, and the switching elements. The first transparent common electrode is disposed on the insulating layer. The pixel electrodes are disposed on the first transparent common electrode and are electrically connected to the switching elements respectively, and in the first direction, any two adjacent pixel electrodes have a first spacing. These light-shielding metal patterns are disposed on the pixel electrodes and extend along a second direction, corresponding to the first spacing. In the second direction, any two adjacent light-shielding metal patterns have a second spacing. On the normal of the first substrate, these light-shielding metal patterns overlap with the data lines, and the second spacings overlap with the scan lines. A second transparent common electrode is disposed on these light-shielding metal patterns, covering and contacting them. A counter substrate is disposed opposite to the array substrate and has a plurality of first light-transmitting areas, which overlap with the data lines on the normal of the first substrate.

[0005] In at least one embodiment of the present invention, the opposing substrate includes a second substrate, a light-shielding pattern layer, and a plurality of spacers. The light-shielding pattern layer is disposed on the second substrate and includes a plurality of light-shielding strips extending along the first direction. On the normal line of the first substrate, these light-shielding strips overlap with the plurality of scan lines, and the plurality of second spacings overlap with these light-shielding strips. The spacers are disposed on the light-shielding pattern layer and located between the light-shielding pattern layer and the array substrate. On the normal line of the second substrate, these spacers overlap with the light-shielding pattern layer, and each spacer has a top surface and a bottom surface facing each other. The top surface faces the array substrate, and the bottom surface faces the light-shielding pattern layer. The width of the bottom surface is greater than the width of the top surface.

[0006] In at least one embodiment of the present invention, the opposing substrate includes a second substrate and a light-shielding pattern layer. The light-shielding pattern layer is disposed on the second substrate and includes a plurality of light-shielding strips extending along the first direction. On the normal line of the first substrate, these light-shielding strips overlap with the plurality of scan lines, and the plurality of second spacings overlap with these light-shielding strips. The array substrate further includes a plurality of spacers disposed on the second transparent common electrode and located between the second transparent common electrode and the opposing substrate. On the normal line of the second substrate, these spacers overlap with the light-shielding pattern layer, and each spacer has a top surface and a bottom surface facing each other. The top surface faces the opposing substrate, and the bottom surface faces the second transparent common electrode. The width of the bottom surface is greater than the width of the top surface.

[0007] In at least one embodiment of the present invention, the width of each of the light-shielding strips is greater than the width of each of the second spacings.

[0008] In at least one embodiment of the present invention, the array substrate further includes a plurality of color filter patterns, which are disposed on the second transparent common electrode and respectively correspond to the plurality of pixel electrodes.

[0009] In at least one embodiment of the present invention, the opposing substrate further includes a second substrate and a plurality of color filter patterns, which are disposed on the second substrate and respectively correspond to the plurality of pixel electrodes.

[0010] In at least one embodiment of the present invention, the array substrate further includes a plurality of color filter patterns, which are respectively disposed on the plurality of pixel electrodes and respectively correspond to the plurality of pixel electrodes, and are located between the first transparent common electrode and the second transparent common electrode.

[0011] In at least one embodiment of the present invention, the array substrate further includes a plurality of light-shielding metal strips and a plurality of spacers. These light-shielding metal strips are disposed on the first substrate and extend along the first direction, and are located between the first substrate and the plurality of scan lines. On the normal line of the first substrate, these light-shielding metal strips overlap with the plurality of scan lines, and the plurality of second spacings overlap with these light-shielding metal strips. These spacers are disposed on the second transparent common electrode and are located between the second transparent common electrode and the opposing substrate. On the normal line of the first substrate, these spacers overlap with these light-shielding metal strips, and each spacer has a top surface and a bottom surface facing each other. The top surface faces the opposing substrate, and the bottom surface faces the second transparent common electrode. The width of the bottom surface is greater than the width of the top surface.

[0012] In at least one embodiment of the present invention, the opposing substrate has a plurality of second light-transmitting areas, wherein these second light-transmitting areas overlap with the plurality of scan lines on the normal line of the first substrate.

[0013] In at least one embodiment of the present invention, the width of each of the light-shielding metal strips is greater than the width of each of the scanning lines.

[0014] In at least one embodiment of the present invention, the width of each of the light-shielding metal strips is greater than the width of each of the second spacings.

[0015] In at least one embodiment of the present invention, the width of each of the light-shielding metal patterns is greater than the width of each of the data lines.

[0016] In at least one embodiment of the present invention, the second transparent common electrode has a plurality of slits on the normal of the first substrate, and these slits overlap with the plurality of pixel electrodes.

Implementation Method

[0017] In the following text, in order to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the drawings will be enlarged proportionally, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the size and shape of the elements, but should cover the size, shape, and deviations of both caused by actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the claims of the present invention.

[0018] Secondly, the terms "approximately," "approximately," or "substantially" used in this invention not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understandable to those skilled in the art to which this invention pertains. This deviation range can be determined by errors generated during measurement, which may be caused by limitations of the measurement system or process conditions, for example. For instance, two objects (e.g., planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular," where "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects may include non-parallelism and non-perpendicularity caused by the permissible deviation range.

[0019] Furthermore, "about" can mean within one or more standard deviations of the above-mentioned values, such as ±30%, ±20%, ±10%, or ±5%. The use of terms such as "about," "approximately," or "substantially" in this invention can be selected based on the optical properties, etching properties, mechanical properties, or other properties to determine an acceptable range of deviations or standard deviations, and does not apply to all of the above-mentioned optical properties, etching properties, mechanical properties, and other properties using only one standard deviation.

[0020] The spatial relative terms used in this invention, such as "below," "under," "above," and "above," are for the convenience of describing the relative relationship between one element or feature and another element or feature, as illustrated in the figures. The true meaning of these spatial relative terms includes other orientations. For example, when the illustration is rotated 180 degrees vertically, the relationship between one element and another may change from "below" or "under" to "above" or "above." Furthermore, the spatial relative descriptions used in this invention should be interpreted in the same way.

[0021] It should be understood that although the present invention may use terms such as "first," "second," and "third" to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are primarily used to distinguish one element from another, or one signal from another. In addition, the term "or" as used in the present invention may, as appropriate, include any combination of one or more of the associated listed items.

[0022] Furthermore, the present invention can be implemented or applied through other different specific embodiments, and the details of the present invention can also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0023] FIG1 is a top view of an electronic device 10 according to at least one embodiment of the present invention. FIG2 is an enlarged view of region A in FIG1. ​​FIG3 is a cross-sectional view drawn along line a-a' in FIG2. Referring to FIG1 to FIG3, the electronic device 10 has a plurality of sub-pixels PX and includes an array substrate 100 and a counter substrate 200.

[0024] As shown in Figures 2 and 3, the array substrate 100 includes a first substrate 102, multiple scan lines 104, multiple data lines 106, multiple switching elements 108, an insulating layer 110, a first transparent common electrode 112, multiple pixel electrodes 114, multiple light-shielding metal patterns 116, and a second transparent common electrode 118.

[0025] The scan lines 104 are disposed on the first substrate 102 and extend along a first direction D1, and the data lines 106 are disposed on the first substrate 102 and extend along a second direction D2, wherein the first direction D1 and the second direction D2 are different. The switching elements 108 are disposed on the first substrate 102 and are electrically connected to one of the scan lines 104 and one of the data lines 106.

[0026] An insulating layer 110 is disposed on the first substrate 102 and covers the scan lines 104, the data lines 106, and the switching elements 108. A first transparent common electrode 112 is disposed on the insulating layer 110. Pixel electrodes 114 are disposed on the first transparent common electrode 112 and are electrically connected to the switching elements 108, respectively. In the first direction D1, any two adjacent pixel electrodes 114 have a first spacing G1 between them.

[0027] These light-shielding metal patterns 116 are disposed on these pixel electrodes 114 and extend along the second direction D2, and respectively correspond to these first spacings G1. In the second direction D2, there is a second spacing G2 between any two adjacent light-shielding metal patterns 116. In the normal (i.e., the third direction D3) of the first substrate 102, these light-shielding metal patterns 116 overlap with these data lines 106 respectively, and these second spacings G2 overlap with these scan lines 104 respectively.

[0028] A second transparent common electrode 118 is disposed on these light-shielding metal patterns 116 and covers and contacts these light-shielding metal patterns 116. The opposing substrate 200 is disposed opposite to the array substrate 100 and has a plurality of first light-transmitting areas T1. On the normal line of the first substrate 102, these first light-transmitting areas T1 overlap with these data lines 106 respectively.

[0029] Since the array substrate 100 includes a light-shielding metal pattern 116 corresponding to the first spacing G1 between any two adjacent pixel electrodes 114 and overlapping with the data line 106 on the normal of the first substrate 102, the opposing substrate 200 may not include a light-shielding pattern corresponding to the data line 106, such as a black matrix, that is, the opposing substrate 200 has a first light-transmitting area T1 overlapping with the data line 106. Therefore, the situation where the light-shielding pattern corresponding to the data line 106 is broken due to excessively thin line width can be avoided, thereby improving the yield of the electronic device 10. In addition, since there is a second spacing G2 between the light-shielding metal patterns 116, which is not a continuous and unbroken metal line, the flatness of the second spacing G2 can be maintained, reducing the probability of debris generated by friction between the alignment layer 113 and the spacer 206, so as to avoid affecting the display quality of the electronic device 10.

[0030] By providing a second transparent common electrode 118 that covers and contacts the light-shielding metal pattern 116, for example, the orthographic projection of the light-shielding metal pattern 116 on the first substrate 102 is located within the orthographic projection of the second transparent common electrode 118 on the first substrate 102, that is, the orthographic projection of the light-shielding metal pattern 116 on the first substrate 102 does not exceed the orthographic projection of the second transparent common electrode 118 on the first substrate 102, the second transparent common electrode 118 can reduce the reflection of the light-shielding metal pattern 116 to reduce visibility.

[0031] Furthermore, the light-shielding metal pattern 116, which is in direct contact with the second transparent common electrode 118, can receive the same voltage as the second transparent common electrode 118, such as a shared voltage. Therefore, the light-shielding metal pattern 116 can be prevented from being in a floating state, thereby reducing the risk of charge accumulation and improving the reliability of the electronic device 10. In addition, a storage capacitor can be formed between the second transparent common electrode 118 and the pixel electrode 114, thereby improving electrical performance and improving the display quality of the electronic device 10.

[0032] Figures 4A and 4B are partially enlarged schematic diagrams of the array substrate 100 and the opposing substrate 200 according to at least one embodiment of the present invention. It is worth noting that, in order to keep the diagram simple, Figure 4A only shows the first substrate 102, scan line 104, data line 106, first transparent common electrode 112, multiple pixel electrodes 114, multiple light-shielding metal patterns 116 and second transparent common electrode 118. Since Figures 2, 4A, and 4B are drawn in units of six sub-pixels, the scan line 104, data line 106, and light-shielding strip LB are presented as line segments, while the first transparent common electrode 112 and the second transparent common electrode 118 are presented as blocks. However, it should be understood that the scan line 104 and data line 106 should be continuous lines extending along the first direction D1 and the second direction D2, respectively, the light-shielding strip LB should be a continuous line extending along the first direction D1, and the first transparent common electrode 112 and the second transparent common electrode 118 should be full-surface electrodes arranged on the plane formed by the first direction D1 and the second direction D2 and having an opening H and a slit SL, respectively.

[0033] Referring to Figures 3 and 4A, the second transparent common electrode 118 has a plurality of slits SL on the normal of the first substrate 102, and these slits SL overlap with the pixel electrode 114. With the aforementioned design, the electric field formed between the pixel electrode 114 and the second transparent common electrode 118 can escape from the slits SL to drive the display medium (not shown), such as liquid crystal, between the array substrate 100 and the opposing substrate 200. The overlapping portion of the second transparent common electrode 118 and the pixel electrode 114 forms a storage capacitor, which can improve electrical performance and thus improve the display quality of the electronic device 10. In some embodiments, the slits SL may be spaced apart along the first direction D1 and extend along the second direction D2, but the present invention is not limited thereto.

[0034] Scan lines 104 and data lines 106 intersect. Scan lines 104 extend along a first direction D1, while data lines 106 extend along a second direction D2. The first direction D1 and the second direction D2 are different and have an angle greater than 0 degrees and less than 180 degrees between them. In this embodiment, the first direction D1 and the second direction D2 are substantially perpendicular to each other, that is, they have an angle of approximately 90 degrees between them, and the third direction D3 is substantially perpendicular to both the first direction D1 and the second direction D2. However, the present invention is not limited thereto, and in other embodiments, the first direction D1 and the second direction D2 may have other angles between them.

[0035] Furthermore, the width W1 of the light-shielding metal pattern 116 is greater than the width W2 of the data line 106. Specifically, as shown in FIG4A, in the first direction D1, the light-shielding metal pattern 116 and the data line 106 have widths W1 and W2 respectively, with width W1 being greater than width W2. Through the aforementioned design, the color shift caused by light leakage between two adjacent sub-pixels PX in the first direction D1 can be reduced, thereby improving the display quality of the electronic device 10.

[0036] Referring to Figures 3, 4A and 4B, the opposing substrate 200 includes a second substrate 202, a light-shielding pattern layer 204 and a plurality of spacers 206. The light-shielding pattern layer 204 is disposed on the second substrate 202 and includes a plurality of light-shielding strips LB extending along a first direction D1. On the normal line of the first substrate 102, these light-shielding strips LB overlap with these scan lines 104 respectively, and these second spacings G2 overlap with these light-shielding strips LB respectively.

[0037] These spacers 206 are disposed on the light-shielding pattern layer 204 and located between the light-shielding pattern layer 204 and the array substrate 100, on the normal (i.e., third direction D3) of the second substrate 202. These spacers 206 overlap with the light-shielding pattern layer 204, and the spacers 206 have opposing top surfaces TS and bottom surfaces BS. The top surface TS faces the array substrate 100, and the bottom surface BS faces the light-shielding pattern layer 204. The width W3 of the bottom surface BS is greater than the width W4 of the top surface TS. In some embodiments, as shown in FIG4B, the light-shielding pattern layer 204 further includes an extension EX protruding from the light-shielding strip LB at the position corresponding to the spacer 206, so as to effectively shield the display medium (e.g., liquid crystal) from being disordered due to the spacers 206.

[0038] As shown in Figures 4A and 4B, the width W5 of the light-shielding strip LB is greater than the width W6 of the second spacing G2. Specifically, in the second direction D2, the light-shielding strip LB and the second spacing G2 have widths W5 and W6 respectively, with W5 being greater than W6. Through this design, the second spacing G2 can be shielded to prevent the exposed second spacing G2 from forming an interference pattern visible to the human eye, thereby improving the display quality of the electronic device 10.

[0039] As shown in Figures 3 and 4A, the array substrate 100 further includes a plurality of color filter patterns 120. These color filter patterns 120 are disposed on the second transparent common electrode 118 and correspond to the pixel electrodes 114, that is, to the sub-pixels PX respectively. With the aforementioned design, when forming the color filter patterns 120, the light-shielding metal pattern 116 can be directly used for alignment, thus avoiding color shift caused by the offset of the color filter patterns 120.

[0040] Please continue to refer to Figures 2 and 3. The opposing substrate 200 further includes an alignment layer 203 disposed on the second substrate 202 and covering the spacer 206, and the array substrate 100 further includes a buffer layer 103, an interlayer insulating layer 105, a first dielectric layer 107, a second dielectric layer 109, a planarization layer 111 and a first alignment layer 113, and the switching element 108 includes an active layer AL, a gate insulating layer GI, a gate GE, a source SE and a drain DE.

[0041] A buffer layer 103 is disposed between the first substrate 102 and the switching element 108. An active layer AL is disposed on the buffer layer 103. A gate insulating layer GI is disposed on the active layer AL. A gate GE is disposed on the gate insulating layer GI and is electrically connected to at least one scan line 104. An interlayer insulating layer 105 is disposed on the gate GE. A source SE and a drain DE are disposed on the interlayer insulating layer 105 and contact the active layer AL through through holes O1 and O2, respectively. The source SE is electrically connected to at least one data line 106.

[0042] A first dielectric layer 107 is disposed between a first transparent common electrode 112 and a pixel electrode 114. The first transparent common electrode 112 has an opening H to expose a drain electrode DE, while the pixel electrode 114 contacts the drain electrode DE through a through-hole O3. A second dielectric layer 109 is disposed between a pixel electrode 114 and a second transparent common electrode 118. A planarization layer 111 is disposed on a color filter pattern 120, and an alignment layer 113 is disposed on the planarization layer 111.

[0043] In some embodiments, the first substrate 102 and the second substrate 202 may be transparent substrates, and their materials may be quartz, glass, polymer materials or other suitable materials. The materials of the buffer layer 103, the gate insulating layer GI, the interlayer insulating layer 105, the insulating layer 110, the first dielectric layer 107, the second dielectric layer 109 and the planarization layer 111 may include transparent insulating materials, such as transparent inorganic insulating materials, organic insulating materials, other suitable materials or single layers, multiple layers or combinations of the aforementioned materials. Inorganic insulating materials include silicon oxide, silicon nitride, silicon oxynitride, etc., and organic insulating materials include acrylic, siloxane, polyimide, epoxy resin, etc.

[0044] In some embodiments, the material of the active layer AL may comprise silicon semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), oxide semiconductor materials, organic semiconductor materials, other suitable materials, or a single layer, multiple layers, or combination of the aforementioned materials. In this embodiment, the switching element 108 is a top-gate type thin-film transistor. However, the present invention is not limited thereto; in other embodiments, the switching element 108 may be a bottom-gate type thin-film transistor, a three-dimensional channel (vertical channel) type thin-film transistor, other suitable forms of thin-film transistors, or other types of switching elements.

[0045] The materials of scan line 104, data line 106, light-shielding metal pattern 116, gate GE, source SE, and drain DE may include metals, alloys, other suitable materials, or single layers, multiple layers, or combinations of the aforementioned materials. Metals include, for example, aluminum, molybdenum, titanium, copper, or silver; alloys include, for example, alloys of the aforementioned metals. The materials of the first transparent common electrode 112, pixel electrode 114, and second transparent common electrode 118 may include transparent conductive materials, such as indium tin oxide, indium zinc oxide, indium gallium zinc oxide, aluminum zinc oxide, other suitable materials, or single layers, multiple layers, or combinations of the aforementioned materials.

[0046] In some embodiments, the alignment layers 113 and 203 may be made of polyimide or the like. The color filter pattern 120 may be a color resist, such as a red color resist, a green color resist, and a blue color resist. The material of the light-shielding pattern layer 204 may include organic materials, inorganic materials, other suitable materials, or combinations thereof. The organic material may be a dark photoresist or a dark ink, and the inorganic material may be a metal or a silicon-containing material. The material of the spacer 206 may include photoresist.

[0047] FIG5 is a partial cross-sectional schematic diagram of an electronic device 10A according to at least another embodiment of the present invention. FIG6A and FIG6B are respectively partial enlarged schematic diagrams of an array substrate 100A and a counter substrate 200A according to at least another embodiment of the present invention. Please refer to FIG5, FIG6A and FIG6B. The embodiments of FIG5, FIG6A and FIG6B are the same as the embodiments of FIG3, FIG4A and FIG4B in most of their component structures, relative positions and materials. Moreover, the top view of the electronic device 10A in FIG5 is substantially the same as the top view of the electronic device 10 in FIG3. Therefore, the same technical features will not be described again here. The main difference between the embodiments of FIG5, FIG6A and FIG6B and the embodiments of FIG3, FIG4A and FIG4B is that the array substrate 100A of the electronic device 10A in the embodiments of FIG5, FIG6A and FIG6B further includes a plurality of spacers 122.

[0048] In detail, as shown in Figures 5, 6A, and 6B, these spacers 122 are disposed on the second transparent common electrode 118 and located between the second transparent common electrode 118 and the opposing substrate 200A. On the normal line of the second substrate 202, these spacers 122 overlap with the light-shielding pattern layer 204, and the spacers 122 have opposing top surfaces TS and bottom surfaces BS. The top surface TS faces the opposing substrate 200A, while the bottom surface BS faces the second transparent common electrode 118. The width W3 of the bottom surface BS is greater than the width W4 of the top surface TS. Since the spacers 122 are disposed in the array substrate 100A, that is, the opposing substrate 200A may not contain spacers, thus simplifying the manufacturing process of the opposing substrate 200A.

[0049] FIG7 is a partial cross-sectional schematic diagram of an electronic device 10B according to at least another embodiment of the present invention. Referring to FIG7, the embodiment of FIG7 has the same component structure, relative positional relationship and materials as the embodiment of FIG5. The partially enlarged schematic diagram of the array substrate 100B and the opposing substrate 200A of the electronic device 10B in FIG7 is substantially the same as the partially enlarged schematic diagram of the array substrate 100A and the opposing substrate 200A in FIG6A and FIG6B. The top view of the electronic device 10B in FIG7 is substantially the same as the top view of the electronic device 10 in FIG3. Therefore, the same technical features will not be described again here. The main difference between the embodiment of FIG7 and the embodiment of FIG5 is that the position of the color filter pattern 120B of the electronic device 10B in FIG7 in the array substrate 100B is different from the position of the color filter pattern 120 of the electronic device 10A in FIG5 in the array substrate 100A.

[0050] In detail, as shown in FIG7, these color filter patterns 120B are respectively disposed on these pixel electrodes 114 and correspond to these pixel electrodes 114, and are located between the first transparent common electrode 112 and the second transparent common electrode 118. With the aforementioned design, the second transparent common electrode 118 with the slit SL can be brought closer to the display medium located between the array substrate 100B and the opposing substrate 200A, so that the electric field formed between the pixel electrodes 114 and the second transparent common electrode 118 can more effectively drive the display medium, thereby improving the display quality of the electronic device 10B.

[0051] FIG8 is a partial cross-sectional schematic diagram of an electronic device 10C according to at least another embodiment of the present invention. FIG9A and FIG9B are respectively partial enlarged schematic diagrams of an array substrate 100C and a counter substrate 200C according to at least another embodiment of the present invention. Referring to FIG8, FIG9A and FIG9B, the embodiments of FIG8, FIG9A and FIG9B have most of the same component structures, relative positions and materials as the embodiments of FIG5, FIG6A and FIG6B. The top view of the electronic device 10C in FIG8 is substantially the same as the top view of the electronic device 10 in FIG3, so the same technical features will not be described again here. The main difference between the embodiments of FIG8, FIG9A and FIG9B and the embodiments of FIG5, FIG6A and FIG6B is that the array substrate 100C of the electronic device 10C in the embodiments of FIG8, FIG9A and FIG9B further includes a plurality of light-shielding metal strips 124.

[0052] In detail, as shown in Figures 8, 9A, and 9B, these light-shielding metal strips 124 are disposed on the first substrate 102 and extend along the first direction D1, and are located between the first substrate 102 and the scan lines 104. On the normal line of the first substrate 102, these light-shielding metal strips 124 overlap with the scan lines 104, and the second spacings G2 overlap with these light-shielding metal strips 124. The spacers 122 overlap with these light-shielding metal strips 124. In some embodiments, the light-shielding metal strips 124 may be in a floating state without receiving any voltage signal, but the present invention is not limited thereto. In other embodiments, the light-shielding metal strips 124 may be electrically connected to the peripheral traces (not shown) of the electronic device 10C and receive a reference voltage, such as a common voltage.

[0053] Since the array substrate 100C includes a light-shielding metal strip 124 that overlaps with the scan lines 104, the opposing substrate 200C may not include a light-shielding strip that overlaps with the scan lines 104. That is, the opposing substrate 200C has a plurality of second light-transmitting regions T2 that overlap with these scan lines 104 on the normal line of the first substrate 102. In other words, the opposing substrate 200C can be a fully light-transmitting substrate, which only includes the second substrate 202 and the alignment layer 203 disposed on the second substrate 202, thus further simplifying the manufacturing process of the opposing substrate 200C.

[0054] Furthermore, the width W7 of the light-shielding metal strip 124 is greater than the width W6 of the second spacing G2, and the width W7 of the light-shielding metal strip 124 is greater than the width W8 of the scan line 104. Specifically, in the second direction D2, the light-shielding metal strip 124 and the scan line 104 have widths W7 and W8 respectively, with W7 being greater than W8. Through the aforementioned design, light leakage between two adjacent sub-pixels PX in the second direction D2 can be reduced, and the second spacing G2 can be shielded to prevent the exposed second spacing G2 from forming an interference pattern visible to the human eye, thereby improving the display quality of the electronic device 10C.

[0055] FIG10 is a partial cross-sectional schematic diagram of an electronic device 10D according to at least another embodiment of the present invention. FIG11A and FIG11B are respectively partial enlarged schematic diagrams of an array substrate 100D and a counter substrate 200D according to at least another embodiment of the present invention. Referring to FIG10, FIG11A and FIG11B, the embodiments of FIG10, FIG11A and FIG11B have most of the same component structure, relative position relationship and materials as the embodiments of FIG3, FIG4A and FIG4B, and the top view schematic diagram of electronic device 10D in FIG10 is substantially the same as the top view schematic diagram of electronic device 10 in FIG3, so the same technical features will not be described again here. The main difference between the embodiments of FIG10, FIG11A and FIG11B and the embodiments of FIG3, FIG4A and FIG4B is that the counter substrate 200D of the electronic device 10D in the embodiments of FIG10, FIG11A and FIG11B further includes a plurality of color filter patterns 208.

[0056] As shown in Figures 10, 11A, and 11B, these color filter patterns 208 are disposed on the second substrate 202 and correspond to these pixel electrodes 114 respectively. In detail, the opposing substrate 200D further includes a planarization layer 205, a light-shielding pattern layer 204 and color filter patterns 208 are disposed on the second substrate 202, the planarization layer 205 is disposed on the light-shielding pattern layer 204 and color filter patterns 208 and covers the light-shielding pattern layer 204 and color filter patterns 208, a spacer 206 is disposed on the planarization layer 205, and an alignment layer 203 is disposed on the spacer 206 and covers the spacer 206 and planarization layer 205. Since the color filter pattern 208 is disposed in the opposing substrate 200D, the array substrate 100D may not contain the color filter pattern, thus simplifying the manufacturing process of the array substrate 100D and preventing the color filter pattern from contaminating the equipment of the array substrate 100D during the manufacturing process.

[0057] In summary, in the electronic device of at least one embodiment of the present invention, since the array substrate includes a light-shielding metal pattern that corresponds to the spacing between any two adjacent pixel electrodes and overlaps with the data lines, the opposing substrate may not include a light-shielding pattern corresponding to the data lines. This can avoid the situation where the light-shielding pattern of the corresponding data lines is broken due to excessively thin line width, thereby improving the yield of the electronic device. Furthermore, the light-shielding metal patterns are spaced apart, which can reduce the probability of debris generated by friction between the spacer and the alignment layer, so as to avoid affecting the display quality of the electronic device.

[0058] Furthermore, by providing a transparent common electrode that covers and contacts the light-shielding metal pattern, the reflection of the light-shielding metal pattern can be reduced to decrease visibility. Also, the light-shielding metal pattern in direct contact with the transparent common electrode can receive the same voltage as the transparent common electrode, such as a shared voltage. Therefore, the light-shielding metal pattern can avoid being in a floating state, reducing the risk of charge accumulation and thus improving the reliability of the electronic device. In addition, a storage capacitor can be formed between the transparent common electrode and the pixel electrode, thereby improving electrical performance and ultimately enhancing the display quality of the electronic device.

[0059] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0060] FIG1 is a top view of an electronic device according to at least one embodiment of the present invention. FIG2 is an enlarged view of region A in FIG1. ​​FIG3 is a cross-sectional view drawn along line a-a' in FIG2. FIG4A and FIG4B are respectively partial enlarged views of the array substrate and the opposing substrate according to at least one embodiment of the present invention. FIG5 is a partial cross-sectional view of an electronic device according to at least another embodiment of the present invention. FIG6A and FIG6B are respectively partial enlarged views of the array substrate and the opposing substrate according to at least another embodiment of the present invention. FIG7 is a partial cross-sectional view of an electronic device according to at least another embodiment of the present invention. FIG8 is a partial cross-sectional view of an electronic device according to at least another embodiment of the present invention. FIG9A and FIG9B are respectively partial enlarged views of the array substrate and the opposing substrate according to at least another embodiment of the present invention. FIG10 is a partial cross-sectional view of an electronic device according to at least another embodiment of the present invention. FIG11A and FIG11B are respectively partial enlarged views of the array substrate and the opposing substrate according to at least another embodiment of the present invention. [Biomaterial Storage]

[0062] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An electronic device comprising: An array substrate includes: a first substrate; a plurality of scan lines disposed on the first substrate and extending along a first direction; a plurality of data lines disposed on the first substrate and extending along a second direction, wherein the first direction is different from the second direction; a plurality of switching elements disposed on the first substrate, wherein each of the switching elements is electrically connected to one of the scan lines and one of the data lines; an insulating layer disposed on the first substrate, covering the scan lines, the data lines and the switching elements; a first transparent common electrode disposed on the insulating layer; and a plurality of pixel electrodes disposed on the first transparent common electrode, respectively electrically connected to the switching elements, wherein in the first direction, any two adjacent pixel electrodes have a first spacing. Multiple light-shielding metal patterns are disposed on the pixel electrodes and extend along the second direction, respectively corresponding to the first spacings. In the second direction, any two adjacent light-shielding metal patterns have a second spacing. On a normal line of the first substrate, the light-shielding metal patterns overlap with the data lines, and the second spacings overlap with the scan lines. A second transparent common electrode is disposed on the light-shielding metal patterns, covering and contacting the light-shielding metal patterns. A pair of opposing substrates are disposed opposite to the array substrate and have multiple first light-transmitting areas, wherein on the normal line of the first substrate, the first light-transmitting areas overlap with the data lines.

2. The electronic device as claimed in claim 1, wherein the opposing substrate comprises: A second substrate; A light-shielding pattern layer is disposed on the second substrate and includes a plurality of light-shielding strips extending along the first direction, wherein the light-shielding strips overlap with the scan lines on the normal line of the first substrate, and the second spacings overlap with the light-shielding strips; and a plurality of spacers are disposed on the light-shielding pattern layer and located between the light-shielding pattern layer and the array substrate, wherein the spacers overlap with the light-shielding pattern layer on a normal line of the second substrate, and each spacer has a top surface and a bottom surface facing each other, the top surface facing the array substrate and the bottom surface facing the light-shielding pattern layer, and the width of the bottom surface is greater than the width of the top surface.

3. The electronic device as claimed in claim 1, wherein the opposing substrate comprises: A second substrate; The array substrate includes a light-shielding pattern layer disposed on the second substrate and comprising a plurality of light-shielding strips extending along the first direction. The light-shielding strips overlap with the scan lines along the normal line of the first substrate, and the second spacing overlaps with the light-shielding strips. The array substrate further includes a plurality of spacers disposed on the second transparent common electrode and located between the second transparent common electrode and the opposing substrate. The spacers overlap with the light-shielding pattern layer along a normal line of the second substrate, and each spacer has a top surface and a bottom surface facing each other. The top surface faces the opposing substrate, and the bottom surface faces the second transparent common electrode. The width of the bottom surface is greater than the width of the top surface.

4. The electronic device as claimed in claim 2 or 3, wherein the width of each of the light-shielding strips is greater than the width of each of the second spacings.

5. The electronic device as claimed in claim 1, wherein the array substrate further comprises: Multiple color filter patterns are disposed on the second transparent common electrode and correspond to the pixel electrodes respectively.

6. The electronic device as claimed in claim 1, wherein the opposing substrate further comprises: A second substrate; Multiple color filter patterns are disposed on the second substrate and correspond to the pixel electrodes respectively.

7. The electronic device as claimed in claim 1, wherein the array substrate further comprises: Multiple color filter patterns are respectively disposed on the pixel electrodes and respectively correspond to the pixel electrodes, and are located between the first transparent common electrode and the second transparent common electrode.

8. The electronic device as claimed in claim 1, wherein the array substrate further comprises: Multiple light-shielding metal strips are disposed on the first substrate and extend along the first direction, located between the first substrate and the scan lines. The light-shielding metal strips overlap with the scan lines along the normal line of the first substrate, and the second spacings overlap with the light-shielding metal strips. A plurality of spacers are disposed on the second transparent common electrode and located between the second transparent common electrode and the opposing substrate. The spacers overlap with the light-shielding metal strips along the normal line of the first substrate, and each spacer has a top surface and a bottom surface facing each other. The top surface faces the opposing substrate, and the bottom surface faces the second transparent common electrode. The width of the bottom surface is greater than the width of the top surface.

9. The electronic device as claimed in claim 8, wherein the opposing substrate has a plurality of second light-transmitting areas, wherein the second light-transmitting areas overlap with the scan lines on the normal line of the first substrate.

10. The electronic device as claimed in claim 8, wherein the width of each of the light-shielding metal strips is greater than the width of each of the scan lines.

11. The electronic device as claimed in claim 8, wherein the width of each of the light-shielding metal strips is greater than the width of each of the second spacings.

12. The electronic device as claimed in claim 1, wherein the width of each of the light-shielding metal patterns is greater than the width of each of the data lines.

13. The electronic device as claimed in claim 1, wherein the second transparent common electrode has a plurality of slits that overlap with the pixel electrodes on the normal of the first substrate.

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