Method of and device for generating layout diagram

Abstract

An embodiment method of generating a via layout diagram of a layout plan of a semiconductor device prior to application of an optical proximity correction (OPC) process includes obtaining an initial layout plan that includes a first layout pattern indicative of a first conductive structure, a second layout pattern indicative of a second conductive structure, and an initial via layout pattern indicative of electrically coupling of the first conductive structure and the second conductive structure. The method includes deriving a first estimated pattern based on the first layout pattern, deriving a second estimated pattern based on the second layout pattern, and determining a modified via layout pattern indicative of a via structure based on the first estimated pattern and the second estimated pattern. The modified via layout pattern has a curved shape prior to the application of the OPC process.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method and elements for generating a layout diagram. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the evolution of ICs, functional density (i.e., the number of interconnected components per wafer area) has generally increased, while geometry (i.e., the smallest component (or line) that can be manufactured using a process, which can be measured as a critical size in some applications) has decreased. This reduction in size typically benefits manufacturing by increasing efficiency and reducing associated costs. However, the resistance of conductive structures within semiconductor devices increases as their width or cross-sectional area (perpendicular to the current direction) decreases. Summary of the Invention

[0003] In some aspects, a photomask for a semiconductor element based on a layout plan includes a substrate and a via mask pattern structure on the substrate. The via mask pattern structure corresponds to a via layout pattern included in the layout plan and indicates the via structure of the semiconductor element, which connects a first conductive structure under the via structure and a second conductive structure on the via structure. The via layout pattern has a curved shape before the application of optical proximity correction (OPC) processes.

[0004] In some aspects, a method for generating a via layout pattern of a semiconductor device prior to applying an Optical Proximity Correction (OPC) process includes obtaining an initial layout plan, which includes a first layout pattern included in a first metallization layout plan and indicating a first conductive structure, a second layout pattern included in a second metallization layout plan and indicating a second conductive structure, and an initial via layout pattern included in the initial via layout plan and indicating electrical coupling between the first and second conductive structures. The method includes deriving a first predicted pattern based on the first layout pattern, deriving a second predicted pattern based on the second layout pattern, and determining a modified via layout pattern based on the first and second predicted patterns. The modified via layout pattern indicates via structures of the semiconductor device, the via structures connecting the first conductive structure under the via structure and the second conductive structure on the via structure. The method further includes saving a via layout pattern corresponding to a layout plan in which the initial via layout pattern in the initial via layout plan is replaced with the modified via layout pattern to a memory element of the process device. The modified via layout pattern has a curved shape prior to applying the OPC process.

[0005] In some aspects, process elements for generating via layout patterns of semiconductor devices prior to applying optical proximity correction (OPC) processes include memory devices and processing circuitry coupled to the memory devices. The processing circuitry is configured to obtain an initial layout plan including a first layout pattern in a first metallized layout plan indicating a first conductive structure, a second layout pattern in a second metallized layout plan indicating a second conductive structure, and an initial via layout pattern in the initial via layout plan indicating electrical coupling between the first and second conductive structures. The processing circuitry is configured to derive a first predicted pattern based on the first layout pattern, derive a second predicted pattern based on the second layout pattern, and determine a modified via layout pattern based on the first and second predicted patterns. The modified via layout pattern indicates via structures of the semiconductor devices, the via structures connecting the first conductive structure under the via structure and the second conductive structure on the via structure. The processing circuitry is further configured to save a via layout pattern corresponding to a layout plan in which the modified via layout pattern replaces the initial via layout pattern in the initial via layout plan in the initial via layout plan into the memory device. The modified via layout pattern has a curved shape before the application of the OPC process. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure are most readily understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for the purpose of discussing clarity. Figure 1 is a block diagram of an integrated circuit (IC) manufacturing system according to some embodiments, and the associated IC manufacturing process. Figure 2 is a cross-sectional view of a semiconductor device according to some embodiments. Figures 3A to 3D are plan views of various layout patterns or predicted patterns of semiconductor element layers at different stages of the masking data preparation process according to some embodiments. Figures 4A to 4C are plan views of various layout patterns or predicted patterns of the first metallization layer, the second metallization layer, and the via layer of a semiconductor element according to some embodiments. Figures 5A and 5B are plan views of via layout patterns of via layers of semiconductor devices according to some embodiments, taking into account predicted patterns of the first and second metallization layers of the semiconductor device. Figures 6A and 6B are plan views of exemplary portions of a photomask based on the through-hole layer of a semiconductor element exemplified in Figures 5A and 5B, according to some embodiments. Figure 7 is a block diagram of a portion of the masking data preparation process according to some embodiments. Figures 8A to 8C are plan views of additional layout pattern examples of a first metallization layer, a second metallization layer, and a via layer with curved patterns according to some embodiments. Figure 9 is a flowchart of a method for generating a via layout diagram of a semiconductor device layout plan before applying an optical proximity correction (OPC) process, according to some embodiments. Figure 10 is a block diagram of an electronic design automation system according to some embodiments. Implementation

[0007] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature on or over a second feature in the following description may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "below," "under," "lower than," "above," and "higher than," are used to easily describe the relationship between one element or feature and another element or feature depicted in the diagram. In addition to the direction depicted in the diagram, spatially relative terms also include different orientations of the element during use or operation. Elements can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this disclosure can also be interpreted in this way. Furthermore, the term "composed of" can mean "includes" or "comprises." In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element selected from A, an element selected from B, and an element selected from C, unless otherwise described.

[0009] Figure 1 is a block diagram of an integrated circuit (IC) manufacturing system 100 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout planning of semiconductor elements, the manufacturing system 100 is used to manufacture (A) one or more photomasks or (B) at least one of one or more features in a layer of a semiconductor element.

[0010] In Figure 1, IC manufacturing system 100 includes entities such as a design house 120, a mask house 130, and an IC manufacturer / fabricator (fab) 150, which interact with each other in design, development, and manufacturing cycles and / or services related to the manufacture of IC components 160. The entities in system 100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 120, mask house 130, and IC manufacturing company 150 are owned by a single larger company. In some embodiments, two or more of the design house 120, mask house 130, and IC manufacturing company 150 coexist in a shared facility and use shared resources.

[0011] Design firm (or design team) 120 generates a layout plan 122 for an IC design. In some embodiments, layout plan 122 includes one or more layout diagrams, each including various geometric patterns designed for an IC element 160 (e.g., a semiconductor element). The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC element 160 to be manufactured. Various layer combinations form various IC features. For example, portions of layout plan 122 include layout patterns indicating various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed based on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design firm 120 implements appropriate design procedures to form layout plan 122. Design procedures include one or more of logic design, physical design, or placement and routing. In some embodiments, each layout diagram of layout plan 122 is presented in one or more data files containing geometric pattern information. For example, each layout diagram of layout plan 122 may be represented in GDSII file format or DFII file format.

[0012] Mask manufacturing end 130 includes mask data preparation 132 and mask manufacturing 144. Mask manufacturing end 130 uses layout planning 122 to manufacture one or more masks 145 for fabricating various layers of IC device 160 according to layout planning 122. Mask manufacturing end 130 performs mask data preparation 132, where layout planning 122 is translated into a representative data file (RDF). Mask data preparation 132 provides the RDF to mask manufacturing 144. Mask manufacturing 144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (photomask) 145 or a semiconductor wafer 153. Layout planning 122 is manipulated by mask data preparation 132 to conform to the specific characteristics of the mask writer and / or the requirements of IC manufacturing company 150. In Figure 1, mask data preparation 132 and mask manufacturing 144 are shown as separate elements. In some embodiments, mask data preparation 132 and mask manufacturing 144 can be collectively referred to as mask data preparation.

[0013] In some embodiments, mask data preparation 132 includes one or more of the following stages: logic operation (LOP) stage 132a, resolution enhancement technique (RET) stage 132b, mask rule checker (MRC) stage 132c, and lithography process checking (LPC) stage 132d. In some embodiments, each of the above stages receives an input layout diagram in GDSII or DFII file format from the previous stage and outputs the processing result as an output layout diagram in GDSII or DFII file format to the subsequent stage. In some embodiments, certain stages and / or operations described herein are omitted, while some additional stages and / or operations are included in mask data preparation 132. In some embodiments, these stages are performed in a different order than in the example in FIG1.

[0014] In some embodiments, the Logic Operation (LOP) phase 132a corresponds to modifying the input layout diagram (e.g., the layout diagram from layout plan 122 from design company 120) according to manufacturing rules. In some embodiments, the Logic Operation (LOP) phase 132a includes checking whether the input layout diagram conforms to a set of rules derived from various manufacturer constraints, and modifying the input layout diagram accordingly to obtain an output layout diagram that conforms to the set of rules.

[0015] In some embodiments, the resolution enhancement technique (RET) phase 132b corresponds to modifying the input layout diagram (e.g., the output layout diagram from the logic operation (LOP) phase 132a) to obtain an output layout diagram that compensates for various constraints in the lithography process used to fabricate the IC element 160. In some embodiments, the resolution enhancement technique (RET) phase 132b includes rule-based optical proximity correction (OPC) processes and / or model-based optical proximity correction (OPC) processes, which correspond to using lithography enhancement techniques to compensate for image errors, such as errors that may be caused by diffraction, interference, other process effects, or similar factors. In some embodiments, the resolution enhancement technique (RET) phase 132b also includes one or more other enhancement techniques, such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, or similar techniques or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats optical proximity correction (OPC) as a reverse imaging problem.

[0016] In some embodiments, the Mask Rule Checker (MRC) stage 132c corresponds to checking the layout drawing that has undergone the process in the Resolution Enhancement Technology (RET) using a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in the semiconductor manufacturing process, or similar factors. In some embodiments, the Mask Rule Checker (MRC) stage 132c also corresponds to modifying the layout drawing to compensate for lithography effects during mask fabrication 144. This may undo some of the modifications performed by the Optical Proximity Correction (OPC) in the Resolution Enhancement Technology (RET) stage 132b to conform to the mask creation rules.

[0017] In some embodiments, the Lithography Process Inspection (LPC) phase 132d corresponds to the process that the analog IC manufacturing company 150 will implement to manufacture IC component 160. The simulation of Lithography Process Inspection phase 132d is based on a layout diagram from a previous phase (e.g., Mask Rule Checker (MRC) phase 132c) to create one or more simulated manufacturing features representing corresponding portions of the IC component 160 to be manufactured based on the layout diagram from Mask Rule Checker (MRC) phase 132c. Process parameters in the Lithography Process Inspection simulation include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The simulation of Lithography Process Inspection phase 132d considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or similar factors or combinations thereof. In some embodiments, after one or more simulated manufacturing features are created in the Lithography Process Inspection (LPC) stage 132d, if the size, shape, and / or spatial relationship of the simulated features does not conform to the design rules or design specifications, the process continues to repeat the Resolution Enhancement Technology (RET) stage 132b and / or the Masking Rule Checker (MRC) stage 132c to further refine the layout diagram.

[0018] In this example, following the Lithography Process Inspection (LPC) stage 132d, the mask data preparation 132 further includes a fracturing process (FRAC) stage 132e. In some embodiments, the fracturing process stage 132e receives an input layout drawing from the previous stage (e.g., the Lithography Process Inspection stage 132d) in GDSII or DFII file format and outputs the process results as a mask file in RDF format to a subsequent stage (e.g., mask manufacturing 144). In some embodiments, the fracturing process stage 132e corresponds to "segmenting" design features into polygons or other component shapes suitable for mask production.

[0019] Following mask data preparation 132 and during mask manufacturing 144, a mask 145 or a set of masks 145 (collectively referred to as "masks 145") is manufactured based on a modified layout drawing and / or a mask file converted from the modified layout drawing. In some embodiments, mask manufacturing 144 includes performing one or more lithography exposures based on the modified layout drawing and / or mask file from mask data preparation 132. In some embodiments, an electron beam or multi-electron beam apparatus is used to form a pattern on the mask (photomask or marker) (e.g., mask 145) based on the modified layout drawing and / or mask file. Mask 145 can be formed using various techniques. In some embodiments, mask 145 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and passes through the transparent areas. In one example, the binary mask version of mask 145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 145 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of mask 145, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and image quality. In various examples, the phase-shift mask can be an attenuating PSM or an alternating PSM. The mask produced by mask fabrication 144 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 153, in etching processes to form various etched regions in semiconductor wafer 153, and / or for other suitable processes.

[0020] An IC manufacturing company is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, an IC manufacturing company is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) of multiple IC products, a second manufacturing facility that provides back-end manufacturing (back-end-of-line, BEOL) for interconnecting and packaging IC products, and a third manufacturing facility that provides other services for the foundry business.

[0021] IC manufacturing companies include manufacturing tools 152 configured to perform various manufacturing operations on semiconductor wafers 153, such that IC components 160 are manufactured according to a mask (e.g., mask 145). In various embodiments, manufacturing tools 152 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a chemical vapor deposition (CVD) chamber or a low-pressure chemical vapor deposition (LPCVD) furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as described herein.

[0022] An IC manufacturing company uses a mask 145, fabricated by mask fabrication end 130, to fabricate IC device 160. Therefore, the IC manufacturing company uses at least indirectly one or more layout patterns of layout plan 122 to fabricate IC device 160. In some embodiments, a semiconductor wafer 153 is fabricated by the IC manufacturing company using mask 145 to form IC device 160. In some embodiments, IC fabrication includes performing one or more lithography exposures based at least indirectly on one or more layout patterns of layout plan 122. Semiconductor wafer 153 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 153 further includes one or more various doped regions, dielectric features, multilayer interconnects, or the like (formed in subsequent fabrication steps).

[0023] Figure 2 is a cross-sectional view of a semiconductor element 200 according to some embodiments. In some embodiments, the semiconductor element 200 corresponds to an IC element 160 manufactured based on the example in Figure 1. In some embodiments, this cross-sectional view is a simplified cross-sectional view, and many features are simplified or not shown.

[0024] The semiconductor device 200 in Figure 2 includes a substrate 210 having an active region 212 and a gate structure 214 formed on or partially within the substrate 210. In this example, the semiconductor device 200 includes a metal-to-drain / source (MD) structure 222 coupled to the active region 212. In this example, the semiconductor device 200 includes a via-to-drain / source (VD) structure coupled to the MD structure 222 and a via-to-gate (VG) structure coupled to the gate structure 214, with a VD / VG layer located above the substrate 210 (relative to the Z direction). In some embodiments, the semiconductor element 200 further includes a plurality of metallization layers (e.g., M0, M1, M2, ..., Mn-1 and Mn layers) and a plurality of via layers (e.g., V0, V1, V2, ..., Vn-2 and Vn-1 layers) over the VD / VG layer and the substrate 210 (n is a positive integer). In some embodiments, the number of metallization layers over the substrate 210 ranges from 8 to 14. In some embodiments, the Vn-1 layer represents a via structure between and connecting conductive structures (e.g., conductive lines) in the Mn-1 layer and the Mn layer. In some embodiments, the M0 layer represents a first metallization layer over the substrate 210. In some embodiments, the plurality of metallization layers and the plurality of via layers comprise conductive materials, including copper, aluminum, gold, tungsten, combinations thereof, or the like.

[0025] The semiconductor element 200 in Figure 2, as a non-limiting example, further includes conductive structures disposed beneath the substrate 210. For example, the semiconductor element 200 further includes backside metallization layers BMO and BM1, and backside via layers BVD and BVO. In this example, the BVD layer represents a backside via structure connecting the backside conductive structures (e.g., conductive lines) in the active region 212 and the BMO layer; while the BVO layer represents a backside via structure connecting the backside conductive structures (e.g., conductive lines) in the BMO and BM1 layers. In some embodiments, the BMO layer represents a first metallization layer beneath the substrate 210. In this example, the semiconductor element 200 includes two backside metallization layers and corresponding via layers. In some embodiments, the number of backside metallization layers beneath the substrate 210 ranges from 2 to 6. In some embodiments, some or all of the back-side conductive structures (e.g., back-side metallization layers BMO and BM1, and back-side via layers BVD and BVO) are at least partially embedded in the substrate 210. In some embodiments, the back-side metallization layers BMO and BM1, and the back-side via layers BVD and BVO comprise conductive materials, including copper, aluminum, gold, tungsten, combinations thereof, or the like. In some other embodiments, the semiconductor element does not include any back-side conductive structures.

[0026] In some embodiments, the semiconductor element 200 includes one or more redistribution layers and conductive pad structures (not shown in FIG. 2) above the redistribution layers. In some embodiments, the semiconductor element 200 further includes conductive terminal structures (e.g., conductive bumps, copper pillar bumps, solder bumps, or the like, not shown in FIG. 2) above the conductive pad structures. In some embodiments, the semiconductor element 200 also includes one or more back-side redistribution layers and back-side conductive pad structures (not shown in FIG. 2) below the back-side redistribution layers. In some embodiments, the semiconductor element 200 also includes back-side conductive terminal structures (e.g., conductive bumps, copper pillar bumps, solder bumps, or the like, not shown in FIG. 2) below the back-side conductive pad structures.

[0027] In some embodiments, the semiconductor element 200 includes transistors formed in a front-end (FEOL) portion of the semiconductor element 200 based on an active region 212 and a gate structure 214. In some embodiments, one or more functional circuit blocks are formed based on electrical connections of transistors in the FEOL portion of the semiconductor element 200. In some embodiments, portions of the semiconductor element 200 at and above a specific metallization layer (e.g., M5 layer and above) correspond to a back-end (BEOL) portion of the semiconductor element 200. In some embodiments, additional transistors, capacitors, resistors, inductors, combinations thereof, or the like are also formed in the BEOL portion of the semiconductor element 200.

[0028] Figure 3A is a plan view of a set of layout patterns of a semiconductor element layer, conforming to some embodiments. Figure 3 includes portions of three layout patterns 312, 314, and 316, the upper and lower portions of which are truncated for simplicity. In this example, layout patterns 312, 314, and 316 correspond to the layout patterns of the metallization layer, indicating the conductive structure of the semiconductor element metallization layer.

[0029] In this example, layout patterns 312, 314, and 316 have Manhattanized curvilinear shapes based on Manhattanized lines. In some applications, "Manhattanized lines" correspond to lines extending along a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), where the first and second horizontal directions are perpendicular to each other. Therefore, Manhattanized curvilinear shapes correspond to shapes having sides formed based on staircase-like line segments.

[0030] The layout pattern with a Manhattan-shaped curve in Figure 3A corresponds to one type of non-straight layout pattern, as a non-limiting example. In some embodiments, as another type of non-straight layout pattern, the layout pattern includes a curved shape with a profile formed based on parametric equations and parameters (also referred to in this disclosure as having a parametric curve shape).

[0031] Figure 3B is a plan view of a set of predicted patterns 322, 324, and 326, which are derived or derivable from layout patterns 312, 314, and 316 in Figure 3A, conforming to some embodiments. In some embodiments, predicted patterns 322, 324, and 326 indicate the estimated size and shape of the resulting features of a semiconductor element (represented by layout patterns 312, 314, and 316), based on how a simulated mask is manufactured (e.g., with respect to the processes of mask data preparation 132 and mask manufacturing 144 in Figure 1) and how the semiconductor element (e.g., IC element 160) is manufactured (e.g., with respect to the processes of IC manufacturing company 150). In some embodiments, predicted patterns 322, 324, and 326 are obtained in a lithography process inspection (LPC) stage (e.g., lithography process inspection stage 132d in Figure 1) after applying an optical proximity correction process to layout patterns 312, 314, and 316. In some embodiments, the predicted patterns 322, 324, and 326 are obtained during the optical proximity correction process in the resolution enhancement technique (RET) stage (e.g., resolution enhancement technique stage 132b in FIG. 1) as target images for the optical proximity correction process based on inverse lithography (ILT).

[0032] Figure 3C is a plan view of a set of layout patterns 332, 334, and 336, corresponding to the result of applying a first optical proximity correction process example to layout patterns 312, 314, and 316 in Figure 3A, conforming to some embodiments. In some embodiments, layout patterns 332, 334, and 336 have Manhattan curve shapes. Figure 3D is a plan view of a set of layout patterns 342, 344, and 346, corresponding to the result of applying a second optical proximity correction process example to layout patterns 312, 314, and 316 in Figure 3A, conforming to some embodiments. In some embodiments, layout patterns 332, 334, and 336 have parametric curve shapes.

[0033] Figure 4A is a plan view of various layout patterns included in the layout planning of semiconductor devices according to some embodiments. In this example, the layout pattern in Figure 4A corresponds to a layout pattern prior to the application of optical proximity correction. In some embodiments, the layout pattern in Figure 4A is included in a corresponding layout drawing from a design firm (e.g., design firm 120 in Figure 1), prior to masking material preparation (e.g., masking material preparation 132 in Figure 1).

[0034] Figure 4A includes layout patterns 312, 314, and 316, which are included in a first metallization layout of a layout plan for a first metallization layer of a semiconductor device, as illustrated in the example of Figure 3A. In some embodiments, layout patterns 312, 314, and 316 indicate conductive structures in the first metallization layer of the semiconductor device. Figure 4A also includes layout pattern 412, which is included in a second metallization layout of a layout plan for a second metallization layer of the semiconductor device. In some embodiments, layout pattern 412 indicates conductive structures in a second metallization layer above the first metallization layer of the semiconductor device. In this example, layout patterns 312, 314, 316, and 412 have Manhattan curve shapes. In some other examples, the layout patterns corresponding to 312, 314, 316, and 412 have parametric curve shapes.

[0035] Figure 4A also includes a via layout pattern 416, which is included in the via layout diagram for a via layer of a semiconductor device. In some embodiments, via layout pattern 416 indicates a via structure that electrically connects the conductive structure indicated by layout pattern 312 and the conductive structure indicated by layout pattern 412. In this example, via layout pattern 416 has a Manhattan shape, such as a square or rectangular shape.

[0036] Figure 4B is a plan view of various predicted patterns and modified via layout pattern 418 according to some embodiments. Figure 4B includes predicted patterns 322, 324, and 326, which can be derived from layout patterns 312, 314, and 316, as described in the example of Figure 3B. Figure 4B also includes predicted pattern 422, which can be derived from layout pattern 412 in Figure 4A. In this example, the layout pattern of the via layer is limited to a Manhattan shape. In this example, because layout patterns 312 and 412 have non-linear sides, via layout pattern 416 can be replaced by a modified via layout pattern 418, which still maintains a Manhattan shape but has a larger area than via layout pattern 416. Therefore, the resistance of the resulting via structure based on the modified via layout pattern 418 will be lower than the resistance of the corresponding via structure based on via layout pattern 416.

[0037] In Figure 4B, predicted patterns 322 and 422 overlap and define an overlap region 430, as further emphasized in Figure 4C. In Figure 4C, the modified via layout pattern 418 is located within the overlap region 430, and the area of ​​the overlap region 430 is much larger than the area of ​​the modified via layout pattern 418. However, due to the Manhattan shape limitation of the via layer layout pattern, a considerable portion of the overlap region 430 is not actually used for electrical connections between the conductive structures corresponding to predicted pattern 322 and the conductive structures corresponding to predicted pattern 422.

[0038] According to one or more embodiments of this disclosure, for a via structure with a first conductive structure below an electrically connected via structure and a second conductive structure above the via structure, the via layout pattern of the via structure is indicated to have a curved shape (rather than a Manhattan shape) before the application of an optical proximity correction process. In some embodiments, the first conductive structure corresponds to a first predicted pattern that can be derived from the first layout pattern, the second conductive structure corresponds to a second predicted pattern that can be derived from the second layout pattern, and the first and second predicted patterns overlap each other and define an overlap region. In some embodiments, based on the via layout pattern with a curved shape, the size and shape of the via layout pattern can better fit the overlap region to increase or maximize the area of ​​the via layout pattern and maximize the area of ​​the overlap region for electrical connection. Therefore, the resistance of the via structure with a curved shape based on one or more embodiments of this disclosure can be further reduced compared to the corresponding structure with a Manhattan shape.

[0039] Figure 5A is a plan view of via layout patterns 512, 521, 522, 523, 524, and 525 of the via layer of a semiconductor device (before the application of optical proximity correction processes). This plan view is based on a first data preparation example and considers predicted patterns 532, 534, 536, and 538 of the first and second metallization layers of the semiconductor device, consistent with some embodiments. In this non-limiting example, predicted patterns 532, 534, and 536 correspond to predicted patterns 322, 324, and 326 that can be derived from layout patterns 312, 314, and 316 of the first metallization layer, as described in the examples of Figures 3A-3B and 4A-4B. In this non-limiting example, predicted layout pattern 538 corresponds to predicted layout pattern 422 that can be derived from layout pattern 412 of the second metallization layer, as described in the examples of Figures 4A-4B.

[0040] As illustrated in the example of Figure 4A, in this non-limiting example, the via layout pattern 512 is based on a modified via layout pattern 416. In this non-limiting example, the via layout pattern 512 has an elliptical shape before the application of the optical proximity correction process. Similar to the example described in Figure 4C, predicted patterns 532 and 538 overlap each other and define an overlap region (e.g., corresponding to overlap region 430 in Figure 4C). In some embodiments, the via layout pattern 512 is determined from a basic elliptical profile in a layout library by adjusting its size, tilt, positioning, or a combination thereof, based on reducing the difference between the modified via layout pattern and the overlap region. In some embodiments, determining the via layout pattern 512 involves creating an error function based on the difference between the area of ​​the elliptical profile and the area of ​​the overlap region, and then adjusting the elliptical profile according to the error function to minimize the difference.

[0041] Furthermore, via layout patterns 521, 522, 523, 524, and 525 correspond to a set of dummy layout patterns of the via layer of a semiconductor device. In some embodiments, each of these dummy layout patterns has a corresponding free shape. In some embodiments, these dummy layout patterns (i.e., via layout patterns 521, 522, 523, 524, and 525) are located within a reference distance from via layout pattern 512. In some embodiments, the reference distance corresponds to the optical proximity correction (OPC) range of an optical proximity correction process to be applied to via layout patterns 512, 521, 522, 523, 524, and 525. In some embodiments, these dummy layout patterns (i.e., via layout patterns 521, 522, 523, 524, and 525) are omitted.

[0042] Figure 5B is a plan view of via layout patterns 514, 541, 542, 543, 544, 545, 546, and 547 (before applying an optical proximity correction process) according to some embodiments for via layers of semiconductor devices, based on a second data preparation example, with reference to predicted patterns 532, 534, 536, and 538 of the first and second metallization layers of the semiconductor device. The non-limiting examples in Figure 5B are variations of the examples in Figure 5A. Therefore, components in Figure 5B that are the same or similar to those in Figure 5A are given the same reference numerals, and their descriptions are simplified or omitted.

[0043] In some embodiments, the via layout pattern 514 prior to the application of the optical proximity correction process has a freeform shape, corresponding to an irregular profile, asymmetry, or both. In some embodiments, the via layout pattern 514 has a freeform profile based on reducing the difference between the freeform profile and the region profile of the overlapping area (e.g., corresponding to the overlapping region 430 in FIG. 4C). In some embodiments, the freeform profile via layout pattern 514 is based on the sidewall fit of predicted patterns 532 and 538 that define the region profile of the overlapping area, taking into account various design rules and / or constraints of masking data preparation.

[0044] Furthermore, via layout patterns 541, 542, 543, 544, 545, 546, and 547 correspond to a set of dummy layout patterns of the via layer of a semiconductor device. In some embodiments, each of these dummy layout patterns has a corresponding free shape. In some embodiments, this set of dummy layout patterns (i.e., via layout patterns 541, 542, 543, 544, 545, 546, and 547) is located within a reference distance from via layout pattern 514. In some embodiments, the reference distance corresponds to the optical proximity correction (OPC) range of the optical proximity correction process to be applied to via layout patterns 541, 542, 543, 544, 545, 546, and 547. In some embodiments, this set of dummy layout patterns (i.e., via layout patterns 541, 542, 543, 544, 545, 546, and 547) is omitted.

[0045] Figure 6A is a plan view of a portion of a first photomask example 600A of a via layer of a semiconductor element according to some embodiments, based on the example in Figure 5A. In some embodiments, the via layout pattern in Figure 5A (also included in Figure 6A as a dashed shape for comparison) is further processed based on one or more process stages of mask data preparation (e.g., mask data preparation 132 in Figure 1), including, for example, an optical proximity correction process, and the photomask 600A is manufactured according to the result of the mask data preparation based on the via layout pattern in Figure 5A. The plan view of the photomask 600A in Figure 6A is a simplified plan view of a portion of the photomask 600A, and some features of the photomask 600A are simplified or omitted in Figure 6A.

[0046] In FIG. 6A, the photomask 600A includes a substrate 610 (e.g., a fused silica substrate) and a via mask pattern structure 612 above the substrate 610. In this example, the via mask pattern structure 612 corresponds to a via layout pattern included in a via layout diagram (e.g., layout pattern 512 in FIG. 5A and shown in FIG. 6A for comparison) and indicates a via structure of a semiconductor element that connects a first conductive structure below the via structure (e.g., indicated by layout pattern 312 in FIG. 4A) and a second conductive structure above the via structure (e.g., indicated by layout pattern 412 in FIG. 4A). In this example, the via layout pattern 512 has a curved shape prior to the application of an optical proximity correction process, and the contour of the via mask pattern structure 612 has additional protrusions and recesses compared to the via layout pattern 512, as a result of one or more other stages of mask data preparation (e.g., including the application of an optical proximity correction process).

[0047] In some embodiments, the first conductive structure corresponds to a first predicted pattern (e.g., predicted pattern 532 in FIG. 5A) that can be derived from a first layout pattern (e.g., layout pattern 312 in FIG. 4A) included in a first metallized layout diagram of the layout plan. In some embodiments, the second conductive structure corresponds to a second predicted pattern (e.g., predicted pattern 538 in FIG. 5A) that can be derived from a second layout pattern (e.g., layout pattern 412 in FIG. 4A) included in a second metallized layout diagram of the layout plan. In some embodiments, the first and second predicted patterns overlap each other and define an overlapping region (e.g., overlapping region 430 in FIG. 4C). In some embodiments, the via layout pattern 512 prior to the application of the optical proximity correction process is located within the overlapping region.

[0048] In some embodiments, as described with reference to the example in FIG5A, the via layout pattern 512 prior to the application of the optical proximity correction process has an elliptical shape. In some embodiments, the via layout pattern 512 prior to the application of the optical proximity correction process has an elliptical profile, which is a basic elliptical profile obtained from a layout library by adjusting the size, positioning, tilting, or a combination thereof, based on reducing the difference between the via layout pattern prior to the application of the optical proximity correction process and the overlapping area.

[0049] In some embodiments, the photomask 600A further includes a set of dummy mask pattern structures 621, 622, 623, 624, and 625 above the substrate. In some embodiments, this set of dummy mask pattern structures corresponds to a set of dummy layout patterns included in a via layout diagram of a layout plan (e.g., via layout patterns 512, 521, 522, 523, 524, and 525 in FIG. 5A). In some embodiments, each of the set of dummy layout patterns has a corresponding free shape.

[0050] Figure 6B is a partial plan view of a second photomask example 600B of a semiconductor element via layer, according to some embodiments and the example in Figure 5B. In some embodiments, the via layout pattern in Figure 5B (also included in Figure 6B as a dashed shape for comparison) is further processed based on one or more mask data preparation process stages (e.g., mask data preparation 132 in Figure 1), including, for example, an optical proximity correction process, and the photomask 600B is manufactured based on the mask data preparation result based on the via layout pattern in Figure 5B. The plan view of the photomask 600B in Figure 6B is a simplified plan view of a portion of the photomask 600B, and some features of the photomask 600B are simplified or omitted in Figure 6B.

[0051] In this non-limiting example, photomask 600B is a variant of photomask 600A, and components in FIG. 6B that are the same or similar to those in FIG. 6A are given the same reference numerals, and their descriptions are simplified or omitted. In FIG. 6B, photomask 600B includes a substrate 610 (e.g., a fused silica substrate) and a via mask pattern structure 614 above the substrate 610. In this example, the via mask pattern structure 614 corresponds to a via layout pattern included in a via layout diagram of a layout plan (e.g., layout pattern 514 in FIG. 5B and presented in FIG. 6B for comparison) and indicates a via structure of a semiconductor element that connects a first conductive structure below the via structure (e.g., indicated by layout pattern 312 in FIG. 4A) and a second conductive structure above the via structure (e.g., indicated by layout pattern 412 in FIG. 4A). In this example, the via layout pattern 514 has a curved shape before the application of the optical proximity correction process, while the via mask pattern structure 614 has protrusions and depressions compared to the via layout pattern 512, which is the result of one or more other masking material preparation stages (including the application of the optical proximity correction process).

[0052] In some embodiments, as described with reference to the example in FIG5B, prior to the application of the optical proximity correction process, the via layout pattern 514 has a freeform shape corresponding to an irregular profile, asymmetry, or both. In some embodiments, prior to the application of the optical proximity correction process, the via layout pattern 514 has a freeform profile based on reducing the difference between the freeform profile and the region profile of the overlapping area.

[0053] In some embodiments, the photomask 600B further includes a set of dummy mask pattern structures 631, 632, 633, 634, 635, 636, and 637 above the substrate. In some embodiments, this set of dummy mask pattern structures corresponds to a set of dummy layout patterns included in a via layout diagram of a layout plan (e.g., via layout patterns 514, 541, 542, 543, 544, 545, 546, and 547 in FIG. 5B). In some embodiments, each of the set of dummy layout patterns has a corresponding free shape.

[0054] Figure 7 is a block diagram of a portion of a mask data preparation process 700 according to some embodiments. In some embodiments, the mask data preparation process 700 is a variation of the mask data preparation 132 in Figure 1. In Figure 7, the mask data preparation process 700 includes various stages for processing via layout diagrams for layout planning of semiconductor elements, with reference to examples in Figures 4A to 5B.

[0055] In Figure 7, the masking data preparation process 700 includes a logic operation stage 710 for the via layer corresponding to logic operation (LOP) stage 132a in Figure 1. The logic operation stage 710 receives a layout map 712 of the via layer from a design firm (e.g., design firm 120) and outputs a refined layout map to a via reshape / rotate stage 720. In this example, the via reshape / rotate stage 720 also receives a predicted pattern of the adjacent metallization layer obtained during the masking data preparation of the layout map of the adjacent metallization layer (e.g., masking data preparation 132 of the adjacent metallization layer, indicated by reference numeral 722 in Figure 7). In some embodiments, the via reshape / rotate stage 720 modifies the via layout pattern based on the method described in the examples of Figures 5A-5B. After stage 720, the mask data preparation process 700 enters the resolution enhancement technique (RET) / optical proximity correction (OPC) stage 730 of the via layer (corresponding to resolution enhancement technique (RET) stage 132b in FIG1), after which the processed layout map is output to one or more other stages of the mask data preparation process 700 (e.g., stages 132c, 132d and 132e in FIG1) (indicated by reference numeral 732 in FIG7).

[0056] Figures 8A to 8C are plan views of additional layout pattern examples 800A, 800B, and 800C according to some embodiments, used for a first metallization layer, a second metallization layer, and a via layer having curved patterns, respectively. In these non-limiting examples, the via layout pattern is based on the masking data preparation example in Figure 5B.

[0057] In Figure 8A, layout pattern example 800A includes layout pattern 812 in a first metallization layout pattern of a layout plan for a first metallization layer of a semiconductor element, and layout pattern 814 in a second metallization layout pattern of a layout plan for a second metallization layer of the semiconductor element. In this example, layout patterns 812 and 814 have Manhattan curve shapes. Furthermore, layout pattern example 800A includes via layout pattern 822 and dummy patterns 823-829 in a via layout pattern of a via layer of the semiconductor element. In some embodiments, via layout pattern 822 represents a via structure electrically connecting a conductive structure indicated by layout pattern 812 and a conductive structure indicated by layout pattern 814. In this example, via layout pattern 822 is based on a fit between the freeform profile of via layout pattern 822 and the region profile of the overlapping area defined by the predicted patterns derived from layout patterns 812 and 814.

[0058] In Figure 8B, layout pattern example 800B includes layout pattern 832 in a first metallization layout pattern of a layout plan for a first metallization layer of a semiconductor element, and layout pattern 834 in a second metallization layout pattern of a layout plan for a second metallization layer of the semiconductor element. In this example, layout patterns 832 and 834 have Manhattan curve shapes. Furthermore, layout pattern example 800B includes via layout pattern 842 and dummy patterns 843-847 in a via layout pattern of a via layer of the semiconductor element. In some embodiments, via layout pattern 842 represents a via structure electrically connecting a conductive structure indicated by layout pattern 832 and a conductive structure indicated by layout pattern 834. In this example, via layout pattern 842 is based on a fit between the freeform profile of via layout pattern 842 and the region profile of the overlapping area defined by the predicted patterns derived from layout patterns 832 and 834.

[0059] In Figure 8C, layout pattern example 800C includes layout pattern 852 in a first metallization layout pattern of a layout plan for a first metallization layer of a semiconductor element, and layout pattern 854 in a second metallization layout pattern of a layout plan for a second metallization layer of the semiconductor element. In this example, layout patterns 852 and 854 have Manhattan curve shapes. Furthermore, layout pattern example 800C includes via layout pattern 862 and dummy patterns 863-874 in a via layout pattern of a via layer of the semiconductor element. In some embodiments, via layout pattern 862 represents a via structure electrically connecting a conductive structure indicated by layout pattern 852 and a conductive structure indicated by layout pattern 834. In this example, via layout pattern 862 is based on a fit between the freeform profile of via layout pattern 862 and the region profile of the overlapping area defined by the predicted patterns derived from layout patterns 852 and 854.

[0060] Figure 9 is a flowchart of a method 900 for generating a via layout pattern of semiconductor devices prior to the application of an optical proximity correction process, according to some embodiments. Method 900 can be implemented, for example, using an electronic design automation (EDA) system 1000 (Figure 10, discussed below) and an integrated circuit (IC) manufacturing system 100 of Figure 1, according to some embodiments. In some embodiments, method 900 is part of a mask data preparation process, such as mask data preparation 132 in Figure 1 or mask data preparation process 700 in Figure 7. Examples of layout patterns that can be generated according to method 900 include the layout patterns described with respect to the examples in Figures 5A-5B and Figures 8A-8C. In Figure 9, method 900 includes blocks 910-950.

[0061] In block 910, an initial layout plan is obtained (e.g., layout plan 122 in FIG. 1 or a layout plan including the layout pattern in FIG. 4A). In some embodiments, the initial layout plan includes a first layout pattern (e.g., layout pattern 312 in FIG. 4A) included in a first metallized layout diagram and indicating a first conductive structure, and a second layout pattern (e.g., layout pattern 412 in FIG. 4A) included in a second metallized layout diagram and indicating a second conductive structure. In some embodiments, the initial layout plan further includes an initial via layout pattern (e.g., layout pattern 416 in FIG. 4A) included in an initial via layout diagram and indicating the electrical coupling of the first and second conductive structures.

[0062] In block 920, a first prediction pattern is derived based on a first layout pattern (e.g., prediction pattern 322 in FIG. 4B). In block 930, a second prediction pattern is derived based on a second layout pattern (e.g., prediction pattern 422 in FIG. 4B). In some embodiments, the first and second prediction patterns overlap each other and define an overlapping region (e.g., overlapping region 430 in FIG. 4C).

[0063] In block 940, a modified via layout pattern is formed based on the first and second predicted patterns (e.g., via layout pattern 512 in FIG. 5A or via layout pattern 514 in FIG. 5B, referring to via layout patterns 822, 842, and 862 in FIG. 8A through 8C). In some embodiments, the modified via layout pattern indicates a via structure of a semiconductor element that connects a first conductive structure below the via structure to a second conductive structure above the via structure. In some embodiments, the modified via layout pattern has a curved shape prior to the application of an optical proximity correction process. In some embodiments, the modified via layout pattern is located within an overlapping region defined by the first and second predicted patterns.

[0064] In some embodiments, referring to the example in FIG5A, the modified via layout pattern has an elliptical shape. In some embodiments, the modified via layout pattern is determined by adjusting the size, tilt, positioning, or a combination thereof to determine the basic elliptical profile as the elliptical profile of the modified via layout pattern, based on reducing the difference between the modified via layout pattern and overlapping areas.

[0065] In some embodiments, referring to the example in FIG5B, the modified via layout pattern has a free shape, corresponding to having an irregular profile, asymmetry, or both. In some embodiments, the modified via layout pattern is determined based on the free shape profile that determines the modified via layout pattern, based on reducing the difference between the free shape profile and the region profile of the overlapping area.

[0066] In some embodiments, method 900 further includes determining a set of dummy layout patterns (e.g., dummy patterns 521-525 in FIG. 5A or dummy patterns 541-547 in FIG. 5B) indicating a set of dummy via structures. In some embodiments, each of the set of dummy layout patterns has a corresponding freeform shape. In some embodiments, the set of dummy layout patterns is located within a reference distance from the modified via layout pattern. In some embodiments, the reference distance corresponds to the OPC range of an optical proximity correction (OPC) process.

[0067] In block 950, the via layout plan is saved to the memory element of the process element. In some embodiments, the via layout plan corresponds to replacing the initial via layout pattern in the initial via layout plan with a modified via layout pattern, as shown in the examples in Figures 4A to 5B.

[0068] Figure 10 is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0069] In some embodiments, the EDA system 1000 includes an automatic placement and routing (APR) system. The design layout methods described herein represent wiring arrangements according to one or more embodiments, which may be implemented, for example, using the EDA system 1000 according to some embodiments.

[0070] In some embodiments, the EDA system 1000 is a general-purpose computing element including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. The storage medium 1004, among others, is encoded with, i.e., stored, computer program code 1006, i.e., a set of executable instructions. The instructions 1006, executed by the hardware processor 1002, represent (at least partially) an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter referred to as the processes and / or methods).

[0071] Processor 1002 is electrically coupled to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014, enabling processor 1002 and computer-readable storage medium 1004 to be connected to external components via network 1014. Processor 1002 is used to execute computer program code 1006 encoded in computer-readable storage medium 1004 so that system 1000 can be used to perform part or all of the process and / or method. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable process unit.

[0072] In one or more embodiments, the computer-readable storage medium 1004 is an electronic system, magnetic system, optical system, electromagnetic system, infrared system, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 1004 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0073] In one or more embodiments, storage medium 1004 stores computer program code 1006, which enables system 1000 (where such execution representation (at least partially) EDA tools) to perform part or all of the process and / or method. In one or more embodiments, storage medium 1004 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 1004 stores a standard cell library 1007, which includes the standard cells disclosed herein. In one or more embodiments, storage medium 1004 stores one or more layout figures 1009 corresponding to one or more layouts disclosed herein.

[0074] EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1002.

[0075] EDA system 1000 also includes a network interface 1012 coupled to processor 1002. Network interface 1012 allows system 1000 to communicate with network 1014, to which one or more other computer systems are connected. Network interface 1012 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethereum, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 1000.

[0076] System 1000 receives information via I / O interface 1010. The information received via I / O interface 1010 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1002. The information is transmitted to processor 1002 via bus 1008. EDA system 1000 receives information related to the user interface (UI) via I / O interface 1010. This information is stored as user interface 1042 in computer-readable medium 1004.

[0077] In some embodiments, a portion or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, a portion or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, a portion or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, a portion or all of the process and / or method is implemented as a software application used by an EDA system 1000. In some embodiments, a layout diagram containing standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or another suitable layout generation tool.

[0078] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs like DVDs, magnetic disks like hard disks, and one or more semiconductor memories such as ROM, RAM, memory cards, etc.

[0079] In some aspects, a photomask for a semiconductor element based on a layout plan includes a substrate and a via mask pattern structure on the substrate. The via mask pattern structure corresponds to a via layout pattern included in the layout plan and indicates the via structure of the semiconductor element, which connects a first conductive structure under the via structure and a second conductive structure on the via structure. The via layout pattern has a curved shape before the application of optical proximity correction (OPC) processes.

[0080] In some aspects, a method for generating a via layout pattern of a semiconductor device prior to applying an Optical Proximity Correction (OPC) process includes obtaining an initial layout plan, which includes a first layout pattern included in a first metallization layout plan and indicating a first conductive structure, a second layout pattern included in a second metallization layout plan and indicating a second conductive structure, and an initial via layout pattern included in the initial via layout plan and indicating electrical coupling between the first and second conductive structures. The method includes deriving a first predicted pattern based on the first layout pattern, deriving a second predicted pattern based on the second layout pattern, and determining a modified via layout pattern based on the first and second predicted patterns. The modified via layout pattern indicates via structures of the semiconductor device, the via structures connecting the first conductive structure under the via structure and the second conductive structure on the via structure. The method further includes saving a via layout pattern corresponding to a layout plan in which the initial via layout pattern in the initial via layout plan is replaced with the modified via layout pattern to a memory element of the process device. The modified via layout pattern has a curved shape prior to applying the OPC process.

[0081] In some aspects, process elements for generating via layout patterns of semiconductor devices prior to applying optical proximity correction (OPC) processes include memory devices and processing circuitry coupled to the memory devices. The processing circuitry is configured to obtain an initial layout plan including a first layout pattern in a first metallized layout plan indicating a first conductive structure, a second layout pattern in a second metallized layout plan indicating a second conductive structure, and an initial via layout pattern in the initial via layout plan indicating electrical coupling between the first and second conductive structures. The processing circuitry is configured to derive a first predicted pattern based on the first layout pattern, derive a second predicted pattern based on the second layout pattern, and determine a modified via layout pattern based on the first and second predicted patterns. The modified via layout pattern indicates via structures of the semiconductor devices, the via structures connecting the first conductive structure under the via structure and the second conductive structure on the via structure. The processing circuitry is further configured to save a via layout pattern corresponding to a layout plan in which the modified via layout pattern replaces the initial via layout pattern in the initial via layout plan in the initial via layout plan into the memory device. The modified via layout pattern has a curved shape before the application of the OPC process.

[0082] The foregoing has outlined the features of several embodiments or examples to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0083] 100: IC Manufacturing System 120: Design Company 122: Layout Planning 130: Mask manufacturing end 132: Preparation of Masking Materials 132a, 710: Logical Operation (LOP) Phase 132b: Resolution Enhancement Technology (RET) Stage 132c: Masking Rule Checker (MRC) Phase 132d: Lithography Process Inspection (LPC) Stage 132e: Fractional Processing (FRAC) Stage 144: Mask Manufacturing 145: Mask 150: IC manufacturing companies 152: Manufacturing Tools 153: Semiconductor Wafers 160: IC components 200: Semiconductor components 210, 610: Substrate 212: Active Region 214: Gate Structure 222: Metal-to-Drain / Source (MD) Structure 312, 314, 316, 332, 334, 336, 342, 344, 346, 412, 812, 814, 832, 834, 852, 854: Layout patterns 322, 324, 326, 422, 532, 534, 536, 538: Predicted Patterns 416, 418, 512, 514, 521, 522, 523, 524, 525, 541, 542, 543, 544, 545, 546, 547, 822, 842, 862: Through-hole layout patterns 418: Modified through-hole layout pattern 430: Overlapping region 541-547: Dummy patterns and through-hole layout patterns 600A: First photomask example, photomask 600B: Second photomask example, photomask 610:Substrate 612, 614: Masking pattern structure 621, 622, 623, 624, 625, 631, 632, 633, 634, 635, 636: Virtual mask pattern structure 700: Masking Data Preparation Process 712: Layout Diagram 720: Through-hole reshaping / rotary stage, stage 722: Predicted patterns of adjacent metallization layers obtained during masking data preparation 730: Resolution Enhancement Technology / Optical Proximity Correction Stage 732: One or more other stages of the masking data preparation process 800A, 800B, 800C: Additional layout pattern examples 823-829, 843-847, 863-874: Dummy Patterns 900: Method Blocks 910, 920, 930, 940, and 950 1000: Electronic Design Automation System 1002: Processor 1004: Computer-readable media 1006: Execute instruction 1007: Standard Cell Library 1008: Busbar 1009: Layout Diagram 1010:I / O interface 1012: Network Interface 1014: Internet 1042: User Interface

Claims

1. A photomask for a semiconductor element based on the layout planning of the semiconductor element, comprising: substrate; The via masking pattern structure above the substrate corresponds to a via layout pattern included in the via layout diagram of the layout plan and indicates the via structure of the semiconductor element. The via structure connects a first conductive structure below the via structure and a second conductive structure above the via structure. The via layout pattern has a curved shape before the application of the optical proximity correction (OPC) process. The first conductive structure corresponds to a first predicted pattern that can be derived from a first layout pattern included in the first metallization layout diagram of the layout plan. The second conductive structure corresponds to a second predicted pattern that can be derived from a second layout pattern included in the second metallization layout diagram of the layout plan. The first predicted pattern and the second predicted pattern overlap each other and define an overlap region. The via layout pattern is located within the overlap region before the application of the optical proximity correction process.

2. The photomask as described in claim 1, wherein: The via layout pattern has an elliptical shape before the optical proximity correction process is applied.

3. The photomask as described in claim 1, wherein: The via layout pattern has a free shape before the optical proximity correction process is applied, and the free shape corresponds to having an irregular profile, asymmetry, or both.

4. The photomask as described in claim 1, further comprising: A set of dummy mask pattern structures above the substrate, the set of dummy mask pattern structures corresponding to a set of dummy layout patterns included in the via layout diagram of the layout plan, and each of the set of dummy layout patterns having a corresponding free shape.

5. A method for generating a via layout pattern for semiconductor devices prior to applying an optical proximity correction (OPC) process, comprising: The process involves obtaining an initial layout plan including: a first layout pattern included in a first metallization layout diagram and indicating a first conductive structure; a second layout pattern included in a second metallization layout diagram and indicating a second conductive structure; and an initial via layout pattern included in an initial via layout diagram and indicating the electrical coupling between the first and second conductive structures; deriving a first predicted pattern based on the first layout pattern; deriving a second predicted pattern based on the second layout pattern; determining a modified via layout pattern based on the first and second predicted patterns, the modified via layout pattern indicating a via structure of the semiconductor element, the via structure connecting a first conductive structure below the via structure and a second conductive structure above the via structure; and saving the via layout plan to a memory element of a process element, the via layout plan corresponding to replacing the initial via layout pattern in the initial via layout diagram with the modified via layout pattern, wherein the modified via layout pattern has a curved shape before applying the optical proximity correction process, wherein: the first and second predicted patterns overlap each other and define an overlap region, and the modified via layout pattern is located within the overlap region.

6. The method as described in request item 5, wherein: The determination of the modified via layout pattern includes determining the freeform profile of the modified via layout pattern based on reducing the difference between the freeform profile and the region profile of the overlapping area.

7. The method as described in request item 5, wherein: The modified through-hole layout pattern has an elliptical shape.

8. The method as described in request item 5, wherein: The modified through-hole layout pattern has a free shape, which corresponds to having an irregular profile, asymmetry, or both.

9. A process element for generating a via layout pattern of a semiconductor element prior to the application of an optical proximity correction (OPC) process, comprising: Memory components; The processing circuitry, coupled to the memory element, is configured to: obtain an initial layout plan including: a first layout pattern included in a first metallization layout diagram and indicating a first conductive structure; a second layout pattern included in a second metallization layout diagram and indicating a second conductive structure; and an initial via layout pattern included in an initial via layout diagram and indicating electrical coupling between the first conductive structure and the second conductive structure; derive a first predicted pattern based on the first layout pattern; derive a second predicted pattern based on the second layout pattern; determine a modified via layout pattern based on the first predicted pattern and the second predicted pattern, the modified via layout pattern indicating a via structure of the semiconductor element, the via structure connecting the first conductive structure below the via structure and the second conductive structure above the via structure; and save the via layout plan to the memory element, the via layout plan corresponding to replacing the initial via layout pattern in the initial via layout diagram with the modified via layout pattern, wherein the modified via layout pattern has a curved shape before the application of the optical proximity correction process, wherein: The first predicted pattern and the second predicted pattern overlap each other and define an overlapping region, and the modified via layout pattern is located within the overlapping region.

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