Arithmetic circuit and memory including the same

Abstract

An arithmetic circuit includes an arithmetic matrix including a plurality of arithmetic units each configured to receive one of a plurality of bits of an X input and one of a plurality of bits of a Y input and configured to perform an arithmetic operation on the received bits and an adder array configured to generate a result value by adding operation results of the arithmetic matrix. A first group, among the plurality of arithmetic units, outputs the results of an AND operation by performing the AND operation on its own input values. A second group, among the plurality of arithmetic units, outputs the results of different arithmetic operations by performing the different arithmetic operations in a high-precision operation mode and a low-precision operation mode.

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