Processing-in-memory system including scale-up architecture

Abstract

A processing-in-memory (PIM) system includes a plurality of PIM devices, and a PIM-centric system configured to control the plurality of PIM devices. The PIM-centric system includes an instruction decoder and sequencer configured to receive a macro instruction and generate and output a plurality of micro instructions based on the macro instruction, a multicast interconnect configured to output one or more sub-micro instruction sets based on the plurality of micro instructions, and a plurality of PIM controllers each coupled to the plurality of PIM devices via a plurality of channels, the plurality of PIM controllers configured to generate and output one or more PIM command sets based on the one or more sub-micro instruction sets.

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