Memory devices and methods for detecting the number of write cycles

Abstract

This invention discloses a memory device and a method for detecting the write count of the same memory. The memory device includes a non-volatile memory and a memory controller coupled thereto. The non-volatile memory includes multiple memory blocks. The memory controller detects the total number of writes to each memory block. When the total number of writes is greater than or equal to 1, the memory controller increments the block count or sets it to a maximum count. When the total number of writes is not greater than or equal to 1, the memory controller decrements the block count or sets it to a minimum count. When the latest block count is greater than or equal to a pre-designed value, the memory controller generates a warning signal and resets the total number of writes to zero.

Description

Technical Field

[0001] This invention relates to a technology for detecting the number of write operations, and more particularly to a memory device and a method for detecting the number of write operations thereon. Prior Technology

[0002] In today's world of advanced computer information products, Electrically Erasable Programmable Read Only Memory (EEPROM) is widely used in electronic products because it has the function of electrically writing and erasing data, and the data will not be lost after the power is turned off.

[0003] However, the number of write cycles per memory address is limited, typically around 1 million. If a write operation is performed once per second, the EEPROM will reach its write cycle limit and may become damaged within approximately two weeks. In recent years, user demand for remote, real-time control has increased, requiring frequent adjustments to voltage and current parameters via communication, such as in applications involving lithium battery charging control and water electrolysis, with adjustments occurring as frequently as every 1 to 2 seconds. Since current power supply products are designed to store setting data locally, frequent writes to the storage integrated circuit (IC) will affect its lifespan. Furthermore, unpredictable abnormal operating modes within the program may cause the EEPROM to prematurely exhaust its lifespan without early detection.

[0004] Therefore, the present invention addresses the aforementioned problems by proposing a memory device and a method for detecting the number of writes thereto, thereby resolving the issues arising from conventional methods. Summary of the Invention

[0005] This invention provides a memory device and a method for detecting the number of write cycles thereto, which reduces write failure rate and extends service life.

[0006] In one embodiment of the present invention, a write count detection method is provided, which is applied to a non-volatile memory, the non-volatile memory comprising multiple memory blocks, and the write count detection method includes the following steps: Set a block count value for each memory block, where the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value; A detection process is performed multiple times at a fixed frequency, and each detection process includes the following steps: Detect the total number of writes to each memory block; Determine if the total number of writes is greater than or equal to 1: If so, determine if the block count corresponding to the total number of writes is equal to the maximum count: If so, maintain the block count value corresponding to the total number of writes; and If not, increment the block count corresponding to the total number of writes; and If not, determine whether the block count value corresponding to the total number of writes is equal to the minimum count value: If so, maintain the block count value corresponding to the total number of writes; and If not, decrement the block count corresponding to the total number of writes; and Determine if the latest block count corresponding to the total number of writes is greater than or equal to a pre-designed value: If so, generate a warning signal and reset the total write count to zero; and If not, determine if a warning signal has been generated: If so, stop generating warning signals and reset the total write count to zero; and If not, reset the total number of writes to zero.

[0007] In one embodiment of the present invention, the minimum count value is 0 and the maximum count value is 255.

[0008] In one embodiment of the present invention, a write latency is increased when an alert signal is generated.

[0009] In one embodiment of the present invention, write latency is reduced when the warning signal is stopped from being generated.

[0010] In one embodiment of the present invention, the non-volatile memory is an electronically erasable rewritable read-only memory (EEPROM).

[0011] In one embodiment of the present invention, a memory device includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of memory blocks, and the memory controller is coupled to the non-volatile memory and is used to set a block count value corresponding to each memory block. The block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value. The memory controller is used to detect the total number of writes to each memory block. When the total number of writes is greater than or equal to 1, the memory controller increments the block count value corresponding to the total number of writes or sets it to the maximum count value. When the total number of writes is not greater than or equal to 1, the memory controller decrements the block count value corresponding to the total number of writes or sets it to the minimum count value. When the latest block count value corresponding to the total number of writes is greater than or equal to a preset value, the memory controller generates a warning signal and resets the total number of writes to zero.

[0012] In one embodiment of the present invention, the memory controller includes a plurality of block counters, a plurality of write counters, a row decoder, a column decoder, and a processor. The block counters are used to count the block count value of a corresponding memory block, and the write counters are used to count the total number of writes to a corresponding memory block. The row decoder and column decoder are coupled to the memory blocks. The processor is coupled to the block counters, write counters, row decoder, and column decoder, and is used to set and detect the block count value and the total number of writes, drive the row decoder and column decoder to perform write operations on the memory blocks, and generate warning signals.

[0013] In one embodiment of the present invention, the minimum count value is 0 and the maximum count value is 255.

[0014] In one embodiment of the present invention, when an alarm signal is generated, the memory controller increases the write latency.

[0015] In one embodiment of the present invention, the non-volatile memory is an electronically erasable rewritable read-only memory (EEPROM).

[0016] Based on the above, the memory device and its write count detection method set a block count value for each memory block and adjust the block count value according to the total number of writes to the memory block. When the block count value is greater than the preset value, an alarm signal is generated to reduce write failure rate and extend service life.

[0017] To enable your review committee to gain a better understanding of the structural features and effects achieved by the present invention, preferred embodiment diagrams and detailed descriptions are provided below: Simple Explanation of the Diagram

[0018] Figure 1 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention. Figure 2 is a schematic diagram of a non-volatile memory according to another embodiment of the present invention. Figure 3 is a schematic diagram of a memory device according to an embodiment of the present invention. Figure 4a is a flowchart of a write count detection method according to an embodiment of the present invention. Figure 4b is a flowchart of a detection process according to an embodiment of the present invention. Figure 5 is a schematic diagram of the total number of writes, block count value and stored value corresponding to each memory block according to an embodiment of the present invention. Figure 6 is a schematic diagram of the total number of writes, block count value and stored value corresponding to each memory block according to another embodiment of the present invention. Figure 7 is a schematic diagram of the total number of writes, block count value and stored value corresponding to each memory block according to another embodiment of the present invention. Implementation

[0019] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings and description represent the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0020] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0021] In the following description of "one embodiment" or "an embodiment," the term refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0022] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a master element coupled to a slave element, it means that the master element can be directly connected to the slave element via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the slave element via other elements or connection means.

[0023] The disclosure is specifically described with reference to the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “the” include “a or at least one” of the element or component. Furthermore, as used in this disclosure, the singular article also includes descriptions of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “on which”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this disclosure and in specific contexts. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are merely illustrative and do not limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0024] Figure 1 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention. Referring to Figure 1, the non-volatile memory 10 includes multiple blocks, such as a first block B1, a second block B2, a third block B3, and a fourth block B4. A common method to extend the lifespan of the non-volatile memory 10 is through wear leveling backup technology, distributing data across different blocks to avoid repeated writing to the same block, thereby balancing the wear of the memory cells and extending their lifespan. Figure 2 is a schematic diagram of a non-volatile memory according to another embodiment of the present invention. When considering the capacity of the non-volatile memory, it can also be divided into two areas, as shown in Figure 2, namely, a backup mechanism of primary area M and backup area B. Upon power-on, if the data in primary area M is found to be incorrect, the data in primary area M is updated using the data in backup area B. If the data in primary area M is found to be correct but inconsistent with the data in backup area B, the data in backup area B is updated using the data in primary area M to ensure data integrity.

[0025] Based on the above backup mechanism, the present invention will now propose a memory device and a write count detection method thereof, which adjusts the block count value and generates an alarm signal when the block count value is greater than a pre-designed value, i.e., when a write error occurs, in order to reduce the write failure rate and increase write latency to extend the service life.

[0026] Figure 3 is a schematic diagram of a memory device according to an embodiment of the present invention. Referring to Figure 3, the memory device 1 includes a non-volatile memory 10 and a memory controller 11, with the non-volatile memory 10 coupled to the memory controller 11. The non-volatile memory 10 may be, but is not limited to, an electronically erasable rewritable read-only memory (EEPROM). The non-volatile memory 10 includes a plurality of memory blocks MB1 and MB2. The memory controller 11 sets a block count value corresponding to each memory block MB1 and MB2, wherein the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value. For example, the minimum count value is 0, and the maximum count value is 255. The memory controller 11 detects the total number of writes to each memory block MB1 and MB2. When the total number of writes is greater than or equal to 1, the memory controller 11 increments the block count value corresponding to the total number of writes or sets it to the maximum count value. When the total number of writes is not greater than or equal to 1, the memory controller 11 decrements the block count value corresponding to the total number of writes, or sets it to the minimum count value. When the latest block count value corresponding to the total number of writes is greater than or equal to a pre-designed value, the memory controller 11 generates a warning signal W and resets the total number of writes to zero to reduce write failure rate. In some embodiments of the present invention, when the warning signal W is generated, the memory controller 11 increases the write latency to reduce the total number of writes within a fixed time period, thereby extending the lifespan of the memory device 1. Write latency refers to the time difference between data preparation and actual data writing.

[0027] In some embodiments of the present invention, the memory controller 11 may include multiple block counters BC1 and BC2, multiple write counters WC1 and WC2, a row decoder 110, a column decoder 111, and a processor 112. Block counters BC1 and BC2 count the block count values ​​of corresponding memory blocks MB1 and MB2, respectively, and write counters WC1 and WC2 count the total number of writes to corresponding memory blocks MB1 and MB2, respectively. The row decoder 110 and column decoder 111 are coupled to memory blocks MB1 and MB2. The processor 112 is coupled to the block counters BC1 and BC2, the write counters WC1 and WC2, the row decoder 110, and the column decoder 111. The processor 112 receives a write instruction K, and accordingly sets and detects the block count value and the total number of writes, and drives the row decoder 110 and column decoder 111 to perform write operations on memory blocks MB1 and MB2, and generates an alert signal W. The write instruction K may be a background write instruction or a user write instruction.

[0028] Figure 4a is a flowchart of a write count detection method according to an embodiment of the present invention. Referring to Figures 3 and 4a, the write count detection method is applied to a non-volatile memory 10, which includes multiple memory blocks MB1 and MB2. In the write count detection method, firstly, as shown in step S10, the processor 112 controls block counters BC1 and BC2 to set a block count value corresponding to each memory block MB1 and MB2. Next, as shown in step S12, the processor 112 performs multiple detection cycles at a fixed frequency, for example, once every five seconds.

[0029] Figure 4b is a flowchart of the detection process according to an embodiment of the present invention. Referring to Figures 3 and 4b, firstly, as shown in step S14, the processor 112 detects the total number of writes for each memory block MB1 and MB2. Next, as shown in step S16, the processor 112 determines whether the total number of writes is greater than or equal to 1. If yes, proceed to step S18; otherwise, proceed to step S20. In step S18, the processor 112 determines whether the block count value corresponding to the total number of writes is equal to the maximum count value. If yes, proceed to step S22; otherwise, proceed to step S24. In step S20, the processor 112 determines whether the block count value corresponding to the total number of writes is equal to the minimum count value. If yes, proceed to step S26; otherwise, proceed to step S28. In step S22, the processor 112 maintains the block count value corresponding to the total number of writes. In step S24, the processor 112 increments the block count value corresponding to the total number of writes, for example, by 1 each time. In step S26, processor 112 maintains the block count value corresponding to the total number of writes. In step S24, processor 112 decrements the block count value corresponding to the total number of writes, for example, by 1 each time. After steps S22, S24, S26, or S28, step S30 is performed. In step S30, processor 112 determines whether the latest block count value corresponding to the total number of writes is greater than or equal to a preset value, for example, a preset count value of 4. If yes, proceed to step S32; otherwise, proceed to step S34. In step S32, processor 112 generates a warning signal W and resets the total number of writes to zero. In step S34, processor 112 determines whether a warning signal W has been generated. If yes, processor 112 stops generating the warning signal W and resets the total number of writes to zero, as shown in step S36; otherwise, processor 112 resets the total number of writes to zero, as shown in step S38. If substantially the same result can be obtained, these steps do not necessarily need to be performed in the execution order shown in Figure 4b. When the warning signal W is generated, the processor 112 can further increase the write latency. When the warning signal W stops being generated, the processor 112 can further reduce the write latency. In addition, in steps S16, S18, S20, S22, S24, S26, S28, S30, S32, S36 and S38, the processor 112 determines or controls the total number of writes or the block count value corresponding to the same memory block MB1 or MB2.

[0030] Figure 5 is a schematic diagram of the total number of writes, block count, and stored value corresponding to each memory block according to an embodiment of the present invention. Referring to Figure 5, in this embodiment, it is assumed that there are 16 memory blocks arranged in a 4×4 array. C1 represents the total number of writes for each memory block, C2 represents the block count for each memory block, and S represents the stored value for each memory block. The non-volatile memory 10 contains the stored value S for each memory block, and the memory controller 11 contains the total number of writes C1 and the block count C2 for each memory block. The total number of writes C1, the block count C2, and the stored value S corresponding to each memory block change sequentially from top to bottom, and a detection process is performed every 5 seconds, with a preset count value of 4. Initially, the total number of writes C1, the block count C2, and the stored value S corresponding to each memory block in the initial state of the detection process are located at the top of Figure 5. Next, a write request is initiated to write 0x64 to the memory block in row 2, column 4. Therefore, 0xDD is immediately written as 0x64, and the corresponding total write count is incremented from 0 to 1. Then, another write request is initiated to write 0x87 to the memory block in row 2, column 4. Therefore, 0x64 is immediately written as 0x87, and the corresponding total write count is incremented from 1 to 2. Then, another write request is initiated to write 0xF2 to the memory block in row 2, column 4. Therefore, 0x87 is immediately written as 0xF2, and the corresponding total write count is incremented from 2 to 3. Finally, at the 5th second, because the block count value in row 2, column 4 is not equal to the maximum count value, the block count value in row 2, column 4 is incremented from 0 to 1, and the total write count is reset from 3 to 0.

[0031] Figure 6 is a schematic diagram of the total number of writes, block count, and stored value corresponding to each memory block according to another embodiment of the present invention. Referring to Figure 6, in this embodiment, it is assumed that there are 16 memory blocks arranged in a 4×4 array. C1 represents the total number of writes for each memory block, C2 represents the block count for each memory block, and S represents the stored value for each memory block. The non-volatile memory 10 contains the stored value S for each memory block, and the memory controller 11 contains the total number of writes C1 and the block count C2 for each memory block. The total number of writes C1, the block count C2, and the stored value S corresponding to each memory block change sequentially from top to bottom, and a detection process is performed every 5 seconds, with a preset count value of 4. First, in the initial state of the detection process, the total number of writes C1, the block count C2, and the stored value S corresponding to each memory block are located at the top of Figure 6. Next, a write request is initiated to write 0x64 to the memory block in row 2, column 4. Therefore, 0xF2 is immediately written as 0x64, and the corresponding total write count is incremented from 0 to 1. Finally, at the 5th second, because the block count value in row 2, column 4 is not equal to the maximum count value, the block count value in row 2, column 4 is incremented from 3 to 4, and the total write count is reset from 1 to 0. At the same time, the memory controller 11 generates an alarm signal.

[0032] Figure 7 is a schematic diagram of the total number of writes, block count, and stored value corresponding to each memory block according to another embodiment of the present invention. Referring to Figure 7, in this embodiment, it is assumed that there are 16 memory blocks arranged in a 4×4 array. C1 represents the total number of writes for each memory block, C2 represents the block count for each memory block, and S represents the stored value for each memory block. The non-volatile memory 10 contains the stored value S for each memory block, and the memory controller 11 contains the total number of writes C1 and the block count C2 for each memory block. The total number of writes C1, the block count C2, and the stored value S corresponding to each memory block change sequentially from top to bottom, and a detection process is performed every 5 seconds, with a preset count value of 4. First, in the initial state of the detection process, the total number of writes C1, the block count C2, and the stored value S corresponding to each memory block are located at the top of Figure 7, where the total number of writes corresponding to the memory block in the 2nd row and 4th column is 1, and the block count is 4. Because the block count is equal to the pre-designed value, write latency is increased. If 0x87 is to be written to the memory block in row 2, column 4, it cannot be written immediately. Then, if no other write requests are initiated within i seconds, the write request for 0x87 is executed after i seconds, as shown in the lower part of Figure 7. If i is greater than or equal to 5, the total write count C1 in the lower right figure will be cleared to 0, and the block count C2 of the memory block in row 2, column 4 will increase to 5. Conversely, if other write requests are initiated within i seconds, the latency count will be reset. Therefore, if a write request is initiated every i seconds, the actual write will be delayed indefinitely, thus protecting non-volatile memory. Since the i-second timing and the timing of the detection process at a fixed frequency are independent, this situation will also cause the total write count C1 and the block count C2 to continuously increase.

[0033] According to the above embodiments, the memory device and its write count detection method adjust the block count value and generate a warning signal when the block count value is greater than a preset value, so as to reduce the write failure rate and extend the service life.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications made to the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

[0035] 1: Memory device 10: Non-volatile memory 11: Memory controller 110: Line Decoder 111: Column Decoder 112: Processor B1: First Block B2: Second Block B3: Third Block B4: Fourth Block M: Main Region B: Backup Area MB1, MB2: Memory Blocks BC1, BC2: Block counters WC1, WC2: Write counter K: Write command W: Warning signal C1: Total number of writes C2: Block count value S: Stored value S10, S12, S14, S16, S18, S20, S24, S26, S28, S30, S32, S34, S36, S38: Steps

Claims

1. A write count detection method applied to a non-volatile memory, the non-volatile memory comprising a plurality of memory blocks, the write count detection method comprising the following steps: setting a block count value corresponding to each of the memory blocks, wherein the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value; performing multiple detection processes at a fixed frequency, each detection process comprising the following steps: detecting the total number of writes to each memory block; determining whether the total number of writes is greater than or equal to 1: if yes, determining whether the block count value corresponding to the total number of writes is equal to the maximum count value: if yes, maintaining the block count value corresponding to the total number of writes; and if no, incrementing the block count value corresponding to the total number of writes; and if no, determining whether the block count value corresponding to the total number of writes is equal to the minimum count value: If yes, maintain the block count value corresponding to the total number of writes; and if no, decrement the block count value corresponding to the total number of writes; and determine whether the latest block count value corresponding to the total number of writes is greater than or equal to a pre-designed value: if yes, generate a warning signal and reset the total number of writes to zero; and if no, determine whether the warning signal has been generated: if yes, stop generating the warning signal and reset the total number of writes to zero; and if no, reset the total number of writes to zero.

2. The write count detection method as described in request item 1, wherein the minimum count value is 0 and the maximum count value is 255.

3. The write count detection method as described in request item 1, wherein when the warning signal is generated, the write latency is increased.

4. The write count detection method as described in request item 3, wherein the write delay is reduced when the warning signal is stopped being generated.

5. The write count detection method as described in claim 1, wherein the non-volatile memory is an electronically erasable rewritable read-only memory (EEPROM).

6. A memory device comprising: a non-volatile memory including a plurality of memory blocks; and a memory controller coupled to the non-volatile memory and configured to set a block count value corresponding to each of the memory blocks, wherein the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value, the memory controller being configured to detect the total number of writes to each of the memory blocks; when the total number of writes is greater than or equal to 1, the memory controller increments the block count value corresponding to the total number of writes or sets it to the maximum count value; when the total number of writes is not greater than or equal to 1, the memory controller decrements the block count value corresponding to the total number of writes or sets it to the minimum count value; and when the latest block count value corresponding to the total number of writes is greater than or equal to a preset value, the memory controller generates a warning signal and resets the total number of writes to zero.

7. The memory device as claimed in claim 6, wherein the memory controller comprises: a plurality of block counters for counting the block count value corresponding to the plurality of memory blocks respectively; a plurality of write counters for counting the total number of writes corresponding to the plurality of memory blocks respectively; a row decoder and a column decoder coupled to the plurality of memory blocks; and a processor coupled to the plurality of block counters, the plurality of write counters, the row decoder and the column decoder, and configured to set and detect the block count value and the total number of writes, drive the row decoder and the column decoder to perform write operations on the memory blocks, and generate the warning signal.

8. The memory device as described in claim 6, wherein the minimum count value is 0 and the maximum count value is 255.

9. The memory device as described in claim 6, wherein when the warning signal is generated, the memory controller increases write latency.

10. The memory device as claimed in claim 6, wherein the non-volatile memory is an electronically erasable rewritable read-only memory (EEPROM).

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