Universal serial bus device and operation method thereof

Abstract

An USB device and an operation method thereof are provided. USB controllers take turns to reset an USB physical layer circuit during an initial setting period to obtain corresponding device controller initial addresses and descriptors. A USB determining processor queues a ready flag of a USB controller indicating that data corresponding to a host request of a host is ready into a ready flag queue waiting list. The USB determining processor transmits data of a corresponding USB controller to the host according to the ready flag queue waiting list.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a universal serial bus device and its operating method. Prior Technology

[0002] Currently, the most commonly used connection interface in computer peripherals is the USB interface, which continues to be used in everything from small mobile devices to large workstations. When a chip (IC) must use multiple one-to-one universal bus controllers and universal bus physical layer circuits, it will significantly increase the chip area and make it prone to mutual interference between physical layer circuits. At the same time, the difficulty of application circuit design will also increase. Summary of the Invention

[0003] This invention provides a universal sequential bus device and its operation method, which can reduce the wafer area and avoid mutual interference between physical layer circuits.

[0004] The Universal Sequence Bus (USB) device of the present invention includes a plurality of USB controllers, a USB decision processor, and a single USB physical layer circuit. The USB decision processor is coupled to the plurality of USB controllers. The USB physical layer circuit is coupled to the USB decision processor. During initial setup, the plurality of USB controllers sequentially reset the USB physical layer circuit to obtain the corresponding device controller initial address and descriptor. The USB decision processor adds the ready flag of the USB controller indicating that it is ready to receive data requested by a host to a ready flag queue. The USB decision processor transmits the data of the corresponding USB controller to the host according to the ready flag queue. Specifically, when the ready flag of the USB controller polled by the host is at the first position in the ready flag queue, the USB decision processor transmits the data of the corresponding USB controller to the host.

[0005] In one embodiment of the present invention, during the initial setup period, when one of the plurality of general sequence bus controllers resets the general sequence bus physical layer circuitry to obtain the corresponding device controller initial address and descriptor, the general sequence bus controller that has obtained the device controller initial address does not respond to the host and remains in the previous state.

[0006] In one embodiment of the invention, the previous state includes a state that does not change the acquired initial address of the device controller or a state that waits to reset the general sequence bus physical layer circuit.

[0007] In one embodiment of the present invention, the aforementioned preparation markers are arranged in a first-in-first-out (FIFO) manner in the preparation marker waiting list.

[0008] In one embodiment of the present invention, when the ready flag corresponding to the Universal Sequence Bus controller polled by the host is not in the first position of the ready flag waiting list, the Universal Sequence Bus Decision Processor transmits a negative acknowledgment signal to the host through the Universal Sequence Bus Entity Layer Circuit.

[0009] In one embodiment of the present invention, the aforementioned plurality of general sequence bus controllers use the same speed level.

[0010] In one embodiment of the present invention, the host does not clear the stored initial address of the device controller.

[0011] This invention also provides an operation method for a Universal Sequence Bus (USB) device. The USB device includes multiple USB controllers, a USB decision processor, and a single USB physical layer circuit. The USB decision processor is coupled to the multiple USB controllers and the USB physical layer circuit. The operation method of the USB device includes the following steps: Controlling the multiple USB controllers to sequentially reset the USB physical layer circuit during an initial setup period to obtain the corresponding device controller initial address and descriptor. Controlling the USB decision processor to add the readiness flag of the USB controller indicating that it is ready to receive data requested by a host to a readiness flag queue. Controlling the USB decision processor to transmit the data of the corresponding USB controller to the host according to the readiness flag queue, wherein when the readiness flag of the USB controller polled by the host is at the first position in the readiness flag queue, the USB decision processor transmits the data of the corresponding USB controller to the host.

[0012] In one embodiment of the present invention, the aforementioned preparation markers are arranged in a first-in-first-out (FIFO) manner in the preparation marker waiting list.

[0013] In one embodiment of the present invention, when the ready flag corresponding to the Universal Sequence Bus controller polled by the host is not in the first position of the ready flag waiting list, the Universal Sequence Bus Decision Processor is controlled to transmit a negative acknowledgment signal to the host through the Universal Sequence Bus physical layer circuit.

[0014] In one embodiment of the present invention, the aforementioned plurality of general sequence bus controllers use the same speed level.

[0015] Based on the above, in this embodiment of the invention, multiple Universal Sequence Bus (USB) controllers take turns resetting the USB physical layer circuit during the initial setup period to obtain the corresponding device controller initial address and descriptor. The USB determination processor adds the preparation flag of the USB controller indicating that it is ready to receive data requested by the host to the preparation flag queue waiting list. The USB determination processor transmits the data of the corresponding USB controller to the host through the USB physical layer circuit according to the preparation flag queue waiting list. When the preparation flag of the USB controller polled by the host is at the first position in the preparation flag queue waiting list, the USB determination processor transmits the data of the corresponding USB controller to the host. By using an architecture in which multiple USB controllers share a single USB physical layer circuit, the chip area can be significantly reduced and mutual interference between physical layer circuits can be avoided.

[0016] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0017] Figures 1 to 4 are schematic diagrams of a general sequence bus device according to an embodiment of the present invention. Figure 5 is a flowchart of the operation method of a general sequence bus device according to an embodiment of the present invention. Implementation

[0018] Figure 1 is a schematic diagram of a universal sequence bus device according to an embodiment of the present invention. As shown in Figure 1, the universal sequence bus device 100 includes universal sequence bus controllers 102-1 to 102-4, a universal sequence bus decision processor 104, and a universal sequence bus physical layer circuit 106. The universal sequence bus decision processor 104 is coupled to the universal sequence bus controllers 102-1 to 102-4 and the universal sequence bus physical layer circuit 106, wherein the universal sequence bus controllers 102-1 to 102-4 use the same speed class. It is worth noting that the number of universal sequence bus controllers is not limited to this embodiment. In other embodiments, the universal sequence bus device 100 may also include more or fewer universal sequence bus controllers.

[0019] Universal Sequence Bus (USB) controllers 102-1 to 102-4 can communicate with the host 108 via USB decision processor 104 and USB physical layer circuitry 106. Furthermore, when USB device 100 establishes a connection with the host 108, USB device 100 enters an initial setup period and communicates with the host 108 via Endpoint 0 to obtain the device controller initial address and descriptor. Specifically, USB controllers 102-1 to 102-4 can sequentially reset USB physical layer circuitry 106 during the initial setup period to obtain their respective device controller initial addresses and descriptors. Moreover, when a USB controller transmits a reset request, the host 108 does not clear the device controller initial address previously stored in the firmware, but instead stores the device controller initial address of the currently polled USB controller (e.g., USB controllers 102-1 to 102-4) in the firmware.

[0020] The Universal Sequence Bus (USB) decision processor 104 may include an uplink connection port and a downlink connection port. The USB Decision Processor 104 can control the connection status between the USB controllers 102-1 to 102-4 and the USB physical layer circuitry 106. For example, during initial setup, when one of the USB controllers 102-1 to 102-4 resets the USB physical layer circuitry 106 to obtain the corresponding device controller initial address and descriptor, the remaining USB controllers 102-1 to 102-4 do not communicate with the host 108. For example, as shown in Figure 2, during the initial setup period, when it is the turn of the Universal Sequence Bus Controller 102-2 to reset the Universal Sequence Bus Physical Layer Circuit 106, the uplink port UP can connect the sequence bus controller 102-2 to the Universal Sequence Bus Physical Layer Circuit 106 and disconnect the other Universal Sequence Bus Controllers 102-1, 102-3, and 102-4 from the Universal Sequence Bus Physical Layer Circuit 106. In other words, during the initial setup period, only one Universal Sequence Bus Controller can communicate with the host 108 at a time through the uplink port UP and the Universal Sequence Bus Physical Layer Circuit 106.

[0021] The sequence bus controller 102-2 can reset the general sequence bus physical layer circuit 106 via the uplink port UP and obtain the corresponding device controller initial address and descriptor. Meanwhile, general sequence bus controllers 102-1, 102-3, and 102-4 do not respond to the host 108 and remain in their previous states. Maintaining the previous state can, for example, mean keeping the already obtained device controller initial address unchanged or waiting to reset the general sequence bus physical layer circuit 106. For instance, in the embodiment of Figure 2, assuming that general sequence bus controller 102-1 has obtained the corresponding device controller initial address and descriptor, while general sequence bus controllers 102-3 and 102-4 have not yet obtained the corresponding device controller initial address and descriptor, when sequence bus controller 102-2 resets the general sequence bus physical layer circuit 106 via the uplink port UP to obtain the corresponding device controller initial address and descriptor, general sequence bus controller 102-1 does not respond to the host 108 and keeps its already obtained device controller initial address and descriptor unchanged. In addition, the general sequence bus controllers 102-3 and 102-4 do not respond to the host 108 and remain in a waiting state so that after the sequence bus controller 102-2 completes the handshake, they will reset the general sequence bus physical layer circuit 106 in the same way to obtain the corresponding device controller initial address and descriptor.

[0022] After the Universal Sequence Bus (USB) controllers 102-1 to 102-4 complete the initial address and descriptor settings for the device controllers, the USB device 100 can exit the initialization phase and enter normal operation mode to begin general communication with the host 108, such as data transmission. For example, as shown in Figure 3, the host 108 can transmit data packets to the USB controllers 102-1 to 102-4 via the downlink port DP. The USB controllers 102-1 to 102-4 can check the address of the data packet. If the address of the data packet matches the initial address of the device controller, they will receive the data packet and send an acknowledgment signal (ACK) through the USB judgment processor 104 to reply to the host 108 that the data packet has been received. Otherwise, they will ignore the data packet and not respond. This avoids interference to USB controllers that are not the destination of data packet transmissions.

[0023] Furthermore, when host 108 transmits a host request to the Universal Sequence Bus Controller (USBC), the USBC responds to the host request in the manner shown in Figure 4. Taking host 108 transmitting a host request to USBC controller 102-2 as an example, USBC controller 102-2 can respond to the host request by providing a preparation flag RDY2 to USBC decision processor 104 after preparing the corresponding data. USBC decision processor 104 can then place the preparation flag RDY2 provided by USBC controller 102-2 into preparation flag queue waiting list 402, for example, by placing the preparation flag RDY2 into preparation flag queue waiting list 402 in a first-in-first-out manner.

[0024] For example, in the embodiment of Figure 4, the Universal Sequence Bus (USB) controllers that prepare the data corresponding to the host request from host 108 are USB controllers 102-2, 102-4, and 102-1 in sequence. USB decision processor 104, following a first-in-first-out (FIFO) approach, sequentially arranges the preparation flags RDY2, RDY4, and RDY1 provided by USB controllers 102-2, 102-4, and 102-1 after they have prepared the data to respond to the host request in the preparation flag queue waiting list 402. USB decision processor 104 can then transmit the data from the USB controllers to host 108 via USB physical layer circuitry 106 according to the preparation flag queue waiting list 402. Furthermore, the host 108 can read the data of the general sequence bus controller in a polling manner. The general sequence bus judgment processor 104 can decide to send a negative acknowledgment signal (NAK), data, or acknowledgment signal (ACK) to the host 108 based on whether the ready flag corresponding to the general sequence bus controller polled by the host 108 is located at the first position in the ready flag queue wait list 402.

[0025] For example, in Figure 4, when host 108 polls the Universal Sequence Bus (USB) controller 102-4, since the first position in the ready flag queue wait list 402 corresponds to the ready flag RDY2 of USB controller 102-2, USB decision processor 104 can send a negative acknowledgment (NAK) signal to host 108 via USB physical layer circuit 106 to respond to the host request. When host 108 polls the USB controller 102-2, USB decision processor 104 can send an acknowledgment (ACK) signal to host 108 via USB physical layer circuit 106, or read the data of the corresponding USB controller 102-2 and send it to host 108. Similarly, after the host 108 finishes reading the data from the Universal Sequence Bus controller 102-2, the ready flag RDY4 in the ready flag queue wait list 402 becomes the first position. Thus, only when the host 108 polls the Universal Sequence Bus controller 102-4 will the Universal Sequence Bus Decision Processor 104 send an acknowledgment signal (ACK) to the host 108 through the Universal Sequence Bus Entity Layer Circuit 106, or read the data of the corresponding Universal Sequence Bus controller 102-4 and send it to the host 108.

[0026] As shown in the above embodiments, the Universal Sequence Bus (USB) device 100 can still perform communication processing for multiple USB controllers in an orderly manner even using only one USB physical layer circuit 106. This achieves benefits such as reducing chip area, avoiding interference between USB physical layer circuits, avoiding eye diagram window shrinkage, performance degradation, and power consumption reduction. Furthermore, since the USB decision processor 104 functions like a virtual hub, the need for a dedicated hub can be eliminated. Additionally, using only one USB physical layer circuit 106 significantly reduces the number of pins and pads, lowering layout complexity and facilitating Automatic Placement & Routing (APR) and layout, thereby reducing design costs and error rates. Moreover, the Field Programmable Gate Array (FPGA) requires only one USB physical layer circuit daughterboard, facilitating verification, increasing the utilization of the Evaluation Board (EVB), and reducing the design difficulty for users.

[0027] Figure 5 is a flowchart of an operation method of a universal sequence bus device according to an embodiment of the present invention. The universal sequence bus device includes multiple universal sequence bus controllers, a universal sequence bus determination processor, and a universal sequence bus physical layer circuit. The universal sequence bus determination processor is coupled to each universal sequence bus controller and the universal sequence bus physical layer circuit. Each universal sequence bus controller uses the same speed level. As can be seen from the above embodiment, the operation method of the universal sequence bus device may include at least the following steps. First, the multiple universal sequence bus controllers are controlled to reset the universal sequence bus physical layer circuit in turn during the initial setting period to obtain the corresponding device controller initial address and descriptor (step S502). When one of the multiple universal sequence bus controllers is controlled to reset the universal sequence bus physical layer circuit to obtain the corresponding device controller initial address and descriptor, the remaining universal sequence bus controllers may be controlled not to respond to the host and remain in the previous state. The previous state may include, for example, a state that does not change the obtained device controller initial address or a state that waits to reset the universal sequence bus physical layer circuit. Furthermore, when a Universal Sequence Bus (USB) controller transmits a reset request, the host does not clear the corresponding device controller initial address previously stored in the firmware via the bus physical layer circuitry, but instead stores the device controller initial addresses of each USB controller in the firmware. Next, the USB controller determining the processor adds the readiness flag of the USB controller that indicates it is ready to receive data corresponding to a host request to a host into the readiness flag queue waiting list (step S504), where the readiness flags can be arranged, for example, in a first-in-first-out (FIFO) manner in the readiness flag queue waiting list. Then, the USB physical layer circuitry transmits the data of the USB controller corresponding to the readiness flag to the host according to the readiness flag queue waiting list (step S506). When the ready flag indicator bit corresponding to the GMAV controller polled by the host is at the first position in the ready flag queue waiting list, the GMAV decision processor is controlled to send an acknowledgment signal to the host through the GMAV physical layer circuitry, or read the data of the polled GMAV controller and send it to the host. When the ready flag indicator bit corresponding to the GMAV controller polled by the host is not at the first position in the ready flag queue waiting list, the GMAV decision processor is controlled to send a negative acknowledgment signal to the host through the GMAV physical layer circuitry to respond to the host request.

[0028] In summary, during the initial setup period, multiple Universal Sequence Bus (USB) controllers in this embodiment of the invention sequentially reset the USB physical layer circuitry to obtain the corresponding device controller initial address and descriptor. The USB determination processor adds the readiness flag of the USB controller that indicates it is ready to receive data requested by the host to the readiness flag queue. The USB determination processor then transmits the data of the corresponding USB controller to the host through the USB physical layer circuitry based on the readiness flag queue. Specifically, when the readiness flag of the USB controller polled by the host is at the first position in the readiness flag queue, the USB determination processor transmits the data of the corresponding USB controller to the host. By using an architecture where multiple general-purpose bus controllers share a single general-purpose bus physical layer circuit, the following advantages can be achieved: significantly reduced chip area; avoidance of mutual interference between physical layer circuits; avoidance of eye diagram window reduction; elimination of hub setup; reduction of pin and pad setup; reduced layout complexity; field-programmable gate arrays require only a single daughterboard of general-purpose bus physical layer circuitry; and ease of verification and improved evaluation board utilization, while reducing the design difficulty for users.

[0029] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0030] 100: Universal Sequential Bus Device 102-1~102-4: General Sequence Bus Controller 104: General Sequence Bus Decision Processor 106: General Sequence Bus Physical Layer Circuit 108: Host UP: Uplink port DP: Downlink Port RDY1, RDY2, RDY4: Prepare for marking 402: Preparing to mark the waiting list S502~S506: Procedures for Operating General Sequence Bus Devices

Claims

1. A universal sequence bus device, comprising: Multiple generic sequence bus controllers; a generic sequence bus decision processor coupled to the generic sequence bus controllers; A Universal Sequence Bus (USB) physical layer circuitry coupled to the USB decision processor, wherein the USB controllers, during an initial setup period, periodically reset the USB physical layer circuitry to obtain the corresponding device controller initial address and descriptor; the USB decision processor increments a readiness flag of a USB controller that is ready to receive data requested by a host from a host into a readiness flag queue wait list; the USB decision processor transmits the corresponding USB controller's data to the host based on the readiness flag queue wait list, wherein when the host polls the USB... When the ready flag corresponding to the bus controller is first in the ready flag waiting list, the Universal Sequence Bus (USB) determines that the processor transmits the data of the corresponding USB controller to the host. During the initial setup period, when one of the USB controllers resets the USB physical layer circuitry to obtain the corresponding device controller initial address and descriptor, the USB controller that has obtained the device controller initial address does not respond to the host and remains in a previous state. The previous state includes either not changing the state of having obtained the device controller initial address or waiting to reset the USB physical layer circuitry.

2. The general sequence bus device as claimed in claim 1, wherein the readiness marker is arranged in a first-in-first-out (FIFO) manner in the readiness marker queue waiting list.

3. The Universal Sequence Bus (USB) device as claimed in claim 1, wherein when the ready flag corresponding to the USB controller polled by the host is not in the first position of the ready flag waiting list, the USB decision processor transmits a negative acknowledgment signal to the host through the USB physical layer circuitry.

4. The universal sequence bus device as claimed in claim 1, wherein the universal sequence bus controllers use the same speed class.

5. The generic sequence bus device as claimed in claim 1, wherein the host does not clear the stored device controller initial address.

6. A method of operating a universal sequence bus device, the universal sequence bus device comprising a plurality of universal sequence bus controllers, a universal sequence bus decision processor, and a universal sequence bus physical layer circuit, the universal sequence bus decision processor being coupled to the universal sequence bus controllers and the universal sequence bus physical layer circuit, the method of operating the universal sequence bus device comprising: The generic bus controllers are controlled to periodically reset the physical layer circuitry of the generic bus during an initial setup period to obtain the corresponding device controller initial address and descriptor; The system controls the GC bus decision processor to add a readiness flag of a GC bus controller that is ready to receive data from a host request to a host into a readiness flag queue wait list; and controls the GC bus decision processor to transmit the data of the corresponding GC bus controller to the host according to the readiness flag queue wait list, wherein when the readiness flag of the GC bus controller polled by the host is at the first position in the readiness flag queue wait list, the system controls the GC bus decision processor to transmit the data of the corresponding GC bus controller to the host, wherein during the initial setup period, when one of the GC bus controllers resets the GC bus physical layer circuitry to obtain the corresponding device controller initial address and descriptor, the GC bus controller that has obtained the device controller initial address does not respond to the host and remains in a previous state, which includes a state that does not change the state of the obtained device controller initial address or a state that waits to reset the GC bus physical layer circuitry.

7. A method of operating a general sequence bus device as described in claim 6, wherein the readiness markers are arranged in a first-in-first-out (FIFO) manner in the readiness marker queue waiting list.

8. A method of operating a Universal Sequence Bus (USB) device as described in claim 6, wherein when the ready flag corresponding to the USB controller polled by the host is not in the first position of the ready flag waiting list, the USB decision processor is controlled to send a negative acknowledgment signal to the host through the USB physical layer circuitry in response to a host request.

9. A method of operating a universal sequence bus device as described in claim 6, wherein the universal sequence bus controllers use the same speed class.

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