Static display driver for multistable displays

Abstract

This invention relates to a static display driver multistable display, comprising a timing control circuit unit, a driving circuit unit, and a panel unit. The timing control circuit unit generates timing control signals. The data signals of the timing control signals include pixel static display header data and pixel static display waveform data. The driving circuit unit determines the pixel display voltage value of the pixel display driving signal output to the panel unit based on the pixel static display header data, and determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data. Since the driving circuit unit only needs to determine the entire waveform of the pixel display driving signal for each pixel electrode based on the pixel static display header data and the pixel static display waveform data, the clock frequency is independent of the working count, which significantly reduces the amount of data that needs to be transmitted and allows the use of a lower clock frequency, thereby reducing power consumption.

Description

Technical Field

[0001] A display, particularly a static display driven multistable display driven by a low-frequency driving method. Prior Technology

[0002] A conventional multistable display, such as a cholesterol liquid crystal display (ChLCD), exhibits bistable liquid crystal display characteristics. Therefore, when displaying an image, this multistable display requires multiple voltage configurations for driving. For example, this multistable display has a panel unit, and each pixel of the panel unit is composed of a plurality of scan electrodes and a plurality of data electrodes, with a liquid crystal layer disposed between these line electrodes and the pixel electrodes. When driving the panel unit, a voltage is applied to these line electrodes and the pixel electrodes, so that a specific voltage is applied at the position of the corresponding pixel, causing the liquid crystal in the liquid crystal layer to rotate to a specific angle.

[0003] However, this multi-stable display requires multiple voltage configurations to drive it. Therefore, in the control signals, the data used to control the voltage configuration of each pixel needs to be transmitted through multiple bits, making it impossible to represent multiple voltage configurations with a single bit. For example, currently, the data used to control the voltage configuration is transmitted through 3 bits of data. That is, every time the voltage configuration of a pixel is changed, 3 bits of data need to be transmitted.

[0004] Furthermore, the multistable display will have a timing controller (TCON) and a driver IC. The timing controller generates a timing control signal to the driver IC, and the driver IC outputs pixel drive signals to the line electrodes and pixel electrodes according to the control signal, thereby driving the multistable display to display a specific image.

[0005] Generally, this timing control circuit unit has a clock output port (clk), a display output enable control port (doe), a display output ground control port (dog), a digital-to-analog conversion control port (d2a), a display start signal control port (dsp), and multiple data output ports (data). The clock output port (clk), display output enable control port (doe), display output ground control port (dog), digital-to-analog conversion control port (d2a), display start signal control port (dsp), and these data output ports of the timing control circuit unit are connected to the driver circuit unit (Driver IC) to output the control signal. The frequency of the clock signal output by the clock output port (clk) greatly affects the overall power consumption. The higher the frequency of the clock signal, the greater the overall power consumption.

[0006] For example, taking a multistable display with Full HD resolution as an example, the resolution is... When transmitting at Single Data Rate (SDR), 2 pixels of data are transmitted per clock cycle, meaning the number of pixels transmitted per clock cycle is 2. Furthermore, the transmission time for each frame is set... The time complexity is 5 milliseconds (ms). Each pixel of this multistable multi-state display requires 3 bits of data to transmit. Furthermore, since each pixel requires 3 bits of data to transmit, and the number of pixels transmitted per clock cycle is 2, the number of data output ports is the number of bits required for each pixel multiplied by the number of pixels transmitted per clock cycle. In other words, there are 6 data output ports.

[0007] Furthermore, for each pixel, multiple voltage configurations are required to complete the output within a frame. Therefore, the voltage waveform needs to be adjusted within a frame. For example, there are multiple duty periods within a frame, and the total number of duty periods within a frame is called the duty count. For instance, the duty count can be adjusted as needed and can be set to 64, usually in powers of 2. When the voltage configuration required for each duty period is different, 3 bits of data need to be transmitted again. Therefore, the more duty periods there are, the more times data needs to be transmitted.

[0008] The clock rate of this multistable display can be calculated using the following formula:

[0009] The resolution is 1920. The number of pixels transmitted per clock clock is 2 in SDR mode. The hold time is set to 1. The duty count can be adjusted as needed and can be set to 64. Transmission time ( The value is 5 milliseconds (ms). Substituting the above figures into the formula yields the following Table 1.

[0010] Resolution (Resolution) Transmission mode (Mode) Pixel Per Clock Duty Count Clock Rate Full HD ( ) SDR 2 64 5 (ms) 12.314 (MHz) Table 1

[0011] As shown in Table 1, under Full HD resolution, the clock rate is quite high because it is related to the duty count. This results in high power consumption and rapid power consumption for the multistable display. Summary of the Invention

[0012] Given that existing multistable displays have relatively high clock rates, resulting in high power consumption and rapid battery drain, this invention provides a static display driver for multistable displays to reduce the clock rate of the multistable display, thereby reducing power consumption.

[0013] The static display driver multistable display includes a timing control circuit unit (TCON), a driver circuit unit (Driver IC), and a panel unit (Panel).

[0014] The timing control circuit unit generates a timing control signal. The drive circuit unit is connected to the timing control circuit unit and receives the timing control signal. The panel unit is connected to the drive circuit unit.

[0015] The timing control signal includes a data signal, which contains one pixel static display header data and one pixel static display waveform data. The driving circuit unit determines the pixel display voltage value of the pixel display driving signal output to the panel unit based on the pixel static display header data, and the driving circuit unit determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data.

[0016] Because the driving circuit unit determines the pixel display voltage value of the pixel display driving signal output to the panel unit based on the pixel static display header data, and determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data, the driving circuit unit only needs to determine the entire waveform of the pixel display driving signal for each pixel electrode based on the pixel static display header data and the pixel static display waveform data. There is no need to readjust the voltage waveform by providing a new voltage value during voltage adjustment. In other words, the clock rate is independent of the duty count. This significantly reduces the amount of data that needs to be transmitted, and allows for the use of a lower clock rate while transmitting the same amount of data in the same amount of time, thereby reducing power consumption. Simple Explanation of the Diagram

[0017] Figure 1 is a block diagram of the static display driving multistable display of the present invention. Figure 2 is a schematic diagram of the electrode structure of the panel unit 30 of the static display driving multistable display of the present invention. Figure 3A is a waveform diagram of the header setting signal output by the header setting control port (dsh) of the first embodiment of the static display driving multistable display of the present invention. Figure 3B is a schematic diagram of the data signal output from the data signal output port of the first embodiment of the static display driving multistable display of the present invention. Figure 4A is a waveform diagram of the header setting signal output by the header setting control port (dsh) of the second embodiment of the static display driving multistable display of the present invention. Figure 4B is a schematic diagram of the data signal output from the data signal output port of the second embodiment of the static display driving multistable display of the present invention. Figure 5A is a waveform diagram of the header setting signal output by the header setting control port (dsh) of the third embodiment of the static display driving multistable display of the present invention. Figure 5B is a schematic diagram of the data signal output from the data signal output port of the third embodiment of the static display driving multistable display of the present invention. Figure 6A is a waveform diagram of the header setting signal output by the header setting control port (dsh) of the fourth embodiment of the static display driving multistable display of the present invention. Figure 6B is a schematic diagram of the data signal output from the data signal output port of the fourth embodiment of the static display driving multistable display of the present invention. Figure 7A is a waveform diagram of the header setting signal output by the header setting control port (dsh) of the fifth embodiment of the static display driving multistable display of the present invention. Figure 7B is a schematic diagram of the data signal output from the data signal output port of the fifth embodiment of the static display driving multistable display of the present invention. Figure 8A is a schematic diagram of the pixel clearing header data of the data signal output port of the static display driving multistable display of the present invention. Figure 8B is a schematic diagram of the pixel clearing header data of the data signals output by the first to third data output terminals (data 0 to data 2) of the static display driving multistable display of the present invention. Figure 9A is a schematic diagram of the pixel clearing waveform data of the data signal output port of the static display driving multistable display of the present invention. Figure 9B is a schematic diagram of the pixel clearing waveform data of the data signals output by the first to third data output terminals (data 0 to data 3) of the static display driving multistable display of the present invention. Figure 10A is a schematic diagram of the pixel static display header data of the data signal output port of the static display driving multistable display of the present invention. Figure 10B is a schematic diagram of the pixel static display header data of the data signals output by the first to third data output terminals (data 0 to data 2) of the static display driving multistable display of the present invention. Figure 11A is a schematic diagram of the pixel static display waveform data of the data signal output port of the static display driving multistable display of the present invention. Figure 11B is a schematic diagram of the pixel static display waveform data of the data signals output by the first to third data output terminals (data 0 to data 2) of the static display driving multistable display of the present invention. Figure 12 is a schematic diagram of the data signals output by the first to third data output terminals (data 0 to data 2) of the static display driving multistable display of the present invention. Figure 13A is a waveform diagram of the data driving signal output from the driving circuit unit of the static display driving multistable display of the present invention to the first pixel electrode. Figure 13B is a waveform diagram of the data driving signal output from the driving circuit unit of the static display driving multistable display of the present invention to the second pixel electrode. Figure 14 is another block diagram of the static display driving multistable display of the present invention. Figure 15A is a schematic diagram of the data signal output from the data signal output port of the static display driving multistable display of the present invention. Figure 15B is a schematic diagram of the conversion control signal output by the digital-to-analog conversion control port (d2a) of the static display driving multistable display of the present invention. Figure 16 is a schematic diagram of the data signals output by the first to third data output terminals (data 0 to data 2) of the static display driving multistable display of the present invention. Figure 17A is a waveform diagram of the data driving signal output from the driving circuit unit of the static display driving multistable display of the present invention to the first pixel electrode. Figure 17B is a waveform diagram of the data driving signal output from the driving circuit unit of the static display driving multistable display of the present invention to the second pixel electrode. Figure 17C is a schematic diagram of the conversion control signal output by the digital-to-analog conversion control port (d2a) of the static display driving multistable display of the present invention. Figure 18 is another block diagram of the static display driving multistable display of the present invention. Figure 19A is a waveform diagram of the header setting signal output by the header setting control port (dsh) of the static display driving multistable display of the present invention. Figure 19B is a schematic diagram of the scan signal output from the scan signal output port of the static display driving multistable display of the present invention. Figure 19C is a schematic diagram of the conversion control signal output by the digital-to-analog conversion control port (d2a) of the static display driving multistable display of the present invention. Figure 20A is a schematic diagram of the static display header data of the scan signal output port of the static display driving multistable display of the present invention. Figure 20B is a schematic diagram of the static display header data of the scan signals output by the first to third scan output terminals (scan 0 to scan 2) of the static display driving multistable display of the present invention. Figure 21A is a schematic diagram of the static display waveform data of the scan signal output from the scan signal output port of the static display driving multistable display of the present invention. Figure 21B is a schematic diagram of the static display waveform data of the scan signals output by the first to third scan output terminals (scan 0 to scan 2) of the static display driving multistable display of the present invention. Figure 22 is a schematic diagram of the scan signals output by the first to third scan output terminals (scan 0 to scan 2) of the static display driving multistable display of the present invention. Figure 23A is a waveform diagram of the scanning drive signal output from the driving circuit unit of the static display driving multistable display of the present invention to the first line electrode. Figure 23B is a waveform diagram of the scanning drive signal output from the driving circuit unit of the static display driving multistable display of the present invention to the second line electrode. Figure 23C is a schematic diagram of the conversion control signal output by the digital-to-analog conversion control port (d2a) of the static display driving multistable display of the present invention. Implementation

[0018] Please refer to Figure 1. The static display driving multistable display of the present invention includes a timing control circuit unit 10, a driving circuit unit 20 and a panel unit 30.

[0019] The timing control circuit unit 10 generates a timing control signal. The drive circuit unit 20 is connected to the timing control circuit unit 10 and receives the timing control signal. The panel unit 30 is connected to the drive circuit unit 20 and receives the timing control signal.

[0020] Please refer to Figure 2, which is a schematic diagram of the structure of the panel unit 30 of the multi-stable display. The panel unit 30 is a passive matrix composed of a plurality of intersecting pixel electrodes 31 (rows 1 to n) and a plurality of line electrodes 32 (columns 1 to m), with each pixel electrode 31 and each line electrode 32 forming a pixel at their intersection. That is, each pixel has a corresponding pixel electrode 31 and a corresponding line electrode 32. In Figure 2, the display panel unit 30 has n pixel electrodes 31 and m line electrodes 32. The panel unit 30 is driven by the driving circuit unit 20 outputting pixel driving signals to the pixel electrodes 31 and line driving signals to the line electrodes 32. For example, the driving circuit unit 20 sequentially outputs pixel driving signals and line driving signals to the pixel electrodes 31 and the line electrodes 32 in a scanning manner.

[0021] Referring to Figures 3A and 3B, the timing control signal includes a data signal 11, which contains pixel static display header data 111 and pixel static display waveform data 112. The driving circuit unit 20 determines a pixel display voltage value for a pixel display driving signal output to the panel unit 30 based on the pixel static display header data 111, and the driving circuit unit 20 determines a pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data 112. In this embodiment, the pixel display driving signal is the pixel driving signal output by the driving circuit unit 20 to the pixel electrodes 31.

[0022] Since the driving circuit unit 20 determines the pixel display voltage value of the pixel display driving signal output to the panel unit 30 based on the pixel static display header data 111, and determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data 112, the driving circuit unit 20 only needs to determine the entire waveform of the pixel display driving signal for each pixel electrode based on the pixel static display header data 111 and the pixel static display waveform data 112, without needing to readjust the voltage waveform by applying a new voltage during voltage adjustment. In other words, the clock rate is independent of the duty count, which significantly reduces the amount of data that needs to be transmitted, and allows for the use of a lower clock rate to transmit the same amount of data in the same amount of time, thereby reducing power consumption.

[0023] Furthermore, referring to Figures 4A and 4B, the data signal 11 also includes pixel clear header data 113. The driving circuit unit 20 determines a pixel clear driving signal to be output to the panel unit 30 based on the pixel clear header data 113. Generally, the pixel clear driving signal is a driving signal with a fixed waveform. Therefore, the driving circuit unit 20 can determine the pixel clear voltage value of the pixel clear driving signal based on the data in the pixel clear header data 113, and then output the pixel clear driving signal with a fixed waveform.

[0024] Furthermore, as shown in Figures 5A and 5B, the data signal 11 also includes pixel clear header data 113 and pixel uniform Lying Helix (ULH) header data 115. The driving circuit unit 20 determines the pixel clear drive signal output to the panel unit 30 based on the pixel clear header data 113, and the driving circuit unit 20 determines the pixel ULH drive signal output to the panel unit 30 based on the pixel ULH header data 115. Typically, the pixel clear drive signal and the pixel ULH drive signal are drive signals with fixed waveforms. Therefore, the driving circuit unit 20 can determine the pixel clear voltage value of the pixel clear drive signal based on the data in the pixel clear header data 113, and then output the pixel clear drive signal with a fixed waveform. Furthermore, the driving circuit unit 20 can determine the pixel ULH voltage value of the pixel ULH driving signal based on the data in the pixel ULH header data 115, and then output the pixel ULH driving signal with a fixed waveform.

[0025] Referring again to Figures 6A and 6B, the data signal 11 also includes pixel clearing header data 113 and pixel clearing waveform data 114. The driving circuit unit 20 determines the pixel clearing voltage value of the pixel clearing driving signal output to the panel unit 30 based on the pixel clearing header data 113, and the driving circuit unit 20 determines the pixel clearing driving duration of the pixel clearing driving signal with the pixel clearing voltage value based on the pixel clearing waveform data 114. In this embodiment, the pixel clearing driving signal is the pixel driving signal output by the driving circuit unit 20 to the pixel electrodes 31.

[0026] Please refer to Figures 7A and 7B. The data signal 11 also includes pixel clear header data 113, pixel clear waveform data 114, pixel ULH header data 115, and pixel ULH waveform data 116. The driving circuit unit 20 determines the pixel clear voltage value of the pixel clear driving signal output to the panel unit 30 based on the pixel clear header data 113, and the driving circuit unit 20 determines the pixel clear driving duration of the pixel clear driving signal with the pixel clear voltage value based on the pixel clear waveform data 114. In addition, the driving circuit unit 20 also determines the pixel ULH voltage value of the pixel ULH driving signal output to the panel unit 30 based on the pixel ULH header data 115, and the driving circuit unit 20 determines the pixel ULH driving duration of the pixel ULH driving signal with the pixel ULH voltage value based on the pixel ULH waveform data 116. In this embodiment, the pixel clear drive signal and the pixel ULH drive signal are both pixel drive signals output by the drive circuit unit 20 to the pixel electrodes 31.

[0027] Furthermore, the data signal 11 also includes a blank data 110. As shown in FIG4B, the blank data 110 is located between the pixel clear header data 113 and the pixel static display header data 111. Alternatively, as shown in FIG5B, the blank data 110 is located between the pixel clear header data 113 and the pixel ULH header data 115, and the blank data 110 is also located between the pixel ULH header data 115 and the pixel static display header data 111. Or, as shown in FIG6B, the blank data 110 is located between the pixel clear waveform data 114 and the pixel static display header data 111. Or, as shown in FIG7B, the blank data 110 is located between the pixel clear waveform data 114 and the pixel ULH header data 115, and the blank data 110 is also located between the pixel ULH waveform data 116 and the pixel static display header data 111.

[0028] The time occupied by the blank data 110 is used for the drive circuit unit 20 to output the pixel clear drive signal or the pixel ULH drive signal to the panel unit 30.

[0029] In detail, as shown in Figure 1, in one embodiment, the timing control circuit unit 10 includes a clock output port (clk), a display output enable control port (doe), a display output ground control port (dog), and a display start pulse control port (dsp). The functions of the clock output port (clk), the display output enable control port (doe), the display output ground control port (dog), and the display start pulse control port (dsp) of the timing control circuit unit 10 are the same as those of the timing control circuit unit 10 of a conventional multi-stable display, and will not be described in detail here.

[0030] Furthermore, the timing control circuit unit 10 includes a header setting control port (dsh) and a data signal output port. In other embodiments, the data output port of the timing control circuit unit 10 includes multiple data output terminals, such as the first to the (n+1)th data output terminals (data 0 to data n). In this embodiment, the first to the third data output terminals (data 0 to data 2) are used as examples, but this is not a limitation.

[0031] The header setting control port (dsh) is connected to the drive circuit unit 20 and outputs a header setting signal 101 to the drive circuit unit 20. The data signal output port (data 0) is connected to the drive circuit unit 20 and outputs the data signal 11 to the drive circuit unit 20.

[0032] As shown in Figures 3A and 3B, when the data signal 11 output by the data signal output port (data 0~data 2) is the static display header data 111 of the pixel, the header setting control port (dsh) outputs the header setting signal 101 at a high voltage level. As shown in Figures 4A and 4B, when the data signal 11 output by the data signal output port (data 0~data 2) is the clear header data 113 of the pixel, the header setting control port (dsh) outputs the header setting signal 101 at a high voltage level. As shown in Figures 5A and 5B, when the data signal 11 output by the data signal output port (data 0~data 2) is the ULH header data 115 of the pixel, the header setting control port (dsh) outputs the header setting signal 101 at a high voltage level. As shown in Figures 7A and 7B, when the data signal 11 output by the data signal output port (data 0~data 2) is not the pixel clear header data 113, the pixel ULH header data 115, or the pixel static display header data 111, the header setting signal 101 output by the header setting control port (dsh) is a low voltage level.

[0033] When the header setting control port (dsh) outputs the header setting signal 101 at the high voltage level, it means that the data signal 11 output by the data signal output port (data 0) is the pixel clear header data 113, the pixel ULH header data 115, or the pixel static display header data 111. In this way, the drive circuit unit 20 can determine whether the currently received data signal 11 is the pixel clear header data 113, the pixel ULH header data 115, or the pixel static display header data 111 based on the header setting signal 101.

[0034] Referring to Figures 8A and 8B, the pixel clear header data 113 includes a positive pixel clear voltage data 1131 and a negative pixel clear voltage data 1132. Furthermore, the pixel clear header data 113 may also include clear clock data. This clear clock data represents the number of clocks per clear unit time. The number of clocks per clear unit time refers to the number of clocks (clk) required for one duty period. For example, the clear clock data is a 3-bit binary number used to represent the decimal value 0~7. For instance, binary 000 represents the decimal value 0, and binary 111 represents the decimal value 7. For example, when the clear clock data is set to 100, it represents a duty period of 4 clocks (clk).

[0035] Furthermore, the pixel positive clear voltage data 1131 includes a first pixel positive clear voltage value 1131a and a second pixel positive clear voltage value 1131b, and the pixel negative clear voltage data 1132 includes a first pixel negative clear voltage value 1132a and a second pixel negative clear voltage value 1132b. In this embodiment, the first pixel positive clear voltage value 1131a is the first value of the first to third data output terminals (data 0 to data 2), and the first pixel positive clear voltage value 1131a is represented by a 3-bit binary data, namely V1(0) to V1(2), corresponding to a first voltage V1. For example, the binary value corresponding to the first voltage V1 is 001, that is, V1(2)=0, V1(1)=0, V1(0)=1. The second pixel positive clear voltage value 1131b is the second value of the first to third data output terminals (data 0 to data 2), and this second pixel positive clear voltage value is also represented by a 3-bit binary data, corresponding to the first voltage V1. Similarly, the first pixel negative clear voltage value 1132a is the third value of the first to third data output terminals (data 0 to data 2), and this first pixel negative clear voltage value is represented by a 3-bit binary data, namely V4(0) to V4(2), corresponding to a fourth voltage V4. For example, the binary value corresponding to the fourth voltage V4 is 100, that is, V4(2)=1, V4(1)=0, V4(0)=0. The second pixel negative clear voltage value 1132b is the fourth value of the first to third data output terminals (data 0 to data 2), and the second pixel negative clear voltage value 1132b is also represented by a 3-bit binary data, corresponding to the fourth voltage V4.

[0036] Please refer to Figures 9A and 9B. The pixel clearing waveform data 114 includes a plurality of pixel electrode clearing data, such as first to nth pixel electrode clearing data 1141 to 114n. These pixel electrode clearing data include at least one first pixel electrode clearing data 1141, and the first pixel electrode clearing data 1141 includes a first clearing voltage unit number. In this embodiment, the first clearing voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the first clearing voltage unit number is represented by a 3-bit binary data format, i.e., pixel 1(0) to pixel 1(2), corresponding to a first pixel electrode. Furthermore, these pixel electrode clearing data may also include second to nth pixel electrode clearing data 1142 to 114n, and the second to nth pixel electrode clearing data 1142 to 114n each include a second to nth clearing voltage unit number. Similarly, the second clear voltage unit number is represented by a 3-bit binary data, namely pixel 2(0)~pixel 2(2), corresponding to a second pixel electrode.

[0037] Furthermore, the drive circuit unit 20 has a duty count, and the drive circuit unit 20 determines a first remaining clear voltage unit by subtracting the first clear voltage unit from the duty count. For example, the duty count can be set to 7. When the first clear voltage unit is 100, representing the decimal value 4, the duty count minus the first clear voltage unit is 7-4=3, and the drive circuit unit 20 sets the first remaining clear voltage unit to 3. In other examples, when the first clear voltage unit is 111, representing the decimal value 7, the duty count minus the first clear voltage unit is 7-7=0, and the drive circuit unit 20 sets the first remaining clear voltage unit to 0.

[0038] In this embodiment, the pixel clearing header data 113 may also include a total number of jobs data. The driving circuit unit 20 can set the total number of jobs based on the total number of jobs data in the pixel clearing header data 113.

[0039] Furthermore, when the driving circuit unit 20 determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the pixel clearing waveform data 114, the driving circuit unit 20 determines a first clearing duration for outputting the pixel clearing drive signal with the first pixel positive clearing voltage value to the first pixel electrode based on the first clearing voltage units of the pixel clearing waveform data 114; the driving circuit unit 20 determines a second clearing duration for outputting the pixel clearing drive signal with the second pixel positive clearing voltage value to the first pixel electrode based on the first remaining clearing voltage units; the driving circuit unit 20 determines a third clearing duration for outputting the pixel clearing drive signal with the first pixel negative clearing voltage value to the first pixel electrode based on the first clearing voltage units of the pixel clearing waveform data; and the driving circuit unit determines a fourth clearing duration for outputting the pixel clearing drive signal with the second negative clearing voltage value to the first pixel electrode based on the first remaining clearing voltage units.

[0040] Please refer to Figures 10A and 10B. The pixel static display header data 111 includes positive display voltage data 1111 and negative display voltage data 1112. Furthermore, the pixel static display header data 111 may also include display clock data, which contains the number of clock cycles per unit time. The number of clock cycles per unit time refers to the number of clock cycles (clk) required for one duty period. For example, the display clock data is a 3-bit binary number used to represent the decimal value 0~7. For instance, binary 000 represents the decimal value 0, and binary 111 represents the decimal value 7. For example, when the display clock data is set to 100, it represents a duty period of 4 clock cycles (clk).

[0041] Furthermore, the positive display voltage data 1111 includes a first positive display voltage value 1111a and a second positive display voltage value 1111b, and the negative display voltage data 1112 includes a first negative display voltage value 1112a and a second negative display voltage value 1112b. In this embodiment, the first positive display voltage value 1111a is the first value of the first to third data output terminals (data 0 to data 2), and the first positive display voltage value is represented by a 3-bit binary data, namely V2(0) to V2(2), corresponding to a second voltage V2. For example, the binary value corresponding to the second voltage V2 is 010, that is, V2(2)=0, V2(1)=1, V2(0)=0. The positive display voltage value 1111b of the second pixel is the second value of the first to third data output terminals (data 0 to data 2), and the positive display voltage value of the second pixel is also represented by a 3-bit binary data form, namely V3(0) to V3(2), corresponding to a third voltage V3. For example, the binary value corresponding to the third voltage V3 is 011, that is, V3(2)=0, V3(1)=1, V3(0)=1. Similarly, the negative display voltage value 1112a of the first pixel is the third value of the first to third data output terminals (data 0 to data 2), and the negative display voltage value 1112a of the first pixel is represented by a 3-bit binary data form, namely V5(0) to V5(2), corresponding to a fifth voltage V5. For example, the binary value corresponding to the fifth voltage V5 is 101, that is, V5(2)=1, V5(1)=0, V5(0)=1. The negative display voltage value 1112b of the second pixel is the fourth value of the first to third data output terminals (data 0 to data 2), and the negative display voltage value of the second pixel is also represented by a 3-bit binary data, namely V6(0) to V6(2), corresponding to a sixth voltage V6. For example, the binary value corresponding to the sixth voltage V6 is 110, that is, V6(2)=1, V6(1)=1, V6(0)=0.

[0042] Please refer to Figures 11A and 11B. The pixel static display waveform data 112 includes a plurality of pixel electrode display data, such as first to nth pixel electrode display data 1121 to 112n. These pixel electrode display data include at least one first pixel electrode display data 1121, and the first pixel electrode display data 1121 includes a first display voltage unit number. In this embodiment, the first display voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the first display voltage unit number is represented by a 3-bit binary data format, i.e., pixel 1(0) to pixel 1(2), corresponding to the first pixel electrode. Furthermore, these pixel electrode display data may also include second to nth pixel electrode display data 1122 to 112n, and the second to nth pixel electrode display data 1122 to 112n each include a second to nth display voltage unit number. Similarly, the second display voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the second display voltage unit number is represented by a 3-bit binary data, namely pixel 2(0) to pixel 2(2), corresponding to the second pixel electrode.

[0043] Furthermore, the drive circuit unit 20 has a duty count, and the drive circuit unit 20 determines a first remaining display voltage unit by subtracting the first display voltage unit from the duty count. For example, the duty count is set to 7. When the first display voltage unit is 100, representing a decimal value of 4, the duty count minus the first display voltage unit is 7-4=3, and the drive circuit unit 20 sets the first remaining display voltage unit to 3. In other examples, when the first display voltage unit is 111, representing a decimal value of 7, the duty count minus the first display voltage unit is 7-7=0, and the drive circuit unit 20 sets the first remaining display voltage unit to 0.

[0044] In this embodiment, the pixel static display header data 111 may also include the total number of jobs data. Furthermore, the driving circuit unit 20 can set the total number of jobs based on the total number of jobs data in the pixel static display header data 111.

[0045] Furthermore, when the driving circuit unit 20 determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data 112, the driving circuit unit 20 determines a first display duration for the pixel display driving signal output to the first pixel electrode with the first positive display voltage value based on the first number of display voltage units in the pixel static display waveform data 112; the driving circuit unit 20 determines a second display duration for the pixel display driving signal output to the first pixel electrode with the second positive display voltage value based on the first remaining number of display voltage units; the driving circuit unit 20 determines a third display duration for the pixel display driving signal output to the first pixel electrode with the first negative display voltage value based on the first number of display voltage units in the pixel static display waveform data; and the driving circuit unit 20 determines a fourth display duration for the pixel display driving signal output to the first pixel electrode with the second negative display voltage value based on the first remaining number of display voltage units.

[0046] For example, as shown in Figure 12, the preset total number of operations is 7. As shown in the first pixel electrode clearing data 1141, the number of first clearing voltage units is 111. As shown in the second pixel electrode clearing data 1142, the number of second clearing voltage units is 111. As shown in the first pixel positive clearing voltage value 1131a, the first pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the second pixel positive clearing voltage value 1131b, the second pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the first pixel negative clearing voltage value 1132a, the first pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the second pixel negative clearing voltage value 1132b, the second pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the first pixel electrode display data 1121, the number of first display voltage units is 100. As shown in the second pixel electrode display data 1122, the number of second display voltage units is 111. As shown by the positive display voltage value 1111a of the first pixel, the positive display voltage value of the first pixel is the second voltage V2, i.e., 010. As shown by the positive display voltage value 1111b of the second pixel, the positive display voltage value of the second pixel is the third voltage V3, i.e., 011. As shown by the negative display voltage value 1112a of the first pixel, the negative display voltage value of the first pixel is the fifth voltage V5, i.e., 101. As shown by the negative display voltage value 1112b of the second pixel, the negative display voltage value of the second pixel is the sixth voltage V6, i.e., 110.

[0047] Since the first clear voltage unit number is 111, the first clear duration of the pixel clear drive signal with the first pixel positive clear voltage value, i.e., the first voltage V1, output by the driving circuit unit 20 to the first pixel electrode is 7 working hours (duty). And since the total number of working hours is 7, the first remaining clear voltage unit number is 0, and the second clear duration of the pixel clear drive signal with the second pixel positive clear voltage value, i.e., the first voltage V1, output by the driving circuit unit 20 to the first pixel electrode is 0 working hours (duty). Furthermore, after the driving circuit unit 20 outputs the pixel clear drive signal with the first voltage V1 to the first pixel electrode, the driving circuit unit 20 enters a negative half-cycle, and then the driving circuit unit 20 outputs the pixel clear drive signal with the first pixel negative clear voltage value, i.e., the fourth voltage V4, to the first pixel electrode for the first clear duration, and the first clear duration is 7 working hours (duty). Since the total number of working units is 7, the number of the first remaining clear voltage units is 0, and the second clear duration of the pixel clear drive signal output by the drive circuit unit 20 to the first pixel electrode having the second pixel negative clear voltage value, i.e. the fourth voltage V4, is 0 working hours (duty).

[0048] Similarly, since the second clear voltage unit number is 111, the first clear duration of the pixel clear drive signal with the first pixel positive clear voltage value, the first voltage V1, output by the driving circuit unit 20 to the second pixel electrode is 7 working hours (duty). And since the total number of working hours is 7, the first remaining clear voltage unit number is 0, and the second clear duration of the pixel clear drive signal with the second pixel positive clear voltage value, i.e., the first voltage V1, output by the driving circuit unit 20 to the second pixel electrode is 0 working hours (duty). Furthermore, after the driving circuit unit 20 outputs the pixel clear drive signal with the first voltage V1 to the second pixel electrode, the driving circuit unit 20 enters a negative half-cycle, and then the driving circuit unit 20 outputs the pixel clear drive signal with the first pixel negative clear voltage value, i.e., the fourth voltage V4, to the second pixel electrode for the first clear duration, and the first clear duration is 7 working hours (duty). Since the total number of working units is 7, the number of the first remaining clear voltage units is 0, and the second clear duration of the pixel clear drive signal output by the drive circuit unit 20 to the second pixel electrode having the second pixel negative clear voltage value, i.e. the fourth voltage V4, is 0 working hours (duty).

[0049] Since the first display voltage unit number is 100, the first display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode, which has the positive display voltage value of the first pixel (i.e., the second voltage V2), is 4 working hours (duty). And since the total number of working hours is 7, the first remaining display voltage unit number is 3, and the second display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode, which has the positive display voltage value of the second pixel (i.e., the third voltage V3), is 3 working hours (duty). Furthermore, after the driving circuit unit 20 outputs the pixel display driving signal with the third voltage V3 to the first pixel electrode, the driving circuit unit 20 enters a negative half-cycle, and then outputs the pixel display driving signal with the negative display voltage value of the first pixel (i.e., the fifth voltage V5) to the first pixel electrode for the first display duration, and the first display duration is 4 working hours (duty). Furthermore, since the total number of working units is 7, the number of the first remaining display voltage units is 3, and the second display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode having the second pixel negative display voltage value, i.e. the sixth voltage V6, is 3 working hours (duty).

[0050] Similarly, since the second display voltage unit number is 111, the first display duration of the pixel display driving signal output by the driving circuit unit 20 to the second pixel, which has the positive display voltage value of the first pixel (i.e., the second voltage V2), is 7 working hours (duty). And since the total number of working hours is 7, the first remaining display voltage unit number is 0, and the second display duration of the pixel display driving signal output by the driving circuit unit 20 to the second pixel, which has the positive display voltage value of the second pixel (i.e., the third voltage V3), is 0 working hours (duty). Furthermore, after the driving circuit unit 20 outputs the pixel display driving signal with the second voltage V2 to the second pixel, the driving circuit unit 20 enters a negative half-cycle, and then outputs the pixel display driving signal with the negative display voltage value of the first pixel (i.e., the fifth voltage V5) to the second pixel for the first display duration, and the first display duration is 7 working hours (duty). Since the total number of working units is 7, the number of the first remaining display voltage units is 0, and the second display duration of the pixel display drive signal output by the drive circuit unit 20 to the second pixel having the negative display voltage value of the second pixel, i.e. the sixth voltage V6, is 0 working hours (duty).

[0051] As shown in Figures 13A and 13B, Figure 13A is a waveform diagram of the first pixel display driving signal 201 output by the driving circuit unit 20 to the first pixel electrode, and Figure 13B is a waveform diagram of the second pixel display driving signal 202 output by the driving circuit unit 20 to the second pixel electrode.

[0052] For example, taking a Full HD resolution static display driving a multistable display as an example, its resolution is... When transmitting at Single Data Rate (SDR), the data for one pixel electrode is transmitted per clock cycle, meaning the number of pixels transmitted per clock cycle is 1. Furthermore, the transmission time for each frame is set... The time is 5 milliseconds (ms).

[0053] The clock rate for driving the multistable display in this static display mode is calculated using the following formula:

[0054] The resolution is 1920. The number of pixels transmitted per clock clock is 1 at Single Data Rate (SDR). Transmission time ( The value is 5 milliseconds (ms). Substituting the above figures into the formula yields the following Table 2.

[0055] Resolution (Resolution) Transmission mode (Mode) Pixel Per Clock Duty Count Clock Rate Full HD ( ) SDR 1 64 5 (ms) 384.8 (kHz) Table 2

[0056] As can be seen from the comparison of Tables 1 and 2, the clock rate of the static display driving multistable display of the present invention can be significantly reduced. In this way, the static display driving multistable display can adopt a low-frequency driving scheme, thereby effectively reducing power consumption.

[0057] Furthermore, as shown in Figure 14, in a fourth embodiment, the timing control circuit unit 10 includes a clock output port (clk), a display output enable control port (doe), a display output ground control port (dog), a display start signal control port (dsp), and a digital-to-analog conversion control port (d2a). The functions of the clock output port (clk), the display output enable control port (doe), the display output ground control port (dog), and the display start signal control port (dsp) of the timing control circuit unit 10 are the same as those of the timing control circuit unit 10 of a conventional multi-stable display, and will not be described in detail here.

[0058] The digital-to-analog conversion control port (d2a) is connected to the drive circuit unit 20.

[0059] In addition, the timing control circuit unit 10 also includes the header setting control port (dsh) and the data signal output port. In other embodiments, the data signal output port of the timing control circuit unit 10 may include multiple data output terminals, such as the first to the (n+1)th data output terminals (data 0 to data n). In this embodiment, the first to the third data output terminals (data 0 to data 2) are used as examples, but this is not a limitation.

[0060] As shown in Figures 15A and 15B, the data signal 11 contains a plurality of blank data 110, one of which is located between the pixel clear waveform data 114 and the pixel ULH header data 115, another of which is located between the pixel ULH waveform data and the pixel static display header data 111, and yet another of which is located after the pixel static display waveform data 112.

[0061] In this embodiment, the drive circuit unit 20 has the total number of jobs. When the data signal 11 is blank data 110, the digital-to-analog converter control port (d2a) outputs a count signal 102 that is an even multiple of the total number of jobs. For example, when the data signal 11 is blank data 110, the digital-to-analog converter control port (d2a) outputs a count signal 102 that is twice the total number of jobs, but this is not a limitation.

[0062] Furthermore, when the data signal 11 is the static display waveform data 112 of the pixel, the digital-to-analog conversion control port (d2a) can also output a count signal 102 that is an even multiple of the total number of operations. For example, when the data signal 11 is the static display waveform data 112 of the pixel, the digital-to-analog conversion control port (d2a) outputs a count signal 102 that is twice the total number of operations, but this is not a limitation.

[0063] Furthermore, as shown in Figure 16, in this embodiment, the pixel clearing header data 113 includes a pixel positive clearing voltage data 1131 and a pixel negative clearing voltage data 1132. The pixel positive clearing voltage data 1131 includes a first pixel positive clearing voltage value 1131a and a second pixel positive clearing voltage value 1131b, and the pixel negative clearing voltage data 1132 includes a first pixel negative clearing voltage value 1132a and a second pixel negative clearing voltage value 1132b. In this embodiment, the timing control circuit unit 10 includes the first to third data output terminals (data 0 to data 2), and the first pixel positive clearing voltage value 1131a is the first value of the first to third data output terminals (data 0 to data 2), and the first pixel positive clearing voltage value 1131a is represented by a 3-bit binary data, namely V1(0) to V1(2), corresponding to a first voltage V1, for example 001. The second pixel positive clear voltage value 1131b is the second value of the first to third data output terminals (data 0 to data 2), and the second pixel positive clear voltage value 1131b is also represented by a 3-bit binary data, corresponding to the first voltage V1, for example, 001. Similarly, the first pixel negative clear voltage value 1132a is the third value of the first to third data output terminals (data 0 to data 2), and the first pixel negative clear voltage value 1132a is represented by a 3-bit binary data, i.e., V4(0) to V4(2), corresponding to a fourth voltage V4, for example, 100. The second pixel negative clear voltage value 1132b is the fourth value of the first to third data output terminals (data 0 to data 2), and the second pixel negative clear voltage value 1132b is also represented by a 3-bit binary data, corresponding to the fourth voltage V4, for example, 100.

[0064] The pixel clearing waveform data 114 contains a plurality of pixel electrode clearing data. These pixel electrode clearing data include at least one first pixel electrode clearing data 1141, and the first pixel electrode clearing data 1141 contains a first clearing voltage unit number. In this embodiment, the first clearing voltage unit number is two values ​​from the first to third data output terminals (data 0 to data 2), and the first clearing voltage unit number is represented by a 3-bit binary data format, i.e., pixel 1(0) to pixel 1(2), corresponding to the first pixel electrode, for example, 111 as shown in the first pixel electrode clearing data 1141. Furthermore, these pixel electrode clearing data may also include second to nth pixel electrode clearing data 1142 to 114n, and the second to nth pixel electrode clearing data 1142 to 114n each contain a second to nth clearing voltage unit number. Similarly, the second clear voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the second clear voltage unit number is represented by a 3-bit binary data, namely pixel 2(0) to pixel 2(2), corresponding to a second pixel electrode, such as 111 shown in the second pixel electrode clear data 1142.

[0065] Furthermore, when the driving circuit unit 20 determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the pixel clearing waveform data 114, the driving circuit unit 20 outputs the pixel clearing drive signal with the first pixel positive clearing voltage value to the first pixel electrode between the first to the Ath count signals 102 output from the digital-to-analog conversion control port (d2a), and the driving circuit unit 20 outputs the pixel clearing drive signal with the first pixel positive clearing voltage value to the first pixel electrode between the (A+1)th to the Bth count signals 102 output from the digital-to-analog conversion control port (d2a). The pixel clearing drive signal with the positive clearing voltage value of the second pixel is sent to the first pixel electrode. The driving circuit unit 20 outputs a pixel clearing drive signal with the negative clearing voltage value of the first pixel to the first pixel electrode between the (B+1)th and (A+B)th count signals 102 output from the digital-to-analog conversion control port (d2a). The driving circuit unit 20 also outputs a pixel clearing drive signal with the negative clearing voltage value of the second pixel to the first pixel electrode between the (A+B+1)th and (2B)th count signals 102 output from the digital-to-analog conversion control port (d2a). In this embodiment, A is the number of units of the first clearing voltage, and B is the total number of working units.

[0066] The pixel static display header data 111 includes a pixel positive display voltage data 1111 and a pixel negative display voltage data 1112. The pixel positive display voltage data 1111 includes a first pixel positive display voltage value 1111a and a second pixel positive display voltage value 1111b, and the pixel negative display voltage data 1112 includes a first pixel negative display voltage value 1112a and a second pixel negative display voltage value 1112b. In this embodiment, the timing control circuit unit 10 includes the first to third data output terminals (data 0 to data 2), and the first pixel positive display voltage value 1111a is the value of the first to third data output terminals (data 0 to data 2), and the first pixel positive display voltage value 1111a is represented by a 3-bit binary data, namely V2(0) to V2(2), corresponding to a second voltage V2, namely 010. The positive display voltage value 1111b of the second pixel is the value of the first to third data output terminals (data 0 to data 2), and the positive display voltage value 1111b of the second pixel is also represented by a 3-bit binary data form, namely V3(0) to V3(2), corresponding to a third voltage V3, namely 011. Similarly, the negative display voltage value 1112a of the first pixel is the value of the first to third data output terminals (data 0 to data 2), and the negative display voltage value 1112a of the first pixel is represented by a 3-bit binary data form, namely V5(0) to V5(2), corresponding to a fifth voltage V5, namely 101. The negative display voltage value of the second pixel is the value of the first to third data output terminals (data 0 to data 2), and the negative display voltage value of the second pixel 1112b is also represented by a 3-bit binary data, namely V6(0) to V6(2), corresponding to a sixth voltage V6, namely 110.

[0067] The pixel static display waveform data 112 includes a plurality of pixel electrode display data. These pixel electrode display data include at least one first pixel electrode display data 1121, and the first pixel electrode display data 1121 includes a first display voltage unit number. In this embodiment, the first display voltage unit number is two values ​​from the first to third data output terminals (data 0 to data 2), and the first display voltage unit number is represented by a 3-bit binary data format, i.e., pixel 1(0) to pixel 1(2), corresponding to the first pixel electrode, for example, 100 as shown by the first pixel electrode display data 1121. Furthermore, these pixel electrode display data may also include second to nth pixel electrode display data 1122 to 112n, and the second to nth pixel electrode display data 1122 to 112n each include a second to nth display voltage unit number. Similarly, the second display voltage unit number is two values ​​from the first to third data output terminals (data 0 to data 2), and the second display voltage unit number is represented by a 3-bit binary data, namely pixel 2(0) to pixel 2(2), corresponding to the second pixel electrode, for example, the second pixel electrode displays data 1122 as 111.

[0068] Furthermore, when the driving circuit unit 20 determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data 112, the driving circuit unit 20 outputs the pixel display driving signal with the first pixel positive display voltage value to a first pixel electrode between the first to C count signals 102 output from the digital-to-analog conversion control port (d2a), and the driving circuit unit 20 outputs the pixel display driving signal with the first pixel positive display voltage value to a first pixel electrode between the (C+1)th to Bth count signals 102 output from the digital-to-analog conversion control port (d2a). The second pixel positive display voltage value is sent to the first pixel electrode, and the driving circuit unit 20 outputs a pixel display driving signal with the first pixel negative display voltage value to the first pixel electrode between the (B+1)th and (B+C)th count signals 102 output from the digital-to-analog conversion control port (d2a). The driving circuit unit 20 also outputs a pixel display driving signal with the second pixel negative display voltage value to the first pixel electrode between the (B+C+1)th and (2B)th count signals 102 output from the digital-to-analog conversion control port (d2a). In this embodiment, C is the number of first display voltage units, and B is the total number of working units.

[0069] For example, the preset total number of operations is 7. As shown in the first pixel electrode clearing data 1141, the number of first clearing voltage units is 111. As shown in the second pixel electrode clearing data 1142, the number of second clearing voltage units is 111. As shown in the first pixel positive clearing voltage value 1131a, the first pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the second pixel positive clearing voltage value 1131b, the second pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the first pixel negative clearing voltage value 1132a, the first pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the second pixel negative clearing voltage value 1132b, the second pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the first pixel electrode display data 1121, the number of first display voltage units is 100. As shown in the second pixel electrode display data 1122, the number of second display voltage units is 111. As shown by the positive display voltage value 1111a of the first pixel, the positive display voltage value of the first pixel is the second voltage V2, i.e., 010. As shown by the positive display voltage value 1111b of the second pixel, the positive display voltage value of the second pixel is the third voltage V3, i.e., 011. As shown by the negative display voltage value 1112a of the first pixel, the negative display voltage value of the first pixel is the fifth voltage V5, i.e., 101. As shown by the negative display voltage value 1112b of the second pixel, the negative display voltage value of the second pixel is the sixth voltage V6, i.e., 110.

[0070] Please refer to Figures 17A to 17C. Since the number of units of the first clear voltage is 111, the first clear duration of the pixel clear drive signal output by the driving circuit unit 20 to the first pixel electrode, having the first pixel positive clear voltage value (i.e., the first voltage V1), is 7 working hours. Therefore, the driving circuit unit 20 outputs the pixel clear drive signal having the first pixel positive clear voltage value (i.e., the first voltage V1) to the first pixel electrode between the 1st and 7th count signals 102 output from the digital-to-analog conversion control port (d2a). Although the driving circuit unit 20 outputs the pixel clear drive signal having the second pixel positive clear voltage value to the first pixel electrode between the A+1th and Bth count signals 102 output from the digital-to-analog conversion control port (d2a), since the number of units of the first clear voltage is 7, i.e., A=7, The total number of jobs is 7, and the number of the first clear voltage units (A) + 1 is greater than the total number of jobs (B), that is... Therefore, the driving circuit unit 20 will not output the pixel clearing driving signal with the second pixel positive clearing voltage value, i.e., the first voltage V1, to the first pixel electrode.

[0071] Furthermore, after the driving circuit unit 20 outputs the pixel clearing drive signal with the first voltage V1 to the first pixel electrode, the driving circuit unit 20 enters the negative half-cycle. The driving circuit unit 20 outputs the pixel clearing drive signal with the first pixel negative clearing voltage value, i.e., the fourth voltage V4, to the first pixel electrode between the 8th and 14th count signals 102 output from the digital-to-analog conversion control port (d2a). Although the driving circuit unit 20 outputs the pixel clearing drive signal with the second pixel negative clearing voltage value to the first pixel electrode between the A+B+1th and 2Bth count signals output from the digital-to-analog conversion control port (d2a), because... ,and In other words, the total number of jobs (B) + the number of the first clear voltage units (A) + 1 is greater than twice the total number of jobs (B). Therefore, the driving circuit unit 20 will not output the pixel clearing driving signal with the second pixel negative clearing voltage value, i.e., the first voltage V4, to the first pixel electrode.

[0072] The generation method of the pixel clearing drive signal output by the drive circuit unit 20 to the second pixel electrode is the same as that output by the drive circuit unit 20 to the first pixel electrode, and will not be described again here.

[0073] Since the first display voltage unit number is 100, the first display duration of the pixel display driving signal with the first pixel positive display voltage value, i.e., the second voltage V2, output by the driving circuit unit 20 to the first pixel electrode is 4 working hours (duty). Therefore, the driving circuit unit 20 outputs the pixel display driving signal with the first pixel positive display voltage value, i.e., the second voltage V2, to the first pixel electrode between the first to fourth count signals 102 output from the digital-to-analog conversion control port (d2a). Furthermore, the driving circuit unit 20 outputs the pixel display driving signal with the second pixel positive display voltage value, i.e., the third voltage V3, to the first pixel electrode between the fifth to seventh count signals output from the digital-to-analog conversion control port (d2a).

[0074] Furthermore, after the driving circuit unit 20 outputs the pixel display driving signal with the third voltage V3 to the first pixel electrode, the driving circuit unit 20 enters the negative half-cycle. During the period between the 8th and 11th count signals 102 output from the digital-to-analog conversion control port (d2a), the driving circuit unit 20 outputs the pixel display driving signal with the negative display voltage value of the first pixel, i.e., the fifth voltage V5, to the first pixel electrode. Furthermore, during the period between the 12th and 14th count signals 102 output from the digital-to-analog conversion control port (d2a), the driving circuit unit 20 outputs the pixel display driving signal with the negative display voltage value of the second pixel, i.e., the sixth voltage V6, to the first pixel electrode.

[0075] Similarly, since the second display voltage unit number is 111, the driving circuit unit 20 outputs a pixel display driving signal with the positive display voltage value of the first pixel, i.e., the second voltage V2, to the second pixel electrode between the first to the seventh count signal 102 output from the digital-to-analog conversion control port (d2a). Since the total number of operations is 7, the period after the seventh count signal 102 is a negative half-cycle, and the driving circuit unit 20 does not output a pixel display driving signal with the positive display voltage value of the second pixel, i.e., the third voltage V3, to the second pixel electrode.

[0076] Furthermore, when the driving circuit unit 20 enters the negative half-cycle, it outputs a pixel display driving signal with the negative display voltage value of the first pixel, i.e., the fifth voltage V5, to the second pixel electrode between the 8th and 14th count signals 102 output from the digital-to-analog conversion control port (d2a). However, since twice the total number of operations is 14, the cycle ends after the 14th count signal 102, and the driving circuit unit 20 does not output a pixel display driving signal with the negative display voltage value of the second pixel, i.e., the sixth voltage V6, to the second pixel electrode.

[0077] As shown in Figures 17A and 17B, Figure 17A is a waveform diagram of the first pixel display driving signal 201 output by the driving circuit unit 20 to the first pixel electrode, and Figure 17B is a waveform diagram of the second pixel display driving signal 202 output by the driving circuit unit 20 to the second pixel.

[0078] For example, taking a Full HD resolution static display driving a multistable display as an example, its resolution is... When transmitting at Single Data Rate (SDR), one pixel of data is transmitted per clock cycle, meaning the number of pixels transmitted per clock cycle is 1. Furthermore, the transmission time for each frame is set... The time is 5 milliseconds (ms).

[0079] The clock rate for driving the multistable display in this static display mode is calculated using the following formula:

[0080] The resolution is 1920. The number of pixels transmitted per clock clock is 1 at Single Data Rate (SDR). Transmission time ( The value is 5 milliseconds (ms). Substituting the above figures into the formula yields the following Table 2.

[0081] Resolution (Resolution) Transmission mode (Mode) Pixel Per Clock Duty Count Clock Rate Full HD ( ) SDR 1 64 5 (ms) 384.8 (kHz) Table 3

[0082] As can be seen from the comparison of Tables 1 and 3, the clock rate of the static display driving multistable display of the present invention can be significantly reduced. In this way, the static display driving multistable display can adopt a low-frequency driving scheme, thereby effectively reducing power consumption.

[0083] In summary, since the clock rate is independent of the duty count, the static display driver multistable display of this invention can achieve the same transmission time ( Under the conditions of, for example The clock rate can be significantly reduced, requiring only the kilohertz (kHz) level. This means that the static display driver for the multistable display can employ a low-frequency driving scheme, thereby effectively reducing power consumption.

[0084] Furthermore, the static display driver multistable display of the present invention only needs to transmit data once to complete the transmission of the voltage waveform of a frame. The voltage configuration of multiple working intervals (duties) within a frame can be directly determined based on the pixel static display header data 111 and the pixel static display waveform data 112, without the need to transmit different voltage configurations for each working interval (duty) within a frame for switching. Therefore, for the display start signal control port (DSP), the display start signal control port (DSP) only needs to output one cycle for each frame, without needing to output one cycle for each working interval (duty), thereby significantly reducing the number of switching times of the display start signal control port (DSP) output signal, and thus reducing dynamic power consumption.

[0085] Furthermore, since the counting signal 102 output by the digital-to-analog conversion control port (d2a) is used for counting, the data signal output port can continuously transmit data during the holding time of the counting signal 102 output by the digital-to-analog conversion control port (d2a), without affecting the digital-to-analog conversion, and thus no data bubble is generated. In other words, during the holding time of the counting signal 102 output by the digital-to-analog conversion control port (d2a), the data signal output port (data 0) can continuously transmit data without interrupting the transmission to avoid data bubble generation, thereby further improving transmission efficiency.

[0086] Furthermore, since the counting signal 102 output by the digital-to-analog conversion control port (d2a) of the static display driving multistable display of the present invention is used for counting, the waveform data of the first frame must be transmitted before the rising edge of the first counting signal 102. During the subsequent counting periods of the second to nth counting signals 102, the waveform data of the next frame can be transmitted, and the transmission must be completed before the rising edge of the (n+1)th counting signal 102. For example, assuming that the voltage waveform of a frame has 4 working intervals, the data signal output port must transmit the waveform data of the first frame before the rising edge of the first counting signal 102. During the subsequent counting periods of the second to fourth counting signals 102, the waveform data of the second frame can be transmitted, and the transmission must be completed before the rising edge of the fifth counting signal 102. In this way, there can be a buffer time between the waveform data of two consecutive frames, without the need for tight continuous transmission, thereby providing greater design flexibility.

[0087] Furthermore, the signal output from the digital-to-analog conversion control port (d2a) of a conventional multistable display is used for digital-to-analog conversion. Therefore, in each working period (duty) of a frame, the digital-to-analog conversion control port (d2a) needs to output one cycle of signal. After the digital-to-analog conversion control port (d2a) outputs one cycle of signal, the data signal output port will output the waveform data of the next working period (duty) until the waveform data of the last working period (duty) is output. More specifically, after the waveform data of the last working period (duty) of the last frame (frame) is output, the digital-to-analog conversion control port (d2a) needs to output another cycle of signal. After the digital-to-analog conversion control port (d2a) outputs the last cycle of signal, the data signal output port no longer needs to output waveform data. In other words, the conventional multistable display's data signal output port will only stop outputting the waveform data after the last signal output from the digital-to-analog conversion control port (d2a).

[0088] However, the counting signal 102 output by the digital-to-analog converter control port (d2a) of the static display driving multistable display of the present invention is used for counting. The data signal output port only needs to complete the transmission of waveform data before the rising edge of the first counting signal 102. Therefore, after the waveform data of the last frame is output, the data signal output port does not need to output the waveform data. That is to say, after the waveform data of the last frame is output, the data signal output port does not need to output the waveform data during the period when the counting signal 102 is output by the digital-to-analog converter control port (d2a). For example, assuming that the voltage waveform of the last frame has 4 duty periods, the data signal output port only needs to complete the transmission of the waveform data of the last frame before the rising edge of the first counting signal 102, and during the counting period of the first to fourth counting signals 102 of the last frame, the data signal output port does not need to transmit waveform data.

[0089] Furthermore, as described in the above embodiments, the driving circuit unit 20 determines the pixel display driving voltage value of the pixel display driving signal output to the panel unit 30 based on the pixel static display header data 111, and determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data 112. Moreover, when the driving circuit unit 20 determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data 112, the driving circuit unit 20 determines the number of display voltage units based on the waveform data 11b, and then determines the display duration of the first pixel positive display voltage value and the first pixel negative display voltage value based on the number of display voltage units. Next, the driving circuit unit 20 also determines the display duration of the second pixel positive display voltage value and the second pixel negative display voltage value after subtracting the number of display voltage units from the total number of operations. In other words, the static display waveform data 112 corresponds to the holding time of each voltage value. When the driving circuit unit 20 receives the static display waveform data 112, it calculates the number of the counting signals 102 output by the digital-to-analog conversion control port (d2a) based on the static display waveform data 112, in order to calculate the pixel display driving duration of the pixel display driving signal with the pixel display voltage value. Therefore, the driving circuit unit 20 only needs the static display waveform data 112 for each pixel to determine the entire waveform of the pixel display driving signal, thereby significantly reducing the amount of data that needs to be transmitted.

[0090] Furthermore, since the timing control circuit unit 10 only outputs a signal to drive the drive circuit unit 20 to output the line drive signal after the pixel clear header data and the pixel clear waveform data have been output, the timing control circuit unit 10 does not need to provide data during the period when the drive circuit unit 20 outputs the pixel positive clear voltage and the pixel negative clear voltage, and in the Uniform Lying Helix (ULH) steady-state mode.

[0091] Referring to Figure 18, the timing control circuit unit 10 also includes a scan output port. In other embodiments, the scan output port of the timing control circuit unit 10 may include multiple scan output terminals, such as the first to the (n+1)th scan output terminals (scan 0 to scan n). In this embodiment, the first to the third data output terminals (scan 0 to scan 2) are used as examples, but this is not a limitation.

[0092] Please refer to Figures 19A to 19C. The timing control signal includes a scan signal 21, and the scan signal 21 includes line static display header data 211 and line static display waveform data 212. The drive circuit unit 20 determines a line drive voltage value of a line drive signal output to the panel unit 30 based on the line static display header data 211, and the drive circuit unit 20 determines a signal waveform of the line drive signal output to the panel unit 30 based on the line drive voltage value and the line static display waveform data 212.

[0093] For example, as shown in Figures 20A and 20B, the static display header data 211 of the line includes at least one line positive display voltage data 2111 and one line negative display voltage data 2112, but is not limited thereto. In this embodiment, the timing control circuit unit 10 includes the first to third scan output terminals (scan 0 to scan 2), and the first line positive display voltage data 2111 includes a first line positive display voltage value 2111a and a second line positive display voltage value 2111b. The first line positive display voltage value 2111a is the value of the first to third scan output terminals (scan 0 to scan 2), i.e., V6(0) to V6(2), which corresponds to the sixth voltage V6. For example, as shown in Figure 22, the first line positive display voltage value 2111a is 110. Similarly, the positive voltage value 2111b of the second line corresponds to V2(0)~V2(2), which corresponds to the second voltage V2. For example, as shown in Figure 22, the positive voltage value 2111b of the second line is 010. The negative voltage data 2112 of the first line includes a negative voltage value 2112a of the first line and a negative voltage value 2112b of the second line. The negative voltage value 2112a of the first line corresponds to V3(0)~V3(2), which corresponds to the third voltage V3. For example, as shown in Figure 22, the negative voltage value 2112a of the first line is 011. The negative voltage value 2112b of the second line corresponds to V5(0)~V5(2), which corresponds to the fifth voltage V5. For example, as shown in Figure 22, the negative voltage value 2112b of the second line is 101.

[0094] Please refer to Figures 21A and 21B. The scan display waveform data 212 includes a plurality of line electrode display data, such as the first to m-th line electrode display data 2121 to 212m. These line electrode display data include at least one first line electrode display data 2121, which contains the type of line drive signal waveform for the first line electrode. The second line electrode display data 2122 contains the type of line drive signal waveform for the second line electrode. In this embodiment, the first line electrode display data is the value of the first to third scan output terminals (scan 0 to scan 5), for example, as shown in Figure 22, the first line electrode display data 2121 is 111. Similarly, the second line electrode display data is the value of the first to third scan output terminals (scan 0 to scan 5), for example, as shown in Figure 22, the second line electrode display data 2122 is 000.

[0095] Referring again to Figures 23A to 23C, the driving circuit unit 20 determines the signal waveform of a first line drive signal 2001 output to the first line electrode based on the first line electrode display data 2121. For example, if the first line electrode display data 2121 is 111, the driving circuit unit 20 determines the signal waveform of the first line drive signal 2001 output to the first line electrode based on the first line electrode display data 2121, which is to first output the sixth voltage V6, then output the third voltage V3, and the output duration of the sixth voltage V6 is 1:1 with the output duration of the third voltage V3. For example, the waveform of the first line drive signal 2001 output by the drive circuit unit 20 to the first line electrode is shown in Figure 23A. That is, the drive circuit unit 20 outputs the line drive signal with the sixth voltage V6 to the first line electrode between the first to the seventh count signals 102 output by the digital-to-analog conversion control port (d2a), and outputs the line drive signal with the third voltage V3 to the first line electrode between the eighth to the fourteenth count signals 102 output by the digital-to-analog conversion control port (d2a).

[0096] Furthermore, the drive circuit unit 20 determines the waveform of a second line drive signal 2002 output to the second line electrode based on the second line electrode display data 2122. For example, if the second line electrode display data 2122 is 000, the drive circuit unit 20 determines the waveform of the second line drive signal 2002 output to the second line electrode based on the second line electrode display data 2122, which is to first output the second voltage V2 and then output the fifth voltage V5, and the output duration ratio of the second voltage V2 and the fifth voltage V5 is 1:1. For example, the waveform of the second line drive signal 2002 output by the drive circuit unit 20 to the second line electrode is shown in Figure 23B. That is, the drive circuit unit 20 outputs the line drive signal with the second voltage V2 to the second line electrode between the first to the seventh count signals 102 output by the digital-to-analog conversion control port (d2a), and outputs the line drive signal with the fifth voltage V5 to the second line electrode between the eighth to the fourteenth count signals 102 output by the digital-to-analog conversion control port (d2a).

[0097] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical display to create equivalent embodiments without departing from the scope of the technical solution of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the display of the technical solution of the present invention shall still fall within the scope of the technical solution of the present invention.

[0098] 10: Timing control circuit unit 101: Header Setting Signal 102: Counting signal 11: Data Signal 110: Blank data 111: Pixel static display header data 1111: Pixel displays voltage data. 1111a: The first pixel displays the voltage value. 1111b: The second pixel displays the voltage value. 1112: Pixel negative display voltage data 1112a: Negative display voltage value for the first pixel 1112b: Second pixel negative display voltage value 112: Pixel static display of waveform data 1121~112n: Display data of the first to nth pixel electrodes 113: Pixel Clear Header Data 1131: Pixel positive clear voltage data 1131a: First pixel positive clear voltage value 1131b: Second pixel positive clear voltage value 1132: Pixel negative clear voltage data 114: Pixel clear waveform data 1141~114n: Electrode clearing data for the first to nth pixels 115: Pixel ULH header data 116: Pixel ULH waveform data; clk: Clock output port doe: Display output enable control port dog: Display output ground control port d2a: Digital-to-Analog Conversion Control Port DSP: Display Start Signal Control Port dsh: Header setting control port data 0~data n: First to n+1 data output terminals data [2:0]: First to third data output terminals scan 0~scan n: First to (n+1)th scan output terminals scan [2:0]: First to third scan output terminals 20: Drive circuit unit 201: First pixel display driver signal 202: Second pixel display driver signal 21: Scanning signal 211: Line static display header data 2111: The line is displaying voltage data. 2111a: The first line is displaying the voltage value. 2111b: The second line is displaying the voltage value. 2112: Line negative display voltage data 2112a: First line negative display voltage value 2112b: Second line negative display voltage value 212: Scan to display waveform data 2121~212m: Electrode display data for lines 1 to m 2001: First line drive signal 2002: Second line drive signal 30: Panel unit

Claims

1. A static display driver for a multistable display, comprising: a timing control circuit unit for generating a timing control signal; a driving circuit unit connected to the timing control circuit unit and receiving the timing control signal; and a panel unit connected to the driving circuit unit; wherein, The timing control signal includes a data signal, and the data signal includes a pixel static display header data and a pixel static display waveform data; wherein, the driving circuit unit determines a pixel display voltage value of the pixel display driving signal output to the panel unit based on the pixel static display header data, and the driving circuit unit determines a pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data.

2. A static display driver for a multistable display as described in claim 1, wherein, The data signal also includes pixel clear header data; wherein, the driving circuit unit determines the pixel clear driving signal to be output to the panel unit based on the pixel clear header data.

3. A static display driver for a multistable display as described in claim 1, wherein, The data signal also includes one pixel clear header data and one pixel uniform Lying Helix (ULH) header data; wherein, the driving circuit unit determines the one pixel clear driving signal output to the panel unit based on the pixel clear header data, and the driving circuit unit determines the one pixel ULH driving signal output to the panel unit based on the pixel ULH header data.

4. A static display driver for a multistable display as described in claim 1, wherein, The data signal also includes pixel clear header data and pixel clear waveform data; wherein, the driving circuit unit determines the pixel clear voltage value of the pixel clear driving signal output to the panel unit based on the pixel clear header data, and the driving circuit unit determines the pixel clear driving duration of the pixel clear driving signal with the pixel clear voltage value based on the pixel clear waveform data.

5. A static display driver for a multistable display as described in claim 1, wherein, The data signal also includes pixel clear header data, pixel clear waveform data, pixel ULH header data, and pixel ULH waveform data; wherein, the driving circuit unit determines the pixel clear voltage value of the pixel clear driving signal output to the panel unit based on the pixel clear header data, and the driving circuit unit determines the pixel clear driving duration of the pixel clear driving signal with the pixel clear voltage value based on the pixel clear waveform data; wherein, the driving circuit unit determines the pixel ULH voltage value of the pixel ULH driving signal output to the panel unit based on the pixel ULH header data, and the driving circuit unit determines the pixel ULH driving duration of the pixel ULH driving signal with the pixel ULH voltage value based on the pixel ULH waveform data.

6. A static display driver for a multistable display as described in claim 1, wherein, The timing control circuit unit includes: a header setting control port connected to the drive circuit unit, which outputs a header setting signal to the drive circuit unit; and a data signal output port connected to the drive circuit unit, which outputs the data signal to the drive circuit unit; wherein, when the data signal output by the data signal output port is the static display header data of the pixel, the header setting signal output by the header setting control port is a high voltage level.

7. A static display driver for a multistable display as described in claim 4 or 5, wherein, The pixel clearing header data includes a positive clearing voltage data for one pixel and a negative clearing voltage data for one pixel; wherein, the positive clearing voltage data includes a first positive clearing voltage value for one pixel and a second positive clearing voltage value for one pixel, and the negative clearing voltage data includes a first negative clearing voltage value for one pixel and a second negative clearing voltage value for one pixel; wherein, the pixel clearing waveform data packet contains a plurality of pixel electrode clearing data; wherein, the pixel electrode clearing data includes at least one first pixel electrode clearing data, and the first pixel electrode clearing data includes a first clearing voltage unit; wherein, the driving circuit unit has a total number of working states, and the driving circuit unit subtracts the first clearing voltage unit from the total number of working states to determine a first remaining number of clearing voltage units; Specifically, when the driving circuit unit determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the pixel clearing waveform data, the driving circuit unit determines a first clearing duration for outputting the pixel clearing drive signal with the first pixel positive clearing voltage value to a first pixel electrode based on the first clearing voltage units of the pixel clearing waveform data; the driving circuit unit determines a second clearing duration for outputting the pixel clearing drive signal with the second pixel positive clearing voltage value to the first pixel electrode based on the first remaining clearing voltage units; the driving circuit unit determines a third clearing duration for outputting the pixel clearing drive signal with the first pixel negative clearing voltage value to the first pixel electrode based on the first clearing voltage units of the pixel clearing waveform data; and the driving circuit unit determines a fourth clearing duration for outputting the pixel clearing drive signal with the second pixel negative clearing voltage value to the first pixel electrode based on the first remaining clearing voltage units.

8. A static display driver for a multistable display as described in any one of claims 1 to 6, wherein, The pixel static display header data includes positive display voltage data for one pixel and negative display voltage data for one pixel; wherein, the positive display voltage data includes a first positive display voltage value for one pixel and a second positive display voltage value for one pixel, and the negative display voltage data includes a first negative display voltage value for one pixel and a second negative display voltage value for one pixel; wherein, the pixel static display waveform data packet contains a plurality of pixel electrode display data; wherein, the pixel electrode display data includes at least one first pixel electrode display data, and the first pixel electrode display data includes a first display voltage unit number; wherein, the driving circuit unit has a total number of working states, and the driving circuit unit subtracts the first display voltage unit number from the total number of working states to determine a first remaining display voltage unit number; Specifically, when the driving circuit unit determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data, the driving circuit unit determines a first display duration for outputting the pixel display driving signal with the positive display voltage value of the first pixel to a first pixel electrode based on the first number of display voltage units in the pixel static display waveform data, a second display duration for outputting the pixel display driving signal with the positive display voltage value of the second pixel to the first pixel electrode based on the first remaining number of display voltage units, a third display duration for outputting the pixel display driving signal with the negative display voltage value of the first pixel to the first pixel electrode based on the first number of display voltage units in the pixel static display waveform data, and a fourth display duration for outputting the pixel display driving signal with the negative display voltage value of the second pixel to the first pixel electrode based on the first remaining number of display voltage units.

9. A static display driver for a multistable display as described in claim 4 or 5, wherein, The timing control circuit unit further includes: a digital-to-analog conversion control port connected to the drive circuit unit, outputting a conversion control signal to the drive circuit unit, and the conversion control signal including a plurality of count signals; wherein the drive circuit unit has a total working count; wherein the pixel clearing header data includes a pixel positive clearing voltage data and a pixel negative clearing voltage data; wherein the pixel positive clearing voltage data includes a first pixel positive clearing voltage value and a second pixel positive clearing voltage value, and the pixel negative clearing voltage data includes a first pixel negative clearing voltage value and a second pixel negative clearing voltage value; wherein the pixel clearing waveform data packet contains a plurality of pixel electrode clearing data; wherein the pixel electrode clearing data includes at least a first pixel electrode clearing data, and the first pixel electrode clearing data includes a first clearing voltage unit number; Specifically, when the driving circuit unit determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the pixel clearing waveform data, the driving circuit unit outputs the pixel clearing drive signal with the first positive pixel clearing voltage value to a first pixel electrode between the first to the Ath count signals output from the digital-to-analog conversion control port, and outputs the pixel clearing drive signal with the second positive pixel clearing voltage value to the first pixel electrode between the (A+1)th to the Bth count signals output from the digital-to-analog conversion control port, and outputs the pixel clearing drive signal with the first negative pixel clearing voltage value to the first pixel electrode between the (B+1)th to the (A+B)th count signals output from the digital-to-analog conversion control port, and outputs the pixel clearing drive signal with the second negative pixel clearing voltage value to the first pixel electrode between the (A+B+1)th to the 2Bth count signals output from the digital-to-analog conversion control port; Where A is the number of the first clear voltage units, and B is the total number of operations.

10. A static display driver for a multistable display as described in any one of claims 1 to 6, wherein, The timing control circuit unit further includes: a digital-to-analog conversion control port connected to the drive circuit unit, outputting a conversion control signal to the drive circuit unit, and the conversion control signal including a complex counting signal; wherein the drive circuit unit has a total working count; wherein the pixel static display header data includes a pixel positive display voltage data and a pixel negative display voltage data; wherein the pixel positive display voltage data includes a first pixel positive display voltage value and a second pixel positive display voltage value, and the pixel negative display voltage data includes a first pixel negative display voltage value and a second pixel negative display voltage value; wherein the pixel static display waveform data packet contains a plurality of pixel electrode display data; wherein the pixel electrode display data includes at least a first pixel electrode display data, and the first pixel electrode display data includes a first display voltage unit count; Specifically, when the driving circuit unit determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the pixel static display waveform data, the driving circuit unit outputs the pixel display driving signal with the first pixel positive display voltage value to a first pixel electrode between the first to Cth count signals output from the digital-to-analog conversion control port, and the driving circuit unit outputs the second pixel display driving signal with the second pixel positive display voltage value between the (C+1)th to Bth count signals output from the digital-to-analog conversion control port. The driving circuit unit outputs a pixel display driving signal with a negative display voltage value to the first pixel electrode between the (B+1)th and (B+C)th count signals output from the digital-to-analog conversion control port, and outputs a pixel display driving signal with a negative display voltage value to the first pixel electrode between the (B+C+1)th and (2B)th count signals output from the digital-to-analog conversion control port, and outputs a pixel display driving signal with a negative display voltage value to the first pixel electrode between the (B+C+1)th and (2B)th count signals output from the digital-to-analog conversion control port; wherein, C is the number of units of the first display voltage, and B is the total number of working units.

11. A static display driver for a multistable display as described in claim 1, wherein, The timing control signal includes a scan signal, and the scan signal includes line static display header data and line static display waveform data; wherein, the drive circuit unit determines a line drive voltage value of a line drive signal output to the panel unit based on the line static display header data, and the drive circuit unit determines a signal waveform of the line drive signal output to the panel unit based on the line drive voltage value and the line static display waveform data.

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