Memory device and method of operation thereof

TW202642517APending Publication Date: 2026-10-16SAMSUNG ELECTRONICS CO LTD
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Patent Information

Application Number
TW115105063
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-04-04
Filing Date
2026-02-09
Publication Date
2026-10-16

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    Figure TWG2TA001081096_002
  • Figure TWG2TA001081096_003
    Figure TWG2TA001081096_003
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Abstract

Provided is a memory device including a first sense amplification circuit connected to a first input and output line pair, a pre-charge circuit connected to a second input and output line pair, and a first switch circuit, wherein the pre-charge circuit is configured to pre-charge the second input and output line pair at a pre-charge voltage after the first switch circuit disconnects the first input and output line pair from the second input and output line pair, and wherein the first switch circuit is configured to connect the first input and output line pair and the second input and output line pair to deliver a voltage of the first input and output line pair, which is amplified by the first sense amplification circuit, to the pre-charged second input and output line pair in a read operation.
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