Memory apparatus

Abstract

A memory apparatus is provided. A first selecting circuit selectively connects a first global word line decoder to part of first global word lines according to a selected even memory block. A second selecting circuit transmits first global word line selection signals to the selected even memory block in accordance with the selected even memory block. A third selecting circuit selectively connects a second global word line decoder to part of second global word lines according to a selected odd memory block. A fourth selecting circuit transmits second global word line selection signals to the selected odd memory block in accordance with the selected odd memory block.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a memory device. Prior Technology

[0002] With the rapid development of semiconductor technology, memory capacity is increasing daily, and the word line length in memory cell arrays is also increasing accordingly. However, longer word lines lead to higher capacitive loads, requiring a corresponding increase in drive current. This results in a larger area of ​​the charge pump circuit and increased current consumption, which is detrimental to energy conservation and carbon reduction. Summary of the Invention

[0003] The present invention provides a memory device that can effectively reduce the high capacitive load caused by long word lines, and avoid increasing the area and current consumption of the charge pump circuit.

[0004] The memory device of the present invention includes a memory cell array, an even-numbered column decoder circuit, and an odd-numbered column decoder circuit. The memory cell array includes a plurality of even-numbered memory blocks and a plurality of odd-numbered memory blocks. The even-numbered column decoder circuit is coupled to the memory cell array and includes a first global character line decoder, a first selection circuit, and a second selection circuit. The first global character line decoder provides a plurality of first global character line selection signals. The first selection circuit is coupled to the first global character line decoder and the plurality of first global character lines, and selects and connects the first global character line decoder to a portion of the first global character lines according to the selected even-numbered memory block. The second selection circuit is coupled to the plurality of first global character lines and the plurality of even-numbered memory blocks, and transmits the plurality of first global character line selection signals to the selected even-numbered memory block according to the selected even-numbered memory block. The odd-numbered column decoder circuit is coupled to the memory cell array and includes a second global character line decoder, a second selection circuit, and a third selection circuit. The second global character line decoder provides multiple second global character line selection signals. A third selection circuit is coupled to the second global character line decoder and the multiple second global character lines, and selects a portion of the second global character lines to be connected to the second global character lines based on the selected odd-numbered memory blocks. A fourth selection circuit is coupled to the aforementioned multiple second global character lines and the aforementioned multiple odd-numbered memory blocks, and transmits the aforementioned multiple second global character line selection signals to the selected odd-numbered memory blocks.

[0005] In one embodiment of the present invention, the memory device described above is a NAND memory device. Based on the above, in this embodiment of the present invention, the first selection circuit selects and connects the first global character line decoder to a portion of the first global character lines based on the selected even-numbered memory blocks; the second selection circuit transmits the first global character line selection signal to the selected even-numbered memory blocks based on the selected even-numbered memory blocks; the third selection circuit selects and connects the second global character line decoder to a portion of the second global character lines based on the selected odd-numbered memory blocks; and the fourth selection circuit transmits the second global character line selection signal to the selected odd-numbered memory blocks based on the selected odd-numbered memory blocks. By selecting and connecting the global character line decoder to a portion of the global character lines based on the selected memory blocks, the length of the global character lines can be shortened, and the number of character line decoders connected to the global character line decoder can be reduced, effectively avoiding increasing the area and current consumption of the charge pump circuit. Simple Explanation of the Diagram

[0006] Figures 1 and 2 are schematic diagrams of memory devices according to embodiments of the present invention. Figure 3 is a schematic diagram of a transmission circuit according to an embodiment of the present invention. Figures 4 and 5 are schematic diagrams of a memory device according to another embodiment of the present invention. Implementation

[0007] To make the contents of this invention more readily apparent, the following specific embodiments are provided as examples on which this invention can indeed be implemented. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts.

[0008] Please refer to Figure 1 below. Figure 1 is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 100 may be, for example, a NAND memory device, which includes a memory cell array 102, an even-numbered column decoder circuit 104, and an odd-numbered column decoder circuit 106. The memory cell array 102 is coupled to the even-numbered column decoder circuit 104 and the odd-numbered column decoder circuit 106. The memory cell array 102 may include multiple memory blocks MB, and the memory blocks MB may include, for example, NAND strings. The even-numbered column decoder circuit 104 can decode the column address and select the corresponding even-numbered memory blocks among the multiple memory blocks MB for reading or writing data. Similarly, the odd-numbered column decoder circuit 106 can decode the column address and select the corresponding odd-numbered memory blocks among the multiple memory blocks MB for reading or writing data.

[0009] Furthermore, in the embodiment of FIG1, the memory cell array 102 may, for example, include 2048 memory blocks MB. The even-numbered column decoder circuit 104, as shown in FIG1, includes a first global character line decoder GWLDR1, a first selection circuit 108, and a second selection circuit 110. The first selection circuit 108 is coupled to the first global character line decoder GWLDR1 and coupled to the second selection circuit 110 through the first global character line EGWL1 and EGWL2. The second selection circuit 110 is also coupled to the even-numbered memory blocks in the memory cell array 102. The first global character line EGWL1 may, for example, be used to couple 512 of the 1024 even-numbered memory blocks, while the first global character line EGWL2 is used to couple the remaining 512 even-numbered memory blocks out of the 1024 even-numbered memory blocks. The first global character line decoder GWLDR1 can be coupled to a portion of the even-numbered memory blocks in the memory cell array 102 via the first selection circuit 108, the first global character line EGWL1, and the second selection circuit 110, and can also be coupled to another portion of the even-numbered memory blocks in the memory cell array 102 via the first selection circuit 108, the first global character line EGWL2, and the second selection circuit 110.

[0010] Similarly, the odd-numbered column decoder circuit 106 may include a second global character line decoder GWLDR2, a third selection circuit 112, and a fourth selection circuit 114. The second selection circuit 110 is coupled to the second global character line decoder GWLDR2 and is coupled to the fourth selection circuit 114 via second global character lines OGWL1 and OGWL2. The fourth selection circuit 114 is also coupled to the odd-numbered memory blocks in the memory cell array 102. The second global character line OGWL1 may, for example, be used to couple 512 of the 1024 odd-numbered memory blocks, while the second global character line OGWL2 is used to couple the remaining 512 odd-numbered memory blocks out of the 1024 odd-numbered memory blocks. The second global character line decoder GWLDR2 can be coupled to a portion of the odd-numbered memory blocks in the memory cell array 102 via the third selection circuit 112, the second global character line OGWL1, and the fourth selection circuit 114, and can also be coupled to another portion of the odd-numbered memory blocks in the memory cell array 102 via the third selection circuit 112, the second global character line OGWL2, and the fourth selection circuit 114.

[0011] The first selection circuit 108 can connect the first global character line decoder GWLDR1 to the first global character line corresponding to the selected even-numbered memory block according to the selected even-numbered memory block, so as to transmit the first global character line selection signal EGWL[31:0] to the selected even-numbered memory block. For example, in the embodiment of FIG1, if the selected even-numbered memory block corresponds to the first global character line EGWL1, the first selection circuit 108 can connect the first global character line decoder GWLDR1 to the first global character line EGWL1 according to the selected even-numbered memory block, and the second selection circuit 110 will transmit the first global character line selection signal EGWL[31:0] from the first global character line EGWL1 to the selected even-numbered memory block according to the selected even-numbered memory block.

[0012] Similarly, the third selection circuit 112 can connect the second global character line decoder GWLDR2 to the second global character line corresponding to the selected odd memory block based on the selected odd memory block, so as to transmit the second global character line selection signal OGWL[31:0] to the selected odd memory block. For example, if the selected odd memory block corresponds to the second global character line OGWL1, the third selection circuit 112 can connect the second global character line decoder GWLDR2 to the second global character line OGWL1 based on the selected odd memory block, and the fourth selection circuit 114 transmits the second global character line selection signal OGWL[31:0] from the second global character line OGWL1 to the selected odd memory block based on the selected odd memory block.

[0013] By selectively connecting the first global character line decoder GWLDR1 to a portion of the first global character lines (for example, as shown in the previous embodiment, connecting the first global character line decoder GWLDR1 to the first global character line EGWL1 corresponding to the selected even-numbered memory block, but not to the first global character line EGWL2), the length of the first global character lines can be effectively shortened, and the number of circuit elements connected to the first global character line decoder GWLDR1 when driving the selected even-numbered memory blocks (e.g., the number of unselected character line decoders) can be reduced. Furthermore, the number of memory blocks connected to the first global character line decoder GWLDR1 can be reduced, thereby significantly reducing the capacitive load of the global character lines and effectively avoiding increasing the area and current consumption of the charge pump circuit used to drive the even-numbered column decoder circuit 104. Similarly, selectively connecting the second global character line decoder GWLDR2 to a portion of the second global character lines can also effectively avoid increasing the area and current consumption of the charge pump circuit used to drive the odd-numbered column decoder circuit 106.

[0014] Furthermore, the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 can be implemented, for example, as multiple transmission circuits. For example, as shown in FIG2, the first selection circuit 108 may include two first transmission circuits BK0[0] and BK0[2], the second selection circuit 110 may include 1024 second transmission circuits BK1[0] to BK1

[2046] , the third selection circuit 112 may include two fourth transmission circuits BK0[1] and BK0[3], and the fourth selection circuit 114 may include 1024 fifth transmission circuits BK1[1] to BK1

[2047] . The first transmission circuit BK0[0] is coupled to the first global character line decoder GWLDR1 and the corresponding first global character line EGWL1, the first transmission circuit BK0[2] is coupled to the first global character line decoder GWLDR1 and the corresponding first global character line EGWL2, the second transmission circuits BK1[0]~BK1

[1022] are respectively coupled to the corresponding first transmission circuit BK0[0] and the corresponding even-numbered memory block, and the second transmission circuits BK1

[1024] ~BK1

[2046] are respectively coupled to the corresponding first transmission circuit BK0[2] and the corresponding even-numbered memory block.

[0015] Similarly, the fourth transmission circuit BK0[1] is coupled to the second global character line decoder GWLDR2 and the corresponding second global character line OGWL1, the fourth transmission circuit BK0[3] is coupled to the second global character line decoder GWLDR2 and the corresponding second global character line OGWL2, the fifth transmission circuits BK1[1]~BK1

[1023] are respectively coupled to the corresponding fourth transmission circuit BK0[1] and the corresponding odd memory block, and the fifth transmission circuits BK1

[1025] ~BK1

[2047] are respectively coupled to the corresponding fourth transmission circuit BK0[3] and the corresponding even memory block.

[0016] The first transmission circuits BK0[0] and BK0[2] can transmit the first global character line selection signal EGWL[31:0] to a portion of the first global character lines (e.g., first global character lines EGWL1 or EGWL2) according to the selected even-numbered memory blocks. The second transmission circuits BK1[0] to BK1

[2046] can transmit the first global character line selection signal EGWL[31:0] to the selected even-numbered memory blocks according to the selected even-numbered memory blocks. The third transmission circuits BK0[1] and BK0[3] can transmit the second global character line selection signal OGWL[31:0] to a portion of the second global character lines (e.g., second global character lines OGWL1 or OGWL2) according to the selected odd-numbered memory blocks. The fourth transmission circuit BK1[1]~BK1

[2047] can transmit the second global character line selection signal OGWL[31:0] to the selected odd memory block according to the selected odd memory block.

[0017] In detail, the first transmission circuits BK0[0], BK0[2], the second transmission circuits BK1[0]~BK1

[2046] , the fourth transmission circuits BK0[1], BK0[3], and the fifth transmission circuits BK1[1]~BK1

[2047] may each include a block decoder and a character line decoder, wherein the character line decoder may include multiple transistors. For example, as shown in Figure 3, taking the second transmission circuit BK1[0] as an example, it includes a block decoder EBD1[0] and a character line decoder WLD1[0]. The character line decoder WLD1[0] includes 32 transistors, each transistor is coupled between the corresponding first global character line and the corresponding local character line, and the control terminal of each transistor is coupled to the block decoder EBD1[0]. When the second transmission circuit BK1[0] is coupled to the selected even-numbered memory blocks, each transistor can be controlled by the block decoder EBD1[0] to provide the first global character line selection signal EGWL[0]~EGWL

[31] as the local character line selection signal WL[0]~WL

[31] to the selected even-numbered memory blocks. When the second transmission circuit BK1[0] is coupled to the unselected even-numbered memory blocks, each transistor is controlled by the block decoder EBD1[0] and is in the off state.

[0018] Similarly, taking the first transmission circuit BK0[0] as an example, each transistor in the first transmission circuit BK0[0] is coupled between the first global character line decoder GWLDR1 and the corresponding first global character line EGWL1, and the conduction state of each transistor is controlled by the corresponding block decoder. When the first transmission circuit BK0[0] is coupled to the selected even-numbered memory blocks, each transistor can be controlled by the corresponding block decoder to transmit the first global character line selection signal EGWL[31:0] to the first global character line EGWL1, while when the first transmission circuit BK0[0] is coupled to the unselected even-numbered memory blocks, each transistor is controlled by the corresponding block decoder and is in the off state. The implementation methods of the first transmission circuit BK0[2], the fourth transmission circuit BK0[1], and BK0[3] are similar to those of the first transmission circuit BK0[0]. The implementation methods of the second transmission circuit BK1[2]~BK1

[2046] and the fifth transmission circuit BK1[1]~BK1

[2047] are similar to those of the second transmission circuit BK1[0], and will not be described again here.

[0019] It is worth noting that in other embodiments, the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 may include more transmission circuits, and are not limited to the above embodiments. As shown in Figures 4 and 5 (to ensure the readability of the diagrams, the implementation details of the even-numbered column decoder circuit 104 and the odd-numbered column decoder circuit 106 are shown in Figures 4 and 5 respectively), the first selection circuit 108 may include 4 first transmission circuits BK0[0]~BK0[6], and the second selection circuit 110 may include 32 second transmission circuits BK1[0]~BK1

[62] and 1024 third transmission circuits BK2[0]~BK2

[2046] , wherein each first transmission circuit is coupled to the corresponding 8 second transmission circuits, and each second transmission circuit is coupled to the corresponding 32 third transmission circuits. For example, the first transmission circuit BK0[0] is coupled to the second transmission circuits BK1[0]~BK1

[14] , the first transmission circuit BK0[2] is coupled to the second transmission circuits BK1

[16] ~BK1

[30] ,..., the first transmission circuit BK0[6] is coupled to the second transmission circuits BK1

[48] ~BK1

[62] . The second transmission circuit BK1[0] is coupled to the third transmission circuits BK2[0]~BK2

[62] , the second transmission circuit BK1[2] is coupled to the third transmission circuits BK2

[64] ~BK2

[0126] ,..., and so on.

[0020] The first transmission circuit BK0[0]~BK0[6], the second transmission circuit BK1[0]~BK1

[62] , and the third transmission circuit BK2[0]~BK2

[2046] of this embodiment can also be implemented in the manner of the embodiment in Figure 3. In this embodiment, the transistors in the first transmission circuit BK0[0]~BK0[6] are coupled between the first global character line decoder GWLDR1 and the corresponding first global character lines EGWL1~EGWL4, the transistors in the second transmission circuit BK1[0]~BK1

[62] are coupled between the corresponding first global character lines EGWL1~EGWL4 and the corresponding third global character lines PGWL1~PGWL32, and the transistors in the third transmission circuit BK2[0]~BK2

[2046] are coupled between the corresponding third global character lines PGWL1~PGWL32 and the corresponding even-numbered memory blocks.

[0021] Similar to the embodiment in Figure 2, the first transmission circuits BK0[0] to BK0[6] can transmit the first global character line selection signal EGWL[31:0] to a portion of the first global character lines (e.g., one of the first global character lines EGWL1 to EGWL4) according to the selected even-numbered memory blocks. The second transmission circuits BK1[0] to BK1

[31] can transmit the first global character line selection signal EGWL[31:0] to a portion of the third global character lines (e.g., one of the third global character lines PGWL1 to PGWL32) according to the selected even-numbered memory blocks. The third transmission circuits BK2[0] to BK2

[1023] can transmit the first global character line selection signal EGWL[31:0] to the selected even-numbered memory blocks according to the selected even-numbered memory blocks.

[0022] For example, if the selected even-numbered memory block is coupled to the third transmission circuit BK2[0], since the third transmission circuit BK2[0] is coupled to the second transmission circuit BK1[0] through the third global character line PGWL1, and the second transmission circuit BK1[0] is coupled to the first global character line decoder GWLDR1 through the first global character line EGWL1, that is, the selected even-numbered memory block is corresponding to the first global character line EGWL1 and the third global character line PGWL1. The first transmission circuit BK0[0] can transmit the first global character line selection signal EGWL[31:0] to the first global character line EGWL1 according to the selected even-numbered memory block. The second transmission circuit BK1[0] can transmit the first global character line selection signal EGWL[31:0] to the third global character line PGWL1 according to the selected even-numbered memory block. The third transmission circuit BK2[0] then transmits the first global character line selection signal EGWL[31:0] to the selected even-numbered memory block. While the third transmission circuit BK2[0] transmits the first global character line selection signal EGWL[31:0] to the selected even-numbered memory block, the third transmission circuit BK2[2]~BK2

[2046] , the second transmission circuit BK1[2]~BK1

[62] and the first transmission circuit BK0[2]~BK0[6] are unable to transmit the first global character line selection signal EGWL[31:0], that is, the transistors in the third transmission circuit BK2[2]~BK2

[2046] , the second transmission circuit BK1[2]~BK1

[62] and the first transmission circuit BK0[2]~BK0[6] are in an off state.

[0023] Compared to the embodiment in Figure 2, this embodiment further reduces the number of circuit elements connected to the first global character line decoder GWLDR1 when driving the selected even-number memory blocks (the number of unselected character line decoders), which can further reduce the capacitive load of the global character lines and reduce the area and current consumption of the charge pump circuit used to drive the even-number column decoder circuit 104.

[0024] Similarly, the implementation of the third selection circuit 112 and the fourth selection circuit 114 can be shown in Figure 5. The third selection circuit 112 and the fourth selection circuit 114 can be connected through the second global character lines OGWL1~OGWL4. The third selection circuit 112 may include four fourth transmission circuits BK0[1]~BK0[7], and the fourth selection circuit 114 may include 32 fifth transmission circuits BK1[1]~BK1

[63] and 1024 sixth transmission circuits BK2[1]~BK2

[2047] . The fifth transmission circuits BK1[1]~BK1

[63] and the sixth transmission circuits BK2[1]~BK2

[2047] can be connected through the fourth global character lines PGWL33~PGWL64. Since the odd-numbered column decoder circuit 106 and the even-numbered column decoder circuit 104 are symmetrical circuit structures, those skilled in the art should be able to deduce the detailed implementation of the odd-numbered column decoder circuit 106 from the above embodiments, which will not be repeated here.

[0025] It is worth noting that, in other embodiments, the number of transmission circuits in the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 is not limited to the above embodiments. By increasing the number of transmission circuits in the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 in the manner described in the above embodiments, the number of circuit elements connected to the first global character line decoder GWLDR1 when driving the selected even-numbered memory blocks can be reduced, which can effectively and significantly reduce the capacitive load of the global character line and reduce the area and current consumption of the charge pump circuit used to drive the even-numbered column decoder circuit 104.

[0026] It should also be noted that, for the sake of simplicity, only one of each of the following four global character lines (EGWL1~EGWL4, OGWL1~OGWL4, PGWL1~PGWL32, and PGWL33~PGWL64) is shown in the examples of Figures 1, 2, 4, and 5 as a representative example. In reality, the number of each of these four global character lines is 32. In other embodiments, the number of the first global character lines EGWL1~EGWL4, the second global character lines OGWL1~OGWL4, the third global character lines PGWL1~PGWL32, and the fourth global character lines PGWL33~PGWL64 are each the same as the number of local character lines in a memory block.

[0027] In summary, the first selection circuit of this embodiment selects and connects the first global character line decoder to a portion of the first global character lines based on the selected even-numbered memory blocks; the second selection circuit transmits the first global character line selection signal to the selected even-numbered memory blocks based on the selected even-numbered memory blocks; the third selection circuit selects and connects the second global character line decoder to a portion of the second global character lines based on the selected odd-numbered memory blocks; and the fourth selection circuit transmits the second global character line selection signal to the selected odd-numbered memory blocks based on the selected odd-numbered memory blocks. This shortens the length of the global character lines and reduces the number of character line decoders connected to the global character line decoder, effectively avoiding increasing the area and current consumption of the charge pump circuit.

[0028] 100: Memory Device 102: Memory Cell Array 104: Even-numbered column decoder circuit 106: Odd-numbered column decoder circuit 108: First Selection Circuit 110: Second selection circuit 112: Third Selection Circuit 114: Fourth Selection Circuit GWLDR1: First Global Line Decoder GWLDR2: Second Global Line Decoder EGWL1~EGWL4: First global character line OGWL1~OGWL4: Second global character line PGWL1~PGWL32: Third global character line PGWL33~PGWL64: Fourth Global Character Line MB: Memory Block EGWL[31:0], EGWL[0]~EGWL

[31] : First global character line selection signal OGWL[31:0]: Second global character line selection signal WL[0]~WL

[31] : Local character line selection signal BK0[0], BK0[2], BK0[4], BK0[6]: First transmission circuit BK1[0], BK1[2]...BK1

[2046] : Second transmission circuit BK2[0], BK2[2]...BK2

[2046] : Third transmission circuit BK0[1], BK0[3], BK0[5], BK0[7]: Fourth transmission circuit BK1[1], BK1[3]...BK1

[2047] : Fifth transmission circuit BK2[1], BK2[3]...BK2

[2047] : Sixth transmission circuit EBD1[0]: Block decoder WLD1[0]: Character Line Decoder

Claims

1. A memory device, comprising: A memory cell array, comprising multiple even-numbered memory blocks and multiple odd-numbered memory blocks; An even-numbered column decoder circuit coupled to the memory cell array includes: a first global character line decoder providing a plurality of first global character line selection signals; a first selection circuit coupled to the first global character line decoder and the plurality of first global character lines, selectively connecting the first global character line decoder to a portion of the first global character lines based on a selected even-numbered memory block; and a second selection circuit coupled to the first global character lines and the even-numbered memory blocks, transmitting the first global character line selection signals to the selected even-numbered memory block based on the selected even-numbered memory block; and an odd-numbered column decoder circuit coupled to the memory cell array includes: a second global character line decoder providing a plurality of second global character line selection signals; A third selection circuit, coupled to the second global character line decoder and multiple second global character lines, selects and connects the second global character line decoder to a portion of the second global character lines based on the selected odd-numbered memory blocks; and a fourth selection circuit, coupled to the second global character lines and the odd-numbered memory blocks, transmits the second global character line selection signals to the selected odd-numbered memory blocks based on the selected odd-numbered memory blocks, wherein the first selection circuit includes: multiple first transmission circuits, respectively coupled to the first global character line decoder and corresponding first global character lines, transmitting the first global character line selection signals to the selected even-numbered memory blocks based on the selected even-numbered memory blocks.

2. The memory device as claimed in claim 1, wherein the second selection circuitry includes: Multiple second transmission circuits are respectively coupled between the corresponding first transmission circuit and the corresponding even-numbered memory blocks, and transmit the first global character line selection signals according to the selected even-numbered memory block, so as to transmit the first global character line selection signals to the selected even-numbered memory block.

3. The memory device as claimed in claim 2, wherein the second selection circuitry further comprises: Multiple third transmission circuits are respectively coupled between the corresponding second transmission circuit and the corresponding even-numbered memory blocks, and transmit the first global character line selection signals according to the selected even-numbered memory block, so as to transmit the first global character line selection signals to the selected even-numbered memory block.

4. The memory device according to any one of claims 2 to 3, wherein each of the first transmission circuits, each of the second transmission circuits, and each of the third transmission circuits comprises: One-block decoder; And a word-line decoder, controlled by the block decoder to transmit the first global word-line selection signals to the selected even-numbered memory block.

5. The memory device as claimed in claim 4, wherein each first character line decoder includes: Multiple first transistors, the control terminals of which are coupled to the even-numbered block decoder, the conduction state of which is controlled by the even-numbered block decoder to transmit the first global character line selection signals.

6. The memory device as claimed in claim 1, wherein the third selection circuitry includes: Multiple fourth transmission circuits are respectively coupled to the second global character line decoder and the corresponding second global character line, and transmit the second global character line selection signals to the second global character line of the selected odd memory block.

7. The memory device as claimed in claim 6, wherein the fourth selection circuitry includes: Multiple fifth transmission circuits are respectively coupled between the corresponding fourth transmission circuit and the corresponding odd memory block, and transmit the second global character line selection signals according to the selected odd memory block, so as to transmit the second global character line selection signals to the selected odd memory block.

8. The memory device as claimed in claim 7, wherein the second selection circuitry includes: Multiple sixth transmission circuits are respectively coupled between the corresponding fifth transmission circuit and the corresponding odd memory block, and transmit the second global character line selection signals according to the selected odd memory block, so as to transmit the second global character line selection signals to the selected odd memory block.

9. The memory device according to any one of claims 6 to 8, wherein each of the fourth transmission circuits, each of the fifth transmission circuits, and each of the sixth transmission circuits comprises: One-block decoder; And a single-line decoder, controlled by the odd-block decoder to transmit the second global character line selection signals to the selected odd-block memory.

10. The memory device as claimed in claim 9, wherein each second character line decoder includes: Multiple second transistors, the control terminals of which are coupled to the odd-numbered block decoder, are controlled by the odd-numbered block decoder to transmit the second global character line selection signals.

11. The memory device as claimed in claim 1, wherein the memory device is a NAND memory device.

Images