Memory device and memory system

Abstract

A memory device includes a memory cell array including a plurality of cell groups, each cell group including adjacent ones of a plurality of cell blocks and alternately sharing sub-word line drivers with adjacent cell groups; a mapping control circuit configured to generate a mapping control signal according to an output option signal, while selectively inverting at least one bit of the mapping control signal based on a row address and a repair control signal including information on a repaired cell group among the plurality of cell groups; and a mapping circuit configured to select one of two adjacent cell groups based on respective bits of the mapping control signal, and to map selected cell groups to a plurality of data pads.

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