Amplifier with high gain and linearity

Abstract

An amplifier includes an input circuit, a coupling circuit, an amplifier circuit and a gain linear enhancement circuit. The input circuit has a first transistor; the coupling circuit is coupled with the input circuit, the coupling circuit has a coupling capacitance, a first coupling inductance and a second coupling inductance, the first coupling is capacitively coupled between the gate terminal of the first transistor and the first coupling inductance, and the second coupling inductor is coupled to the drain terminal of the first transistor; the amplifier circuit with input circuit and coupling circuit; The gain linear enhancement circuit is coupled with the amplification circuit, and the gain linear enhancement circuit has a second transistor and a first circuit inductance, the gate terminal of the second transistor is coupled to the amplifier circuit, and the second transistor's drain terminal is coupled to the first circuit inductance. This results in high gain and improved linearity.

Description

Technical Field

[0001] This disclosure relates to an amplifier, and more particularly to an amplifier with high gain and linearity. Prior Technology

[0002] At high frequencies, due to the inherent characteristics of circuit components, the high-frequency gain of the amplifier decreases significantly, and the tuning range shrinks. Furthermore, the amplifier cannot stably maintain linear gain at high frequencies, thus reducing its performance. On the other hand, amplifiers used in high-frequency gain applications suffer from higher power losses, significantly reducing power efficiency. Summary of the Invention

[0003] The purpose of this disclosure is to provide an amplifier that improves the gain and linearity of the amplifier.

[0004] The foregoing objectives do not preclude the existence of other objectives. Objectives that can be deduced by a person skilled in the art from the description, claims, or drawings disclosed herein are also included within the objectives of this disclosure. Therefore, the objectives of this disclosure are not limited to those listed above.

[0005] To achieve the above objectives, this disclosure provides an amplifier with high gain and linearity, comprising an input circuit, a coupling circuit, an amplification circuit, and a gain linearization enhancement circuit. The input circuit has a first transistor; the coupling circuit is coupled to the input circuit and has a coupling capacitor, a first coupling inductor, and a second coupling inductor. One end of the coupling capacitor is coupled to the gate of the first transistor, and the other end of the coupling capacitor is coupled to one end of the first coupling inductor. One end of the second coupling inductor is coupled to the drain of the first transistor. The amplification circuit is coupled to both the input circuit and the coupling circuit; the gain linearization enhancement circuit is coupled to the amplification circuit and has a second transistor and a first circuit inductor. The gate of the second transistor is coupled to the amplification circuit, and the drain of the second transistor is coupled to one end of the first circuit inductor.

[0006] Therefore, this disclosure enhances the gain through coupling circuitry and achieves a better noise figure. Furthermore, at the same gain, this disclosure improves linearity through a gain linearization enhancement circuit, thereby reducing the amplifier's output power. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of an amplifier circuit with high gain and linearity according to an embodiment of the present disclosure, especially a schematic diagram showing the coupling relationship of the components. Figure 2a is a schematic diagram of a curve of one embodiment disclosed herein (I). Figure 2b is a schematic diagram of a curve of one embodiment of this disclosure (II). Figure 3 is a schematic diagram of a curve of one embodiment of this disclosure (III). Figure 4 is a schematic diagram of a curve of one embodiment of this disclosure (IV). Implementation

[0008] To facilitate the description of the central ideas disclosed in the foregoing section, specific embodiments are provided below. The various objects in the embodiments are depicted to a scale, size, deformation, or displacement suitable for illustration, and are not drawn to the scale of actual components; this will be stated prior to the description.

[0009] The exemplary embodiments of this disclosure are described in detail below with reference to the various drawings. It is not intended to limit the technical principles of this disclosure to the specific disclosed embodiments, but the scope of this disclosure is limited only by the scope of the claims and covers alternatives, modifications and equivalents.

[0010] Please refer to Figures 1 to 4. In this embodiment of the disclosure, an amplifier 100 with high gain and linearity is provided.

[0011] Please refer to Figure 1. The amplifier 100 includes an input circuit 10, a coupling circuit 20, an amplification circuit 30, and a gain linear enhancement circuit 40.

[0012] The input circuit 10 includes a first transistor Q1. The first transistor Q1 is a common-source input transistor. In one embodiment of this disclosure, the input circuit 10 includes a first source inductor LS1 and a first base resistor RB1. One end of the first source inductor LS1 is coupled to the source terminal of the first transistor Q1, and the other end of the first source inductor LS1 is coupled to a ground terminal GND. One end of the first base resistor RB1 is coupled to the base terminal of the first transistor Q1, and the other end of the first base resistor RB1 is coupled to the ground terminal GND.

[0013] Furthermore, the input circuit 10 includes a first gate inductor LG1, a first gate resistor RG1, and a first bypass capacitor C1a. The first gate inductor LG1 is coupled between the gate terminal of the first transistor Q1 and one end of the first gate resistor RG1. One end of the first gate resistor RG1 is coupled to an input terminal In, and the other end of the first gate resistor RG1 is coupled to one end of the first bypass capacitor C1a; wherein, the other end of the first gate resistor RG1 is coupled to a first gate voltage terminal VG1. The other end of the first bypass capacitor C1a is coupled to the ground terminal GND.

[0014] The coupling circuit 20 is coupled to the input circuit 10. The coupling circuit 20 is used to enhance gain and noise coefficient, and is a coupled transmission line (CTL) circuit. The coupling circuit 20 has a coupling capacitor Cctl, a first coupling inductor Lctl1, and a second coupling inductor Lctl2. One end of the coupling capacitor Cctl is coupled to the gate terminal of the first transistor Q1, and the other end of the coupling capacitor Cctl is coupled to one end of the first coupling inductor Lctl1. The other end of the first coupling inductor Lctl1 is coupled to ground GND. One end of the second coupling inductor Lctl2 is coupled to the drain terminal of the first transistor Q1, and the other end of the second coupling inductor Lctl2 is coupled to a first drain voltage terminal VD1; the other end of the second coupling inductor Lctl2 can also be coupled to a third bypass capacitor C3a.

[0015] Please refer to Figure 2a for an explanation of the relationship between the frequency of coupling circuit 20 and S21. Figure 2a shows the simulated and calculated S21 and the frequency characteristics of the low-noise amplifier. The simulated S21 is 22.6 ± 1.5 dB in the frequency range of 21.3 GHz to 28 GHz; and the calculated S21 is 23.9 ± 1.5 dB in the frequency range of 22.7 GHz to 27.9 GHz.

[0016] Please refer to Figure 2b for an explanation of the relationship between the frequency and noise figure (NF) of the coupling circuit 20. Figure 2b shows the simulated and calculated frequencies and noise figures. The simulated noise figure ranges from 2.23 dB to 2.93 dB at frequencies from 21.9 GHz to 29.1 GHz; the calculated noise figure ranges from 2.23 dB to 2.86 dB at the same frequencies.

[0017] The amplifier circuit 30 is coupled to the input circuit 10 and the coupling circuit 20.

[0018] The gain linear enhancement circuit 40 is coupled to the amplifier circuit 30. The gain linear enhancement circuit 40 has a second transistor Q2 and a first circuit inductor L1. The gate of the second transistor Q2 is coupled to the amplifier circuit 30, the source of the second transistor Q2 is coupled to ground GND, and the drain of the second transistor Q2 is coupled to one end of the first circuit inductor L1. The second transistor Q2 is a common-source switching transistor used to reuse the current from the input circuit 10 and the amplifier circuit 30 to achieve low power consumption and high power gain. The other end of the first circuit inductor L1 is coupled to an output terminal Out.

[0019] Please refer to Figure 3 for an explanation of the relationship between the gain and power of the gain linear enhancement circuit 40. Figure 3 shows that the gain linear enhancement circuit 40 increases IIP3 by 2dBm and OIP3 by 2dBm. Under the same gain conditions, because the gain linear enhancement circuit 40 improves linearity, the output power of amplifier 100 is reduced by 4dBm.

[0020] In one embodiment of this disclosure, the amplifier circuit 30 includes a third transistor Q3 and a second base resistor RB2. The drain terminal of the third transistor Q3 is coupled to the gate terminal of the second transistor Q2; wherein, the third transistor Q3 is a stacked transistor and is configured as a common source to achieve low power consumption. One end of the second base resistor RB2 is coupled to the base terminal of the third transistor Q3, and the other end of the second base resistor RB2 is coupled to the ground terminal GND.

[0021] Furthermore, the amplifier circuit 30 includes a first circuit capacitor C1b, a second circuit inductor L2, a second gate resistor RG2, and a second bypass capacitor C2a. The first circuit capacitor C1b is coupled between the drain terminal of the first transistor Q1 and one end of the second circuit inductor L2. The other end of the second circuit inductor L2 is coupled between the gate terminal of the third transistor Q3 and one end of the second gate resistor RG2. The other end of the second gate resistor RG2 is coupled to one end of the second bypass capacitor C2a; wherein, the other end of the second gate resistor RG2 is coupled to a second gate voltage terminal VG2. The other end of the second bypass capacitor C2a is coupled to the ground terminal GND.

[0022] Furthermore, the amplifier circuit 30 includes a fourth transistor Q4, a second circuit capacitor C2b, a second source inductor LS2, a third base resistor RB3, and a third gate resistor RG3. The fourth transistor Q4 is a digital switching transistor. The second circuit capacitor C2b is coupled between the gate terminal of the second transistor Q2 and the drain terminal of the fourth transistor Q4. One end of the second source inductor LS2 is coupled to the source terminal of the fourth transistor Q4, and the other end of the second source inductor LS2 is coupled to ground GND. The third base resistor RB3 is coupled between the base terminal of the fourth transistor Q4 and one end of the third gate resistor RG3; wherein, one end of the third gate resistor RG3 is coupled to a first control voltage VC1. The other end of the third gate resistor RG3 is coupled to the gate terminal of the fourth transistor Q4.

[0023] The amplifier 100, featuring high gain and linearity, further includes an output circuit 50. The output circuit 50 is coupled to the amplifier circuit 30 and the gain linearity enhancement circuit 40. The output circuit 50 has a fifth transistor Q5 and a fourth base resistor RB4. The drain terminal of the fifth transistor Q5 is coupled to the other end of the first circuit inductor L1; wherein the fifth transistor Q5 is used to dissipate additional DC power to adjust the tuning of the first transistor Q1 to S21. The fourth base resistor RB4 is coupled between the base terminal of the fifth transistor Q5 and the ground terminal GND. The amplifier circuit 30 has a third circuit inductor L3, which is coupled between the source terminal of the fifth transistor Q5 and the gate terminal of the second transistor Q2.

[0024] In one embodiment disclosed herein, the output circuit 50 includes a third circuit capacitor C3b, a fourth circuit inductor L4, a second gate inductor LG2, and a feedback resistor Rfb. The third circuit capacitor C3b and the fourth circuit inductor L4 are connected in series. The third circuit capacitor C3b and the fourth circuit inductor L4 are coupled between one end of the second gate inductor LG2 and the gate terminal of the second transistor Q2. The other end of the second gate inductor LG2 is coupled to the gate terminal of the fifth transistor Q5. The feedback resistor Rfb is coupled between one end of the second gate inductor LG2 and the other end of the first circuit inductor L1.

[0025] Furthermore, the output circuit 50 includes a sixth transistor Q6, a fifth base resistor RB5, and a fourth gate resistor RG4. The sixth transistor Q6 is a digital switching transistor. The drain terminal of the sixth transistor Q6 is coupled to the other end of the first circuit inductor L1. The source terminal of the sixth transistor Q6 is coupled to the source terminal of the fifth transistor Q5. The fifth base resistor RB5 is coupled between the base terminal of the sixth transistor Q6 and one end of the fourth gate resistor RG4; wherein one end of the fourth gate resistor RG4 is coupled to a second control voltage VC2. The other end of the fourth gate resistor RG4 is coupled to the gate terminal of the sixth transistor Q6.

[0026] Please refer to Figure 4 for an illustration of the tuning range of the amplifier circuit 30 and the output circuit 50. A better S21 tuning range is achieved when the second control voltage VC2 is between 0 volts and 1.5 volts, which is -8.7 dB to 21.4 dB. The IIP3 range is between -1.3 dBm and -17.9 dBm.

[0027] Furthermore, the output circuit 50 has a fifth circuit inductor L5. One end of the fifth circuit inductor L5 is coupled to the drain terminal of the fifth transistor Q5, and the other end of the fifth circuit inductor L5 is coupled to a second drain voltage terminal VD2; wherein, the other end of the fifth circuit inductor L5 may also be coupled to a fourth bypass capacitor C4a.

[0028] Furthermore, the output circuit 50 has a fourth circuit capacitor C4b. One end of the fourth circuit capacitor C4b is coupled to the source terminal of the fifth transistor Q5 and the source terminal of the sixth transistor Q6, and the other end of the fourth circuit capacitor C4b is coupled to the ground terminal GND.

[0029] In one embodiment of this disclosure, the parameters are set as follows:

[0030] The coefficient of the first transistor Q1 is 3.6 x 20 μm / 90 nm, the coefficient of the second transistor Q2 is 4.5 x 2 μm / 90 nm, the coefficient of the third transistor Q3 is 4 x 14 μm / 90 nm, the coefficient of the fourth transistor Q4 is 2 x 10 μm / 90 nm, the coefficient of the fifth transistor Q5 is 3 x 16 μm / 90 nm, and the coefficient of the sixth transistor Q6 is 3 x 8 μm / 90 nm.

[0031] The inductance of both the first coupling inductor Lctl1 and the second coupling inductor Lctl2 is 201.5 pH. The inductance of the first source inductor LS1 is 100.8 pH, and the inductance of the second source inductor LS2 is 44 pH. The inductance of the first gate inductor LG1 is 523 pH, and the inductance of the second gate inductor LG2 is 31 pH. The inductance of the first circuit inductor L1 is 159 pH, the inductance of the second circuit inductor L2 is 213.1 pH, the inductance of the third circuit inductor L3 is 158.9 pH, the inductance of the fourth circuit inductor L4 is 237.5 pH, and the inductance of the fifth circuit inductor L5 is 217.6 pH.

[0032] The capacitance of the first bypass capacitor C1a is 8.27pF, the capacitance of the second bypass capacitor C2a is 8.27pF, the capacitance of the third bypass capacitor C3a is 5.51pF, and the capacitance of the fourth bypass capacitor C4a is 6.89pF. The capacitance of the coupling capacitor Cctl is 6.67fF. The capacitance of the first circuit capacitor C1b is 1.38pF, the capacitance of the second circuit capacitor C2b is 922fF, the capacitance of the third circuit capacitor C3b is 617fF, and the capacitance of the fourth circuit capacitor C4b is 8.27pF.

[0033] The resistance of the first base resistor RB1 is 6.42kΩ. The resistances of the second, third, fourth, and fifth base resistors RB2, RB3, RB4, and RB5 are all 3.21kΩ. The resistances of the first, second, third, and fourth gate resistors RG1, RG2, RG3, and RG4 are all 3.21kΩ. The resistance of the feedback resistor Rfb is 2.8kΩ.

[0034] In summary, this disclosure enhances gain through coupling circuit 20 and achieves a better noise figure. Furthermore, at the same gain, this disclosure improves linearity through gain linearity enhancement circuit 40, thereby reducing the output power of amplifier 100. On the other hand, this disclosure combines amplifier circuit 30 and output circuit 50 to achieve a better tuning range.

[0035] The aforementioned effects do not preclude the existence of other effects. Effects that can be derived by those skilled in the art from the description, claims, or drawings are also included in the effects disclosed herein. Therefore, the effects disclosed herein are not limited to those listed above.

[0036] The embodiments described above are merely illustrative of this disclosure and are not intended to limit its scope. All modifications or variations made without departing from the spirit of this disclosure are within the scope of protection intended by this disclosure.

[0037] 100: Amplifier 10: Input Circuit 20: Coupling circuit 30: Amplifier Circuit 40: Gain Linear Enhancement Circuit 50: Output Circuit Cctl: Coupling capacitor C1a: First bypass capacitor C2a: Second bypass capacitor C3a: Third bypass capacitor C4a: Fourth bypass capacitor C1b: First circuit capacitor C2b: Second circuit capacitor C3b: Capacitor in the third circuit C4b: Fourth circuit capacitor GND: Ground terminal In: Input end L1: Inductance of the first circuit L2: Second circuit inductor L3: Third circuit inductor L4: Fourth Circuit Inductor L5: Fifth Circuit Inductor Lctl1: First coupled inductor Lctl2: Second coupling inductor LS1: First source inductor LS2: Second source inductor LG1: First gate inductor LG2: Second gate inductor Out: Output terminal Q1: First transistor Q2: Second transistor Q3: Third transistor Q4: Fourth transistor Q5: Fifth transistor Q6: Sixth transistor Rfb: Feedback resistor RB1: First base resistance RB2: Second base resistance RB3: Third base resistance RB4: Fourth base resistance RB5: Fifth base resistor RG1: First gate resistor RG2: Second gate resistor RG3: Third gate resistor RG4: Fourth gate resistor VC1: First control voltage VC2: Second control voltage VD1: First drain voltage terminal VD2: Second drain voltage terminal VG1: First gate voltage terminal VG2: Second gate voltage terminal

Claims

1. An amplifier with high gain and linearity, comprising: An input circuit having a first transistor; A coupling circuit coupled to the input circuit, the coupling circuit having a coupling capacitor, a first coupling inductor and a second coupling inductor, one end of the coupling capacitor being coupled to the gate of the first transistor, the other end of the coupling capacitor being coupled to one end of the first coupling inductor, and one end of the second coupling inductor being coupled to the drain of the first transistor; an amplifier circuit coupled to the input circuit and the coupling circuit; and a gain linear enhancement circuit coupled to the amplifier circuit; wherein the amplifier circuit has a fourth transistor, a second circuit capacitor, a second source inductor, a third base resistor and a third gate resistor, the second circuit capacitor being coupled to the drain of the fourth transistor, one end of the second source inductor being coupled to the source of the fourth transistor, the third base resistor being coupled between the base of the fourth transistor and one end of the third gate resistor, and the other end of the third gate resistor being coupled to the gate of the fourth transistor.

2. An amplifier with high gain and linearity as described in claim 1, wherein, The input circuit has a first source inductor and a first base resistor. One end of the first source inductor is coupled to the source terminal of the first transistor, and one end of the first base resistor is coupled to the base terminal of the first transistor.

3. An amplifier with high gain and linearity as described in claim 2, wherein, The input circuit has a first gate inductor, a first gate resistor and a first bypass capacitor. The first gate inductor is coupled between the gate terminal of the first transistor and one end of the first gate resistor, and the other end of the first gate resistor is coupled to one end of the first bypass capacitor.

4. An amplifier with high gain and linearity as described in claim 1, wherein, The amplifier circuit has a third transistor and a second base resistor, one end of which is coupled to the base terminal of the third transistor.

5. An amplifier with high gain and linearity as described in claim 4, wherein, The amplifier circuit has a first circuit capacitor, a second circuit inductor, a second gate resistor, and a second bypass capacitor. The first circuit capacitor is coupled between the drain terminal of the first transistor and one end of the second circuit inductor. The other end of the second circuit inductor is coupled between the gate terminal of the third transistor and one end of the second gate resistor. The other end of the second gate resistor is coupled to one end of the second bypass capacitor.

6. An amplifier with high gain and linearity as described in claim 5, wherein, The gain linear enhancement circuit further includes a second transistor and a first circuit inductor. The gate of the second transistor is coupled to the amplifier circuit, the drain of the second transistor is coupled to one end of the first circuit inductor, the second circuit capacitor is coupled between the gate of the second transistor and the drain of the fourth transistor, and the drain of the third transistor is coupled to the gate of the second transistor.

7. An amplifier with high gain and linearity as described in claim 6, wherein, It further includes an output circuit coupled to the amplifier circuit and the gain linear enhancement circuit. The output circuit has a fifth transistor and a fourth base resistor. The drain terminal of the fifth transistor is coupled to the other end of the first circuit inductor. The fourth base resistor is coupled to the base terminal of the fifth transistor. The amplifier circuit has a third circuit inductor coupled between the source terminal of the fifth transistor and the gate terminal of the second transistor.

8. An amplifier with high gain and linearity as described in claim 7, wherein, The output circuit has a third circuit capacitor, a fourth circuit inductor, a second gate inductor, and a feedback resistor. The third circuit capacitor and the fourth circuit inductor are connected in series. The third circuit capacitor and the fourth circuit inductor are coupled between one end of the second gate inductor and the gate terminal of the second transistor. The other end of the second gate inductor is coupled to the gate terminal of the fifth transistor. The feedback resistor is coupled between one end of the second gate inductor and the other end of the first circuit inductor.

9. An amplifier with high gain and linearity as described in claim 8, wherein, The output circuit has a sixth transistor, a fifth base resistor and a fourth gate resistor. The source terminal of the sixth transistor is coupled to the source terminal of the fifth transistor. The fifth base resistor is coupled between the base terminal of the sixth transistor and one end of the fourth gate resistor. The other end of the fourth gate resistor is coupled to the gate terminal of the sixth transistor.

10. An amplifier with high gain and linearity as described in claim 9, wherein, The drain terminal of the sixth transistor is coupled to the other end of the first circuit inductor.

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