Level shifting circuit with integrated latch

Abstract

A level shifting circuit includes a front stage and a rear stage. The front stage and the rear stage are operated according to a first clock and a second clock. During a first phase of the first clock, the front stage is in a conversion mode, the rear stage is in a propagation mode, and the front stage is served as a level shifter. Furthermore, the input signal between a first supply voltage and a ground voltage is converted into a shifted signal between a second supply voltage and the ground voltage. During a second phase of the first clock, the front stage is in a tri-state output mode, the rear stage is in a retention mode, and the rear stage is served as a latch. Furthermore, the output signal from the rear stage is maintained at a specified logic level.

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