Level shifter circuit

Abstract

A level shifter circuit includes an input stage, a first inverter, a second inverter, and a feedback transistor. The input stage is configured to receive an input signal and an operating voltage, and provide the operating voltage to a first node based on the input signal and a control signal. A first input terminal of the first inverter is coupled to the first node. A second input terminal of the second inverter is coupled to a first output terminal of the first inverter. The feedback transistor is controlled by the control signal and coupled to the first node and a second output terminal of the second inverter.

Description

Technical Field

[0001] This invention relates to a level shifter circuit; in particular, a level shifter circuit that achieves high-speed voltage shifting by cutting the feedback establishment interval. Prior Technology

[0002] When displaying a screen, the massive amount of data necessitates that the display driver chip operate with low-voltage signals (e.g., transmission, encoding, decoding, alignment, or computation). However, the output unit must provide corresponding analog voltage outputs to match different types of display panels (e.g., liquid crystal displays, organic light-emitting diode displays, or micro-light-emitting diodes) or different panel driving technologies. This voltage conversion process requires a level shifter circuit to achieve this.

[0003] The complexity of the configuration and layout of the level shifter circuit is directly proportional to the display effect of the display panel (e.g., color, image resolution, or detail). In other words, the more efficient the display panel, the more display driver chips or complex level shifter circuits are required. However, the area of ​​the display driver chip accounts for a very high percentage of the overall manufacturing cost. Therefore, effectively saving the area of ​​the level shifter circuit is an important issue for cost reduction.

[0004] Furthermore, the response speed of the high-voltage signal output by the level shifter circuit will determine the performance of its subsequent interconnected circuits. If the voltage conversion of the level shifter circuit is too slow, it will cause the transition process to be uneven, affecting the subsequent interconnected circuits and thus affecting image quality. Summary of the Invention

[0005] Therefore, the present invention proposes a level shifter circuit to effectively solve the above-mentioned problems encountered by the prior art.

[0006] A preferred embodiment of the present invention provides a level shifter circuit. The level shifter circuit includes an input stage, a first inverter, a second inverter, and a feedback transistor. The input stage is configured to receive an input signal and an operating voltage, and to provide an operating voltage to a first node according to the input signal and a control signal. A first input terminal of the first inverter is coupled to the first node. A second input terminal of the second inverter is coupled to a first output terminal of the first inverter. The feedback transistor is controlled by a control signal and coupled to the first node and the second output terminal of the second inverter.

[0007] In one embodiment, the control signal has a first on-time, and the input signal has a second on-time greater than the first on-time.

[0008] In one embodiment, the first activation point of the control signal does not lag behind the second activation point of the input signal.

[0009] In one embodiment, the level shifter circuit further includes an enabling transistor. The enabling transistor is controlled by a control signal and coupled between the operating voltage and the input stage.

[0010] In one embodiment, during the initial stage, a control signal turns off the enable transistor and turns on the feedback transistor.

[0011] In one embodiment, during the write phase, a control signal turns on the enable transistor and turns off the feedback transistor.

[0012] In one embodiment, during the latching phase, a control signal turns off the enabling transistor and turns on the feedback transistor.

[0013] According to a preferred embodiment of the present invention, a level shifter circuit is provided. The level shifter circuit includes a first transistor, an enable transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a feedback transistor. The first transistor is controlled by an input signal. The enable transistor is controlled by a control signal and is coupled to the first transistor via a first node. The gate of the second transistor is coupled to the first node. The gate of the third transistor is coupled to the first node, and the third transistor is coupled to the second transistor via a first output node. The gate of the fourth transistor is coupled to the first output node. The gate of the fifth transistor is coupled to the first output node, and the fifth transistor is coupled to the fourth transistor via a second output node. The feedback transistor is controlled by a control signal and is coupled between the first node and the second output node.

[0014] In one embodiment, the level shifter circuit further includes a sixth transistor. The sixth transistor is controlled by a first bias voltage and coupled to the end of the enable transistor that is not coupled to the first node.

[0015] In one embodiment, the level shifter circuit further includes a seventh transistor. The seventh transistor is controlled by a second bias and coupled between the first node and the first transistor.

[0016] In one embodiment, the control signal has a first on-time, and the input signal has a second on-time greater than the first on-time.

[0017] In one embodiment, the first activation point of the control signal does not lag behind the second activation point of the input signal.

[0018] In one embodiment, during the initial stage, a control signal turns off the enable transistor and turns on the feedback transistor.

[0019] In one embodiment, during the write phase, a control signal turns on the enable transistor and turns off the feedback transistor.

[0020] In one embodiment, during the latching phase, a control signal turns off the enabling transistor and turns on the feedback transistor.

[0021] As described above, the level shifter circuit of the present invention forms a feedback path at the output of the high-voltage latch via a feedback transistor coupled between the first node and the second output node. The feedback transistor can be switched to control the feedback establishment interval. By segmenting the feedback establishment interval, the level shifter circuit of the present invention can achieve a high-speed voltage shifting effect. Simple Explanation of the Diagram

[0022] The accompanying drawings presented in this invention are intended to help describe various embodiments of the invention. However, to simplify the drawings and / or highlight what they are meant to convey, known structures and / or elements may be depicted in a simplified schematic manner or omitted. Furthermore, the number of elements in the drawings may be singular or plural. The accompanying drawings presented in this invention are for illustrative purposes only and are not intended to limit the scope of the invention.

[0023] Figure 1 illustrates a block diagram of a level shifter circuit in one embodiment of the present invention.

[0024] Figure 2 illustrates a block diagram of a level shifter circuit in one embodiment of the present invention.

[0025] Figures 3A-3C illustrate schematic diagrams of the level shifter circuit at various operating stages in one embodiment of the present invention.

[0026] Figure 4 illustrates a schematic diagram of control signals and input signals in one embodiment of the present invention.

[0027] Figure 5 shows a circuit diagram of a level shifter circuit in one embodiment of the present invention.

[0028] Figure 6 illustrates a circuit diagram of a level shifter circuit in one embodiment of the present invention.

[0029] Figure 7 illustrates a circuit diagram of a level shifter circuit in one embodiment of the present invention.

[0030] Figures 8A-8C illustrate schematic diagrams of the level shifter circuit at various operating stages in one embodiment of the present invention. Implementation

[0031] Any reference to elements referred to herein by names such as "first," "second," etc., does not generally limit the number or order of these elements. Rather, these names are used herein as a convenient way to distinguish two or more elements or instances of elements. Therefore, it should be understood that the names "first," "second," etc., in the claim do not necessarily correspond to the same names in the written description. Furthermore, it should be understood that references to first and second elements do not imply that only two elements can be used or that the first element must precede the second element. The terms "comprising," "including," "having," "containing," etc., as used herein are open-ended, meaning they include but are not limited to.

[0032] The term "connection" is used in this document to refer to a direct or indirect link between two structures. For example, in one example of an indirect connection, one structure may be connected to another structure via a band.

[0033] In this invention, the terms "exemplary" and "for example" are used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other aspects of the invention. The terms "about" and "approximately" as used herein with respect to specified values ​​or characteristics are intended to mean within a certain value (e.g., 10%) of the specified value or characteristic.

[0034] A preferred embodiment of the present invention is a level shifter circuit. Referring to FIG1, FIG1 illustrates a level shifter circuit 100 comprising an input stage 110, a first inverter 120, a second inverter 130, and a feedback transistor (T_FB). The input stage 110 is configured to receive an input signal (VIN) and an operating voltage (AVDD), and to provide the operating voltage (AVDD) to a first node (A) according to the input signal (VIN) and a control signal (ENB). The first input terminal 121 of the first inverter 120 is coupled to the first node (A). The second input terminal 131 of the second inverter 130 is coupled to the first output terminal 122 of the first inverter 120. The feedback transistor (T_FB) is controlled by the control signal (ENB) and is coupled to the first node (A) and the second output terminal 132 of the second inverter 130.

[0035] The input stage 110, the first inverter 120, and / or the second inverter 130 can be configured using transistor circuitry, and the present invention is not limited to the circuit configuration of the input stage 110, the first inverter 120, and / or the second inverter 130. A feedback transistor (T_FB) is coupled between the first node (A) (i.e., the input terminal of the first inverter 120) and the second output terminal 132 of the second inverter 130 to form a feedback path.

[0036] In one embodiment, the input stage 110 can be controlled via a transistor to de-latch and save power. Referring to Figure 2, the level shifter circuit 200 further includes an enable transistor (T_EN). The enable transistor (T_EN) is controlled by a control signal (ENB) and coupled between the operating voltage (AVDD) and the input stage 110. The enable transistor (T_EN) can control the current and latch-up to ensure efficient power consumption and smooth operation of the level shifter circuit 200.

[0037] In this embodiment, the level shifter circuit 200 has an initialization phase, a write phase, and a latching phase. Referring to Figure 3A, in the initialization phase, the control signal (ENB) turns on the feedback transistor (T_FB) and turns off the enable transistor (T_EN). With the enable transistor (T_EN) off, the input stage 110 receives no current from the operating voltage (AVDD), achieving energy saving and waiting for input. Next, referring to Figure 3B, in the write phase, the control signal (ENB) turns off the feedback transistor (T_FB) and turns on the enable transistor (T_EN). Because the enable transistor (T_EN) is on, the voltage at the input of the first inverter 120 (i.e., the first node (A)) can be amplified to the output of the second inverter 130 through the shifting between the first inverter 120 and the second inverter 130. When the output of the second inverter 130 completes the transition, please refer to Figure 3C. During the latching phase, the control signal (ENB) turns on the feedback transistor (T_FB) and turns off the enable transistor (T_EN).

[0038] In this embodiment, the transition time of the control signal (ENB) needs to be earlier than or equal to the transition time of the input signal (VIN), and the control signal (ENB) will transition again after the level shifter circuit output has completed its transition. Specifically, referring to Figure 4, the control signal (ENB) has a first on-time (t1), and the input signal (VIN) has a second on-time (t2) that is greater than the first on-time (t1). The first on-time (s1) of the control signal (ENB) does not lag behind the second on-time (s2) of the input signal (VIN). This allows a feedback path to be established in the initial stage before signal input, and during the write stage, the feedback path is closed to allow the voltage to quickly respond to the output of the second inverter 130. When the transition of the output signal (OUT) at the output terminal is completed, the feedback path is opened and the voltage signal at the output terminal is maintained, waiting for the next write stage. It should be noted that the high state (digit 1) and low state (digit 0) of the control signal (ENB) shown in Figure 4 are for illustrative purposes only and are not intended to limit the types of feedback transistor (T_FB) and enable transistor (T_EN) of the present invention.

[0039] In one embodiment, the level shifter circuit can be composed of transistors. Specifically, referring to FIG5, as shown in FIG5, the level shifter circuit 500 includes a first transistor (T1), an enable transistor (T_EN), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), and a feedback transistor (T_FB). The first transistor (T1) is controlled by an input signal (VIN). The enable transistor (T_EN) is controlled by a control signal (ENB) and is coupled to the first transistor (T1) via a first node (A). The gate of the second transistor (T2) is coupled to the first node (A). The gate of the third transistor (T3) is coupled to the first node (A), and the third transistor (T3) is coupled to the second transistor (T2) via a first output node. The gate of the fourth transistor (T4) is coupled to the first output node. The gate of the fifth transistor (T5) is coupled to the first output node, and the fifth transistor (T5) is coupled to the fourth transistor (T4) via the second output node. The feedback transistor (T_FB) is controlled by the control signal (ENB) and coupled between the first node (A) and the second output node.

[0040] In one embodiment, the enable transistor (T_EN) of the level shifter circuit can be indirectly coupled to the operating voltage (AVDD) via a transistor to achieve the effect of regulating current. Specifically, referring to FIG6, the level shifter circuit 600 further includes a sixth transistor (T6). The sixth transistor (T6) is controlled by a first bias voltage (VBP) and coupled to the end of the enable transistor (T_EN) that is not coupled to the first node (A). When the enable transistor (T_EN) is turned on in response to the control signal (ENB), the sixth transistor (T6) can regulate the current flowing through the enable transistor (T_EN). In this way, the size of the enable transistor (T_EN) can be further reduced, achieving the goal of reducing the overall size.

[0041] In one embodiment, the level shifter circuit may have a transistor disposed between the first node (A) and the first transistor (T1), thereby reducing the overall operating voltage. Specifically, referring to FIG7, the level shifter circuit 700 further includes a seventh transistor (T7). The seventh transistor (T7) is controlled by a second bias voltage (VBN) and coupled between the first node (A) and the first transistor (T1). In this embodiment, the withstand voltage or transistor pressure parameter of the first transistor (T1) will be at least lower than that of the seventh transistor (T7) so that the level shifter circuit can operate in a low-voltage environment.

[0042] In this embodiment, the operation of the level shifter circuit in the initial stage, write stage, and latching stage is described in Figures 8A to 8C. As shown in Figure 8A, in the initial stage, the control signal (ENB) (e.g., bit "1") turns on the feedback transistor (T_FB) and turns off the enable transistor (T_EN). With the enable transistor (T_EN) off, the input stage 110 receives no current from the operating voltage (AVDD), achieving energy saving and waiting for input. As shown in Figure 8B, in the write stage, the control signal (ENB) (e.g., changing from bit "1" to bit "0") turns off the feedback transistor (T_FB) and turns on the enable transistor (T_EN). Because the enable transistor (T_EN) is turned on, the voltage at the input of the first inverter 120 (i.e., the first node (A)) becomes high (H), which can be amplified to the output of the second inverter 130 through the shifting of the first inverter 120 and the second inverter 130. When the output of the second inverter 130 completes the state transition, as shown in Figure 8C, during the latch-up phase, the control signal (ENB) turns on the feedback transistor (T_FB) and turns off the enable transistor (T_EN).

[0043] In summary, the level shifter circuit of the present invention forms a feedback path at the output of the high-voltage latch via a feedback transistor coupled between the first node and the second output node. The feedback transistor can be switched to control the feedback establishment interval. By segmenting the feedback establishment interval, the level shifter circuit of the present invention can achieve a high-speed voltage shifting effect.

[0044] The prior description of the invention is provided to enable those skilled in the art to make or practice the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations or embodiments can be combined with or implemented individually without departing from the spirit or scope of the invention. Therefore, the invention is not intended to be limited to the examples described herein, but is accorded the widest scope consistent with the principles and novel features of the invention herein.

[0045] 100: Level shifter circuit 110: Input Level 120: First Inverter 121: First input terminal 122: First output terminal 130: Second Inverter 131: Second input terminal 132: Second output terminal 200: Level shifter circuit 500: Level shifter circuit 600: Level shifter circuit 700: Level Shifter Circuit A: First node AVDD: Operating voltage ENB: Control Signal s1: First start time s2: Second start time t1: First opening time t2: Second opening time T1: First transistor T2: Second transistor T3: Third transistor T4: Fourth transistor T5: Fifth Transistor T6: Sixth Transistor T7: Seventh Transistor T_EN: Enabling transistor T_FB: Feedback transistor VBP: First bias voltage VBN: Second bias voltage VIN: Input signal

Claims

1. A level shifter circuit, comprising: a first transistor controlled by an input signal; an enabling transistor controlled by a control signal and coupled to the first transistor via a first node; a second transistor, the gate of which is coupled to the first node; a third transistor, the gate of which is coupled to the first node and the third transistor is coupled to the second transistor via a first output node; a fourth transistor, the gate of which is coupled to the first output node; a fifth transistor, the gate of which is coupled to the first output node and the fifth transistor is coupled to the fourth transistor via a second output node; and a feedback transistor controlled by the control signal and coupled between the first node and the second output node; wherein during a write phase, the control signal turns on the enabling transistor and turns off the feedback transistor.

2. The level shifter circuit as claimed in claim 1 further comprises: a sixth transistor controlled by a first bias voltage and coupled to the end of the enabling transistor that is not coupled to the first node.

3. The level shifter circuit as claimed in claim 2 further comprises: a seventh transistor controlled by a second bias voltage and coupled between the first node and the first transistor.

4. The level shifter circuit as described in claim 1, wherein the control signal has a first on-time and the input signal has a second on-time greater than the first on-time.

5. The level shifter circuit as described in claim 1, wherein a first on-time of the control signal does not lag behind a second on-time of the input signal.

6. The level shifter circuit as claimed in claim 1, wherein in an initial phase, the control signal turns off the enable transistor and turns on the feedback transistor.

7. The level shifter circuit as claimed in claim 1, wherein during a latching phase, the control signal turns off the enabling transistor and turns on the feedback transistor.

8. A level shifter circuit, comprising: an input stage configured to receive an input signal and an operating voltage, and to provide the operating voltage to a first node according to the input signal and a control signal; a first inverter, a first input terminal of the first inverter being coupled to the first node; and a second inverter, a second input terminal of the second inverter being coupled to a first output terminal of the first inverter. A power-receiving crystal, controlled by the control signal, is coupled to the first node and a second output terminal of the second inverter; And a power transistor, controlled by the control signal and coupled between the operating voltage and the input stage, wherein during a write phase, the control signal turns on the power transistor and turns off the feedback transistor.

9. The level shifter circuit as claimed in claim 8, wherein the control signal has a first on-time and the input signal has a second on-time greater than the first on-time.

10. The level shifter circuit as described in claim 8, wherein a first on-time of the control signal does not lag behind a second on-time of the input signal.

11. The level shifter circuit as claimed in claim 8, wherein in an initial phase, the control signal turns off the enable transistor and turns on the feedback transistor.

12. The level shifter circuit as described in claim 8, wherein during a latching phase, the control signal turns off the enable transistor and turns on the feedback transistor.

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