Dynamic decoding method, memory storage device and memory control circuit unit

Abstract

A dynamic decoding method, a memory storage device and a memory control circuit unit are provided. The dynamic decoding method includes: reading a first codeword from a physical unit of a non-volatile memory module, wherein the first codeword includes at least two groups; performing a decoding operation according to a first group of the first codeword; in the decoding operation, checking whether a syndrome data of the first codeword is equal to zero; and in response to the syndrome data being equal to zero, outputting the first codeword.

Description

[Technical Field]

[0001] This invention relates to a memory management technology, and more particularly to a dynamic decoding method, a memory storage device, and a memory control circuit unit. [Previous Technology]

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] When data in a rewritable non-volatile memory module is read, a decoding operation is performed based on error correction codes. If the data read from the rewritable non-volatile memory module contains erroneous bits, the decoding time will increase. In traditional iterative decoding operations, erroneous bits in the data may be successfully corrected during the decoding operation, causing the error to converge. However, each iteration is performed based on the complete codeword, and unnecessary calculations may be performed on the converged bits in subsequent iterations, thus affecting performance. [Summary of the Invention]

[0004] The present invention provides a dynamic decoding method, a memory storage device, and a memory control circuit unit, which can significantly improve decoding speed, reduce hardware costs, and maintain error correction capabilities.

[0005] An exemplary embodiment of the present invention provides a dynamic decoding method for a rewritable non-volatile memory module, the dynamic decoding method comprising: reading a first codeword from a physical unit of the rewritable non-volatile memory module, wherein the first codeword comprises at least two groups; performing a decoding operation based on a first group of the first codeword; in the decoding operation, checking whether the check data of the first codeword is equal to zero; and outputting the first codeword in response to the check data being equal to zero.

[0006] In an exemplary embodiment of the present invention, the dynamic decoding method further includes: after completing the decoding operation performed according to the first group, in response to the check data not being equal to zero, performing the decoding operation according to the complete first codeword.

[0007] In an exemplary embodiment of the present invention, the dynamic decoding method further includes: determining whether the current iteration number of the decoding operation is less than a predetermined number; and in response to the current iteration number being less than the predetermined number, performing the decoding operation according to the first group.

[0008] In an exemplary embodiment of the present invention, the dynamic decoding method further includes: in response to the current iteration number being not less than the predetermined number, performing the decoding operation based on the complete first codeword.

[0009] In an exemplary embodiment of the present invention, the decoding capabilities of the at least two groups are different, and the decoding capability of the first group is lower than that of the second group of the first codeword.

[0010] In an exemplary embodiment of the present invention, the dynamic decoding method further includes: establishing a lookup table based on the at least two groups; and querying the lookup table according to the current iteration number of the decoding operation to determine whether to perform the decoding operation based on one of the at least two groups or the complete first codeword.

[0011] An exemplary embodiment of the present invention further provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit issues a read instruction sequence to the rewritable non-volatile memory module, the read instruction sequence instructing the reading of a first codeword from a physical unit of the rewritable non-volatile memory module, wherein the first codeword comprises at least two groups. The memory control circuit unit is further configured to perform a decoding operation based on a first group of the first codeword. In the decoding operation, the memory control circuit unit is further configured to check whether the checksum data of the first codeword is equal to zero. In response to the checksum data being equal to zero, the memory control circuit unit is further configured to output the first codeword.

[0012] In an exemplary embodiment of the present invention, after the decoding operation performed according to the first group is completed, in response to the check data not being equal to zero, the memory control circuit unit is further configured to perform the decoding operation according to the complete first codeword.

[0013] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether the current iteration number of the decoding operation is less than a predetermined number. In response to the current iteration number being less than the predetermined number, the memory control circuit unit is further configured to perform the decoding operation according to the first group.

[0014] In an exemplary embodiment of the present invention, in response to the current iteration number being not less than the predetermined number, the memory control circuit unit is further configured to perform the decoding operation based on the complete first codeword.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to establish a lookup table based on the at least two groups. The memory control circuit unit is further configured to query the lookup table according to the current iteration number of the decoding operation to determine whether to perform the decoding operation based on one of the at least two groups or the complete first codeword.

[0016] An exemplary embodiment of the present invention further provides a memory control circuit unit disposed in a memory storage device. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is coupled to a connection interface unit. The memory interface is coupled to a rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit issues a read instruction sequence to the rewritable non-volatile memory module, the read instruction sequence instructing the reading of a first codeword from a physical unit of the rewritable non-volatile memory module, wherein the first codeword includes at least two groups. The memory management circuit is further configured to perform a decoding operation based on a first group of the first codeword. In the decoding operation, the memory management circuit is further configured to check whether the checksum data of the first codeword is equal to zero. In response to the checksum data being equal to zero, the memory management circuit is further configured to output the first codeword.

[0017] In an exemplary embodiment of the present invention, after the decoding operation performed according to the first group is completed, in response to the check data not being equal to zero, the memory management circuit is further configured to perform the decoding operation according to the complete first codeword.

[0018] In an exemplary embodiment of the present invention, the memory management circuit is further configured to determine whether the current iteration number of the decoding operation is less than a predetermined number. In response to the current iteration number being less than the predetermined number, the memory management circuit is further configured to perform the decoding operation according to the first group.

[0019] In an exemplary embodiment of the present invention, in response to the current iteration number being not less than the predetermined number, the memory management circuit is further configured to perform the decoding operation based on the complete first codeword.

[0020] In an exemplary embodiment of the present invention, the memory management circuit is further configured to establish a lookup table based on the at least two groups. The memory management circuit is further configured to query the lookup table according to the current iteration number of the decoding operation to determine whether to perform the decoding operation based on one of the at least two groups or the complete first codeword.

[0021] Based on the above, the dynamic decoding method, memory storage device and memory control circuit unit of the present invention can perform decoding operation only on the first group of codewords with low decoding capability when the current iteration number is less than a predetermined number, and perform decoding operation on the complete codeword when the current iteration number is not less than a predetermined number. This can avoid performing unnecessary calculations on converged bits, thereby improving the decoding speed while maintaining the error correction capability.

Implementation Method

[0022] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0023] FIG1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention. FIG2 is a schematic diagram of a host system, memory storage device and I / O device according to an exemplary embodiment of the present invention.

[0024] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and ROM 114 may be coupled to a system bus 110.

[0025] In one exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 may be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0026] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0027] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0028] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0029] FIG3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple memory modules to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0030] FIG4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0031] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The interface unit 41 may be packaged in the same chip as the memory control circuit unit 42, or the interface unit 41 may be disposed outside the chip containing the memory control circuit unit 42.

[0032] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0033] The rewritable non-volatile memory module 43 is used to store the data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0034] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". With the change of the threshold voltage, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored in that memory cell.

[0035] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical programming unit. Generally, in MLC NAND flash memory, the write rate of lower physical programming units is greater than that of upper physical programming units, and / or the reliability of lower physical programming units is higher than that of upper physical programming units.

[0036] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of memory cells to be erased. For example, the entity erasure unit is an entity block.

[0037] FIG5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0038] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0039] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0040] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data) in the form of program code. Furthermore, the memory management circuit 51 has a microprocessor unit (not shown), read-only memory (not shown), and random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0041] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erasure circuit issues an erasure command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit processes data to be written to and read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0042] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0043] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program code. For example, a read instruction sequence may include information such as the read identifier and memory address.

[0044] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0045] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0046] In one exemplary embodiment, the error checking and correction circuit 54 may support low-density parity-check (LDPC) codes. For example, the error checking and correction circuit 54 may use low-density parity-check codes for encoding and decoding. In one exemplary embodiment, the error checking and correction circuit 54 may also employ other types of encoding / decoding algorithms, such as BCH or Reed-Solomon (RS) codes, etc., which are not limited by the present invention.

[0047] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10.

[0048] In one exemplary embodiment, the rewritable non-volatile memory module 43 of FIG4 may include a flash memory module. In one exemplary embodiment, the memory control circuit unit 42 of FIG4 may include a flash memory controller. In one exemplary embodiment, the memory management circuit 51 of FIG5 may include a flash memory management circuit.

[0049] FIG6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0050] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units.

[0051] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0052] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logic unit corresponds to a logic address. For example, a logic address may include one or more logical block addresses (LBAs) or other logic management units. In an exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logic addresses.

[0053] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0054] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0055] In one exemplary embodiment, the error checking and correction circuit 54 may include an encoding circuit 541 and a decoding circuit 542. The encoding circuit 541 is used to encode data. The decoding circuit 542 is used to decode data. In one exemplary embodiment, the encoding circuit 541 and the decoding circuit 542 may also be combined into a single encoding / decoding circuit.

[0056] In one exemplary embodiment, before the memory management circuit 51 writes data to the rewritable non-volatile memory module 43, the data is first encoded to generate corresponding parity data. The data and parity data are then stored in the rewritable non-volatile memory module 43. The data that the memory management circuit 51 wants to write to the rewritable non-volatile memory module 43 (also referred to as write data) may be, for example, user data written by the host system 11, or management data of the memory management circuit 51. When the memory management circuit 51 wants to read a physical cell, the memory management circuit 51 can read the data in the physical cell and its corresponding parity data. The decoding circuit 542 in the error checking and correction circuit 54 can perform a decoding operation based on the parity data and the data read from the physical cell to detect and correct errors in the data.

[0057] In one exemplary embodiment, the error checking and correction circuit 54 uses a low-density parity-check code for encoding and decoding. In a low-density parity-check code, a check matrix (also called a parity check matrix) is used to define a valid codeword. Hereinafter, the parity check matrix is ​​denoted as H, and the codeword is denoted as CW. According to the following equation (1), if the product of the parity check matrix H and the codeword CW is a zero vector, it means that CW is a valid codeword. Wherein the operator × represents matrix multiplication modulo 2. In other words, the null space of matrix H contains all valid codewords. However, the present invention does not limit the content of the codeword CW. For example, the codeword CW may also include error correction codes or error checking codes generated by any algorithm.

[0058] CW×HT=0 (1)

[0059] The codeword CW may include message bits and parity bits, that is, the codeword CW can be represented as [MP]. Vector M is composed of message bits. Vector P is composed of parity bits. Vector M is also called written data (or data to be encoded). Vector P is also called parity data. In a codeword, parity bits (i.e., parity data) are used to protect message bits (i.e., written data) and can be regarded as error correction codes or error checking codes generated corresponding to message bits. In addition, protecting message bits, for example, means maintaining the correctness of message bits. For example, when reading message bits from the rewritable non-volatile memory module 43, the parity bits corresponding to this message bit can be used to correct errors that may exist in the message bit.

[0060] When decoding a codeword CW, a parity check operation is first performed on the codeword CW, for example, multiplying the matrix H with the codeword CW to produce a vector (hereinafter referred to as S, as shown in the following equation (2)). Each element in the vector S is also called a syndrome. The vector S is also called the syndrome data. If the vector S is a zero vector (i.e., each element in the vector S is zero), the codeword CW can be directly output. If the vector S is not a zero vector (i.e., at least one element in the vector S is not zero), it indicates that there is at least one error in the codeword CW and the codeword CW is not a valid codeword. If the codeword CW is not a valid codeword, the error checking and correction circuit 54 can perform a decoding operation to try to correct the error in the codeword CW.

[0061] CW×HT=S (2)

[0062] In one exemplary embodiment, the error checking and correction circuit 54 performs an iterative decoding operation. An iterative decoding operation is used to decode a piece of data from the rewritable non-volatile memory module 43. The decoding unit is, for example, a codeword. In an iterative operation, a parity check operation to check the correctness of the data and a decoding operation to correct errors in the data are repeatedly executed until decoding is successful or the number of iterations reaches a termination number. Specifically, if the number of iterations reaches this termination number, it indicates that decoding has failed, and the error checking and correction circuit 54 will stop decoding. The value of the termination number can be designed according to actual needs, and the present invention is not limited thereto. Furthermore, if the parity check operation determines that there are no errors in the data, the error checking and correction circuit 54 will output the data.

[0063] Figure 7 is a schematic diagram of a codeword according to an exemplary embodiment of the present invention. Referring to Figure 7, assuming that the data read from the rewritable nonvolatile memory module 43 includes codeword 701 (also referred to as the first codeword), then in the parity check operation, according to equation (2), the parity check matrix H can be multiplied with codeword 701 to obtain vector S. If vector S is a zero vector, it indicates that there are no error bits in codeword 701, and the error checking and correction circuit 54 can directly output codeword 701. Conversely, if vector S is not a zero vector, it indicates that there are at least one error bit in codeword 701, and the error checking and correction circuit 54 will perform a decoding operation on codeword 701 to correct the error bits in the codeword.

[0064] In an exemplary embodiment, codeword 701 is composed of multiple matrices, which may be, for example, permutation matrices and zero matrices. Codeword 701 can be represented as 24 columns, as shown in Figure 7, with each column having a unique index value. Column 1 of codeword 701 corresponds to index value 0, column 2 of codeword 701 corresponds to index value 1, and so on. In an exemplary embodiment, columns 1 to 18 of codeword 701 are composed of message bits, and columns 19 to 24 of codeword 701 are composed of parity bits.

[0065] In one exemplary embodiment, each column in codeword 701 has a different decoding capability. For example, columns 1 to 6 of codeword 701 are each composed of permutation matrices. In one exemplary embodiment, each permutation matrix may be, for example, a check node. Specifically, columns 1 to 6 of codeword 701 each have 6 check nodes. Similarly, columns 7 to 19 of codeword 701 each have 3 check nodes. Columns 20 to 24 of codeword 701 each have 2 check nodes. The more check nodes a column in codeword 701 has, the higher its decoding capability. In other words, columns 1 to 6 of codeword 701 have the highest decoding capability, columns 7 to 19 have the second highest decoding capability, and columns 20 to 24 have the lowest decoding capability.

[0066] In an exemplary embodiment, when decoding codeword 701, the error checking and correction circuit 54 performs an iterative decoding operation. The memory management circuit 51 (error checking and correction circuit 54) can perform the decoding operation based on codeword 701. Specifically, an iteration operation is, for example, the memory management circuit 51 (error checking and correction circuit 54) completing a parity check operation (and decoding operation) for the complete codeword 701. For example, the memory management circuit 51 can sequentially calculate from column 1 to column 24 in codeword 701 to determine whether there is an error in codeword 701, and output codeword 701 in response to the absence of an error or attempt to correct the error in codeword 701 in response to the presence of an error, thus completing one iteration operation.

[0067] Generally, each iteration in the iterative decoding operation is performed based on all columns of codeword 701. However, the decoding capability of each column in codeword 701 is not the same, and the number of decoding operations required also varies. Error bits in the data may be successfully corrected during the decoding operation, causing the error to converge. For example, columns 1 to 6 of codeword 701 have the highest decoding capability (meaning that the decoding capability of the bits included in columns 1 to 6 is the highest), and the convergence speed of columns 1 to 6 of codeword 701 is the fastest. For example, columns 20 to 24 of codeword 701 have the lowest decoding capability (meaning that the decoding capability of the bits included in columns 20 to 24 is the lowest), and the convergence speed of columns 20 to 24 of codeword 701 is the slowest. For example, the bits in columns 1 to 6 of codeword 701 may converge within a predetermined number of iterations, meaning that erroneous bits in columns 1 to 6 of codeword 701 may be corrected within a predetermined number of iterations. In other words, erroneous bits in columns 7 to 24 of codeword 701 may require more iterations (more than the predetermined number) to be corrected.

[0068] As described above, conventional iterative decoding operations (i.e., performing each decoding operation based on all columns in codeword 701) may require unnecessary calculations for converged bits in subsequent iterations. Therefore, this invention provides a dynamic decoding method that can perform the corresponding decoding operation for the current iteration number, thereby improving decoding speed while maintaining error correction capabilities.

[0069] FIG8 is a flowchart illustrating a dynamic decoding method according to an exemplary embodiment of the present invention. Referring to FIG8, in step S801, the memory management circuit 51 can read codeword 701 from the physical unit of the rewritable non-volatile memory module 43. In an exemplary embodiment, the memory management circuit 51 can group codeword 701 into a first group GP1 and a second group GP2. Specifically, the memory management circuit 51 can group codeword 701 into the first group GP1 and the second group GP2 based on decoding capability, wherein the decoding capability of the first group GP1 is lower than that of the second group GP2. For example, the memory management circuit 51 can group codeword 701 based on the number of check nodes included in each column of codeword 701. For example, the memory management circuit 51 can group codeword 701 according to a predetermined number (e.g., 4). If the number of check nodes included in a column of codeword 701 is less than 4, then this column can be grouped into the first group GP1. Conversely, if a column in codeword 701 includes at least four check nodes, then this column can be grouped into the second group GP2. That is, the memory management circuit 51 can group columns 7 to 24 of codeword 701 into the first group GP1, and columns 1 to 6 of codeword 701 into the second group GP2. The value of the predetermined number can be designed according to actual needs; this invention is not limited by it.

[0070] In another embodiment, the memory management circuit 51 may, for example, group columns in codeword 701 with the same number of check nodes into the same group. For example, the memory management circuit 51 may group columns 1 to 6, columns 7 to 19, and columns 20 to 24 of codeword 701 into a group respectively. In another embodiment, the memory management circuit 51 may, for example, pre-group the data when performing an encoding operation based on the written data (or the data to be encoded) to distinguish between a group with weaker decoding capabilities and another group with stronger decoding capabilities, and store these two groups in the physical unit of the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 wants to read this physical unit, the memory management circuit 51 may first read the group with weaker decoding capabilities to perform the decoding operation.

[0071] In step S802, the memory management circuit 51 may determine whether the current iteration number is less than a predetermined number. In an exemplary embodiment, the memory management circuit 51 may determine whether the current iteration number is less than a predetermined number (e.g., 3 times) to decide whether to perform a decoding operation based on the complete codeword 701 or based on a portion of the codeword (e.g., the first group GP1).

[0072] If the current iteration number (e.g., the first iteration) is less than a predetermined number, proceed to step S803. At this time, it is the first iteration in the iterative decoding operation. Conversely, if the current iteration number is not less than the predetermined number, proceed to step S804. The value of the predetermined number can be designed according to actual needs; this invention is not limited by it.

[0073] In step S803, the memory management circuit 51 (error checking and correction circuit 54) may perform a decoding operation based on the first group GP1. In an exemplary embodiment, the memory management circuit 51 (error checking and correction circuit 54) may first perform a decoding operation on the first column of the first group GP1 (i.e., the seventh column of codeword 701), and then check whether the checksum data of the complete codeword 701 is equal to zero.

[0074] If the check data is equal to zero, it means that there is no error in codeword 701, and the memory management circuit 51 (error checking and correction circuit 54) can directly output codeword 701.

[0075] Conversely, if the check data is not equal to zero, it indicates that there is an error in the codeword 701. The memory management circuit 51 (error checking and correction circuit 54) can perform decoding operations on other columns of the first group GP1 (that is, columns 8 to 24 of codeword 701) to try to correct the error in the first group GP1, so that the error in the first group GP1 tends to converge.

[0076] It should be noted that, since the decoding capability of the first group GP1 is relatively low, the first group GP1 may need to be decoded multiple times before convergence. Therefore, the memory management circuit 51 (error checking and correction circuit 54) can perform decoding operations only on the first group GP1 within a predetermined number of iterations, while the second group GP2, which has a higher decoding capability and can converge quickly, can be decoded in subsequent iterations. In this way, the decoding speed can be effectively improved.

[0077] On the other hand, in step S804, the memory management circuit 51 (error checking and correction circuit 54) may perform a decoding operation based on the complete codeword 701. In an exemplary embodiment, the memory management circuit 51 (error checking and correction circuit 54) may first perform a decoding operation on the first column of the codeword 701, and then check whether the checksum data of the complete codeword 701 is equal to zero.

[0078] If the check data is equal to zero, it means that there is no error in codeword 701, and the memory management circuit 51 (error checking and correction circuit 54) can directly output codeword 701.

[0079] Conversely, if the check data is not equal to zero, it indicates that there is an error in codeword 701. The memory management circuit 51 (error checking and correction circuit 54) can perform decoding operations on other columns of codeword 701 (that is, columns 2 to 24 of codeword 701) to try to correct the error in codeword 701, so that the error in codeword 701 tends to converge. If all the errors in codeword 701 are corrected, the memory management circuit 51 (error checking and correction circuit 54) can output codeword 701.

[0080] Subsequently, after completing step S803 or step S804, the process proceeds to step S805. In step S805, the memory management circuit 51 (error checking and correction circuit 54) can determine whether decoding has been successful. Specifically, the memory management circuit 51 (error checking and correction circuit 54) can determine whether decoding has been successful based on whether it has output codeword 701. If the memory management circuit 51 (error checking and correction circuit 54) has output codeword 701, it indicates that decoding has been successful, and the dynamic decoding method in Figure 8 can be terminated.

[0081] Conversely, if the memory management circuit 51 (error checking and correction circuit 54) has not yet output code word 701, it means that the decoding has not been successful, and the process proceeds to step S806.

[0082] In step S806, the memory management circuit 51 (error checking and correction circuit 54) can determine whether the current iteration number has reached the termination number.

[0083] If the current iteration count has not reached the termination count, return to step S802.

[0084] Conversely, if the current iteration count reaches the termination count, it indicates that decoding has failed, and the dynamic decoding method of FIG8 ends. In an exemplary embodiment, the memory management circuit 51 (error checking and correction circuit 54) can continue to perform further decoding operations (e.g., soft bit decoding operation, Redundant Array of Independent Disks (RAID) decoding operation, etc.) after the dynamic decoding method of FIG8 ends.

[0085] According to the above, the dynamic decoding method in Figure 8 can perform decoding operations only on the first group GP1 with low decoding capability in codeword 701 when the current iteration number is less than a predetermined number, and perform decoding operations on the complete codeword 701 (i.e., the first group GP1 and the second group GP2) when the current iteration number is not less than a predetermined number. By reducing the number of decoding operations on the second group GP2 with high decoding capability, unnecessary calculations are avoided for converged bits. This can improve the decoding speed while maintaining the error correction capability.

[0086] Figure 9 is a schematic diagram of a lookup table according to an exemplary embodiment of the present invention. Referring to Figure 9, the lookup table 901 records the starting index value and the ending index value corresponding to the current iteration number. In an exemplary embodiment, the memory management circuit 51 can group the codeword 701 into a first group GP1 and a second group GP2. Specifically, the memory management circuit 51 can group the codeword 701 into a first group GP1 with low decoding capability and a second group GP2 with high decoding capability. The implementation details of grouping the codeword 701 into the first group GP1 and the second group GP2 have been clearly explained in the foregoing exemplary embodiments, and will not be repeated here. It should be noted that the codeword 701 can be grouped into at least two groups, and the number of groups can be designed according to actual needs; the present invention does not impose any limitations on this.

[0087] Subsequently, the memory management circuit 51 can establish a lookup table 901 based on the first group GP1 and the second group GP2. As shown in Figure 9, the lookup table 901 includes, but is not limited to, the current iteration number, the starting index value, and the ending index value. The starting index value is the index value corresponding to the starting column of a decoding operation, and the ending index value is the index value corresponding to the ending column of a decoding operation. N is the termination number of the iterative decoding operation. The value of the termination number (i.e., N) can be designed according to actual needs, and this invention is not limited thereto.

[0088] In an exemplary embodiment, in response to the current iteration number being less than a preset number (e.g., 6 times), the memory management circuit 51 may selectively not perform a decoding operation based on the complete codeword 701. As shown in FIG9, if the current iteration number is 1, 4, or 5, the start index value and the end index value are 6 and 23, respectively; and if the current iteration number is 2 or 3, the start index value and the end index value are 0 and 23, respectively. That is, the 1st iteration operation, the 4th iteration operation, and the 5th iteration operation are decoding operations performed based on columns 7 to 24 of codeword 701 (i.e., the first group GP1), and the 2nd iteration operation and the 3rd iteration operation are decoding operations performed based on columns 1 to 24 of codeword 701 (i.e., the complete codeword 701). Conversely, in response to the current iteration number being not less than a preset number (i.e., 6 times), the memory management circuit 5 may perform a decoding operation based on the complete codeword 701. In other words, if the current iteration number is one of 6 to N, the starting index value and the ending index value are 0 and 23 respectively, meaning that the 6th iteration operation to the Nth iteration operation is a decoding operation performed based on the complete codeword 701.

[0089] In an exemplary embodiment, after the memory management circuit 51 reads the codeword 701 from the rewritable non-volatile memory module 43, as shown in FIG9, the memory management circuit 51 (error checking and correction circuit 54) can perform the first iteration operation. As shown in FIG9, the memory management circuit 51 (error checking and correction circuit 54) can perform a decoding operation according to the first group GP1. Specifically, the memory management circuit 51 (error checking and correction circuit 54) can first perform a decoding operation on the first column of the first group GP1, and then check whether the check data of the codeword 701 is equal to zero. If the check data is equal to zero, it means that there is no error in the codeword 701, and the memory management circuit 51 (error checking and correction circuit 54) can directly output the codeword 701.

[0090] On the other hand, if the checksum data is not equal to zero, it indicates that there is an error in the codeword 701. The memory management circuit 51 (error checking and correction circuit 54) can perform decoding errors on other columns of the first group GP1, so that the errors in the first group GP1 gradually converge, thereby improving the decoding success rate. Afterwards, the memory management circuit 51 (error checking and correction circuit 54) can continue to perform the second iteration operation. As shown in FIG9, the memory management circuit 51 (error checking and correction circuit 54) can perform the decoding operation based on the complete codeword 701. The implementation details of performing the decoding operation based on the complete codeword 701 have been clearly explained in the aforementioned exemplary embodiments, and therefore will not be repeated here.

[0091] In other words, after completing the decoding operation based on the first group GP1 (i.e., the first iteration operation), in response to the checksum data of codeword 701 not being equal to zero (i.e., decoding has not yet succeeded), the memory management circuit 51 (error checking and correction circuit 54) can perform the decoding operation based on the complete codeword 701 (i.e., the second iteration operation). It should be noted that, since the memory management circuit 51 (error checking and correction circuit 54) performed the decoding operation on the first group GP1 in the first iteration operation, the errors in the first group GP1 tend to converge, thereby improving the decoding success rate. Therefore, in the second iteration operation, the memory management circuit 51 (error checking and correction circuit 54) can instead perform the decoding operation based on the complete codeword 701. Since the errors in the first group GP1 have converged, there is a chance that decoding will succeed.

[0092] As described above, the memory management circuit 51 can establish a lookup table 901 based on the decoding capabilities of all columns of the codeword 701 and actual needs. In response to the current iteration number being less than a preset number, it can selectively reduce the decoding operations performed based on the complete codeword 701, thereby improving the decoding speed while maintaining the error correction capability.

[0093] FIG10 is a flowchart illustrating a dynamic decoding method according to an exemplary embodiment of the present invention. Referring to FIG10, in step S1001, a first codeword is read from a physical cell of a rewritable non-volatile memory module, wherein the first codeword includes at least two groups. In step S1002, a decoding operation is performed according to a first group of the first codeword. In step S1003, during the decoding operation, it is checked whether the checksum data of the first codeword is equal to zero. In step S1004, in response to the checksum data being equal to zero, the first codeword is output.

[0094] However, the steps in Figure 10 have been described in detail above, and will not be repeated here. It is worth noting that each step in Figure 10 can be implemented as multiple pieces of code or circuits, and the present invention is not limited thereto. In addition, the method in Figure 10 can be used in conjunction with the above exemplary embodiments, or it can be used alone, and the present invention is not limited thereto.

[0095] In summary, the dynamic decoding method, memory storage device, and memory control circuit unit provided in the exemplary embodiments of the present invention can selectively perform decoding operations only on the first group of codewords with low decoding capabilities when the current iteration number is less than a predetermined number, and perform decoding operations on the complete codeword when the current iteration number is not less than a predetermined number. This avoids unnecessary calculations for converged bits, thereby improving decoding speed while maintaining error correction capabilities. [Simplified Explanation of the Diagram]

[0096] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention. Figure 3 is a schematic diagram of a host system and memory storage device according to an exemplary embodiment of the present invention. Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 7 is a schematic diagram of a codeword according to an exemplary embodiment of the present invention. Figure 8 is a flowchart of a dynamic decoding method according to an exemplary embodiment of the present invention. Figure 9 is a schematic diagram of a lookup table according to an exemplary embodiment of the present invention. Figure 10 is a flowchart of a dynamic decoding method according to an exemplary embodiment of the present invention.

Claims

1. A dynamic decoding method for a rewritable non-volatile memory module, the dynamic decoding method comprising: A first codeword is read from a physical unit of the rewritable non-volatile memory module, wherein the first codeword comprises at least two groups; Perform a decoding operation based on the first group of the first codeword; determine whether the current iteration number of the decoding operation is less than a predetermined number; in response to the current iteration number being less than the predetermined number, perform the decoding operation based on the first group; in the decoding operation, check whether the checksum data of the first codeword is equal to zero; and in response to the checksum data being equal to zero, output the first codeword.

2. The dynamic decoding method as described in claim 1 further includes: After completing the decoding operation performed according to the first group, in response to the check data not being equal to zero, the decoding operation is performed according to the complete first codeword.

3. The dynamic decoding method as described in claim 1 further includes: In response to the current iteration number being not less than the predetermined number, the decoding operation is performed based on the complete first codeword.

4. The dynamic decoding method as described in claim 1, wherein the decoding capabilities of the at least two groups are different, and the decoding capability of the first group is lower than that of the second group of the first codeword.

5. The dynamic decoding method as described in claim 1 further includes: A lookup table is established based on the at least two groups; And query the lookup table based on the current iteration number of the decoding operation to determine whether to perform the decoding operation based on one of the at least two groups or the complete first codeword.

6. A memory storage device, comprising: A connection interface unit for coupling to the host system; Rewritable non-volatile memory modules; The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: issue a read instruction sequence to the rewritable non-volatile memory module, the read instruction sequence being configured to instruct the reading of a first codeword from a physical unit of the rewritable non-volatile memory module, wherein the first codeword comprises at least two groups; perform a decoding operation based on a first group of the first codeword; determine whether the current iteration number of the decoding operation is less than a predetermined number; in response to the current iteration number being less than the predetermined number, perform the decoding operation based on the first group; in the decoding operation, check whether the checksum data of the first codeword is equal to zero; and in response to the checksum data being equal to zero, output the first codeword.

7. The memory storage device as claimed in claim 6, wherein the memory control circuit unit is further configured to: after completing the decoding operation performed according to the first group, in response to the check data not being equal to zero, perform the decoding operation based on the complete first codeword.

8. The memory storage device as claimed in claim 6, wherein the memory control circuit unit is further configured to: perform the decoding operation based on the complete first codeword in response to the current iteration number being not less than the predetermined number.

9. The memory storage device as claimed in claim 6, wherein the decoding capabilities of the at least two groups are different, and the decoding capability of the first group is lower than that of the second group of the first codeword.

10. The memory storage device of claim 6, wherein the memory control circuit unit is further configured to: establish a lookup table based on the at least two groups; and query the lookup table according to the current iteration number of the decoding operation to determine whether to perform the decoding operation based on one of the at least two groups or the complete first codeword.

11. A memory control circuit unit disposed in a memory storage device, the memory control circuit unit comprising: The host interface is used to couple to the connection interface unit; A memory interface for coupling to a rewritable, non-volatile memory module; The system also includes a memory management circuit coupled to the host interface and the memory interface, wherein the memory management circuit is configured to: issue a read instruction sequence to the rewritable non-volatile memory module, the read instruction sequence instructing the reading of a first codeword from a physical cell of the rewritable non-volatile memory module, wherein the first codeword comprises at least two groups; perform a decoding operation based on a first group of the first codeword; determine whether the current iteration number of the decoding operation is less than a predetermined number; in response to the current iteration number being less than the predetermined number, perform the decoding operation based on the first group; in the decoding operation, check whether the checksum data of the first codeword is equal to zero; and in response to the checksum data being equal to zero, output the first codeword.

12. The memory control circuit unit as claimed in claim 11, wherein the memory management circuit is further configured to: after completing the decoding operation performed according to the first group, in response to the check data not being equal to zero, perform the decoding operation based on the complete first codeword.

13. The memory control circuit unit as claimed in claim 11, wherein the memory management circuit is further configured to: perform the decoding operation based on the complete first codeword in response to the current iteration number being not less than the predetermined number.

14. The memory control circuit unit as claimed in claim 11, wherein the decoding capabilities of the at least two groups are different, and the decoding capability of the first group is lower than that of the second group of the first codeword.

15. The memory control circuit unit of claim 11, wherein the memory management circuit is further configured to: establish a lookup table based on the at least two groups; and query the lookup table according to the current iteration number of the decoding operation to determine whether to perform the decoding operation based on one of the at least two groups or the complete first codeword.

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