Artificial intelligence integrated circuit system configured with stacked three-dimensional memory devices

Abstract

A stacked AI engine system using three-dimensional (3D) memory devices. The system includes one or more memory integrated circuit (IC) devices coupled to a logic IC device in a stacked configuration. The memory ICs each include a plurality of first memory devices configured on a first semiconductor substrate and the logic IC includes multiple chiplets, each having multiple gangs, and each gang having multiple slices configured on a second semiconductor substrate. Each slice includes a first network-on-chip (NoC) device coupled to one of the first memory devices, a second NoC device coupled to a second memory device, multiple compute engine devices coupled to the NoC devices, an output buffer (OB) device coupled to compute engines, and a single instruction, multiple data (SIMD) device coupled to the OB device. These IC devices can be configured overlying an organic substrate member and coupled to each other via interconnections in underfill layers.

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