Memory device and method for manufacturing the same

Abstract

A memory device and a method for manufacturing the same are provided. The memory device includes a substrate, a first stacked structure, a second stacked structure, at least one transistor and a metal routing layer. The substrate includes an array region and a peripheral region. The first stacked structure is in the array region. The first stacked structure includes a first conductive layer, a second conductive layer and an insulating layer between the first conductive layer and the second conductive layer. The first conductive layer, the insulating layer and the second conductive layer are stacked along a first direction. The second stacked structure is in the peripheral region. The at least one transistor is in the second stacked structure. The at least one transistor includes a conductive film, a dielectric film and a semiconductor film stacked along the first direction. The metal routing layer is above the first stacked structure and the second stacked structure. The metal routing layer is electrically connected to the at least one transistor, the first conductive layer and the second conductive layer.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of manufacturing them, and more particularly to memory devices and methods of manufacturing them. Prior Technology

[0002] Generally, a memory device comprises multiple memory cells (forming a memory array) located in the array region and peripheral circuitry located in the peripheral region. The peripheral circuitry is electrically connected to the memory array to operate the memory cells. The sequence of manufacturing steps in a memory device can limit its design. For example, process temperature may restrict the material selection for components in the memory device, leading to poor performance. Summary of the Invention

[0003] The present invention provides a memory device and a method for manufacturing the same, which allows for better integration of the peripheral area and the array area without limiting the design choices of the peripheral area and the array area due to the manufacturing process, thereby improving the performance of the memory device.

[0004] According to some embodiments of the present invention, a memory device is provided. The memory device includes a substrate, a first stacked structure, a second stacked structure, at least one transistor, and a metal winding layer. The substrate includes an array region and a peripheral region. The first stacked structure is located in the array region. The first stacked structure includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The first conductive layer, the insulating layer, and the second conductive layer are stacked along a first direction. The second stacked structure is located in the peripheral region. At least one transistor is located in the second stacked structure. The at least one transistor has a conductive film, a dielectric film, and a semiconductor film stacked along the first direction. The metal winding layer is located above the first stacked structure and the second stacked structure. The metal winding layer is electrically connected to the at least one transistor, the first conductive layer, and the second conductive layer.

[0005] According to some embodiments of the present invention, a method for manufacturing a memory device is provided. The method includes: providing a substrate including an array region and a peripheral region; forming a layer stack in the array region, the layer stack including a semiconductor material layer, a dielectric layer, and an insulating layer between the semiconductor material layer and the dielectric layer; forming a channel pillar penetrating the layer stack; forming an extension adjacent to the layer stack, wherein the extension includes a plurality of semiconductor layers stacked and extending along a first direction and a second direction, the first direction being perpendicular to the second direction; and forming at least one transistor in the peripheral region, the at least one transistor including a stacked conductive film, a dielectric film, and a semiconductor film.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0007] Figure 1 is a cross-sectional schematic diagram illustrating a memory device according to one embodiment of the present invention; Figure 2A shows the circuit diagram of the memory device in Figure 1; Figure 2B illustrates the critical voltage distribution of the memory device in Figure 1; Figure 3 is a cross-sectional schematic diagram of a memory device according to another embodiment of the present invention; Figures 4 through 23 are schematic cross-sectional views illustrating multiple stages of a method for manufacturing a memory device according to some embodiments of the present invention; and Figures 24 to 37 are schematic cross-sectional views illustrating multiple stages of a method for manufacturing a memory device according to some embodiments of the present invention. Implementation

[0008] The drawings are simplified to clearly illustrate the embodiments, and the dimensions in the drawings are not drawn to scale with the actual product. In the following manufacturing methods, there may be one or more additional operations between the operations, and the order of the operations may vary. Therefore, the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of the invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0009] The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order in the structure; these ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "above," "above," "higher than," "top," "below," "below," "below," "lower than," "bottom," etc., describe the relative spatial or positional relationship between one element and another in the drawings, and these spatial or positional relationships can be direct or indirect (with other elements disposed between the two elements), unless otherwise specified. Spatial terms may cover structures shown in other orientations, not limited to the orientation shown in the drawings. Structures can be flipped or rotated at various angles, and the spatial descriptions used herein can be interpreted accordingly. The singular forms "a," "an," "the," and "described" used in the specification and claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The use of "and / or" in the specification and the claims includes any and all combinations of one or more of the listed items.

[0010] Furthermore, the term "electrical connection" used in the specification and accompanying claims can mean multiple elements forming an ohmic contact, current flowing between multiple elements, or multiple elements having an operational relationship. An operational relationship can be, for example, one element driving another element, but current may not flow directly between the two elements. The term "adjacent" used in the specification and accompanying claims means "adjacent and in contact." The term "deposition" used in the specification and accompanying claims includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and epitaxial growth. Depending on the type of material to be formed, those skilled in the art can select a suitable technique for forming the material. The terms "etching" and "etch-back" used in the specification and accompanying claims include, but are not limited to, dry etching and wet etching. The term "grinding" used in the specification and accompanying claims includes, but is not limited to, chemical-mechanical planarization (CMP) and ion milling. The terms "etching," "re-etching," and "grinding" used in the specification and accompanying patent application are interchangeable. Those skilled in the art can select a suitable removal technique based on the structure and material.

[0011] The embodiments of this invention can be applied to various types of three-dimensional memory devices. For example, multiple embodiments of this invention can be applied to, but are not limited to, NAND memory devices, NOR memory devices, or any type of memory device. Embodiments of this invention can be applied to memory devices employing a CMOS near array (CNA) architecture, that is, the array region (where the memory array is disposed) and the peripheral region (where the peripheral circuitry is disposed) of the memory device are disposed side-by-side on the same wafer. The following describes various embodiments of this invention using an NOR memory device as an example, but this invention is not limited to a specific type of device.

[0012] Please refer to Figure 1. Figure 1 is a cross-sectional schematic diagram illustrating a memory device 10 according to an embodiment of the present invention. The memory device 10 includes a substrate 100, at least one stacked structure 110, at least one stacked structure 120, at least one transistor 130, and at least one metal winding layer 140 located above the stacked structures 110 and 120. The substrate 100 includes an array region 101 and a peripheral region 102. The peripheral region 102 may be disposed near the array region 101. The peripheral region 102 may be adjacent to the array region 101. The array region 101 and the peripheral region 102 may be disposed along a second direction D2 and / or a third direction D3. The stacked structure 110 is located in the array region 101. The stacked structure 110 is disposed on the substrate 100 along a first direction D1. The stacked structure 110 may include a conductive layer 112, a conductive layer 114, and an insulating layer 113 disposed between the conductive layers 112 and 114. Conductive layer 112, insulating layer 113, and conductive layer 114 can be stacked along a first direction D1. A stacked structure 120 is located in the peripheral region 102. The stacked structure 120 is disposed on the substrate 100 along the first direction D1. The stacked structure 120 can be disposed on one side of the stacked structure 110 along a second direction D2 and / or a third direction D3. The stacked structure 120 can be adjacent to the stacked structure 110. A transistor 130 is located in the stacked structure 120. The transistor 130 has a conductive film 1331, a dielectric film 1333, and a semiconductor film 1332 stacked along the first direction D1. A metal winding layer 140 can electrically connect the transistor 130, conductive layer 112, and conductive layer 114. The first direction D1, the second direction D2, and the third direction D3 can be perpendicular to each other. For example, the first direction D1 may be the normal direction of the surface of the substrate 100 facing the stacked structures 110 and 120, and the second direction D2 and the third direction D3 may be parallel to the surface of the substrate 100. The transistor 130 may be part of the peripheral circuitry of the memory device 10. The peripheral circuitry of the memory device 10 may also include other active and / or passive semiconductor elements, such as transistors, diodes, capacitors, resistors, etc.

[0013] The stacked structure 110 may further include an insulating layer 111, an insulating layer 115, an insulating layer 116, and a barrier layer 117. The insulating layer 111, conductive layer 112, insulating layer 113, conductive layer 114, and insulating layer 115 may be sequentially stacked on the substrate 100 along a first direction D1. The insulating layer 111 may be disposed between the conductive layer 112 and the substrate 100. The conductive layer 112 is closer to the substrate 100 than the conductive layer 114. The barrier layer 117 may be disposed on or cover the upper surface, lower surface, and sidewalls of the conductive layer 112, the upper surface, lower surface, and sidewalls of the conductive layer 114. The lower surfaces of the conductive layers 112 and 114 face the substrate 100. The barrier layer 117 may be located between the insulating layer 111 and the conductive layer 112. Barrier layer 117 may be located between conductive layer 112 and insulating layer 113. Barrier layer 117 may be located between insulating layer 113 and conductive layer 114. Barrier layer 117 may be located between conductive layer 114 and insulating layer 115. Barrier layer 117 may be located between insulating layer 116 and conductive layer 112. Barrier layer 117 may be located between insulating layer 116 and conductive layer 114. Insulating layer 116 may be disposed on top of conductive layer 112 in a first direction D1. Insulating layer 116 may be disposed on one side of conductive layer 114 in a second direction D2 and / or a third direction D3. Insulating layer 116 may be adjacent to insulating layer 113 and insulating layer 115.

[0014] The stacked structure 120 may include an insulating film 121, a deflection portion 122, and an insulating film 123. The deflection portion 122 may be adjacent to one end of the conductive layer 112. The deflection portion 122 may include multiple semiconductor layers, such as semiconductor layer 1221 and semiconductor layer 1222, stacked and extending along a first direction D1 and a second direction D2. The number of semiconductor layers included in the deflection portion 122 is not limited to the number shown in Figure 1; the deflection portion 122 may include two or more semiconductor layers. On the plane formed by the first direction D1 and the second direction D2, semiconductor layer 1221 and semiconductor layer 1222 may have an L-shaped cross-section. Semiconductor layer 1221 and semiconductor layer 1222 may extend on the plane formed by the second direction D2 and the third direction D3, and may also extend on the plane formed by the first direction D1 and the third direction D3. Semiconductor layer 1222 may be disposed on semiconductor layer 1221. The insulating film 123 may be disposed on semiconductor layer 1222. The insulating film 123 may be adjacent to the upper surface of the semiconductor layer 1222 and the sidewall facing away from the stacked structure 110. The semiconductor layer 1221 may be adjacent to the sidewall of the insulating layer 116, the sidewall of the barrier layer 117, and the sidewall of the insulating layer 111. The deflection portion 122 and the insulating film 123 may be located between the insulating film 121 and the stacked structure 110.

[0015] Transistor 130 has a source 131, a drain 132, and a gate 133. The gate 133 is disposed between the source 131 and the drain 132. The source 131 and the drain 132 are located in the substrate 100. The gate 133 is located on the substrate 100. The gate 133 may be formed of a conductive film 1331, a dielectric film 1333, and a semiconductor film 1332. The semiconductor film 1332 may be disposed between the conductive film 1331 and the dielectric film 1333. The dielectric film 1333, the semiconductor film 1332, and the conductive film 1331 may be stacked sequentially along a first direction D1. In this embodiment, the semiconductor film 1332 has a multilayer structure, comprising semiconductor material films 1332A and 1332B stacked along the first direction D1. However, the invention is not limited thereto; the semiconductor film 1332 may have three or more layers of semiconductor material films, or it may have a single-layer structure. In this embodiment, the dielectric films 1333 of the two transistors 130 shown in Figure 1 have different heights along the first direction D1, but the invention is not limited thereto.

[0016] The memory device 10 may further include at least one channel post 150, a plurality of memory cells MS, a plurality of shallow trench isolation (STI) structures 170, at least one source contact structure 171, at least one drain contact structure 172, at least one gate contact structure 173, at least one conductive contact structure 174, at least one conductive contact structure 175, at least one channel contact structure 176, at least one dielectric film 177, at least one conductive post 178, at least one spacer element 181, at least one spacer element 182, a cover layer 183, at least one isolation element 1711, at least one isolation element 1721, at least one isolation element 1731, at least one isolation element 1781, and interlayer insulating layers 191 and 192. Interlayer insulating layers 191 and 192 may extend on the plane formed by the second direction D2 and the third direction D3 and span the array region 101 and the peripheral region 102. Interlayer insulating layer 191 and interlayer insulating layer 192 can be disposed between stacked structure 110 and metal winding layer 140, and can also be disposed between stacked structure 120 and metal winding layer 140. Interlayer insulating layer 191 and interlayer insulating layer 192 can be stacked sequentially along the first direction D1.

[0017] Channel post 150 may extend along a direction opposite to the first direction D1 (e.g., a negative first direction D1) and penetrate the stack structure 110. Channel post 150 may be disposed in array region 101 and on substrate 100. Channel post 150 may include insulating post 151, channel layer 152, charge storage layer 153, and pad 154. Channel layer 152 may be tubular and surround insulating post 151. Charge storage layer 153 may be tubular and surround channel layer 152 and insulating post 151. Outer wall of charge storage layer 153 may contact insulating layer 111, insulating layer 113, insulating layer 115, and barrier layer 117. Barrier layer 117 may isolate channel post 150 from conductive layer 112 and conductive layer 114. Pad 154 may be disposed at or in contact with first end of insulating post 151, first end of channel layer 152, and first end of charge storage layer 153. The second end of the insulating pillar 151 (relative to the first end), the second end of the channel layer 152 (relative to the first end), and the second end of the charge storage layer 153 (relative to the first end) are contactable with the substrate 100. A plurality of memory cells MS are located between the conductive layer 114 and the channel pillar 150.

[0018] A plurality of shallow trench isolations 170 may be disposed in the substrate 100. The plurality of shallow trench isolations 170 are disposed in the peripheral region 102 and located below the stacked structure 120. The plurality of shallow trench isolations 170 may be alternately distributed with transistors 130. The shallow trench isolations 170 can electrically isolate the plurality of transistors 130 from each other.

[0019] Source contact structure 171 and drain contact structure 172 may extend to the surface of substrate 100 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Source contact structure 171 may extend to the surface of source electrode 131 of transistor 130 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Drain contact structure 172 may extend to the surface of drain electrode 132 of transistor 130 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Gate contact structure 173 may extend to the surface of gate electrode 133 of transistor 130 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Source contact structure 171, drain contact structure 172 and gate contact structure 173 may be disposed separately on substrate 100. Source contact structure 171, drain contact structure 172 and gate contact structure 173 may penetrate stack structure 120, interlayer insulating layer 191 and interlayer insulating layer 192. Source contact structure 171 is electrically connected to the source 131 of transistor 130. Drain contact structure 172 is electrically connected to the drain 132 of transistor 130. Gate contact structure 173 is electrically connected to the gate 133 of transistor 130. In this embodiment, the height 171H of source contact structure 171 from substrate 100 and the height 172H of drain contact structure 172 from substrate 100 are greater than the height 150H of channel post 150 from substrate. Heights 171H, 172H, and 150H are in the first direction D1. Height 171H can also be understood as the distance between the upper surface of source contact structure 171 and the upper surface of source 131. Height 172H can also be understood as the distance between the upper surface of drain contact structure 172 and the upper surface of drain 132. Height 150H can also be understood as the distance between the upper surface of pad 154 and the surface of substrate 100.

[0020] Isolating elements 1711, 1721, and 1731 are on substrate 100. Isolating elements 1711, 1721, and 1731 can penetrate the stacked structure 120 and the interlayer insulating layer 191. Isolating element 1711 can be disposed on the sidewall of source contact structure 171. Isolating element 1711 can surround source contact structure 171. Source contact structure 171 can extend beyond isolation element 1711. Isolating element 1721 can be disposed on the sidewall of drain contact structure 172. Isolating element 1721 can surround drain contact structure 172. Drain contact structure 172 can extend beyond isolation element 1721. Isolating element 1731 can be disposed on the sidewall of gate contact structure 173. Isolating element 1731 can surround gate contact structure 173. Gate contact structure 173 can extend beyond isolation element 1731. In this embodiment, the upper surfaces of isolation elements 1711, 1721 and 1731 can be at the same height as the upper surface of the interlayer insulating layer 191.

[0021] Spacer elements 181, 182, and a capping layer 183 are disposed on substrate 100. Spacer elements 181, 182, and a capping layer 183 are disposed in peripheral region 102. Spacer elements 181, 182, and a capping layer 183 are disposed in stacked structure 120. Spacer element 181 may be located on the sidewall of gate 133 of transistor 130. Spacer element 181 may be disposed on opposite sidewalls of gate 133. Spacer element 181 may be located on the sidewalls of conductive film 1331 and semiconductor film 1332 of gate 133 of transistor 130. Spacer element 181 may be located above dielectric film 1333 of gate 133. Spacer element 181 may be located between source 131 and semiconductor film 1332. Spacer element 181 may be located between drain 132 and semiconductor film 1332. Spacer element 181 can contact dielectric film 1333, semiconductor film 1332, conductive film 1331, and isolation element 1731. In the first direction D1, one end of spacer element 181 may be higher than the upper surface of conductive film 1331. Spacer element 182 may be disposed on the sidewall of the deflection portion 122 and the sidewall of insulating film 123. Spacer element 182 may be located at the end of the deflection portion 122 away from conductive layer 112. Spacer element 182 may be disposed above dielectric film 177. The height of spacer element 181 in the first direction D1 may be substantially the same as the height of spacer element 182 in the first direction D1. Cover layer 183 may cover spacer element 181, spacer element 182, and shallow trench isolation 170. Cover layer 183 may cover dielectric film 177. Cover layer 183 may be located between insulating film 121 and spacer element 182. Cover layer 183 may be located between insulating film 121 and dielectric film 177. The cover layer 183 may be located between the insulating film 121 and the shallow trench isolation 170. The cover layer 183 may be located between the insulating film 121 and the spacer element 181.

[0022] A dielectric film 177 is disposed in the peripheral region 102 and below the stacked structure 120. The dielectric film 177 may extend from the boundary of the peripheral region 102 to the shallow trench isolation 170. In this embodiment, the height of the dielectric film 177 in the first direction D1 is the same as or substantially the same as the height of the dielectric film 1333 of the transistor 130 adjacent to the dielectric film 177 in the first direction D1, but the invention is not limited thereto.

[0023] Conductive pillars 178 are disposed on substrate 100. Conductive pillars 178 are disposed in array region 101. Conductive pillars 178 can penetrate stacked structure 110, interlayer insulating layer 191, and interlayer insulating layer 192. Conductive pillars 178 can extend to the surface of substrate 100 in a direction opposite to the first direction D1 (e.g., a negative first direction D1). Conductive pillars 178 can be electrically connected to substrate 100. Isolation element 1781 is on substrate 100. Isolation element 1781 can penetrate stacked structure 110 and interlayer insulating layer 191. Isolation element 1781 can be disposed on the sidewall of conductive pillar 178. Isolation element 1781 can surround conductive pillar 178. Conductive pillar 178 can extend beyond isolation element 1781.

[0024] Conductive contact structures 174 and 175 are disposed separately on the substrate 100. Conductive contact structures 174 and 175 are disposed in the array region 101. Conductive contact structure 174 is above conductive layer 112. Conductive contact structure 174 can land on or contact conductive layer 112. Conductive contact structure 174 can penetrate interlayer insulating layer 192, interlayer insulating layer 191, insulating layer 116, and a portion of barrier layer 117 on the upper surface of conductive layer 112 and is electrically connected to conductive layer 112. Conductive contact structure 175 is above conductive layer 114. Conductive contact structure 175 can land on or contact conductive layer 114. Conductive contact structure 175 can penetrate interlayer insulating layer 192, interlayer insulating layer 191, insulating layer 115, and a portion of barrier layer 117 on the upper surface of conductive layer 114 and is electrically connected to conductive layer 114. The height 171H of the source contact structure 171 from the substrate 100 and the height 172H of the drain contact structure 172 from the substrate 100 can be greater than the height 178H of the conductive pillar 178 from the substrate 100. The height 178H is in the first direction D1. The height 178H can also be understood as the distance between the upper surface of the conductive pillar 178 and the surface of the substrate 100.

[0025] Channel contact structure 176 is on substrate 100. Channel contact structure 176 is disposed in array region 101. Channel contact structure 176 is above channel pillar 150 and stack structure 110. Channel contact structure 176 may extend along a first direction D1 and penetrate interlayer insulating layer 191 and interlayer insulating layer 192. Channel contact structure 176 may be disposed between channel pillar 150 and metal winding layer 140.

[0026] The metal winding layer 140 may include an insulating material 142 and a plurality of conductors 141 disposed in the insulating material 142. One of the plurality of conductors 141 may be electrically connected to a source 131 via a source contact structure 171. One of the plurality of conductors 141 may be electrically connected to a drain 132 via a drain contact structure 172. One of the plurality of conductors 141 may be electrically connected to a gate 133 via a gate contact structure 173. One of the plurality of conductors 141 may be electrically connected to a substrate 100 via a conductive post 178. Conductive contact structures 174 and 175 are electrically connected to the conductors 141 of the metal winding layer 140. One of the plurality of conductors 141 may be electrically connected to a conductive layer 112 via a conductive contact structure 174. One of the plurality of conductors 141 may be electrically connected to a conductive layer 114 via a conductive contact structure 175. One of the plurality of conductors 141 may be electrically connected to a channel post 150 via a channel contact structure 176.

[0027] The number of components included in the memory device 10 is not limited to the number shown in Figure 1, and the number of each component can be increased or decreased as needed.

[0028] The transistor formed at the intersection of conductive layer 112 and channel post 150 can serve as a selection transistor, and conductive layer 112 can serve as a selection gate line. The transistor formed at the intersection of conductive layer 114 and channel post 150 can serve as a data storage transistor, and conductive layer 114 can serve as a word line. The wire 141 electrically connected to channel post 150 in metal winding layer 140 can serve as a bit line.

[0029] Please refer to both Figure 1 and Figure 2A. Figure 2A is a circuit diagram of the memory device 10 in Figure 1. Figure 2A shows four data storage transistors TD1~TD4 and four selection transistors TS1~TS4. Data storage transistor TD1 is connected in series with selection transistor TS1. Data storage transistor TD2 is connected in series with selection transistor TS2. Data storage transistor TD3 is connected in series with selection transistor TS3. Data storage transistor TD4 is connected in series with selection transistor TS4. Data storage transistor TD1 and selection transistor TS1 form a memory cell MS and are electrically connected between bit line BL1 and common source line CSL. Data storage transistor TD2 and selection transistor TS2 form a memory cell MS and are electrically connected between bit line BL2 and common source line CSL. Data storage transistor TD3 and selection transistor TS3 form a memory cell MS and are electrically connected between bit line BL1 and common source line CSL. Data storage transistor TD4 and select transistor TS4 form a memory cell MS and are electrically connected between bit line BL2 and common source line CSL. Data storage transistors TD1 and TD2 are electrically connected to word line MG1. Select transistors TS1 and TS2 are electrically connected to select gate line SG1. Data storage transistors TD3 and TD4 are electrically connected to word line MG2. Select transistors TS3 and TS4 are electrically connected to select gate line SG2. For example, the operation of memory device 10 may include: applying a voltage to bit line BL1 and common source line CSL electrically connected to data storage transistor TD1 and select transistor TS1, applying a voltage to word line MG1 electrically connected to data storage transistor TD1, and applying a voltage to select gate line SG1 electrically connected to select transistor TS1 to perform read, write, or erase operations.

[0030] Please refer to Figure 2B. Figure 2B shows the critical voltage distribution for the memory device 10 in Figure 1 in write and erase states. In Figure 2B, the horizontal axis represents the critical voltage Vt, and the vertical axis represents the number of memory cells. The read voltage V_read in Figure 2B is applied to the word line during a read operation to identify the data stored in the memory cell. The read voltage V_read is typically set between the erase voltage and the write voltage. In a comparative example where the memory cell does not contain a select transistor, the erase voltage is set slightly higher than 0 V to prevent the data storage transistor from being normally ON, and the write voltage must be set to a higher value to ensure that the memory device has sufficient sensing margin for read operations, thus requiring the use of a charge pump circuit to boost the voltage. In the memory device of the present invention, since the memory cell includes a data storage transistor and a select transistor, and the select transistor can be used to turn the data storage transistor on or off, the critical voltage distribution of the data storage transistor in the erase state can be set to a lower value (compared to the comparative example). For example, the critical voltage distribution of the data storage transistor in the erase state can be set to below 0 V (as shown in Figure 2B), and the critical voltage distribution of the data storage transistor in the write state can also be set to a lower value (compared to the comparative example). Even if such a critical voltage distribution setting may cause the data storage transistor to be in a normally on state, leakage can be avoided by turning off the select transistor. Therefore, the memory device of the present invention can achieve a lower read voltage (e.g., the read voltage can be set to the supply voltage Vdd) and a lower write voltage, eliminating the need for a charge pump circuit to boost the voltage, shortening the word line setup time, simplifying circuit design, and accelerating operation speed. The memory device of the present invention is beneficial for low-power, high-speed applications.

[0031] Please refer to Figure 3. Figure 3 is a cross-sectional schematic diagram illustrating a memory device 20 according to another embodiment of the present invention. The memory device 20 differs from the memory device 10 shown in Figure 1 in that the memory device 20 further includes a conductive portion 324, and the memory device 20 uses a conductive film 3331 instead of the conductive film 1331 of the memory device 10. The memory device 20 may include a substrate 100, at least one stacked structure 110, at least one stacked structure 320, at least one transistor 330, at least one metal winding layer 140 located above the stacked structures 110 and 320, at least one channel post 150, a plurality of memory cells MS, a plurality of shallow trench isolations 170, at least one source contact structure 171, at least one drain contact structure 172, at least one gate contact structure 173, at least one conductive contact structure 174, at least one conductive contact structure 175, at least one channel contact structure 176, at least one dielectric film 177, at least one conductive post 178, at least one spacer element 181, at least one spacer element 182, a cover layer 183, at least one isolation element 1711, at least one isolation element 1721, at least one isolation element 1731, at least one isolation element 1781, an interlayer insulating layer 191, and an interlayer insulating layer 192.

[0032] A stacked structure 320 is located in the peripheral region 102. The stacked structure 320 is disposed on the substrate 100 along a first direction D1. The stacked structure 320 may be disposed on one side of the stacked structure 110 along a second direction D2 and / or a third direction D3. The stacked structure 320 may be adjacent to the stacked structure 110. The stacked structure 320 includes an insulating film 121, a deflection portion 122, an insulating film 123, and a conductive portion 324. The conductive portion 324 is disposed between the insulating film 123 and the deflection portion 122. The conductive portion 324 may extend along the first direction D1 and the second direction D2 and is stacked on the deflection portion 122. The conductive portion 324 may have an L-shaped cross-section in the plane formed by the first direction D1 and the second direction D2. The conductive portion 324 may extend in the plane formed by the second direction D2 and the third direction D3, and may also extend in the plane formed by the first direction D1 and the third direction D3. A transistor 330 is located in the peripheral region 102. Transistor 330 is located in stacked structure 320. Transistor 330 includes a source 131, a drain 132, and a gate 333 disposed between the source 131 and the drain 132. Gate 333 includes a dielectric film 1333, a semiconductor film 1332, and a conductive film 3331 sequentially stacked along a first direction D1. Gate contact structure 173 may be disposed on conductive film 3331. Gate contact structure 173 may contact conductive film 3331. Metal winding layer 140 may be electrically connected to gate 333 of transistor 330 through gate contact structure 173. The material of conductive film 3331 of memory device 20 may be different from the material of conductive film 1331 of memory device 10. Conductive portion 324 and conductive film 3331 may contain the same material or different materials. Transistor 330 may be part of peripheral circuitry of memory device 20. The peripheral circuitry of memory device 20 may also include other active and / or passive semiconductor components, such as transistors, diodes, capacitors, resistors, etc. The circuit diagram and critical voltage distribution during operation of memory device 20 are similar to those of memory device 10.

[0033] In one embodiment, in array region 101, the stacked structure of memory device 10 and memory device 20 may include only two stacked transistors (one data storage transistor and one selection transistor) in the first direction D1, without including any additional transistors stacked along the first direction D1. In one embodiment, memory device 10 and memory device 20 may be low-power, high-efficiency, and low-density (compared to reverse-intercept memory devices) memory devices.

[0034] Figures 4 through 23 are schematic cross-sectional views illustrating multiple stages of a method for manufacturing a memory device according to some embodiments of the present invention. The steps shown in Figures 4 through 23 may be performed sequentially or in other orders, and the present invention is not limited thereto.

[0035] Please refer to Figure 4. Figure 4 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. A substrate 100 is provided, comprising an array region 101 and a peripheral region 102. A layer stack 410 is formed in the array region 101 and the peripheral region 102. The layer stack 410 is disposed on the substrate 100 along a first direction D1. The layer stack 410 may extend in a plane formed by a second direction D2 and a third direction D3 and span the array region 101 and the peripheral region 102. The layer stack 410 may include an insulating layer 411, a semiconductor material layer 412, an insulating layer 413, a dielectric layer 414, and an insulating layer 415. The insulating layer 411 may be disposed between the substrate 100 and the semiconductor material layer 412. The insulating layer 413 may be disposed between the semiconductor material layer 412 and the dielectric layer 414. The insulating layer 415 may be disposed on the side of the layer stack 410 away from the substrate 100. An insulating layer 411, a semiconductor material layer 412, an insulating layer 413, a dielectric layer 414, and an insulating layer 415 can be sequentially formed on the upper surface 100U of a substrate 100 by deposition to form a layer stack 410. The substrate 100 may contain a semiconductor material, such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, germanium, etc. In one embodiment, the substrate 100 contains doped or undoped single-crystal silicon. The insulating layers 411, 413, and 415 may contain an insulating material, such as an oxide. In one embodiment, the insulating layers 411, 413, and 415 contain silicon oxide. The semiconductor material layer 412 may contain a semiconductor material, such as doped or undoped polycrystalline silicon. The dielectric layer 414 may contain a dielectric material, such as a nitride. In one embodiment, the dielectric layer 414 contains silicon nitride.

[0036] Next, at least one channel pillar 450 can be formed through the stacked layers 410. The channel pillar 450 is disposed in the array region 101 and on the substrate 100. Multiple channel pillars 450 can be disposed separately from each other. The channel pillar 450 may include an insulating pillar 151, a channel layer 152, a charge storage layer 153, and a pad 454. The outer sidewall of the charge storage layer 153 may contact the insulating layer 411, the semiconductor material layer 412, the insulating layer 413, the dielectric layer 414, and the insulating layer 415. The pad 454 may be disposed on or in contact with the first end of the insulating pillar 151, the first end of the channel layer 152, and the first end of the charge storage layer 153. The second end of the insulating pillar 151 (relative to the first end), the second end of the channel layer 152 (relative to the first end), and the second end of the charge storage layer 153 (relative to the first end) may contact the substrate 100. The method of forming the channel pillar 450 may include: forming at least one hole 4501 in the layer stack 410 by etching, the hole 4501 extending along a first direction D1, the hole 4501 exposing the sidewalls of the insulating layer 411, the sidewalls of the semiconductor material layer 412, the sidewalls of the insulating layer 413, the sidewalls of the dielectric layer 414, the sidewalls of the insulating layer 415, and the upper surface 100U of the substrate 100; then, forming a charge storage layer 153, a channel layer 152 and an insulating pillar 151 sequentially in the hole 4501 by deposition; then, forming a pad 454 in the hole 4501 by deposition. In one embodiment, the deposition process used to form pad 454 causes the material of pad 454 to be formed in the hole 4501 and on the insulating layer 415. The material of pad 454 on the insulating layer 415 (which can also be understood as the material of pad 454 outside the hole 4501) can be removed by an etching back process, thereby forming pad 454.

[0037] The charge storage layer 153 may comprise a multilayer structure known in the field of memory technology, such as an ONO (oxide-nitride-oxide) structure, an ONONO (oxide-nitride-oxide-nitride-oxide) structure, an ONONONO (oxide-nitride-oxide-nitride-oxide-oxide) structure, a SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a BE-SONOS (bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, a MA BE-SONOS (metal-high dielectric constant material bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, or a combination thereof. The channel layer 152 may comprise a semiconductor material, such as doped or undoped polycrystalline silicon. The insulating post 151 may comprise an insulating material, such as an oxide. In one embodiment, the insulating post 151 comprises silicon oxide. The pad 454 may comprise a semiconductor material, such as doped or undoped polycrystalline silicon.

[0038] The structure of the channel pillar is not limited to the channel pillar 450 shown in Figure 4. For example, the channel pillar can be the channel pillar 550 shown in Figure 4A. The channel pillar 550 may include a channel layer 552 and a charge storage layer 553. The charge storage layer 553 may be tubular and surround the channel layer 552. The outer wall of the charge storage layer 553 may contact the insulating layer 411, the semiconductor material layer 412, the insulating layer 413, the dielectric layer 414, and the insulating layer 415. The channel pillar 550 may contact the substrate 100. The method of forming the channel pillar 550 may include: forming the charge storage layer 553 in the cavity 4501 by a deposition process; and then forming the channel layer 552 in the cavity 4501 by a deposition process or an epitaxial growth process. The charge storage layer 553 may comprise a multilayer structure known in the field of memory technology, such as an ONO (oxide-nitride-oxide) structure, an ONONO (oxide-nitride-oxide-nitride-oxide) structure, an ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, a SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a BE-SONOS (bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, a MA BE-SONOS (metal-high dielectric constant material bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, or a combination thereof. The channel layer 552 may comprise a semiconductor material, such as doped or undoped monocrystalline silicon, doped or undoped polycrystalline silicon, etc. In one embodiment, the channel layer 552 may comprise monocrystalline silicon formed by an epitaxial growth process.

[0039] Please refer to Figure 5. Figure 5 is a schematic cross-sectional view of a stage of the method for manufacturing a memory device. The layer stack 410 with the removed portion is shown. Specifically, the portion of layer stack 410 located in the peripheral region 102 is removed, while the portion of layer stack 410 located in the array region 101 is retained; the retained portion is layer stack 410A. The upper surface 100U of the substrate 100 in the peripheral region 102 is exposed. A portion of insulating layer 411, a portion of semiconductor material layer 412, a portion of insulating layer 413, a portion of dielectric layer 414, and a portion of insulating layer 415 located in the peripheral region 102 can be removed by etching. The retained portion of insulating layer 411 is insulating layer 411A, the retained portion of semiconductor material layer 412 is semiconductor material layer 412A, the retained portion of insulating layer 413 is insulating layer 413A, the retained portion of dielectric layer 414 is dielectric layer 414A, and the retained portion of insulating layer 415 is insulating layer 415A. The insulating layer 411A, the semiconductor material layer 412A, the insulating layer 413A, the dielectric layer 414A and the insulating layer 415A form a stacked layer 410A.

[0040] Please refer to Figure 6. Figure 6 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. Dielectric films 6771 and 6772 are formed in the peripheral region 102. Dielectric films 6771 and 6772 may have different heights in the first direction D1, but the present invention is not limited thereto. In this embodiment, the height of dielectric film 6771 in the first direction D1 is greater than the height of dielectric film 6772 in the first direction D1. Dielectric film 6771 can serve as a dielectric film for a high-voltage element, such as a gate dielectric film. Dielectric film 6772 can serve as a dielectric film for a low-voltage element, such as a gate dielectric film. The exposed substrate 100 may undergo one or more oxidation processes to form dielectric films 6771 and 6772. In one embodiment, the oxidation process used to form dielectric films 6771 and 6772 is a dry oxidation process.

[0041] Please refer to Figure 7. Figure 7 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. A semiconductor layer 7221 and a filler element 7223 are formed. The semiconductor layer 7221 extends on the plane formed by the second direction D2 and the third direction D3 and spans the array region 101 and the peripheral region 102. A portion of the semiconductor layer 7221 is on the layer stack 410A, and another portion of the semiconductor layer 7221 is on the dielectric films 6771 and 6772. The semiconductor layer 7221 can contact the upper surface and sidewalls of the layer stack 410A. The semiconductor layer 7221 can contact the dielectric films 6771 and 6772. The filler element 7223 is on the semiconductor layer 7221. The filler element 7223 is in the peripheral region 102. In this embodiment, the semiconductor layer 7221 on the upper surface 7221U of the array region 101 and the fill element 7223 on the upper surface 7223U of the peripheral region 102 may be coplanar (or may have substantially the same height in the first direction D1). The semiconductor layer 7221 can be formed on the layer stack 410A and the substrate 100 by deposition, followed by deposition to form the fill element 7223 on the semiconductor layer 7221. In one embodiment, the deposition process for forming the fill element 7223 may cause the material of the fill element 7223 to cover the semiconductor layer 7221 in the array region 101 and the peripheral region 102. A portion of the material of the fill element 7223 may be removed by a polishing process to expose the semiconductor layer 7221 on the upper surface 7221U of the array region 101, thereby forming the fill element 7223. The semiconductor layer 7221 may contain a semiconductor material, such as doped or undoped polysilicon. The fill element 7223 may contain an insulating material, such as an oxide. In one embodiment, the filling element 7223 comprises silicon oxide.

[0042] Please refer to Figure 8. Figure 8 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. At least one hole 8501 is formed in the peripheral region 102. Multiple holes 8501 may be arranged separately from each other. The holes 8501 may extend along a first direction D1. The holes 8501 may penetrate the filling element 7223A, the semiconductor layer 7221A, the dielectric film 177, the dielectric film 6771A, the dielectric film 6772A, and the substrate 100. The holes 8501 may expose the sidewalls of the filling element 7223A, the semiconductor layer 7221A, the dielectric film 6771A, the dielectric film 177, the dielectric film 6772A, the sidewalls of the substrate 100, and the surface of the substrate 100. The bottom of the holes 8501 may be lower than the upper surface 100U of the substrate 100. A portion of the filler element 7223, a portion of the semiconductor layer 7221, a portion of the dielectric film 6771, a portion of the dielectric film 6772, and a portion of the substrate 100 can be removed by etching to form a hole 8501. The portion of the filler element 7223 that is retained is the filler element 7223A. The portion of the semiconductor layer 7221 that is retained is the semiconductor layer 7221A. The portion of the dielectric film 6771 that is retained can be divided into dielectric film 6771A and 177, and the hole 8501 separates dielectric film 6771A and 177 from each other. The portion of the dielectric film 6772 that is retained is the dielectric film 6772A.

[0043] Please refer to Figure 9. Figure 9 is a structural cross-sectional schematic diagram of a stage of a method for manufacturing a memory device. At least one isolation element 970 is formed. The isolation element 970 can be formed in a cavity 8501 by a deposition process. In one embodiment, the deposition process for forming the isolation element 970 causes the material of the isolation element 970 to cover the semiconductor layer 7221A in the array region 101 and the filler element 7223A in the peripheral region 102. The portion of the material of the isolation element 970 above the semiconductor layer 7221A and the filler element 7223A can be removed by a polishing process, leaving the portion of the material of the isolation element 970 within the cavity 8501, thereby forming the isolation element 970. The isolation element 970 may contain an insulating material, such as an oxide. In one embodiment, the isolation element 970 contains silicon oxide.

[0044] Please refer to Figure 10. Figure 10 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. At least one isolation element 970A, a semiconductor layer 7222, and a gate oxide layer 7224 are formed. The isolation element 970A extends along a first direction D1 and penetrates the semiconductor layer 7221A, dielectric film 6771A, dielectric film 177, dielectric film 6772A, and substrate 100. The upper surface 970U of the isolation element 970A and the upper surface 72AU of the semiconductor layer 7221A are coplanar. The semiconductor layer 7222 and the gate oxide layer 7224 extend along a plane formed by a second direction D2 and a third direction D3, spanning the array region 101 and the peripheral region 102. The semiconductor layer 7222 and the gate oxide layer 7224 are disposed on the semiconductor layer 7221A. The semiconductor layer 7222 may be located between the gate oxide layer 7224 and the semiconductor layer 7221A. A portion of the filler element 7223A and the isolation element 970 above the upper surface 72AU of the semiconductor layer 7221A can be removed by an etch-back process; the retained portion of the isolation element 970 is the isolation element 970A. After forming the isolation element 970A, a semiconductor layer 7222 and a gate oxide layer 7224 can be sequentially formed on the semiconductor layer 7221A by a deposition process. The semiconductor layer 7222 and the gate oxide layer 7224 can be conformally formed on the semiconductor layer 7221A. The semiconductor layer 7222 may contain a semiconductor material, such as doped or undoped polysilicon. The gate oxide layer 7224 may contain an insulating material, such as an oxide. In one embodiment, the gate oxide layer 7224 contains silicon oxide.

[0045] Please refer to Figure 11. Figure 11 is a schematic cross-sectional view of a stage of a method for manufacturing a memory device. Semiconductor layer 7221B, semiconductor layer 7222A, and gate oxide layer 7224A are formed. The upper surfaces of semiconductor layer 7221B, semiconductor layer 7222A, gate oxide layer 7224A, and the upper surface of the layer stack 410A are coplanar. The portions of semiconductor layer 7221A, semiconductor layer 7222A, and gate oxide layer 7224A above the upper surface of the layer stack 410A can be removed by etching. The portion of semiconductor layer 7221A remaining is semiconductor layer 7221B, the portion of semiconductor layer 7222A remaining is semiconductor layer 7222A, and the portion of gate oxide layer 7224A remaining is gate oxide layer 7224A.

[0046] Please refer to Figure 12. Figure 12 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. In the peripheral region 102, an extension 122 comprising semiconductor layers 1221 and 1222, an insulating film 123, a semiconductor film 1332 comprising semiconductor material films 1332A and 1332B, a gate oxide layer 7224B, and a shallow trench isolation 170 are formed. At least one hole 1201 is formed in the peripheral region 102. A plurality of holes 1201 may be arranged separately from each other. One of the plurality of holes 1201 may expose the upper surface of the dielectric film 177, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6771A, the sidewall of the extension 122, the sidewall of the insulating film 123, the sidewall of the semiconductor film 1332, and the sidewall of the gate oxide layer 7224B. One of the multiple holes 1201 can expose the upper surface of the dielectric film 6771A, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6772A, the sidewall of the semiconductor film 1332, and the sidewall of the gate oxide layer 7224B. The upper surfaces of the shallow trench isolation 170, the dielectric film 177, the dielectric film 6771A, and the dielectric film 6772A can be coplanar. The deflection portion 122 can be adjacent to the layer stack 410A. The semiconductor layer 1222 in the deflection portion 122 can be located between the semiconductor layer 1221 and the insulating film 123. The deflection portion 122 can be disposed at the boundary of the peripheral region 102, or the deflection portion 122 can serve as the boundary between the array region 101 and the peripheral region 102.

[0047] A portion of the isolation element 970A, a portion of the semiconductor layer 7221B, a portion of the semiconductor layer 7222A, and a portion of the gate oxide layer 7224A can be removed by etching, thereby forming a hole 1201. The portion of the isolation element 970A that is retained is the shallow trench isolation 170. The portion of the semiconductor layer 7221B that is retained can be divided into semiconductor layer 1221 and semiconductor material film 1332B. The portion of the semiconductor layer 7222A that is retained can be divided into semiconductor layer 1222 and semiconductor material film 1332A. The portion of the gate oxide layer 7224A that is retained can be divided into insulating film 123 and gate oxide layer 7224B. The hole 1201 separates semiconductor layer 1221 from semiconductor material film 1332B. The hole 1201 separates semiconductor layer 1222 from semiconductor material film 1332A. The hole 1201 separates insulating film 123 from gate oxide layer 7224B.

[0048] Please refer to Figure 13. Figure 13 is a structural cross-sectional schematic diagram of a stage of a method for manufacturing a memory device. A plurality of spacer elements 181 and at least one spacer element 182 are formed in a peripheral region 102. Spacer elements 181 and 182 are located in a hole 1201. Figure 13 illustrates spacer elements 181 and 182 as having arcuate sidewalls 181S and 182S, respectively, but this is not a limitation of the invention. Spacer element 181 may be adjacent to the sidewall of semiconductor film 1332 and the sidewall of gate oxide layer 7224B. Spacer element 182 may be adjacent to the sidewall of diffracted portion 122 and the sidewall of insulating film 123. Spacer elements 181 and 182 are disposed separately from each other. Spacer elements 181 and 182 may comprise an insulating material, such as an oxide or nitride. In one embodiment, spacer elements 181 and 182 comprise silicon oxide or silicon nitride. Spacer element 181 and spacer element 182 may contain the same material or different materials. An insulating material (i.e., the material of spacer element 181 and spacer element 182) may be formed in the hole 1201 by a deposition process, and the insulating material may fill the hole 1201; then a portion of the insulating material may be removed by an etching process, and the portion of the insulating material that is retained may be divided into spacer element 181 and spacer element 182.

[0049] In one embodiment, after forming spacer elements 181 and 182, an ion implantation process can be performed on the surface of the structure shown in Figure 13 (e.g., the surface indicated by the dashed line in Figure 13) to introduce N-type or P-type dopants to the surface of the structure shown in Figure 13. The ion implantation process can be performed simultaneously on the structure located in array region 101 and the structure located in peripheral region 102.

[0050] Please refer to Figure 14. Figure 14 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. A capping layer 1483 is formed. The capping layer 1483 extends on the plane formed by the second direction D2 and the third direction D3 and spans the array region 101 and the peripheral region 102. The capping layer 1483 may cover the upper surface of the layer stack 410A, the upper surface of the semiconductor layer 1221, the upper surface of the semiconductor layer 1222, the upper surface of the insulating film 123, the sidewall 182S of the spacer element 182, the upper surface of the dielectric film 177, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6771A, the sidewall 181S of the spacer element 181, the upper surface of the gate oxide layer 7224B, and the upper surface of the dielectric film 6772A. A capping layer 1483 can be conformally formed on the layer stack 410A, the diffracted portion 122, the insulating film 123, the spacer element 182, the dielectric film 177, the shallow trench isolation 170, the dielectric film 6771A, the spacer element 181, and the gate oxide layer 7224B by a deposition process. The capping layer 1483 may contain a dielectric material, such as a nitride.

[0051] Please refer to Figure 15. Figure 15 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. A hole 1501 is formed in the array region 101. The hole 1501 penetrates the capping layer 1483A, insulating layer 415B, dielectric layer 414B, and insulating layer 413B. The hole 1501 exposes the sidewalls of the capping layer 1483A, the insulating layer 415B, the dielectric layer 414B, the insulating layer 413B, the upper surface of the semiconductor material layer 412A, and the sidewalls of the semiconductor layer 1221. The hole 1501 may be located at the boundary of the array region 101. The hole 1501 can be formed by removing a portion of the capping layer 1483A, a portion of the insulating layer 415A, a portion of the dielectric layer 414A, and a portion of the insulating layer 413A through an etching process. The portion of capping layer 1483 that is retained is capping layer 1483A, the portion of insulating layer 415A that is retained is insulating layer 415B, the portion of dielectric layer 414A that is retained is dielectric layer 414B, and the portion of insulating layer 413A that is retained is insulating layer 413B. Insulating layer 411A, semiconductor material layer 412A, insulating layer 413B, dielectric layer 414B, and insulating layer 415B form a stacked layer 410B.

[0052] Please refer to Figure 16. Figure 16 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. An insulating layer 1616 is formed in the array region 101. An insulating film 1621 is formed in the peripheral region 102. The insulating layer 1616 is disposed in the aperture 1501. The insulating film 1621 is disposed on the cover layer 1483A. The insulating layer 1616 and the insulating film 1621 can be formed by deposition and polishing processes. The insulating layer 1616 and the insulating film 1621 may contain an insulating material, such as an oxide. The insulating layer 1616 and the insulating film 1621 may contain the same material or different materials. In one embodiment, the insulating layer 1616 and the insulating film 1621 contain silicon oxide.

[0053] Please refer to Figure 17. Figure 17 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. An insulating film 1621A, a capping layer 1483B, and an insulating layer 116 are formed. The insulating film 1621A and the capping layer 1483B are in the peripheral region 102. The insulating layer 116 is in the array region 101. The portion of the capping layer 1483A located above the upper surface of the layer stack 410B, above the upper surface of the diffracted portion 122, above the upper surface of the insulating film 123, and above the upper surface of the gate oxide layer 7224B can be removed by an etch-back process, and the portions of the insulating layer 1616 and the insulating film 1621 above the upper surface of the layer stack 410B can be removed to form the structure shown in Figure 17. The portion of the capping layer 1483A that is retained is the capping layer 1483B. The portion of the insulating layer 1616 that is retained is the insulating layer 116. The portion of the insulating film 1621 that is retained is the insulating film 1621A.

[0054] In other embodiments, the steps shown in Figure 17 may be omitted.

[0055] Please refer to Figure 18. Figure 18 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. An interlayer insulating layer 1891 and a hole 1801 penetrating the interlayer insulating layer 1891 are formed. The interlayer insulating layer 1891 may extend on the plane formed by the second direction D2 and the third direction D3 and span the array region 101 and the peripheral region 102. The hole 1801 may be disposed in the array region 101. The hole 1801 may extend along the first direction D1 and penetrate the insulating layer 115, the dielectric layer 414C and the insulating layer 113. The hole 1801 may expose the sidewalls of the interlayer insulating layer 1891, the sidewalls of the insulating layer 115, the sidewalls of the dielectric layer 414C, the sidewalls of the insulating layer 113, and the upper surface of the semiconductor material layer 412A. The hole 1801 may be disposed between a plurality of channel pillars 450. An interlayer insulating layer 1891 can be formed over the layer stack 410B, gate oxide layer 7224B, and insulating film 1621A by deposition. Then, a portion of the interlayer insulating layer 1891, a portion of insulating layer 415B, a portion of dielectric layer 414B, and insulating layer 413B can be removed by etching to form a hole 1801. The retained portion of insulating layer 415B is insulating layer 115, the retained portion of dielectric layer 414B is dielectric layer 414C, and the retained portion of insulating layer 413B is insulating layer 113. Insulating layer 411A, semiconductor material layer 412A, insulating layer 113, dielectric layer 414C, and insulating layer 115 form a layer stack 410C. The interlayer insulating layer 1891 may contain an insulating material, such as an oxide. In one embodiment, the interlayer insulating layer 1891 may contain silicon oxide.

[0056] Please refer to Figure 19. Figure 19 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. In array region 101, a stacked structure 110 is formed, comprising an insulating layer 111, a conductive layer 112, an insulating layer 113, a conductive layer 114, an insulating layer 115, an insulating layer 116, and a barrier layer 117; a conductive post 178 penetrating the stacked structure 110; and an isolation element 1781 disposed between the conductive post 178 and the barrier layer 117. Conductive layers 112 and 114 may comprise conductive materials, such as metals. Conductive layers 112 and 114 may comprise the same or different materials. In one embodiment, conductive layers 112 and 114 may comprise tungsten. The barrier layer 117 may comprise a multilayer structure, such as an oxide / nitride / oxide (ONO) multilayer structure. The conductive post 178 may comprise conductive materials, such as metals. In one embodiment, the conductive post 178 may comprise tungsten. The insulating element 1781 may comprise an insulating material, such as an oxide. In one embodiment, the insulating element 1781 may comprise silicon oxide.

[0057] The dielectric layer 414C and the semiconductor material layer 412A can be removed through the aperture 1801 by etching to form the space 1902 between the insulating layer 113 and the insulating layer 115, and the space 1901 between the insulating layer 113 and the insulating layer 411A. Next, a barrier layer 117 can be formed on the space 1902, the space 1901, the sidewall of the insulating layer 113 exposed by the aperture 1801, the sidewall of the insulating layer 115 exposed by the aperture 1801, and the sidewall of the interlayer insulating layer 1891 exposed by the aperture 1801 by deposition. Then, a conductive material can be formed in the remaining space of the space 1902 (i.e., the space not filled by the barrier layer 117), the remaining space of the space 1901 (i.e., the space not filled by the barrier layer 117), and the remaining space of the aperture 1801 (i.e., the space not filled by the barrier layer 117) by deposition. Next, a portion of the conductive material in the aperture 1801 can be removed by an etching process, and a portion of the insulating layer 411A can be removed by an etching process to expose the substrate 100; the portion of the insulating layer 411A retained is the insulating layer 111. The portion of the conductive material retained in the space 1902 is the conductive layer 114. The portion of the conductive material retained in the space 1901 is the conductive layer 112. The sidewalls of the conductive layer 114 exposed by the aperture 1801 can be recessed relative to the sidewalls of the barrier layer 117 exposed by the aperture 1801 to form a recess. The sidewalls of the conductive layer 112 exposed by the aperture 1801 can be recessed relative to the sidewalls of the barrier layer 117 exposed by the aperture 1801 to form a recess. Next, conductive pillars 178 and isolation elements 1781 can be formed in the aperture 1801 by a deposition process and an etching process. A portion of the isolation element 1781 can be formed in the recess.

[0058] In one embodiment, after the conductive pillar 178 and the isolation element 1781 are formed, a grinding process may be performed to make the upper surface of the conductive pillar 178, the upper surface of the isolation element 1781, the upper surface of the barrier layer 117 and the upper surface of the interlayer insulating layer 1891 coplanar.

[0059] Please refer to Figure 20. Figure 20 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. An interlayer insulating layer 191 is formed. A portion of the interlayer insulating layer 191 is in the array region 101, and another portion is in the peripheral region 102. A hole 2001 penetrating the interlayer insulating layer 191 is formed in the array region 101. Holes 2002 and 2003 penetrating the interlayer insulating layer 191, the insulating film 121, and the cover layer 183 are formed in the peripheral region 102. A hole 2004 penetrating the interlayer insulating layer 191 and the insulating film 121 is formed in the peripheral region 102. The number and location of the holes 2001 correspond to the number and location of the channel posts 450. The holes 2001 expose the upper surface of the channel posts 450 (i.e., the upper surface of the pads 454) and the sidewalls of the interlayer insulating layer 191. Holes 2002 and 2003 may be disposed on opposite sides of hole 2004. The number and position of holes 2004 may correspond to the number and position of semiconductor film 1332. Holes 2002 and 2003 may extend along the first direction D1 to the upper surface of substrate 100. Holes 2002 and 2003 may expose substrate 100. Hole 2004 may expose semiconductor material film 1332A of semiconductor film 1332.

[0060] A portion of the interlayer insulating layer 1891 can be removed by etching to form holes 2001. A portion of the interlayer insulating layer 1891, a portion of the insulating film 1621A, a portion of the capping layer 1483B, a portion of the dielectric film 6771A, and a portion of the dielectric film 6772A can be removed by etching to form holes 2002 and 2003. A portion of the interlayer insulating layer 1891 and the gate oxide layer 7224B can be removed by etching to form holes 2004. After the etching processes used to form holes 2001 to 2004, the portion of the interlayer insulating layer 1891 retained is the interlayer insulating layer 191, the portion of the insulating film 1621A retained is the insulating film 121, the portion of the capping layer 1483B retained is the capping layer 183, and the portions of the dielectric films 6771A and 6772A retained are the dielectric films 1333. The insulating film 121, the diffracted portion 122 and the insulating film 123 can form a stacked structure 120.

[0061] Please refer to Figure 21. Figure 21 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. At least one transistor 130 is formed in the peripheral region 102. Channel pillars 150 are formed in the array region 101. Metallic material can be formed in the holes 2001-2004 by deposition, followed by a rapid thermal process (RTP) to react the metallic material (e.g., titanium, tungsten, cobalt, or nickel) with the underlying semiconductor material (e.g., silicon) to form the pad 154 in the hole 2001, the source 131 in the hole 2002, the drain 132 in the hole 2003, and the conductive film 1331 in the hole 2004. In this embodiment, the pad 454 reacts with the metallic material to form the pad 154, a portion of the substrate 100 reacts with the metallic material to form the source 131, a portion of the substrate 100 reacts with the metallic material to form the drain 132, and a portion of the semiconductor film 1332 reacts with the metallic material to form the conductive film 1331. The conductive film 1331, the semiconductor film 1332, and the dielectric film 1333 can form a gate 133. The source 131, the drain 132, and the gate 133 can form a transistor 130. The insulating pillar 151, the channel layer 152, the charge storage layer 153, and the pad 154 can form a channel pillar 150.

[0062] In one embodiment, after the pad 154 and transistor 130 are formed, unreacted metal material can be removed by etching. The pad 154, source 131, drain 132, and conductive film 1331 may comprise metal silicides, such as titanium silicon, tungsten silicon, cobalt silicon, nickel silicon, etc. In one embodiment, the pad 154, source 131, drain 132, and conductive film 1331 comprise cobalt silicon.

[0063] Please refer to Figure 22. Figure 22 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. An interlayer insulating layer 192 is formed. A portion of the interlayer insulating layer 192 is in the array region 101, and another portion of the interlayer insulating layer 192 is in the peripheral region 102. A channel contact structure 176 is formed in the array region 101. A source contact structure 171, an isolation element 1711 on the sidewall of the source contact structure 171, a drain contact structure 172, an isolation element 1721 on the sidewall of the drain contact structure 172, a gate contact structure 173, and an isolation element 1731 on the sidewall of the gate contact structure 173 are formed in the peripheral region 102.

[0064] Isolation elements 1711 can be formed in vias 2002, 1721 in vias 2003, and 1731 in vias 2004 by deposition. Next, an interlayer insulating layer 192 can be formed over the interlayer insulating layer 191 by deposition. Then, a channel contact structure 176 penetrating the interlayer insulating layers 191 and 192, a source contact structure 171 penetrating the interlayer insulating layer 192 and the isolation element 1711, a drain contact structure 172 penetrating the interlayer insulating layer 192 and the isolation element 1721, and a gate contact structure 173 penetrating the interlayer insulating layer 192 and the isolation element 1731 can be formed by etching and deposition. The interlayer insulating layer 192 may comprise an insulating material, such as an oxide. In one embodiment, the interlayer insulating layer 192 comprises silicon oxide. The channel contact structure 176, source contact structure 171, drain contact structure 172, and gate contact structure 173 may comprise conductive materials, such as metals. These structures may comprise the same or different materials. In one embodiment, the channel contact structure 176, source contact structure 171, drain contact structure 172, and gate contact structure 173 comprise tungsten. Isolation elements 1711, 1721, and 1731 may comprise insulating materials, such as oxides. In one embodiment, isolation elements 1711, 1721, and 1731 comprise silicon oxide.

[0065] Please refer to Figure 23. Figure 23 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. Conductive contact structures 175 and 174 are formed. A metal winding layer 140 comprising insulating material 142 and multiple conductors 141 is formed on the interlayer insulating layer 192. The insulating material 142 electrically isolates the multiple conductors 141 from each other. The positions of the conductors 141 may correspond to the positions of the channel contact structure 176, conductive post 178, conductive contact structure 175, conductive contact structure 174, source contact structure 171, drain contact structure 172, and gate contact structure 173 to form an electrical connection. The insulating material 142 may comprise an oxide, such as silicon oxide. The conductors 141 may comprise a conductive material, such as a metal. In one embodiment, the conductors 141 comprise tungsten. The conductive contact structures 175 and 174 can be formed in the array region 101 by etching and deposition processes. After forming conductive contact structures 175 and 174, a metal winding layer 140 can be formed in the array region 101 and the peripheral region 102 by etching and deposition processes. In one embodiment, the steps shown in Figures 22 and 23 can be performed in the back-end-of-the-line (BEOL) process of semiconductor manufacturing.

[0066] In one embodiment, the memory device 10 shown in Figure 1 can be obtained by performing the method illustrated in Figures 4 to 23.

[0067] Figures 24 to 37 are schematic cross-sectional views illustrating multiple stages of a method for manufacturing a memory device according to some embodiments of the present invention. The steps shown in Figures 24 to 37 may be performed sequentially or in other orders, and the present invention is not limited thereto. In some embodiments, the manufacturing steps described in Figures 24 to 37 may be performed after the manufacturing steps described in Figures 4 to 9.

[0068] Please refer to Figure 24. Figure 24 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. At least one isolation element 970A, a semiconductor layer 7222, a conductive film 2431, and a gate oxide layer 7224 are formed. The semiconductor layer 7222, conductive film 2431, and gate oxide layer 7224 extend on a plane formed by a second direction D2 and a third direction D3, spanning the array region 101 and the peripheral region 102. The semiconductor layer 7222, conductive film 2431, and gate oxide layer 7224 can be disposed on the semiconductor layer 7221A. The semiconductor layer 7222 can be located between the conductive film 2431 and the semiconductor layer 7221A. The conductive film 2431 can be located between the gate oxide layer 7224 and the semiconductor layer 7222. A portion of the filler element 7223A and the isolation element 970 above the upper surface 72AU of the semiconductor layer 7221A can be removed by an etching process; the retained portion of the isolation element 970 is the isolation element 970A. After forming the isolation element 970A, a semiconductor layer 7222, a conductive film 2431, and a gate oxide layer 7224 can be sequentially formed on the semiconductor layer 7221A by a deposition process. The semiconductor layer 7222, the conductive film 2431, and the gate oxide layer 7224 can be conformally formed on the semiconductor layer 7221A. The conductive film 2431 may contain a conductive material, such as a metal silicate. The metal silicate may be, for example, titanium silicate, tungsten silicate, cobalt silicate, nickel silicate, etc. In one embodiment, the conductive film 2431 contains tungsten silicate.

[0069] Please refer to Figure 25. Figure 25 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. Semiconductor layer 7221B, semiconductor layer 7222A, conductive film 2431A, and gate oxide layer 7224A are formed. The upper surfaces of semiconductor layer 7221B, semiconductor layer 7222A, conductive film 2431A, gate oxide layer 7224A, and the upper surface of the layer stack 410A are coplanar. The portions of semiconductor layer 7221A, semiconductor layer 7222, conductive film 2431, and gate oxide layer 7224 above the upper surface of layer stack 410A can be removed by etching. The portion of semiconductor layer 7221A that is above the upper surface of layer stack 410A, semiconductor layer 7222 that is above the upper surface of layer stack 410A, and gate oxide layer 7224 that is above the upper surface of layer stack 410A are all removed by etching. The portion of semiconductor layer 7221A that is retained is semiconductor layer 7221B, the portion of semiconductor layer 7222 that is retained is semiconductor layer 7222A, the portion of conductive film 2431 that is retained is conductive film 2431A, and the portion of gate oxide layer 7224 that is retained is gate oxide layer 7224A.

[0070] Please refer to Figure 26. Figure 26 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. In the peripheral region 102, an extension 122 comprising semiconductor layers 1221 and 1222, a conductive portion 324, an insulating film 123, a semiconductor film 1332 comprising semiconductor material films 1332A and 1332B, a conductive film 3331, a gate oxide layer 7224B, and a shallow trench isolation 170 are formed. At least one aperture 2601 is formed in the peripheral region 102. Multiple apertures 2601 may be arranged separately from each other. One of the plurality of apertures 2601 may expose the upper surface of dielectric film 177, the upper surface of shallow trench isolation 170, the upper surface of dielectric film 6771A, the sidewall of the deflection portion 122, the sidewall of the conductive portion 324, the sidewall of insulating film 123, the sidewall of semiconductor film 1332, the sidewall of conductive film 3331, and the sidewall of gate oxide layer 7224B. One of the plurality of apertures 2601 may expose the upper surface of dielectric film 6771A, the upper surface of shallow trench isolation 170, the upper surface of dielectric film 6772A, the sidewall of semiconductor film 1332, the sidewall of conductive film 3331, and the sidewall of gate oxide layer 7224B. The upper surfaces of shallow trench isolation 170, dielectric film 177, dielectric film 6771A, and dielectric film 6772A may be coplanar. The semiconductor layer 1222 in the derivation portion 122 can be disposed between the semiconductor layer 1221 and the conductive portion 324. The conductive portion 324 can be disposed between the semiconductor layer 1222 and the insulating film 123. The derivation portion 122 can be disposed at the boundary of the peripheral region 102, or the derivation portion 122 can serve as the boundary between the array region 101 and the peripheral region 102.

[0071] A portion of the isolation element 970A, a portion of the semiconductor layer 7221B, a portion of the semiconductor layer 7222A, a portion of the conductive film 2431A, and a portion of the gate oxide layer 7224A can be removed by etching, thereby forming a hole 2601. The portion of the isolation element 970A that is retained is the shallow trench isolation 170. The portion of the semiconductor layer 7221B that is retained can be divided into semiconductor layer 1221 and semiconductor material film 1332B. The portion of the semiconductor layer 7222A that is retained can be divided into semiconductor layer 1222 and semiconductor material film 1332A. The portion of the conductive film 2431A that is retained can be divided into conductive portion 324 and conductive film 3331. The portion of the gate oxide layer 7224A that is retained can be divided into insulating film 123 and gate oxide layer 7224B. The hole 2601 separates the semiconductor layer 1221 and the semiconductor material film 1332B from each other. The hole 2601 also separates the semiconductor layer 1222 and the semiconductor material film 1332A from each other. Hole 2601 allows the conductive part 324 to be separated from the conductive film 3331. Hole 2601 also allows the insulating film 123 to be separated from the gate oxide layer 7224B.

[0072] Please refer to Figure 27. Figure 27 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. A plurality of spacer elements 181 and at least one spacer element 182 are formed in the peripheral region 102. Spacer elements 181 and 182 are located in holes 2601. Figure 27 illustrates spacer elements 181 and 182 as having arcuate sidewalls 181S and 182S, respectively, but this is not a limitation of the invention. Spacer element 181 may be adjacent to the sidewalls of semiconductor film 1332, conductive film 3331, and gate oxide layer 7224B. Spacer element 182 may be adjacent to the sidewalls of the diffracted portion 122, conductive portion 324, and insulating film 123. An insulating material (i.e., the material of spacer element 181 and spacer element 182) can be formed in the hole 2601 by deposition, and the insulating material can fill the hole 2601; then a portion of the insulating material can be removed by etching, and the portion of the insulating material that is retained can be divided into spacer element 181 and spacer element 182.

[0073] In one embodiment, after forming spacer elements 181 and 182, an ion implantation process can be performed on the surface of the structure shown in Figure 27 (e.g., the surface indicated by the dashed line in Figure 27) to introduce N-type or P-type dopants onto the surface of the structure shown in Figure 27. The ion implantation process can be performed simultaneously on the structure located in array region 101 and the structure located in peripheral region 102.

[0074] Please refer to Figure 28. Figure 28 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. A capping layer 1483 is formed. The capping layer 1483 may cover the upper surface of the layer stack 410A, the upper surface of the semiconductor layer 1221, the upper surface of the semiconductor layer 1222, the upper surface of the conductive portion 324, the upper surface of the insulating film 123, the sidewall 182S of the spacer element 182, the upper surface of the dielectric film 177, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6771A, the sidewall 181S of the spacer element 181, the upper surface of the gate oxide layer 7224B, and the upper surface of the dielectric film 6772A. A capping layer 1483 can be conformally formed on the layer stack 410A, the diffracted portion 122, the conductive portion 324, the insulating film 123, the spacer element 182, the dielectric film 177, the shallow trench isolation 170, the dielectric film 6771A, the spacer element 181, and the gate oxide layer 7224B by deposition.

[0075] Please refer to Figures 29 through 33. Figures 29 through 33 are schematic cross-sectional views of the structure of multiple stages of a method for manufacturing a memory device. A hole 1501 is formed in the array region 101 (Figure 29). An insulating layer 1616 is formed in the array region 101; an insulating film 1621 is formed in the peripheral region 102 (Figure 30). An insulating film 1621A, a cover layer 1483B, and an insulating layer 116 are formed (Figure 31). In other embodiments, the steps shown in Figure 31 may be omitted. An interlayer insulating layer 1891 and a hole 1801 penetrating the interlayer insulating layer 1891 are formed (Figure 32). In the array region 101, a stacked structure 110 is formed, comprising an insulating layer 111, a conductive layer 112, an insulating layer 113, a conductive layer 114, an insulating layer 115, an insulating layer 116 and a barrier layer 117, a conductive pillar 178 penetrating the stacked structure 110, and an isolation element 1781 disposed between the conductive pillar 178 and the barrier layer 117 (Figure 33).

[0076] In one embodiment, the structure shown in Figures 29 to 33 can be formed using the manufacturing method and materials described with reference to Figures 15 to 19, which will not be repeated here.

[0077] Please refer to Figure 34. Figure 34 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. An interlayer insulating layer 191 is formed. A portion of the interlayer insulating layer 191 is in the array region 101, and another portion is in the peripheral region 102. A hole 3401 penetrating the interlayer insulating layer 191 is formed in the array region 101. Holes 3402 and 3403 penetrating the interlayer insulating layer 191, the insulating film 121, and the cover layer 183 are formed in the peripheral region 102. A hole 3404 penetrating the interlayer insulating layer 191 and the insulating film 121 is formed in the peripheral region 102. The number and location of the holes 3401 correspond to the number and location of the channel posts 450. The holes 3401 expose the upper surface of the channel posts 450 (i.e., the upper surface of the pads 454) and the sidewalls of the interlayer insulating layer 191. Holes 3402 and 3403 may be disposed on opposite sides of hole 3404. The number and position of holes 3404 may correspond to the number and position of semiconductor film 1332. Holes 3402 and 3403 may extend along the first direction D1 to the upper surface of substrate 100. Holes 3402 and 3403 may expose substrate 100. Hole 3404 may expose conductive film 3331.

[0078] A portion of the interlayer insulating layer 1891 can be removed by etching to form holes 3401. A portion of the interlayer insulating layer 1891, a portion of the insulating film 1621A, a portion of the capping layer 1483B, a portion of the dielectric film 6771A, and a portion of the dielectric film 6772A can be removed by etching to form holes 3402 and 3403. A portion of the interlayer insulating layer 1891 and the gate oxide layer 7224B can be removed by etching to form holes 3404. After the etching processes used to form holes 3401 to 3404, the portion of the interlayer insulating layer 1891 retained is the interlayer insulating layer 191, the portion of the insulating film 1621A retained is the insulating film 121, the portion of the capping layer 1483B retained is the capping layer 183, and the portions of the dielectric films 6771A and 6772A retained are the dielectric films 1333. The insulating film 121, the diffracted portion 122, the insulating film 123 and the conductive portion 324 can form a stacked structure 320.

[0079] Please refer to Figure 35. Figure 35 is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. At least one transistor 330 is formed in the peripheral region 102. Channel pillars 150 are formed in the array region 101. In one embodiment, a metallic material can be formed in the holes 3401-3403 by a deposition process, followed by a rapid thermal treatment to react the metallic material (e.g., titanium, tungsten, cobalt, or nickel) with the underlying semiconductor material (e.g., silicon) to form a pad 154 in the hole 3401, a source 131 in the hole 3402, and a drain 132 in the hole 3403. In this embodiment, the pad 454 reacts with the metallic material to form the pad 154, a portion of the substrate 100 reacts with the metallic material to form the source 131, and a portion of the substrate 100 reacts with the metallic material to form the drain 132. In another embodiment, an ion implantation process can be performed to introduce N-type or P-type dopants into the surfaces exposed by holes 3401-3403 to form a pad 154 in hole 3401, a source 131 in hole 3402, and a drain 132 in hole 3403. A conductive film 3331, a semiconductor film 1332, and a dielectric film 1333 can form a gate 333. The source 131, drain 132, and gate 333 can form a transistor 330. An insulating pillar 151, a channel layer 152, a charge storage layer 153, and a pad 154 can form a channel pillar 150. In one embodiment, after forming the pad 154 and the transistor 330, unreacted metal material can be removed by etching.

[0080] Please refer to Figure 36. Figure 36 is a structural cross-sectional view of one stage of a method for manufacturing a memory device. An interlayer insulating layer 192 is formed. A portion of the interlayer insulating layer 192 is in the array region 101, and another portion of the interlayer insulating layer 192 is in the peripheral region 102. A channel contact structure 176 is formed in the array region 101. A source contact structure 171, an isolation element 1711 on the sidewall of the source contact structure 171, a drain contact structure 172, an isolation element 1721 on the sidewall of the drain contact structure 172, a gate contact structure 173, and an isolation element 1731 on the sidewall of the gate contact structure 173 are formed in the peripheral region 102. Isolation element 1711 can be formed in a cavity 3402, isolation element 1721 in a cavity 3403, and isolation element 1731 in a cavity 3404 by deposition processing. Next, an interlayer insulating layer 192 can be formed above the interlayer insulating layer 191 by deposition. Next, a channel contact structure 176 penetrating the interlayer insulating layers 191 and 192, a source contact structure 171 penetrating the interlayer insulating layer 192 and the isolation element 1711, a drain contact structure 172 penetrating the interlayer insulating layer 192 and the isolation element 1721, and a gate contact structure 173 penetrating the interlayer insulating layer 192 and the isolation element 1731 can be formed by etching and deposition.

[0081] Please refer to Figure 37. Figure 37 is a schematic cross-sectional view of a stage of a method for manufacturing a memory device. Conductive contact structures 175 and 174 are formed. A metal winding layer 140 comprising insulating material 142 and multiple conductive lines 141 is formed on the interlayer insulating layer 192. Conductive contact structures 175 and 174 can be formed in the array region 101 by etching and deposition processes. After forming conductive contact structures 175 and 174, the metal winding layer 140 can be formed in the array region 101 and the peripheral region 102 by etching and deposition processes. In one embodiment, the steps shown in Figures 36 and 37 can be performed in the back-end processes of semiconductor manufacturing.

[0082] In one embodiment, the memory device 20 shown in Figure 3 can be obtained by performing the method illustrated in Figures 24 to 37.

[0083] Conventional methods for manufacturing memory devices using a peripheral circuit adjacent array (CNA) architecture or a CMOS under array (CUA) architecture involve forming the peripheral circuitry first, followed by the memory array. However, the high-temperature processing steps used to form the memory array can adversely affect the peripheral circuitry, reducing its performance. The present invention's memory device manufacturing method alternates between the memory array manufacturing steps and the peripheral circuitry manufacturing steps, avoiding or reducing the adverse effects of high-temperature processing steps on the peripheral circuitry, thereby improving the performance of the memory device and providing a wider process window. Furthermore, the present invention's memory device manufacturing method performs an ion implantation process (to form the transistor gate) after forming the channel layer and charge storage layer, avoiding or reducing the adverse effects of the high-temperature processing steps used to form the channel layer and charge storage layer on the state of the ion implantation region. Therefore, the present invention avoids the peripheral circuitry limiting the thermal budget during memory array manufacturing, improves the thermal budget during memory array manufacturing, and increases the crystallinity of the channel layer (due to the improved thermal budget), thus improving the carrier mobility of the memory device. Furthermore, in order to accommodate the high-temperature processing steps used to form the memory array, conventional memory device manufacturing methods require the use of high-temperature resistant materials (typically with high resistivity) to form transistors, rather than using materials that are not heat resistant (typically with low resistivity). The memory device and its manufacturing method of the present invention can use materials with even lower resistivity (e.g., titanium silicon, tungsten silicon, cobalt silicon, and nickel silicon) as the source and / or drain and / or gate of the transistor, which can improve contact resistance, improve gate resistance, improve device performance, and improve thermal budget.

[0084] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0085] 10,20: Memory device 72AU, 100U, 970U, 7221U, 7223U: Top surface 100:Substrate 101: Array Area 102: Surrounding Area 110, 120, 320: Stacked structure 111,113,115,116,411,411A,413,413A,413B,415,415A,415B,1616: Insulation layer 112, 114: Conductive layer 117: Barrier Layer 121,123,1621,1621A: Insulating film 122: Derivative section 130, 330: Transistors 131: Source Extreme 132: Jiji 133,333: Gate 140: Metal winding layer 141: Conductor 142: Insulating materials 150, 450, 550: Channel Columns 150H, 171H, 172H, 178H: Height 151: Insulating Post 152,552: Channel layer 153,553: Charge storage layer 154,454: Seam Pad 170: Shallow trench isolation 171: Source contact structure 172: Drain contact structure 173: Gate contact structure 174, 175: Conductive contact structure 176: Channel Contact Structure 177,1333,6771,6771A,6772,6772A: Dielectric film 178: Conductive column 181, 182: Spacer elements 181S, 182S: Sidewall 183, 1483, 1483A, 1483B: Overlay layer 191, 192, 1891: Interlayer insulation 324: Conductive part 410, 410A, 410B, 410C: Layer stacking 412, 412A: Semiconductor material layer 414, 414A, 414B, 414C: Dielectric layers 970, 970A: Isolation element 1201,1501,1801,2001,2002,2003,2004,2601,3401,3402,3403,3404,4501,8501: Holes 1221,1222,7221,7221A,7221B,7222,7222A: Semiconductor layer 1331, 2431, 2431A, 3331: Conductive film 1332: Semiconductor film 1332A, 1332B: Semiconductor material films 1711, 1721, 1731, 1781: Isolation elements 1901, 1902: Space 7223, 7223A: Filler element 7224, 7224A, 7224B: Gate oxide layer BL1, BL2: Bit lines CSL: Common Source Line D1: First Direction D2: Second Direction D3: Third direction MG1, MG2: Character lines SG1, SG2: Select gate lines TD1~TD4: Data storage transistors TS1~TS4: Selected Transistors

Claims

1. A memory device, comprising: a substrate including an array region and a peripheral region; a first stacked structure located in the array region, the first stacked structure including a first conductive layer, a second conductive layer and an insulating layer disposed between the first conductive layer and the second conductive layer, the first conductive layer, the insulating layer and the second conductive layer being stacked along a first direction; and a second stacked structure located in the peripheral region, the second stacked structure including a deflection adjacent to one end of the first conductive layer, the deflection including a plurality of semiconductor layers stacked extending along the first direction and in a direction perpendicular to the first direction; At least one transistor is located in the second stacked structure, the at least one transistor having a conductive film, a dielectric film and a semiconductor film stacked along the first direction; And a metal winding layer, located above the first stacked structure and the second stacked structure, wherein the metal winding layer is electrically connected to the at least one transistor, the first conductive layer and the second conductive layer.

2. The memory device as claimed in claim 1 further includes at least one channel post and a plurality of memory cells, the at least one channel post extending along a second direction opposite to the first direction and penetrating the first stacked structure, the first conductive layer being closer to the substrate than the second conductive layer, and the plurality of memory cells being located between the second conductive layer and the at least one channel post.

3. The memory device as claimed in claim 2 further includes a source contact structure and a drain contact structure, wherein the at least one transistor has a source, a drain, and a gate, the gate being formed by the conductive film, the dielectric film, and the semiconductor film, the source and the drain being located in the substrate, the source contact structure and the drain contact structure extending along the second direction to the surface of the substrate, and the height of the source contact structure from the substrate and the height of the drain contact structure from the substrate being greater than the height of the at least one channel post from the substrate.

4. The memory device as claimed in claim 2 further includes a conductive post that penetrates the first stack structure and extends along the second direction to the surface of the substrate, the conductive post being electrically connected to the substrate.

5. The memory device as claimed in claim 4 further includes a source contact structure and a drain contact structure, wherein the at least one transistor has a source, a drain, and a gate, the gate being formed by the conductive film, the dielectric film, and the semiconductor film, the source and the drain being located in the substrate, and the height of the source contact structure from the substrate and the height of the drain contact structure from the substrate being greater than the height of the conductive post from the substrate.

6. The memory device as claimed in claim 1 further includes a first conductive contact structure and a second conductive contact structure, the first conductive contact structure being above the first conductive layer and electrically connected to the first conductive layer, the second conductive contact structure being above the second conductive layer and electrically connected to the second conductive layer, and the first conductive contact structure and the second conductive contact structure being electrically connected to the metal winding layer.

7. The memory device as claimed in claim 1, further comprising at least one first spacer element in the second stacked structure, wherein the at least one first spacer element is located on the sidewalls of the conductive film and the semiconductor film of the at least one transistor.

8. The memory device as claimed in claim 7, further comprising a second spacer element in the second stacked structure, wherein the second spacer element is located at one end of the diffracted portion away from the first conductive layer.

9. A method for manufacturing a memory device, comprising: providing a substrate including an array region and a peripheral region; forming a layer stack in the array region, the layer stack including a semiconductor material layer, a dielectric layer, and an insulating layer between the semiconductor material layer and the dielectric layer; forming a channel pillar through the layer stack; forming a diffraction adjacent to the layer stack, wherein the diffraction includes a plurality of semiconductor layers stacked and extending along a first direction and a second direction, the first direction being perpendicular to the second direction; and forming at least one transistor in the peripheral region, the at least one transistor including a stacked conductive film, a dielectric film, and a semiconductor film.

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