Semiconductor memory device and fabrication method thereof

Abstract

A semiconductor memory device includes a substrate having a logic region and a memory region thereon; a first dielectric layer on the substrate, covering the logic region and the memory region; a first contact and a second contact disposed in the first dielectric layer within the logic region and the memory region, respectively; a dielectric mask layer disposed over the first dielectric layer within the logic region; a memory stack structure disposed on the second contact within the memory region; and a second dielectric layer disposed on the memory stack structure and the first dielectric layer within the memory region, and on the dielectric mask layer within the logic region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an improved resistive memory structure and its fabrication method. Prior Technology

[0002] A resistive random access memory cell (RRAM cell or ReRAM cell) typically consists of two conductive electrodes sandwiching a switching layer. This switching layer allows the memory cell to switch between two different states: a high resistance state (HRS), representing logic "0", and a low resistance state (LRS), representing logic "1".

[0003] The operation of RRAM relies on the formation and breakage of conductive filaments within the transition layer. These filaments create low-resistance paths between electrodes, thereby transitioning the memory cell to a low-resistance state (LRS). However, the unpredictable number and distribution of these filaments lead to unstable electrical characteristics of the device, such as fluctuations in the set voltage (switching to a low-resistance state) or reset voltage (switching to a high-resistance state).

[0004] The current RRAM manufacturing process faces the problem that when etching the resistive switching electrode (RSE) in the memory region, the etchant also damages the tungsten contacts in the logic region. Therefore, further improvements to the existing process are needed. Summary of the Invention

[0005] The main objective of this invention is to provide an improved resistive memory structure and its manufacturing method to overcome the shortcomings or disadvantages of existing technologies.

[0006] The present invention provides a semiconductor memory device, comprising: a substrate having a logic region and a memory region thereon; a first dielectric layer located on the substrate, covering the logic region and the memory region; a first contact and a second contact disposed within the first dielectric layer, respectively located in the logic region and the memory region; a dielectric masking layer disposed on the first dielectric layer within the logic region; a memory stack structure disposed on the second contact, located within the memory region; and a second dielectric layer disposed on the memory stack structure and the first dielectric layer within the memory region, and disposed on the dielectric masking layer within the logic region.

[0007] According to an embodiment of the present invention, the dielectric masking layer covers the logic region but does not extend to the memory region.

[0008] According to an embodiment of the present invention, the thickness of the dielectric shielding layer is 600-1000 angstroms.

[0009] According to an embodiment of the present invention, the dielectric shielding layer comprises silicon oxide.

[0010] According to an embodiment of the present invention, the dielectric shielding layer is in direct contact with the first dielectric layer.

[0011] According to an embodiment of the present invention, the second dielectric layer comprises a low dielectric constant dielectric material.

[0012] According to an embodiment of the present invention, the memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, and a top electrode layer disposed on the switching layer, wherein the bottom electrode layer is electrically connected to the second contact.

[0013] According to an embodiment of the present invention, the first contact and the second contact are tungsten contacts.

[0014] According to an embodiment of the present invention, the semiconductor memory device further includes: a first sidewall disposed on the sidewall of the dielectric mask layer, located at the junction of the logic region and the memory region; and a second sidewall disposed on the sidewall of the memory stack structure, located within the memory region.

[0015] According to an embodiment of the present invention, the semiconductor memory device further includes: a first conductive via disposed in the second dielectric layer and the dielectric masking layer within the logic region, wherein the first conductive via is electrically connected to the first contact; a first metal layer disposed on the second dielectric layer and in direct contact with the first conductive via; a second conductive via disposed in the second dielectric layer within the memory region, wherein the second conductive via is electrically connected to the second contact; and a second metal layer disposed on the second dielectric layer and in direct contact with the second conductive via.

[0016] Another aspect of the present invention provides a method for forming a semiconductor memory device, comprising: providing a substrate having a logic region and a memory region thereon; forming a first dielectric layer on the substrate, covering the logic region and the memory region; forming a first contact and a second contact within the first dielectric layer, respectively located in the logic region and the memory region; forming a dielectric masking layer on the first contact in the logic region; forming a memory stack structure on the second contact in the memory region; and forming a second dielectric layer on the memory stack structure in the memory region, the first dielectric layer, and the dielectric masking layer in the logic region.

[0017] According to an embodiment of the present invention, the dielectric masking layer covers the logic region but does not extend to the memory region.

[0018] According to an embodiment of the present invention, the thickness of the dielectric shielding layer is 600-1000 angstroms.

[0019] According to an embodiment of the present invention, the dielectric shielding layer comprises silicon oxide.

[0020] According to an embodiment of the present invention, the dielectric shielding layer is in direct contact with the first dielectric layer.

[0021] According to an embodiment of the present invention, the second dielectric layer comprises a low dielectric constant dielectric material.

[0022] According to an embodiment of the present invention, the memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, and a top electrode layer disposed on the switching layer, wherein the bottom electrode layer is electrically connected to the second contact.

[0023] According to an embodiment of the present invention, the first contact and the second contact are tungsten contacts.

[0024] According to an embodiment of the present invention, the method further includes: forming a first sidewall on the sidewall of the dielectric masking layer at the junction of the logic region and the memory region; and forming a second sidewall on the sidewall of the memory stack structure within the memory region.

[0025] According to an embodiment of the present invention, the method further includes: forming a first conductive via within the second dielectric layer and the dielectric masking layer in the logic region, wherein the first conductive via is electrically connected to the first contact; forming a first metal layer on the second dielectric layer and directly contacting the first conductive via; forming a second conductive via within the second dielectric layer in the memory region, wherein the second conductive via is electrically connected to the second contact; and forming a second metal layer on the second dielectric layer and directly contacting the second conductive via. Simple Explanation of the Diagram

[0026] Figures 1 to 7 are schematic diagrams illustrating a method for forming a semiconductor memory device according to an embodiment of the present invention. Implementation

[0027] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments can be implemented. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0028] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0029] Please refer to Figures 1 through 7, which are schematic diagrams illustrating a method for forming a semiconductor memory device according to an embodiment of the present invention. As shown in Figure 1, a substrate 100, such as a silicon substrate, is first provided, having a logic region LR and a memory region MR thereon. Next, a chemical vapor deposition process can be performed to form a dielectric layer 110, such as a silicon oxide layer, on the substrate 100, covering the logic region LR and the memory region MR.

[0030] According to an embodiment of the present invention, circuit element D1 can be formed on substrate 100 within logic region LR, and circuit element D2 can be formed on substrate 100 within memory region MR. For example, circuit element D1 and circuit element D2 may include transistors, but are not limited thereto. According to an embodiment of the present invention, dielectric layer 110 covers circuit element D1 and circuit element D2.

[0031] Next, photolithography, etching, deposition, and chemical mechanical polishing processes can be performed, while contacts C1-C4 are formed in the dielectric layer 110 within the logic region LR and the memory region MR. Contacts C1-C2 are located within the logic region LR, and contacts C3-C4 are located within the memory region MR. According to an embodiment of the present invention, contacts C1-C4 are, for example, tungsten contacts. Contacts C1-C4 can be electrically connected to the corresponding terminals of circuit elements D1 and D2, for example, drains or sources. At this time, the top surface of each contact C1-C4 is flush with the top surface of the dielectric layer 110.

[0032] Next, as shown in Figure 2, a dielectric layer BL, such as a silicon oxide layer, with a thickness of approximately 600-1000 angstroms is deposited over the entire substrate 100. A photoresist pattern PR1 is then formed on the dielectric layer BL, which covers the logic region LR but does not cover the memory region MR.

[0033] Next, as shown in Figure 3, an anisotropic dry etching process is performed to remove the dielectric layer BL not covered by the photoresist pattern PR1, leaving only the dielectric layer BL located on the logic region LR, forming the dielectric mask layer BM. According to an embodiment of the present invention, the dielectric mask layer BM is in direct contact with the dielectric layer 110. At this time, the contacts C1-C2 located in the logic region LR are covered by the dielectric mask layer BM. According to an embodiment of the present invention, the dielectric mask layer BM covers the logic region LR but does not extend to the memory region MR. Subsequently, the remaining photoresist pattern PR1 is removed.

[0034] As shown in Figure 4, a deposition process is then performed to form a memory stack film 200 on the substrate 100. According to an embodiment of the present invention, the memory stack film 200 includes, for example, a bottom electrode layer 201, a switching layer 202 disposed on the bottom electrode layer 201, and a top electrode layer 203 disposed on the switching layer 202, wherein the bottom electrode layer 201 directly contacts contacts C3-C4. Within the logic region LR, the memory stack structure 200 is deposited on a dielectric masking layer BM, and therefore does not directly contact contacts C1-C2.

[0035] Next, a photoresist pattern PR2 is formed on the memory stack film 200 within the memory region MR. According to an embodiment of the present invention, an additional bottom anti-reflective layer 210 may be formed between the photoresist pattern PR2 and the memory stack film 200.

[0036] As shown in Figure 5, an anisotropic dry etching process is then performed to etch the bottom anti-reflective layer 210 and the memory stack film 200 that are not covered by the photoresist pattern PR2 until the dielectric masking layer BM is exposed. At this time, a plurality of patterned memory stack structures 200a are formed in the memory region MR, respectively located on the corresponding contacts C3-C4. Due to the over-etching, the surface of the dielectric layer 110 in the memory region MR will be slightly recessed, but the surfaces of the dielectric layer 110 and contacts C1-C2 in the logic region LR will not be recessed and will remain flat due to the protection of the dielectric masking layer BM.

[0037] Next, a sidewall submaterial layer 310, such as a silicon nitride layer, is deposited over the memory region MR and logic region LR. The sidewall submaterial layer 310 is deposited conformally on the surfaces of the dielectric mask layer BM, the memory stack structure 200a, and the dielectric layer 110.

[0038] As shown in Figure 6, an anisotropic dry etching process is then performed to form sidewall SP1 on the sidewall of the dielectric mask layer BM at the boundary between the logic region LR and the memory region MR, and sidewall SP2 on the sidewall of the memory stack structure 200a within the memory region MR. Next, a dielectric layer 120 is formed on the memory stack structure 200a and dielectric layer 110 within the memory region MR, and on the dielectric mask layer BM within the logic region LR. According to an embodiment of the present invention, the dielectric layer 120 may, for example, comprise a low dielectric constant dielectric material.

[0039] As shown in Figure 7, the dielectric layer 120 can then be planarized. Next, conductive vias V1-V2 are formed in the dielectric layer 120 and the dielectric masking layer BM within the logic region LR, wherein the conductive vias V1-V2 are electrically connected to contacts C1-C2, respectively. Simultaneously, conductive vias V3-V4 are formed in the dielectric layer 120 within the memory region MR, wherein the conductive vias V3-V4 are electrically connected to the top electrode layer 203 of the memory stack structure 200a, respectively.

[0040] Subsequently, metal layers ML1-ML4 are formed on the dielectric layer 120 and directly contact the conductive vias V1-V4, thus completing the fabrication of the semiconductor memory device 10. According to an embodiment of the present invention, the conductive vias V3-V4 and the metal layers ML1-ML4 can be formed using a copper damascene process.

[0041] Structurally, as shown in Figure 7, the semiconductor memory device 10 includes a substrate 100 having a logic region LR and a memory region MR, a dielectric layer 110 located on the substrate 100 and covering the logic region LR and the memory region MR, contacts C1-C2 and contacts C3-C4 disposed within the dielectric layer 110 and respectively located in the logic region LR and the memory region MR, a dielectric masking layer BM disposed on the dielectric layer 110 within the logic region LR, a memory stack structure 200a disposed on contacts C3-C4 and located within the memory region MR, and a dielectric layer 120 disposed on the memory stack structure 200a and the dielectric layer 110 within the memory region MR, and disposed on the dielectric masking layer BM within the logic region LR.

[0042] According to an embodiment of the present invention, the dielectric masking layer BM covers the logic region LR but does not extend into the memory region MR. According to an embodiment of the present invention, the thickness of the dielectric masking layer BM is approximately 600-1000 angstroms. According to an embodiment of the present invention, the dielectric masking layer BM comprises, for example, silicon carbide. According to an embodiment of the present invention, the dielectric masking layer BM is in direct contact with the dielectric layer 110. According to an embodiment of the present invention, the dielectric layer 120 comprises, for example, a low dielectric constant dielectric material.

[0043] According to an embodiment of the present invention, the memory stack structure 200a includes a bottom electrode layer 201, a switching layer 202 disposed on the bottom electrode layer 201, and a top electrode layer 203 disposed on the switching layer 202, wherein the bottom electrode layer 201 is electrically connected to contacts C3-C4.

[0044] According to an embodiment of the present invention, contacts C1-C2 and contacts C3-C4 are tungsten contacts.

[0045] According to an embodiment of the present invention, the semiconductor memory device 10 further includes: a sidewall SP1 disposed on the sidewall of the dielectric masking layer BM, located at the junction of the logic region LR and the memory region MR; and a sidewall SP2 disposed on the sidewall of the memory stack structure 200a, located within the memory region MR.

[0046] According to an embodiment of the present invention, the semiconductor memory device 10 further includes: conductive vias V1-V2 disposed in the dielectric layer 120 and the dielectric masking layer BM within the logic region LR, wherein the conductive vias V1-V2 are electrically connected to contacts C1-C2 respectively; and metal layers ML1-ML2 disposed on the dielectric layer 120 and in direct contact with the conductive vias V1-V2.

[0047] According to an embodiment of the present invention, the semiconductor memory device 10 further includes: conductive vias V3-V4 disposed in a dielectric layer 120 within the memory region MR, wherein the conductive vias V3-V4 are electrically connected to contacts C3-C4; and metal layers ML3-ML4 disposed on the dielectric layer 120 and in direct contact with the conductive vias V3-V4. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0048] 10: Semiconductor memory devices 100:Substrate 110, 120: Dielectric layer 200: Memory Stacking Film 200a: Memory stacking structure 201: Bottom Electrode Layer 202: Switching Layer 203: Top electrode layer 210: Bottom anti-reflective layer 310: Sidewall Submaterial Layer BL: Dielectric layer BM: Dielectric shielding layer C1-C4: Contact D1, D2: Circuit components LR: Logical Region MR: Memory Region PR1, PR2: Photoresist patterns SP1, SP2: Sidewall V1-V4: Conductive vias ML1-ML4: Metallic layers

Claims

1. A semiconductor memory device, comprising: a substrate having a logic region and a memory region thereon; a first dielectric layer located on the substrate and covering the logic region and the memory region; a first contact and a second contact disposed within the first dielectric layer and respectively located in the logic region and the memory region; a dielectric masking layer disposed on the first dielectric layer within the logic region; a memory stack structure disposed on the second contact and located in the memory region; and a second dielectric layer disposed on the memory stack structure and the first dielectric layer within the memory region, and disposed on the dielectric masking layer within the logic region.

2. The semiconductor memory device as claimed in claim 1, wherein, The dielectric masking layer covers the logic region but does not extend into the memory region.

3. The semiconductor memory device as claimed in claim 1, wherein, The thickness of the dielectric shielding layer is 600-1000 angstroms.

4. The semiconductor memory device as claimed in claim 1, wherein, The dielectric shielding layer contains silicon oxide.

5. The semiconductor memory device as claimed in claim 1, wherein, The dielectric shielding layer is in direct contact with the first dielectric layer.

6. The semiconductor memory device as claimed in claim 1, wherein, The second dielectric layer contains a low dielectric constant dielectric material.

7. The semiconductor memory device as claimed in claim 1, wherein, The memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, and a top electrode layer disposed on the switching layer, wherein the bottom electrode layer is electrically connected to the second contact.

8. The semiconductor memory device as claimed in claim 1, wherein, The first contact and the second contact are tungsten contacts.

9. The semiconductor memory device of claim 1, further comprising: a first sidewall disposed on the sidewall of the dielectric mask layer at the junction of the logic region and the memory region; and a second sidewall disposed on the sidewall of the memory stack structure at the memory region.

10. The semiconductor memory device of claim 1, further comprising: a first conductive via disposed in the second dielectric layer and the dielectric masking layer within the logic region, wherein, The first conductive via is electrically connected to the first contact; a first metal layer is disposed on the second dielectric layer and is in direct contact with the first conductive via; a second conductive via is disposed in the second dielectric layer within the memory region, wherein the second conductive via is electrically connected to the second contact; and a second metal layer is disposed on the second dielectric layer and is in direct contact with the second conductive via.

11. A method of forming a semiconductor memory device, comprising: providing a substrate having a logic region and a memory region thereon; forming a first dielectric layer on the substrate, covering the logic region and the memory region; forming a first contact and a second contact within the first dielectric layer, respectively located in the logic region and the memory region; forming a dielectric masking layer on the first contact in the logic region; forming a memory stack structure on the second contact in the memory region; and forming a second dielectric layer on the memory stack structure in the memory region, the first dielectric layer, and the dielectric masking layer in the logic region.

12. The method as described in claim 11, wherein, The dielectric masking layer covers the logic region but does not extend into the memory region.

13. The method as described in claim 11, wherein, The thickness of the dielectric shielding layer is 600-1000 angstroms.

14. The method as described in claim 11, wherein, The dielectric shielding layer contains silicon oxide.

15. The method as described in claim 11, wherein, The dielectric shielding layer is in direct contact with the first dielectric layer.

16. The method as described in claim 11, wherein, The second dielectric layer contains a low dielectric constant dielectric material.

17. The method as described in claim 11, wherein, The memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, and a top electrode layer disposed on the switching layer, wherein the bottom electrode layer is electrically connected to the second contact.

18. The method as described in claim 11, wherein, The first contact and the second contact are tungsten contacts.

19. The method of claim 11, further comprising: forming a first sidewall on the sidewall of the dielectric mask layer at the boundary between the logic region and the memory region; and forming a second sidewall on the sidewall of the memory stack structure within the memory region.

20. The method of claim 11, further comprising: forming a first conductive via within the second dielectric layer and the dielectric masking layer in the logic region, wherein, The first conductive via is electrically connected to the first contact; a first metal layer is formed on the second dielectric layer and is in direct contact with the first conductive via; a second conductive via is formed in the second dielectric layer in the memory region, wherein the second conductive via is electrically connected to the second contact; and a second metal layer is formed on the second dielectric layer and is in direct contact with the second conductive via.

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