Transistor isolation structures and methods of formation

Abstract

The present disclosure is directed to a method for fabricating spacer structures between source / drain (S / D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructured layers on a substrate. The method also includes etching edge portions of the first nanostructured layers in the fin structure to form cavities and depositing a polymer spacer layer within the cavities to form inner spacers. The method further includes forming S / D epitaxial structures on the substrate to abut the fin structure and the inner spacers so that an air gap is formed between sidewall portions of the S / D epitaxial structures and the inner spacers.

Images