Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device at least includes a dielectric layer, an oxide semiconductor layer disposed on the dielectric layer, a gate electrode, a gate insulating layer, first spacers, second spacers, a protection layer, and a plurality of source / drain electrode layers. The oxide semiconductor layer is disposed on the dielectric layer, the gate electrode is disposed above the oxide semiconductor layer, and the gate insulating layer is disposed between the gate electrode and the oxide semiconductor layer. The first spacers are disposed on the sidewalls of the oxide semiconductor layer, and the second spacers are disposed on the sidewalls of the gate electrode. The protection layer is located between the second spacers and the oxide semiconductor layer. The source / drain electrode layers are disposed on the oxide semiconductor layer at two sides of the gate electrode.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same using an oxide semiconductor as a channel. [Previous Technology]

[0002] Oxide semiconductor field-effect transistors (OSFETs) are provided in a BEOL (back-end) structure for advanced applications, such as oxide semiconductor (OS) / silicon (Si) drivers for organic light-emitting diode (OLED) displays.

[0003] However, during the manufacturing of oxide semiconductor field-effect transistors, the etching process performed to form the source / drain electrode layers will etch into the oxide semiconductor layer and leave metal residues on its surface. If the oxide semiconductor layer is damaged by etching, it will affect the Id-Vg characteristics; the metal residues will cause source / drain short circuits (S / D short) or leakage. [Summary of the Invention]

[0004] The present invention provides a semiconductor device and a method for manufacturing the same, which can avoid metal residues on the oxide semiconductor layer, thereby ensuring that the electrical characteristics of the semiconductor device are not affected.

[0005] A semiconductor device according to the present invention includes a dielectric layer, an oxide semiconductor layer disposed on the dielectric layer, a gate electrode, a gate insulating layer, a first spacer wall, a second spacer wall, a protective layer, and a plurality of source and drain electrode layers. The oxide semiconductor layer is disposed on the dielectric layer, the gate electrode is disposed above the oxide semiconductor layer, and the gate insulating layer is disposed between the gate electrode and the oxide semiconductor layer. The first spacer wall is disposed on the sidewall of the oxide semiconductor layer, and the second spacer wall is disposed on the sidewall of the gate electrode. The protective layer is located between the second spacer wall and the oxide semiconductor layer. The source and drain electrode layers are disposed on the oxide semiconductor layers on both sides of the gate electrode.

[0006] In one embodiment of the present invention, the material of the protective layer is different from the material of the first gap wall.

[0007] In one embodiment of the present invention, the above-mentioned source and drain electrode layers extend to cover the first gap wall.

[0008] In one embodiment of the present invention, the top surface of the gate electrode is coplanar with the top surfaces of the source and drain electrode layers.

[0009] In one embodiment of the present invention, the gate insulating layer extends between the gate electrode and the protective layer.

[0010] In one embodiment of the present invention, the gate insulating layer extends between the gate electrode and the second gap wall.

[0011] A method for manufacturing a semiconductor device according to the present invention includes the following steps: Forming an oxide semiconductor layer on a dielectric layer. Forming a first protective layer on the oxide semiconductor layer. Forming a second protective layer on the first protective layer. Patterning the second protective layer to form a patterned structure. Patterning the first protective layer and the oxide semiconductor layer. Forming a first gap wall on the sidewall of the oxide semiconductor layer and a second gap wall on the sidewall of the patterned structure, exposing a portion of the first protective layer. Removing the exposed first protective layer until the oxide semiconductor layer is exposed. Forming a conductor layer on the oxide semiconductor layer and the patterned structure. Forming an interlayer dielectric layer on the conductor layer. Planarizing the interlayer dielectric layer until the conductor layer is exposed. Planarizing the conductor layer until the second protective layer is exposed. Removing the second protective layer until the first protective layer is exposed. Removing the exposed first protective layer until the oxide semiconductor layer is exposed. Forming a gate insulating layer on the surface of the oxide semiconductor layer. Forming a gate electrode on the gate insulating layer.

[0012] In another embodiment of the present invention, the step of forming the gate insulating layer includes: conformally depositing the gate insulating layer on the surface of the second spacer wall and the oxide semiconductor layer.

[0013] In another embodiment of the present invention, the material of the second protective layer includes polycrystalline silicon.

[0014] In another embodiment of the present invention, the method of patterning the second protective layer is to use the first protective layer as a stop layer.

[0015] In order to make the above features of the present invention more obvious and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0016] The present invention can be understood by referring to the following detailed description and in conjunction with the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.

[0017] FIG1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

[0018] In FIG1, the semiconductor device of the first embodiment includes a dielectric layer 100, an oxide semiconductor layer OS, a gate electrode 102, a gate insulating layer 104, a first spacer S1, a second spacer S2, a protective layer 106, and a plurality of source and drain electrode layers 108. In some embodiments, the dielectric layer 100 may be a layer in a back-end process (BEOL) structure (not shown), which means that a semiconductor substrate and other semiconductor elements may be disposed below the dielectric layer 100, but the present invention is not limited thereto. The oxide semiconductor layer OS is disposed on the dielectric layer 100, wherein the material of the oxide semiconductor layer OS is, for example, gallium oxide (GaO x), zinc gallium oxide (Ga 2Zn xO y), or indium gallium zinc oxide (IGZO), but is not limited thereto. A gate electrode 102 is disposed above the oxide semiconductor layer OS. The material of the gate electrode 102 can be a metallic material, such as copper (Cu), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), titanium nitride (TiN), tungsten (W), and / or tantalum (Ta), but is not limited thereto. A gate insulating layer 104 is disposed between the gate electrode 102 and the oxide semiconductor layer OS. The material of the gate insulating layer 104 is such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, gallium oxide, or zinc gallium oxide, but is not limited thereto.

[0019] Referring to Figure 1, a first gap wall S1 is disposed on the sidewalls OSs of the oxide semiconductor layer OS. The material of the first gap wall S1 can be a dielectric material, such as silicon oxide, silicon nitride, etc., but is not limited thereto. A second gap wall S2 is disposed on the sidewalls 102s of the gate electrode 102. The material of the second gap wall S2 can be a dielectric material, such as silicon oxide, silicon nitride, etc., but is not limited thereto. In some embodiments, the gate insulating layer 104 may also extend between the gate electrode 102 and the second gap wall S2, so the second gap wall S2 is not in contact with the sidewalls 102s of the gate electrode 102. In some embodiments, the first gap wall S1 and the second gap wall S2 can be formed by the same process, so the first gap wall S1 and the second gap wall S2 can be made of the same material; or, the thickness t1 of the first gap wall S1 is the same as or close to the thickness t2 of the second gap wall S2. The processes for the first gap wall S1 and the second gap wall S2 will be described below. The protective layer 106 is located between the second spacer wall S2 and the oxide semiconductor layer OS. The material of the protective layer 106 can be a dielectric material, such as silicon oxide, silicon nitride, etc., but is not limited thereto. In some embodiments, in order to protect the underlying oxide semiconductor layer OS, the material of the protective layer 106 can be different from the material of the first spacer wall S1, for example, a dielectric material that has etch selectivity compared to the first spacer wall S1. In some embodiments, the gate insulating layer 104 can also extend between the gate electrode 102 and the protective layer 106, so the protective layer 106 does not contact the sidewall 102s of the gate electrode 102. In some embodiments, the thickness of the protective layer 106 is greater than the thickness of the gate insulating layer 104.

[0020] Referring again to Figure 1, the source and drain electrode layers 108 are disposed on the oxide semiconductor layer OS on both sides of the gate electrode 102. The material of the source and drain electrode layers 108 can be a metallic material, such as Cu, Al, Mo, Cr, Ti, TiN and / or Ta, but is not limited thereto. In some embodiments, the source and drain electrode layers 108 may also extend to cover the first spacer wall S1 and contact the dielectric layer 100. The source and drain electrode layers 108 may be conformally deposited on the oxide semiconductor layer OS and the first spacer wall S1, so their surfaces are not planar. In some embodiments, due to the process (e.g., planarization process), the top surface of the gate electrode 102 is coplanar with the top surface of the source and drain electrode layers 108, and the top surface of the gate electrode 102 here refers to the topmost surface of the gate electrode 102, but the present invention is not limited thereto; in other embodiments, the top surface of the gate electrode 102 may be higher or lower than the top surface of the source and drain electrode layers 108. In addition, the semiconductor device may also include an interlayer dielectric layer (ILD) 110 formed on the source and drain electrode layers 108.

[0021] Figures 2A to 2F are schematic cross-sectional views of the manufacturing process of a semiconductor device according to a second embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be repeated here.

[0022] Referring to FIG2A, an oxide semiconductor layer 200 is formed on the dielectric layer 100. In some embodiments, the step of forming the oxide semiconductor layer 200 includes depositing the oxide semiconductor layer 200 all over the dielectric layer 100, wherein the material of the oxide semiconductor layer 200 is, for example, gallium oxide (GaO x), zinc gallium oxide (Ga 2Zn xO y), or indium gallium zinc oxide (IGZO), but is not limited thereto. A first protective layer 202 is formed on the oxide semiconductor layer 200. A second protective layer 204 is formed on the first protective layer 202, wherein the second protective layer 204 is made of a different material from the first protective layer 202. In some embodiments, the material of the first protective layer 202 may be a dielectric material, such as silicon oxide, silicon nitride, etc.; the material of the second protective layer 204 may be, for example, polycrystalline silicon, but is not limited thereto.

[0023] Referring to FIG2B, the second protective layer 204 in FIG2A is patterned to form a patterned structure PA. In some embodiments, the above patterning method involves first forming a patterned mask (not shown) to cover a portion of the patterned structure PA, and then using the first protective layer 202 as a stop layer to etch the second protective layer 204 in FIG2A. Afterwards, the first protective layer 202 and the oxide semiconductor layer 200 in FIG2A are patterned to form an oxide semiconductor layer OS and a first protective layer 202 having the same contour as the oxide semiconductor layer OS. However, the present invention is not limited thereto. In other embodiments, the second protective layer 204, the first protective layer 202, and the oxide semiconductor layer 200 in FIG2A can be patterned simultaneously, and then a second patterning process can be performed on the uppermost second protective layer 204 to form the patterned structure PA.

[0024] Referring to Figure 2C, a first gap wall S1 is formed on the sidewalls OSs of the oxide semiconductor layer OS, and a second gap wall S2 is formed on the sidewalls PAs of the patterned structure PA, exposing a portion of the first protective layer 202. In some embodiments, the formation of the first gap wall S1 and the second gap wall S2 involves, for example, firstly, conformally depositing a dielectric material (not shown) on the patterned structure PA, the first protective layer 202, the sidewalls OSs of the oxide semiconductor layer OS, and the dielectric layer 100, and then etching back this dielectric material until the first protective layer 202 is exposed. Therefore, the first gap wall S1 and the second gap wall S2 are dielectric materials and can be the same material. Next, the exposed first protective layer 202 is removed until the oxide semiconductor layer OS is exposed. Since the patterned structure PA and the first protective layer 202 are made of different materials, and the first gap wall S1 and the second gap wall S2 can be selected as dielectric materials with etching selectivity compared to the first protective layer 202, the oxide semiconductor layer OS under the patterned structure PA can be protected during the etching process of removing the first protective layer 202.

[0025] Referring to Figure 2D, a conductor layer 206 is deposited on the oxide semiconductor layer OS and the patterned structure PA, and then an interlayer dielectric layer 208 is formed on the conductor layer 206. The material of the conductor layer 206 can be a metallic material, such as Cu, Al, Mo, Cr, Ti, TiN and / or Ta, but is not limited thereto.

[0026] Referring to Figure 2E, a planarization process is performed until the second spacer wall S2 is exposed. For example, the interlayer dielectric layer 208 in Figure 2D can be planarized first until the conductor layer 206 is exposed; then the conductor layer 206 in Figure 2D is planarized until the patterned structure PA (i.e., the second protective layer) in Figure 2D is exposed, wherein the aforementioned planarization process is, for example, a chemical mechanical polishing (CMP) process. Then, the patterned structure PA is completely removed until the first protective layer 202 in Figure 2D is exposed. Since the patterned structure PA and the first protective layer 202 are different materials, the etching process can be precisely controlled so as not to etch through the first protective layer 202 and the interlayer dielectric layer 110. After that, the exposed first protective layer 202 is removed until the oxide semiconductor layer OS is exposed, and the remaining protective layer 106 will be located between the second spacer wall S2 and the oxide semiconductor layer OS. Since the etching target of this removal step is the dielectric material (first protective layer 202), no metal residue will remain on the surface of the oxide semiconductor layer OS.

[0027] Referring to FIG2F, a gate insulating layer 104 is formed on the surface of the oxide semiconductor layer OS. In some embodiments, the step of forming the aforementioned gate insulating layer 104 is, for example, conformally depositing the gate insulating layer on the surface of the second spacer wall S2 and the oxide semiconductor layer OS. A gate electrode 102 is formed on the gate insulating layer 104. In some embodiments, the step of forming the aforementioned gate electrode 102 is, for example, first filling the space between the second spacer walls S2 with metal material, and then removing the excess metal material using an etching or planarization process.

[0028] Based on the above, during the manufacturing process of the semiconductor device of the present invention, plasma etching of metal materials is avoided to form the source and drain electrodes. Instead, different protective layers are used to first form a virtual gate on the surface of the oxide semiconductor layer. The protective layer is removed only after the source and drain electrodes are formed. Therefore, the surface of the oxide semiconductor layer is hardly damaged, and there is no metal residue. Thus, the present invention can improve the Id-Vg characteristics and avoid source / drain short circuits or leakage.

[0029] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0030] FIG1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG2A to FIG2F are schematic cross-sectional views of the manufacturing process of a semiconductor device according to a second embodiment of the present invention.

Claims

1. A semiconductor device, comprising: Dielectric layer; An oxide semiconductor layer is disposed on the dielectric layer; The gate electrode is disposed above the oxide semiconductor layer; A gate insulating layer is disposed between the gate electrode and the oxide semiconductor layer; a first gap wall is disposed on the sidewall of the oxide semiconductor layer, wherein the top surface of the first gap wall is coplanar with the top surface of the oxide semiconductor layer; a second gap wall is disposed on the sidewall of the gate electrode; a protective layer is disposed between the second gap wall and the oxide semiconductor layer; and a plurality of source and drain electrode layers are disposed on the oxide semiconductor layer on both sides of the gate electrode.

2. The semiconductor device as claimed in claim 1, wherein the material of the protective layer is different from the material of the first spacer wall.

3. The semiconductor device as claimed in claim 1, wherein the plurality of source and drain electrode layers extend to cover the first gap wall.

4. The semiconductor device of claim 1, wherein the top surface of the gate electrode is coplanar with the top surfaces of the plurality of source and drain electrode layers.

5. The semiconductor device of claim 1, wherein the gate insulating layer extends between the gate electrode and the protective layer.

6. The semiconductor device of claim 1, wherein the gate insulating layer extends between the gate electrode and the second spacer wall.

7. A method for manufacturing a semiconductor device, comprising: An oxide semiconductor layer is formed on the dielectric layer; A first protective layer is formed on the oxide semiconductor layer; A second protective layer is formed on the first protective layer; The process involves: patterning the second protective layer to form a patterned structure; patterning the first protective layer and the oxide semiconductor layer; forming a first spacer wall on the sidewall of the oxide semiconductor layer and a second spacer wall on the sidewall of the patterned structure, exposing a portion of the first protective layer; removing the exposed first protective layer until the oxide semiconductor layer is exposed; forming a conductor layer on the oxide semiconductor layer and the patterned structure; forming an interlayer dielectric layer on the conductor layer; planarizing the interlayer dielectric layer until the conductor layer is exposed; planarizing the conductor layer until the second protective layer is exposed; removing the second protective layer until the first protective layer is exposed; removing the exposed first protective layer until the surface of the oxide semiconductor layer is exposed; forming a gate insulating layer on the surface of the oxide semiconductor layer; and forming a gate electrode on the gate insulating layer.

8. A method of manufacturing a semiconductor device as claimed in claim 7, wherein the step of forming the gate insulating layer comprises: A gate insulating layer is conformally deposited on the surface of the second gap wall and the oxide semiconductor layer.

9. A method of manufacturing a semiconductor device as claimed in claim 7, wherein the material of the second protective layer comprises polycrystalline silicon.

10. A method for manufacturing a semiconductor device as claimed in claim 7, wherein the method for patterning the second protective layer is to use the first protective layer as a stop layer.

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