Semiconductor device

Abstract

Disclosed is a semiconductor device, which includes an epitaxial substrate, a gate structure, a source electrode and a drain electrode. The epitaxial substrate includes a semiconductor substrate, a buffer layer formed on the semiconductor substrate, a gallium nitride channel layer formed on the buffer layer, and a barrier layer formed on the gallium nitride channel layer. A two-dimensional electron gas (2DEG) is generated in the gallium nitride channel layer adjacent to the barrier layer. The gate structure, the source electrode and the drain electrode are disposed on the epitaxial substrate. The source electrode and the drain electrode are disposed on the opposite sides of the gate structure respectively. One of the source electrode and the drain electrode is connected to an antenna, the other one of the source electrode and the drain electrode is connected to a tuning element, and the gate structure is configured to control a connection between the tuning element and the antenna. Therefore, the breakdown capability of the semiconductor device is increased, and the semiconductor device is suitable for an antenna tuning switch.

Description

Technical Field

[0001] This application relates to a semiconductor element, and more particularly to a semiconductor element used in an antenna tuner. Prior Technology

[0002] Antennas are essential components in mobile communication systems with multiple operating frequency bands. An antenna tuner is positioned between the antenna and the RF front-end. The antenna tuner provides adjustable impedance tuning through tuning elements, matching the impedance between the transceiver and the antenna, and adjusting the antenna's resonant frequency, thereby improving signal transmission efficiency and quality.

[0003] Antenna tuners comprise a plurality of switching circuits connected in parallel and their corresponding tuning elements connected in series. Existing switching circuits typically employ silicon-on-insulator (SOI) transistors. Since SOI transistors have a relatively low breakdown voltage, existing switching circuits typically include at least twenty-five SOI transistors connected in series to achieve a breakdown voltage of 100 volts, making them suitable for antenna tuners in high-power environments (e.g., 34 dBm RF power in 5G systems). However, because at least twenty-five SOI transistors are connected in series in the switching circuit, capacitors are required to compensate for nonlinear changes caused by voltage variations, resulting in a large form factor and poor linear control.

[0004] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a semiconductor element that, when applied to an antenna tuner, can solve the problems of large size and poor linear control in existing antenna tuners, which require at least twenty-five silicon-insulator-coated transistors in series to achieve high breakdown voltage and require capacitors to compensate for nonlinear changes caused by voltage variations.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows:

[0007] This application provides a semiconductor element used in an antenna tuner. The semiconductor element includes: an epitaxial substrate, a gate structure, a source electrode, and a drain electrode. The epitaxial substrate includes a semiconductor substrate, a buffer layer formed on the semiconductor substrate, a gallium nitride channel layer formed on the buffer layer, and a barrier layer formed on the gallium nitride channel layer. A two-dimensional electron gas is generated in the gallium nitride channel layer near the barrier layer. The gate structure, source electrode, and drain electrode are disposed on the epitaxial substrate. The source electrode and drain electrode are respectively disposed on opposite sides of the gate structure. One of the source electrode and drain electrode is used to connect to an antenna, and the other of the source electrode and drain electrode is used to connect to a tuning element. The gate structure is used to control the on / off state of the tuning element and the antenna.

[0008] In this embodiment, the breakdown capability of the semiconductor element is increased by leveraging the material properties (i.e., wide bandgap) of the gallium nitride channel layer. This allows the antenna tuner's switching circuit to achieve the required high breakdown voltage with only a single semiconductor element or a small number of semiconductor elements connected in series (less than 25). Furthermore, because only a small number of semiconductor elements are connected in series, there is no need to use capacitors to compensate for nonlinear changes caused by voltage variations. Therefore, the antenna tuner using the semiconductor element described in this application has a smaller form factor and better linear control, and is suitable for high-output-power operating systems. Simple Explanation of the Diagram

[0009] The drawings illustrated herein are provided to further illustrate this application and form part of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 is a schematic diagram of an embodiment of an antenna tuner incorporating semiconductor elements applied in this application; Figure 2 is a schematic diagram of the first embodiment of the antenna tuner connected to the antenna in Figure 1; Figure 3 is a schematic diagram of a second embodiment of the antenna tuner connected to the antenna in Figure 1; Figure 4 is a schematic diagram of a third embodiment of the antenna tuner connected to the antenna in Figure 1; and Figure 5 is a schematic diagram of the fourth embodiment of the antenna tuner connected to the antenna in Figure 1. Implementation

[0010] The embodiments of the present invention will be described below with reference to the accompanying drawings. Directional terms used in the following embodiments, such as up, down, left, right, front, and back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention. In these drawings, the same reference numerals denote the same or similar elements or method flows.

[0011] It must be understood that the terms "including" and "comprising" used in this specification are used to indicate the presence of specific technical features, values, method steps, operation processes and / or components, but do not preclude the addition of more technical features, values, method steps, operation processes, components, or any combination thereof.

[0012] It is important to understand that when a component is described as "connected" or "coupled" to another component, it can be a direct connection or coupling to another component, and intermediate components may be involved. Conversely, when a component is described as "directly connected" or "directly coupled" to another component, there are no intermediate components involved.

[0013] Please refer to Figure 1, which is a schematic diagram of an embodiment of an RF circuit including an antenna tuner using the semiconductor elements of this application. As shown in Figure 1, the RF circuit 100 includes an RF front-end 110, an antenna tuner 121, an antenna tuner 122, an antenna 131, and an antenna 132. The RF front-end 110 includes a first signal receiver 11, a first signal output 21, a first power amplifier 31, a first single-pole double-throw (SPDT) switch 41, a first filter 51, a first low-noise amplifier (LNA) 61, a first double-pole double-throw (DPDT) switch 71, a first coupler 81, a second signal receiver 12, a second signal output 22, a second power amplifier 32, a second SPDT switch 42, a second filter 52, a second low-noise amplifier 62, a second DPDT switch 72, and a second coupler 82.

[0014] Antennas 131 and 132 can be a single-stage antenna, an inverted F-shaped antenna (IFA), a loop antenna, a dipole antenna, or a planar inverted-F antenna (PIFA), respectively. The first power amplifier 31 is configured to amplify the radio frequency signal with a first frequency band from the first signal output terminal 21, and the second power amplifier 32 is configured to amplify the radio frequency signal with a second frequency band from the second signal output terminal 22.

[0015] The first filter 51 is a bandpass filter configured to allow radio frequency (RF) signals in a first frequency band to pass through, and the second filter 52 is a bandpass filter configured to allow RF signals in a second frequency band to pass through. The bandpass filters may be filters configured to allow RF signals (e.g., with attenuation of less than 3 dB) to pass through within the frequency band. The first filter 51 and the second filter 52 may include acoustic filters, inductor-capacitor (LC) filters, cavity filters, combinations thereof, etc., and the acoustic filters may include surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, etc. The first frequency band may be an LTE frequency band, and the second frequency band may be a wireless local area network (WLAN) frequency band.

[0016] The first low-noise amplifier 61 is configured to amplify the radio frequency signal with a first frequency band passing through the first filter 51, and output the amplified radio frequency signal with the first frequency band; the second low-noise amplifier 62 is configured to amplify the radio frequency signal with a second frequency band passing through the second filter 52, and output the amplified radio frequency signal with the second frequency band. The first coupler 81 and the second coupler 82 may be, but are not limited to, directional couplers.

[0017] Antenna tuner 121 is connected to antenna 131, and antenna tuner 122 is connected to antenna 132. Antenna 131 and antenna 132 are used to transmit and receive signals in different frequency bands. Antenna tuner 121 is used to match the impedance of antenna 131 with RF front-end 110 and adjust the resonant frequency of antenna 131. Antenna tuner 122 is used to match the impedance of antenna 132 with RF front-end 110 and adjust the resonant frequency of antenna 132.

[0018] After the first signal output terminal 21 receives a radio frequency signal with a first frequency band from the radio frequency transceiver (not shown), the transmission path of the radio frequency signal with the first frequency band is as follows: it is transmitted to the antenna 131 via the first power amplifier 31, the first single-pole double-throw switch 41, the first filter 51, the second double-pole double-throw switch 72, the first coupler 81, and the antenna tuner 121. This allows the antenna 131 to convert the radio frequency signal with the first frequency band into an electromagnetic wave with the first frequency band and radiate the electromagnetic wave with the first frequency band. The antenna 131 can receive electromagnetic waves with the first frequency band in space and convert them into a radio frequency signal with the first frequency band. The transmission path of the radio frequency signal with the first frequency band is as follows: it is transmitted to the radio frequency transceiver via the antenna tuner 121, the first coupler 81, the second double-pole double-throw switch 72, the first filter 51, the first single-pole double-throw switch 41, the first low-noise amplifier 61, the first double-pole double-throw switch 71, and the first signal receiving terminal 11.

[0019] After the second signal output terminal 22 receives the radio frequency signal with a second frequency band from the radio frequency transceiver, the transmission path of the radio frequency signal with a second frequency band is as follows: it is transmitted to the antenna 132 via the second power amplifier 32, the second single-pole double-throw switch 42, the second filter 52, the second double-pole double-throw switch 72, the second coupler 82 and the antenna tuner 122, so that the antenna 132 can convert the radio frequency signal with a second frequency band into an electromagnetic wave with a second frequency band and radiate the electromagnetic wave with a second frequency band. The antenna 132 can receive electromagnetic waves with a second frequency band in space and convert the electromagnetic waves with a second frequency band into a radio frequency signal with a second frequency band. The transmission path of the radio frequency signal with a second frequency band is as follows: it is transmitted to the radio frequency transceiver via the antenna tuner 122, the second coupler 82, the second double-pole double-throw switch 72, the second filter 52, the second single-pole double-throw switch 42, the second low noise amplifier 62, the first double-pole double-throw switch 71 and the second signal receiving terminal 12.

[0020] The antenna tuner 121, antenna tuner 122, first single-pole double-throw switch 41, first double-pole double-throw switch 71, second single-pole double-throw switch 42, and second double-pole double-throw switch 72 can be controlled by the radio frequency transceiver. The circuit architecture of antenna tuner 121 and antenna tuner 122 can be the same or different, and can be adjusted and designed according to actual needs. Antenna tuner 121 and antenna tuner 122 can be high-power antenna tuners, such as 4G or 5G antenna tuners used in smartphones, WiFi antenna tuners used in routers, Internet of Things (IoT) radio frequency front-end antenna tuners or transfer switches used in wireless modules, but this embodiment is not intended to limit this application.

[0021] Please refer to Figures 1 and 2. Figure 2 is a schematic diagram of the first embodiment of the antenna tuner connected to the antenna in Figure 1. The switching circuit 1211 of the antenna tuner 121 can use a single semiconductor element 200 (i.e., the semiconductor element 200 is applied to the antenna tuner 121). The semiconductor element 200 includes: an epitaxial substrate 210, a gate structure 220, a source electrode 230, and a drain electrode 240. The epitaxial substrate 210 includes a semiconductor substrate 211, a buffer layer 212 formed on the semiconductor substrate 211, a gallium nitride channel layer 213 formed on the buffer layer 212, and a barrier layer 214 formed on the gallium nitride channel layer 213. A two-dimensional electron gas 90 is generated in the gallium nitride channel layer 213 near the barrier layer 214. The two-dimensional electron gas 90 refers to the phenomenon that electron gas can move freely in two dimensions but is restricted in the third dimension. It can significantly improve the carrier / electron migration speed of the semiconductor element 200. The two-dimensional electron gas 90 forms a conductive channel of the semiconductor element 200. A gate structure 220, a source electrode 230, and a drain electrode 240 are disposed on an epitaxial substrate 210. The source electrode 230 and the drain electrode 240 are respectively disposed on opposite sides of the gate structure 220. One of the source electrode 230 and the drain electrode 240 is used to connect to the antenna 131, and the other of the source electrode 230 and the drain electrode 240 is used to connect to the tuning element 120. The gate structure 220 is used to control the on / off state of the tuning element 120 and the antenna 131.

[0022] It should be noted that, in order to facilitate explanation and help understand the structure of the semiconductor element 200 of this application, the drawings of this application show spatial reference directions such as the first direction F1, the second direction F2 and the third direction F3. The first direction F1 and the second direction F2 are perpendicular to each other and parallel to the surface of the epitaxial substrate 210, and the third direction F3 is perpendicular to the surface of the epitaxial substrate 210.

[0023] In this embodiment, the source electrode 230 can be connected to the tuning element 120, which can be an inductor. The drain electrode 240 can be connected to the antenna 131. The buffer layer 212, the gallium nitride channel layer 213, and the barrier layer 214 can form a gallium nitride heterostructure. The buffer layer 212, the gallium nitride channel layer 213, and the barrier layer 214 can all be formed by epitaxial growth processes, such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), combinations thereof, or other similar methods. The semiconductor element 200 can be a gallium nitride high electron mobility transistor (GaN HEMT). The radio frequency front end can be used to control the gate structure 220, thereby controlling the on / off state of the tuning element 120 and the antenna 131. However, this embodiment is not intended to limit this application.

[0024] By leveraging the material properties (i.e., wide bandgap) of the gallium nitride channel layer 213, the breakdown capability of the semiconductor element 200 is increased. This allows the semiconductor element 200 to achieve the required high breakdown voltage when applied to the antenna tuner 121, resulting in high power handling performance. It eliminates the need for capacitors to compensate for nonlinear changes caused by voltage variations. Consequently, the antenna tuner 121 using the semiconductor element 200 has a smaller form factor and better linear control, and is suitable for high-output-power operating systems.

[0025] It should be noted that the switching circuit 1211 of the antenna tuner 121 can also use M semiconductor elements 200 connected in series, and M is a positive integer greater than or equal to 2.

[0026] In one embodiment, when the switching circuit 1211 of the antenna tuner 121 comprises M semiconductor elements 200 connected in series, the drain electrode 240 of the first semiconductor element 200 among the plurality of semiconductor elements 200 connected in series is connectable to the tuning element 120, and the source electrode 230 of the M-th semiconductor element 200 among the plurality of semiconductor elements 200 connected in series is connectable to the antenna 131. When M is a positive integer greater than or equal to 3, the drain electrode 240 of the K-th semiconductor element 200 (1<K<M) is connectable to the source electrode 230 of the semiconductor element 200 on one adjacent side, and the source electrode 230 of the K-th semiconductor element 200 is connectable to the drain electrode 240 of the semiconductor element 200 on the other adjacent side. In other words, the drain electrode 240 of each semiconductor element 200 among the plurality of semiconductor elements 200 connected in series can directly or indirectly connect to the tuning element 120, and the source electrode 230 of each semiconductor element 200 among the plurality of semiconductor elements 200 connected in series can directly or indirectly connect to the antenna 131.

[0027] In another embodiment, when the switching circuit 1211 of the antenna tuner 121 comprises M semiconductor elements 200 connected in series, the source electrode 230 of the first semiconductor element 200 among the plurality of semiconductor elements 200 connected in series is connectable to the tuning element 120, and the drain electrode 240 of the M-th semiconductor element 200 among the plurality of semiconductor elements 200 connected in series is connectable to the antenna 131. When M is a positive integer greater than or equal to 3, the source electrode 230 of the K-th semiconductor element 200 (1<K<M) is connectable to the drain electrode 240 of the semiconductor element 200 on one adjacent side, and the drain electrode 240 of the K-th semiconductor element 200 is connectable to the source electrode 230 of the semiconductor element 200 on the other adjacent side. In other words, the source electrode 230 of each semiconductor element 200 among the plurality of semiconductor elements 200 connected in series can directly or indirectly connect to the tuning element 120, and the drain electrode 240 of each semiconductor element 200 among the plurality of semiconductor elements 200 connected in series can directly or indirectly connect to the antenna 131.

[0028] In one embodiment, the semiconductor substrate 211 may be, but is not limited to, a substrate with a resistivity greater than 500 ohm-cm. Since the gallium nitride channel layer 213 is formed on the high-resistivity semiconductor substrate 211, isolation can be improved, thereby avoiding radio frequency signal loss. In one example, the semiconductor substrate 211 may be made of Si (111) and may be a silicon substrate grown using a floating zone growth method (i.e., floating zone silicon grown by vertical zone melting / refining of high-purity polycrystalline rods). In another example, the semiconductor substrate 211 may be made of silicon carbide.

[0029] In one embodiment, the buffer layer 212 may include carbon-doped gallium nitride (C-GaN), iron-doped gallium nitride (Fe-GaN), a multilayer stack of carbon-doped gallium nitride and iron-doped gallium nitride, or an aluminum gallium nitride back barrier layer. The thickness of the buffer layer 212 may be, but is not limited to, 500 nanometers to 1500 nanometers. The buffer layer 212 can be used as a stress buffer layer to release stress formed in the semiconductor layer (e.g., gallium nitride channel layer 213) above the semiconductor substrate 211 and reduce radio frequency signal leakage through the semiconductor substrate 211. When the buffer layer 212 includes an aluminum gallium nitride (GaN) back barrier layer, the GaN back barrier layer can prevent current collapse due to surface polarization. Because the GaN back barrier layer is disposed on the lower surface of the GaN channel layer 213 and the barrier layer 214 is disposed on the upper surface of the GaN channel layer 213, and the GaN channel layer 213 is polarized, potential wells are generated near the GaN back barrier layer and the barrier layer 214, thus providing conductive channels and improving the stability and reliability of the semiconductor device 200. When the buffer layer 212 includes carbon-doped gallium nitride and / or iron-doped gallium nitride, the presence of p-type dopant helps to improve the breakdown voltage of the semiconductor device 200. When the buffer layer 212 includes multiple stacked layers of carbon-doped gallium nitride and iron-doped gallium nitride, the resistance is increased, thereby preventing leakage current.

[0030] In one embodiment, the thickness of the gallium nitride channel layer 213 may be, but is not limited to, 50 nanometers to 1000 nanometers. Since the overall polarization charge between the barrier layer 214 and the gallium nitride channel layer 213 is positive, a potential dip will be formed at the interface. Free carriers will accumulate at the potential dip due to the influence of the polarization field distribution. Therefore, a two-dimensional electron gas 90 is generated in the gallium nitride channel layer 213 near the barrier layer 214.

[0031] In one embodiment, the barrier layer 214 may be made of, but is not limited to, aluminum gallium nitride (AlxGaN), and the percentage of aluminum in the aluminum gallium nitride may be, but is not limited to, 15% to 35%. In one embodiment, the thickness of the barrier layer 214 may be, but is not limited to, 5 nanometers to 40 nanometers. The barrier layer 214 is used to increase the polarization effect to induce a two-dimensional electron gas 90 in the gallium nitride channel layer 213. When the percentage of aluminum in the aluminum gallium nitride is higher or the thickness of the barrier layer 214 is greater, the barrier layer 214 has a greater polarization effect, but it will generate greater stress. Therefore, considering the balance between stress generation and polarization effect, when the material of the barrier layer 214 is aluminum gallium nitride (AlxGaN), the percentage of aluminum in the aluminum gallium nitride can be controlled to be 15% to 35%, and the thickness of the barrier layer 214 can be controlled to be 5 nanometers to 40 nanometers. In addition, when the buffer layer 212 includes an aluminum gallium nitride back barrier layer and the material of the barrier layer is aluminum gallium nitride, epitaxial consistency and electrical uniformity can be ensured.

[0032] In one embodiment, the epitaxial substrate 210 may further include a spacer layer 215 disposed between the barrier layer 214 and the gallium nitride channel layer 213 (as shown in Figure 3, which is a schematic diagram of a second embodiment of the antenna tuner connected to the antenna in Figure 1). The spacer layer 215 may be made of, but is not limited to, aluminum nitride; its thickness may be, but is not limited to, less than 5 nanometers; and it is used to generate quantum confinement to improve the mobility and density of the two-dimensional electron gas 90. Additionally, in Figure 3, the source electrode 230 may be connected to the antenna 131, and the drain electrode 240 may be connected to the tuning element 120, which may be a capacitor.

[0033] In one embodiment, the epitaxial substrate 210 may further include a capping layer 216 disposed on the barrier layer 214 (as shown in Figure 4, which is a schematic diagram of the third embodiment of the antenna tuner connected to the antenna in Figure 1). The material of the capping layer 216 may be, but is not limited to, gallium nitride; the thickness of the capping layer 216 may be, but is not limited to, less than 5 nanometers; the capping layer 216 is used to prevent aluminum oxidation in the barrier layer 214. Additionally, in Figure 4, the source electrode 230 may be connected to the antenna 131, and the drain electrode 240 may be connected to two parallel tuning elements 120, which may be a capacitor and an inductor.

[0034] In one embodiment, the epitaxial substrate 210 may further include a spacer layer 215 and a capping layer 216. The spacer layer 215 is disposed between the barrier layer 214 and the gallium nitride channel layer 213, and the capping layer 216 is disposed on the barrier layer 214 (as shown in Figure 5, which is a schematic diagram of the fourth embodiment of the antenna tuner connected to the antenna in Figure 1). Additionally, in Figure 5, the source electrode 230 may be connected to two parallel tuning elements 120, which may be two capacitors, and the drain electrode 240 may be connected to the antenna 131.

[0035] In one embodiment, when the epitaxial substrate 210 includes a semiconductor substrate 211, a buffer layer 212, a gallium nitride channel layer 213 and a barrier layer 214 stacked in sequence, the gate structure 220, the source electrode 230 and the drain electrode 240 are in direct contact with the barrier layer 214 (as shown in FIG2).

[0036] In another embodiment, when the epitaxial substrate 210 includes a semiconductor substrate 211, a buffer layer 212, a gallium nitride channel layer 213, and a barrier layer 214 stacked sequentially, the gate structure 220, the source electrode 230, and the drain electrode 240 can extend into the epitaxial substrate 210 in addition to directly contacting the barrier layer 214. In other words, a gate recess 221, a source recess 231, and a drain recess 241 can be formed in the epitaxial substrate 210 first, and then the gate structure 220, the source electrode 230, and the drain electrode 240 can be formed in the gate recess 221, the source recess 231, and the drain recess 241. The gate structure 220 extends a first distance G (the depth of the gate groove 221) into the epitaxial substrate 210 (i.e., in the opposite direction of the third direction F3), and the first distance G can be less than or equal to 50 nanometers; the source electrode 230 and the drain electrode 240 extend a second distance D (the depths of the source groove 231 and the drain groove 241, respectively) into the epitaxial substrate 210, and the second distance D can be less than or equal to 50 nanometers (as shown in Figure 3). The source electrode 230 and the drain electrode 240 can selectively contact the two-dimensional electron gas 90 according to the second distance D; when the source electrode 230 and the drain electrode 240 directly contact the source electrode 230 and the drain electrode 240, the output current of the semiconductor device 200 can be increased. Since the source electrode 230 and the drain electrode 240 extend into the epitaxial substrate 210 respectively, the source electrode 230 and the drain electrode 240 and the epitaxial substrate 210 can have a large contact area; the large contact area can result in the semiconductor device 200 having a lower contact resistance, thereby having better performance during the operation of the semiconductor device 200.

[0037] In one embodiment, the source electrode 230 and the drain electrode 240 may form ohmic contacts with the epitaxial substrate 210, respectively. The source electrode 230 and the drain electrode 240 may each comprise a conductive material or a regrown N-type gallium nitride (GaN). The conductive material may include titanium (Ti), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), chromium (Cr), copper (Cu), iridium (Ir), titanium nitride (TiN), and tungsten (W), their compounds, composite layers, or alloys thereof, but are not limited thereto. The regrown N-type gallium nitride may be, but is not limited to, silicon-gallium nitride (Si-GaN). Alternatively, the source electrode 230 and the drain electrode 240 may also be stacked layers that form ohmic contacts with the epitaxial substrate 210, such as Ti / Al, Ti / Al / Ti / TiN, Ti / Al / Ti / Au, or Ti / Al / Ni / Au, but are not limited thereto.

[0038] In one embodiment, the distance d1 between the gate structure 220 and the source electrode 230, and the distance d2 between the gate structure 220 and the drain electrode 240, can be greater than or equal to 0.5 micrometers and less than or equal to 4 micrometers. Furthermore, the distance d1 between the gate structure 220 and the source electrode 230, and the distance d2 between the gate structure 220 and the drain electrode 240, can be the same or different.

[0039] In one embodiment, the number of gate structures 220 is N, where N is a positive integer less than or equal to 6. Source electrodes 230 and drain electrodes 240 are respectively disposed on opposite sides of the N gate structures 220 (as shown in Figures 2 to 5). The radio frequency front-end can simultaneously control the N gate structures 220 through a single control terminal 60 (as shown in Figure 5); the arrangement of multiple gate structures 220 can increase the breakdown voltage of the semiconductor device 200 (e.g., 50 volts to 400 volts).

[0040] In one embodiment, the distance d3 between any two adjacent gate structures 220 can be greater than or equal to 0.5 micrometers and less than or equal to 4 micrometers.

[0041] In one embodiment, the gate structure 220 may be a metal-insulator-semiconductor (MIS) structure (as shown in Figures 2 and 3). The MIS structure includes a dielectric layer 222 in contact with the epitaxial substrate 210 and a gate electrode 224 disposed on the dielectric layer 222. The gate electrode 224 may include titanium, aluminum, nickel, gold, platinum, chromium, copper, iridium, titanium nitride, its compounds, its composite layers, or alloys thereof. The dielectric layer 222 may include silicon nitride (SiNx), silicon oxide (SiOx), hafnium oxide (HfOx), or aluminum oxide (AlOx). However, this embodiment is not intended to limit the scope of this application. By designing the gate structure 220 as a metal-insulator-semiconductor structure, the gate leakage current of the semiconductor device 200 can be reduced, and the breakdown capability of the semiconductor device 200 can be improved. The dielectric layer 222 can be formed through an atomic layer deposition (ALD) process. ALD technology is suitable for depositing dielectric layer 222 because it has good uniformity, thickness control, low deposition temperature (heat treatment budget), and no plasma deposition (which can avoid plasma-induced damage to the underlying epitaxial layer).

[0042] In Figure 2, since the epitaxial substrate 210 includes a semiconductor substrate 211, a buffer layer 212, a gallium nitride channel layer 213 and a barrier layer 214 stacked in sequence, and the gate structure 220 directly contacts the barrier layer 214, the dielectric layer 222 of the gate structure 220 directly contacts the barrier layer 214, and the gate electrode 224 of the gate structure 220 is disposed on the dielectric layer 222.

[0043] In Figure 3, since the gate structure 220 extends into the epitaxial substrate 210, the dielectric layer 222 of the gate structure 220, in addition to the contact barrier layer 214, also selectively contacts the gallium nitride channel layer 213 and the spacer layer 215 according to the first distance G of the gate structure 220 extending into the epitaxial substrate 210. The gate electrode 224 of the gate structure 220 is disposed on the dielectric layer 222.

[0044] In another embodiment, the gate structure 220 may include a gallium nitride layer 226 in contact with the epitaxial substrate 210 and a gate electrode 228 disposed on the gallium nitride layer 226 (as shown in FIG. 4). The gate electrode 228 may form a Schottky contact with the gallium nitride layer 226. The gate electrode 228 may include titanium, aluminum, nickel, gold, platinum, chromium, copper, iridium, titanium nitride, or compounds thereof. The contact between the gate electrode 228 and the gallium nitride layer 226 will generate a Schottky barrier at their contact surface (i.e., the so-called heterojunction), which can improve the breakdown capability and noise immunity of the semiconductor device 200.

[0045] In Figure 4, since the epitaxial substrate 210 includes a semiconductor substrate 211, a buffer layer 212, a gallium nitride channel layer 213, a barrier layer 214 and a capping layer 216 stacked in sequence, and the gate structure 220 directly contacts the capping layer 216, the gallium nitride layer 226 of the gate structure 220 directly contacts the capping layer 216, and the gate electrode 228 of the gate structure 220 is disposed on the gallium nitride layer 226.

[0046] In another embodiment, the gate structure 220 is a P-type gallium nitride gate (as shown in Figure 5). The P-type gallium nitride gate includes carbon-doped gallium nitride or magnesium-doped gallium nitride. Furthermore, the P-type gallium nitride gate is used to deplete the charge carriers generated in the underlying gallium nitride channel layer 213, causing the semiconductor device 200 to transition to a normally-off state. Moreover, the P-type gallium nitride gate can be formed using epitaxial growth processes, such as metal-organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor phase epitaxy, and the pattern of the P-type gallium nitride gate can be defined using photolithography.

[0047] In another embodiment, the gate structure 220 is a fluorine-doped gallium nitride gate.

[0048] In summary, by leveraging the material properties (i.e., wide bandgap) of the gallium nitride channel layer to increase the breakdown capability of semiconductor devices, when these devices are used in antenna tuners, the switching circuit of the antenna tuner only requires a single semiconductor device or a small number of semiconductor devices connected in series (less than 25) to achieve the required high breakdown voltage. Furthermore, because of the small number of semiconductor devices connected in series, capacitors are not needed to compensate for nonlinear changes caused by voltage variations. Therefore, antenna tuners using the semiconductor devices of this application have a smaller form factor and better linear control, and are suitable for high-output-power operating systems. In addition, the gallium nitride channel layer is formed on a semiconductor substrate with high resistivity (i.e., resistivity greater than 500 ohm-cm), which improves isolation and avoids RF signal loss. Moreover, the multiple gate structures further enhance the breakdown voltage of the semiconductor device. Furthermore, the design of the gate structure as a metal-insulator-semiconductor structure reduces gate leakage current and improves the breakdown capability of the semiconductor device.

[0049] While the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. Rather, this invention encompasses modifications and similar arrangements that will be obvious to those skilled in the art. Therefore, the scope of the patent application should be interpreted in the broadest possible sense to include all obvious modifications and similar arrangements.

[0050] 11: First signal receiving end 12: Second signal receiver 21: First signal output terminal 22: Second signal output terminal 31: First power amplifier 32: Second power amplifier 41: First Single-Pole Double-Throw Switch 42: Second Single-Pole Double-Throw Switch 51: First Filter 52: Second Filter 60: Control Terminal 61: First low-noise amplifier 62: Second low-noise amplifier 71: First Double-Pole Double-Throw Switch 72: Second Double-Pole Double-Throw Switch 81: First Coupler 82: Second Coupler 90: Two-dimensional electron gas 100: Radio Frequency Circuit 110: Radio Frequency Front End 120: Tuning element 121, 122: Antenna tuner 131, 132: Antenna 200: Semiconductor components 210: Epitaxial substrate 211: Semiconductor substrate 212: Buffer layer 213: Gallium nitride channel layer 214: Barrier Layer 215: Spacing layer 216: Cap layer 220: Gate structure 221: Gate groove 222: Dielectric layer 224, 228: Gate electrodes 226: Gallium nitride layer 230: Source electrode 231: Source groove 240: Drain electrode 241: Drain groove 1211: Switching circuit G: First distance D: Second distance d1, d2, d3: Distance F1: First Direction F2: Second direction F3: Third-party

Claims

1. A semiconductor element used in an antenna tuner, the semiconductor element comprising: An epitaxial substrate includes a semiconductor substrate, a buffer layer formed on the semiconductor substrate, a gallium nitride channel layer formed on the buffer layer, and a barrier layer formed on the gallium nitride channel layer, wherein a two-dimensional electron gas (2DEG) is generated in the gallium nitride channel layer near the barrier layer; a gate structure is disposed on the epitaxial substrate; and a source electrode and a drain electrode are respectively disposed on opposite sides of the gate structure and respectively disposed on the epitaxial substrate, wherein one of the source electrode and the drain electrode is used to connect an antenna, and the other of the source electrode and the drain electrode is used to connect a tuning element, and the gate structure is used to control the on / off state of the tuning element and the antenna.

2. The semiconductor element as claimed in claim 1, wherein, The gate structure is a metal-insulator-semiconductor (MIS) structure, which includes a dielectric layer in contact with the epitaxial substrate and a gate electrode disposed on the dielectric layer.

3. The semiconductor element as claimed in claim 2, wherein, The gate electrode comprises titanium, aluminum, nickel, gold, platinum, chromium, copper, iridium, titanium nitride, its compounds, its composite layers or alloys thereof, and the dielectric layer is selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx), hafnium oxide (HfOx) and aluminum oxide (AlOx) and combinations thereof.

4. The semiconductor element as claimed in claim 1, wherein, The gate structure includes a gallium nitride layer in contact with the epitaxial substrate and a gate electrode disposed on the gallium nitride layer, wherein a Schottky contact is formed between the gate electrode and the gallium nitride layer.

5. The semiconductor element as claimed in claim 4, wherein, The gate electrode includes titanium, aluminum, nickel, gold, platinum, chromium, copper, iridium, titanium nitride, or compounds thereof.

6. The semiconductor element as claimed in claim 1, wherein, The gate structure is a P-type gallium nitride gate.

7. The semiconductor element as claimed in claim 6, wherein, The P-type gallium nitride gate includes either carbon-doped gallium nitride or magnesium-doped gallium nitride.

8. The semiconductor element as claimed in claim 1, wherein, The gate structure is a fluorine-doped gallium nitride gate.

9. The semiconductor element as claimed in claim 1, wherein, The gate structure extends into the epitaxial substrate by a first distance, the first distance being less than or equal to 50 nanometers.

10. The semiconductor element as claimed in claim 1, wherein, The number of gate structures is N, where N is a positive integer less than or equal to 6, and the source electrode and the drain electrode are respectively disposed on opposite sides of the N gate structures.

11. The semiconductor element as claimed in claim 10, wherein, The distance between any two adjacent gate structures is greater than or equal to 0.5 micrometers and less than or equal to 4 micrometers.

12. The semiconductor element as claimed in claim 1, wherein, The source electrode and the drain electrode respectively form ohmic contacts with the epitaxial substrate.

13. The semiconductor element as claimed in claim 1, wherein, The source electrode and the drain electrode extend into the epitaxial substrate by a second distance, the second distance being less than or equal to 50 nanometers.

14. The semiconductor element as claimed in claim 1, wherein, The epitaxial substrate also includes a spacer layer disposed between the barrier layer and the gallium nitride channel layer.

15. The semiconductor element as claimed in claim 1, wherein, The epitaxial substrate also includes a capping layer disposed on the barrier layer.

16. The semiconductor element as claimed in claim 1, wherein, The semiconductor substrate has a resistivity greater than 500 ohm-cm.

17. The semiconductor element as claimed in claim 16, wherein, The semiconductor substrate is made of Si (111) or silicon carbide.

18. The semiconductor element as claimed in claim 1, wherein, The buffer layer includes carbon-doped gallium nitride (C-GaN), iron-doped gallium nitride (Fe-GaN), multiple stacked layers of carbon-doped gallium nitride and iron-doped gallium nitride, or aluminum gallium nitride back barrier layer.

19. The semiconductor element as claimed in claim 1, wherein, The distance between the gate structure and the source electrode, and the distance between the gate structure and the drain electrode, are greater than or equal to 0.5 micrometers and less than or equal to 4 micrometers.

20. The semiconductor element as claimed in claim 1, wherein, The barrier layer is made of aluminum gallium nitride (AlxGaN), with aluminum comprising 15% to 35% of the material.

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