Semiconductor device manufacturing method

Abstract

A method, includes: providing a semiconductor structure including a plurality of vertically spaced channel structures, a plurality of vertically spaced interlayer oxide regions positioned between the plurality of vertically spaced channel structures, a sacrificial gate structure disposed above the plurality of vertically spaced channel structures, a source feature, and a drain feature; removing the sacrificial gate structure via dry etching operations; removing interlayer oxide above a top channel structure of the plurality of vertically spaced channel structures via dry etching operations; and removing remaining portions of the plurality of vertically spaced interlayer oxide regions via chemical etching operations.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device. Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on them.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device includes: providing a semiconductor structure including a plurality of vertically spaced channel structures and a plurality of vertically spaced sacrificial structures located between the vertically spaced channel structures; patterning a sacrificial gate structure over the vertically spaced channel structures, wherein the patterning provides a smoothness to one sidewall of the sacrificial gate structure; and including: performing a main etching process; performing a breakthrough etching process; performing a plurality of smoothing etching processes; and performing an over-etching process; forming a plurality of gate spacers, wherein the smoothness of the sidewall of the sacrificial gate structure is transferred to the gate spacers. A sidewall; forming a plurality of source features and a plurality of drain features; removing the sacrificial gate structure; and forming a metal gate structure, wherein a smoothness of the sidewall of the gate spacer is transferred to a sidewall of the metal gate structure, wherein a bend ratio in the metal gate structure is less than 10%, and wherein a bend is defined as a location on a vertically extending sidewall of the metal gate structure, wherein a particular sidewall location differs from an average value of a first sidewall location at a predetermined distance above a particular sidewall location and a first sidewall location at a predetermined distance below a particular sidewall location in a horizontal position by at least 0.5 nm.

[0005] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device includes: providing a semiconductor structure including a plurality of vertically spaced channel structures, a plurality of vertically spaced interlayer oxide regions located between the vertically spaced channel structures, a sacrificial gate structure disposed above the vertically spaced channel structures, a source feature, and a drain feature; removing the sacrificial gate structure by a dry etching operation; removing an interlayer oxide layer above a top channel structure of the vertically spaced channel structures by a dry etching operation; and removing a remaining portion of the vertically spaced interlayer oxide regions by a chemical etching operation.

[0006] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device includes: providing a semiconductor structure including a plurality of vertically spaced channel structures, a plurality of vertically spaced interlayer oxide regions located between the vertically spaced channel structures, a sacrificial gate structure disposed above the vertically spaced channel structures, a source feature, and a drain feature; removing the sacrificial gate structure by a dry etching operation; removing the interlayer oxide above a top channel structure of the vertically spaced channel structures by a dry etching operation; removing a remaining portion of the vertically spaced interlayer oxide regions by a chemical etching operation; and forming a metal gate structure around the vertically spaced channel structures, the metal gate structure including a first metal gate region disposed above a top vertically spaced channel structure of the vertically spaced channel structures, the first metal gate region including: a vertically extending sidewall; a horizontally extending contact region located at the bottom of the first metal gate region, which contacts a top vertically spaced channel structure; and a corner angle of less than 100 degrees measured at a corner between the sidewall and the contact region. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various parts are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various parts may be arbitrarily increased or decreased. Figure 1 is a flowchart illustrating a semiconductor manufacturing paradigm method including the fabrication of multi-gate elements according to some embodiments. Figures 2 to 3, 4A to 4C, 5, 6A to 6B, and 7 to 18 are schematic diagrams illustrating exemplary semiconductor elements or structures at various manufacturing stages according to some embodiments. Figures 19 to 22 are schematic diagrams of exemplary semiconductor structures that have undergone processes of removing the sacrificial oxide layer and releasing the nanosheet during the fabrication of a GAA device according to some embodiments. Figures 23 to 26 are schematic diagrams of various features of example semiconductor structures after removing the sacrificial oxide layer between channel layers according to some embodiments. Figures 27 and 28 are schematic diagrams of various features of example semiconductor structures after subsequent metal gate fabrication operations according to some embodiments. Figures 29 and 30 are schematic diagrams illustrating various features of an example short-channel semiconductor structure after removing the sacrificial oxide layer between the channel layers according to some embodiments. Figures 31 and 32 are schematic diagrams illustrating various features of an example long-channel semiconductor structure after removing the sacrificial oxide layer between the channel layers according to some embodiments. Figures 33 and 34 are schematic diagrams of another exemplary semiconductor structure following subsequent metal gate fabrication operations according to some embodiments. Figure 35 is a flowchart of a semiconductor manufacturing paradigm method including the fabrication of multi-gate elements according to some embodiments. Figures 36 to 38 show schematic diagrams of semiconductor devices at various manufacturing stages according to some embodiments. Figure 39 shows a process flow diagram of an exemplary etching sequence according to some embodiments. Figures 40 and 41 are schematic cross-sectional views of semiconductor structures according to some embodiments, depicting multiple dummy gate structures disposed above an epitaxial stack. Figure 42 is a schematic cross-sectional view of an example bending feature of a dummy gate on a semiconductor structure according to some embodiments. Figure 43 is a diagram of an example formula used to determine the bending ratio according to some embodiments. Figure 44 is a diagram of an example calculation performed using the formula in Figure 43 according to some embodiments. Figure 45 is a schematic cross-sectional view of an exemplary metal gate structure formed after a bias reduction process during a dummy gate patterning operation, according to some embodiments. Figures 46 and 47 show schematic cross-sectional views of exemplary metal gate structures formed after a bias reduction process during dummy gate patterning operations, according to some embodiments. Figures 48 and 49 illustrate another example semiconductor structure following a metal gate fabrication operation, according to some embodiments, when a bias reduction process is used during a dummy gate patterning operation. Implementation

[0008] The following disclosure provides many different embodiments or examples for implementing the various features of this disclosure. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting.

[0009] For the sake of brevity, this document will not describe in detail the conventional techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functions not described in detail herein. Specifically, various processes for manufacturing semiconductor devices are well known; therefore, for the sake of brevity, many conventional processes will only be briefly mentioned or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon fully reading this disclosure that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products. Furthermore, it is noteworthy that semiconductor device structures include varying numbers of components, and a single component shown in the illustrations may represent multiple components.

[0010] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, parts, and / or segments, these elements, components, areas, layers, parts, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, part, or segment from another. Therefore, the first element, component, area, layer, part, or segment discussed below may be referred to as a second element, component, area, layer, part, or segment without departing from the teachings of this disclosure.

[0011] Furthermore, for ease of description, this document may use spatial relative terms such as "over," "overlying," "above," "upper," "top," "under," "underlying," "below," "lower," and "bottom" to describe the relationship between one element or feature and another, as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. When spatial relative terms (such as those listed above) are used to describe a first element relative to a second element, the first element may be directly on top of the other element, or there may be intermediate elements or layers.

[0012] Furthermore, reference numerals and / or letters may be repeated in various examples within this disclosure. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0013] It should be noted that the terms "an embodiment," "embodiment," "exemplary embodiment," "exemplary," and "example" used in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, those skilled in the art will understand that the feature, structure, or characteristic can be influenced by other embodiments, whether or not explicitly described.

[0014] In some embodiments herein, a "material layer" is a layer comprising at least 50% by weight of the identified material, such as at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of the identified material; or a designated material, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight. For example, in some embodiments, an aluminum layer and an aluminum layer are each at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of aluminum.

[0015] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation, so that those skilled in the art may interpret the terminology or terminology of this specification based on the teachings herein.

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the disclosed subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Throughout this specification, unless otherwise stated, the same reference numerals in different figures denote the same or similar parts formed using the same or similar methods and materials.

[0017] Although the accompanying drawings illustrate various embodiments of the semiconductor device, additional features may be added to the semiconductor device shown in the drawings, and some features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0018] Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. Additional features may be added to the semiconductor device structure. For different embodiments, some of the features described below may be replaced or eliminated. Although some embodiments discuss operations performed in a specific order, these operations may also be performed in another logical order.

[0019] As used in this article, a "layer" is a region, such as a region with arbitrary boundaries, and does not necessarily have a uniform thickness. For example, a layer can be a region that includes at least some variations in thickness.

[0020] This disclosure generally relates to semiconductor devices and their fabrication, and in some cases to multi-gate devices. Multi-gate devices include transistors with gate structures formed on at least two sides of a channel region. These multi-gate devices can include n-type metal-oxide-semiconductor (MOS) devices or p-type MOS multi-gate devices. Specific examples may be presented herein and referred to as a multi-gate transistor called a full-gate field-effect transistor (GAAFET). A GAAFET includes any device having a gate structure or a portion thereof formed on four sides of a channel region (e.g., around a portion of the channel region). Devices presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure are described herein. Other examples of semiconductor devices that may benefit from aspects of this disclosure will be recognized by those skilled in the art.

[0021] During the fabrication of various multi-gate devices (e.g., GAAFETs, nanosheet transistors (NSFETs), forked transistors, complementary transistors (CFETs), vertical field-effect transistors (VFETs), etc.), the contact area at the bottom of the metal gate (MG) may decrease, leading to a decline in drain-induced barrier lowering (DIBL) performance. The structure and techniques disclosed in this paper can increase the contact area from the metal gate (MG) to the Si channel, thereby reducing DIBL degradation.

[0022] During the fabrication of various multi-gate devices, metal gate (MG) sidewall bending can occur, which reduces manufacturing yield and device performance. The structures and techniques disclosed herein can reduce MG sidewall bending.

[0023] Figure 1 is a flowchart illustrating an exemplary method 100 for semiconductor manufacturing, including the fabrication of a multi-gate element, according to various aspects of this disclosure. The term "multi-gate element" as used herein is used to describe a device (e.g., a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel member of the device. In some examples, a multi-gate element may be referred to as a GAA element having gate material disposed on four sides of at least one channel member of the device. The channel member may be referred to as a "nanostructure" or "nanosheet," which is used herein to denote any portion of material having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term "nanostructure" or "nanosheet" as used herein refers to elongated portions of material with circular and substantially circular cross-sections, as well as beam or strip-shaped portions of material, such as those comprising cylindrical or substantially rectangular cross-sections.

[0024] Figure 1 is described in conjunction with Figures 2-3, 4A-4C, 5, 6A-6B, and 7-18, which illustrate a semiconductor structure 200 or a structure at various manufacturing stages according to some embodiments. In some figures, reference numerals for components or features shown may be omitted to avoid obscuring other components or features; this is for ease of depiction. Method 100 is merely an example and is not intended to limit the scope of this disclosure beyond what is expressly stated in the claims. Additional steps may be provided before, during, and after method 100, and some steps described may be moved, replaced, or eliminated for additional embodiments of method 100. Additional features may be added to the semiconductor structure 200 depicted in the figures, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0025] As with other method embodiments and exemplary devices discussed herein, it should be understood that portions of a semiconductor device can be manufactured using semiconductor technology processes; therefore, only some processes are briefly described herein. Furthermore, exemplary semiconductor devices may include a variety of other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, dials, fuses, and / or other logic devices, but simplifications have been made for better understanding of the concepts disclosed herein. In some embodiments, exemplary elements include multiple interconnectable semiconductor elements (e.g., transistors), including PFETs, NFETs, etc. Moreover, it is worth noting that the process steps of method 100, including any descriptions given with reference to the accompanying drawings, are merely exemplary, as are the remainder of the methods provided in this disclosure and the exemplary drawings, and are not intended to limit the scope beyond what is specifically described in the following claims.

[0026] At block 102, exemplary method 100 includes providing a substrate. Referring to the example of FIG2, in the embodiment of block 102, a substrate 202 is provided to form a semiconductor structure 200. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. In some embodiments, substrate 202 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 202 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. Substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Depending on design requirements, substrate 202 may include various doping configurations. For example, different doping distributions (e.g., n-wells, p-wells) may be formed on substrate 202 in regions designed for different device types (e.g., n-type field-effect transistors (NFETs), p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 has isolation features (e.g., shallow trench isolation (STI) features), and the insertion provides regions for different device types. Furthermore, the substrate 202 may be strained to enhance performance, and may include a silicon-on-insulator (SOI) structure, and / or have other suitable reinforcing features.

[0027] At block 104, exemplary method 100 includes forming an epitaxial stack comprising multiple epitaxial layers over a substrate. Referring to the example of FIG3, in the embodiment of block 104, an epitaxial stack 212 is formed over a substrate 202. The epitaxial stack 212 includes a sacrificial epitaxial layer 214 of a first composition, with a channel epitaxial layer 216 of a second composition interposed therebetween. The first and second compositions may be different. In one embodiment, the sacrificial epitaxial layer 214 is formed of SiGe, while the channel epitaxial layer 216 is formed of silicon (Si). However, other embodiments are also possible, including embodiments providing a first composition and a second composition with different oxidation rates and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 comprises SiGe, while the channel epitaxial layer 216 comprises silicon (Si). However, other embodiments are also possible, including embodiments providing a first composition and a second composition with different oxidation rates and / or etch selectivity. In some embodiments, the sacrificial epitaxial layer 214 comprises SiGe, and the channel epitaxial layer 216 comprises Si, wherein the Si oxidation rate of the channel epitaxial layer 216 is lower than the SiGe oxidation rate of the sacrificial epitaxial layer 214. It is noteworthy that Figure 3 shows three (3) layers each of epitaxial layers 214 and 216, which is for illustrative purposes only and is not intended to limit the scope beyond what is specifically described in the claims. In various embodiments, any number of epitaxial layers may be formed in the epitaxial stack 212; the number of layers depends on the number of channel regions required for structure 200. In some embodiments, the number of channel epitaxial layers 216 is between 1 and 5, for example, 3, 4, or 5.

[0028] In some embodiments, the thickness of the sacrificial epitaxial layer 214 ranges from about 4 nm to about 12 nm. The thickness of the sacrificial epitaxial layer 214 can be substantially uniform. In some embodiments, the thickness of the channel epitaxial layer 216 ranges from about 3 nm to about 6 nm. In some embodiments, the thickness of the stacked channel epitaxial layers 216 is substantially uniform.

[0029] As described in more detail below, the channel epitaxial layer 216 can be used as the channel region for subsequently formed multi-gate devices, and its thickness is selected based on device performance considerations. The sacrificial epitaxial layer 214 can reserve a gap (or clearance) between adjacent channel regions for subsequently formed multi-gate elements, and its thickness is selected based on device performance considerations.

[0030] For example, the epitaxial growth of the epitaxial stack 212 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer (e.g., channel epitaxial layer 216) comprises the same material as the substrate 202, such as silicon (Si). In some embodiments, epitaxial layers 214 and 216 comprise materials different from the substrate 202. As described above, in at least some examples, the sacrificial epitaxial layer 214 comprises an epitaxially grown Si1-xGex layer (e.g., x is approximately 25-55%), while the channel epitaxial layer 216 comprises an epitaxially grown Si layer. Alternatively, in some embodiments, either the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or antimony alloyed semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof). As described above, the materials of the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 can be selected to provide different oxidation and etch selectivity characteristics. In various embodiments, epitaxial layers 214 and 216 are substantially dopant-free (i.e., having an intrinsic dopant concentration of about 0 cm⁻³ to about 1 × 10¹⁷ cm⁻³), for example, without intentional doping during epitaxial growth.

[0031] At block 106, exemplary method 100 includes patterning an epitaxial stack to form a semiconductor fin (also referred to as a fin). Referring to the examples of Figures 4A, 4B, and 4C, in the embodiment of block 106, a plurality of fins 220 extending from a substrate 202 are formed. In various embodiments, each fin 220 includes an upper portion of staggered epitaxial layers 214 and 216 and a bottom portion protruding from the substrate 202.

[0032] Fins 220 can be fabricated using appropriate processes including photolithography and etching. The photolithography process may include forming a photoresist layer over substrate 202 (e.g., over epitaxial stack 212), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a photomask element containing the photoresist. In some embodiments, an electron beam lithography process may be used to pattern the resist to form the photomask element. A masking element can then be used to protect areas of substrate 202 and the epitaxial stack 212 formed thereon, while an etching process forms trenches in the unprotected areas through the masking layer (e.g., a hard mask), leaving multiple extended fins. The trenches can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The trenches may be filled with a dielectric material, forming, for example, shallow trench isolation features between the fins.

[0033] At block 108, exemplary method 100 includes forming one or more sacrificial layers / features over a substrate. Referring to the example of FIG5, in the embodiment of block 108, a sacrificial gate dielectric layer (not shown) is blanket-deposited over interlayer oxide 222, which is formed over fin 220, which is formed over substrate 202. A sacrificial gate electrode layer 228 is then blanket-deposited on the sacrificial gate dielectric layer and over substrate 202. The sacrificial gate electrode layer 228 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 1 nm to about 5 nm. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is planarized. The sacrificial gate dielectric layer and the sacrificial gate electrode layer 228 can be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes.

[0034] At block 110, exemplary method 100 includes patterning one or more sacrificial layers / features to form a dummy gate structure on the channel region of the fin. Referring to the examples of Figures 6A and 6B, in the embodiment of block 110, a sacrificial gate structure 224 is formed over the portion of the fin 220 that will become the channel region. The sacrificial gate structure 224 defines the channel region of the GAA device. The sacrificial gate structure 224 includes a sacrificial gate dielectric layer and a sacrificial gate electrode layer 228. The sacrificial gate structure 224 is formed by forming a masking layer over the sacrificial gate electrode layer. The masking layer may include a pad silicon oxide layer and a silicon nitride masking layer. Subsequently, the masking layer is patterned, and the sacrificial gate dielectric layer and electrode layer are patterned into the sacrificial gate structure 224. By patterning the sacrificial gate structure 224, the fin 220 is exposed on opposite sides of the sacrificial gate structure 224, thereby defining the source / drain (S / D) region. In this disclosure, the source and drain can be used interchangeably, and their structures are essentially the same.

[0035] Subsequently, as discussed in block 130 of reference method 100, the sacrificial gate structure 224 is removed and replaced by the final gate stack in subsequent processing stages of structure 200. Specifically, as described below, the sacrificial gate structure 224 is replaced by a high-k dielectric layer (HK) and a metal gate electrode (MG) in subsequent processing stages.

[0036] At block 112, exemplary method 100 includes forming a gate sidewall spacer on the sidewall of the sacrificial gate structure. Referring to the example of FIG7, in the embodiment of block 112, a gate sidewall spacer 232 is formed on the sidewall of the sacrificial gate structure 224. In various embodiments, the gate sidewall spacer 232 may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), SiCN film, silicon oxycarbonate (SiOC), silicon carbonitride, or combinations thereof. In some embodiments, the gate sidewall spacer 232 includes multiple layers, such as a main spacer wall, a liner layer, etc. For example, the gate sidewall spacer 232 can be formed by depositing a dielectric material layer over the sacrificial gate structure 224 using processes such as CVD, sub-atmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. In some embodiments, an etch-back process (e.g., anisotropic) is performed after depositing the dielectric material layer to expose portions of the fin 220 adjacent to and not covered by the sacrificial gate structure 224 (e.g., S / D regions). The dielectric material layer may remain on the sidewall of the sacrificial gate structure 224 as the gate sidewall spacer 232. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The thickness of the gate sidewall spacer 232 may be from about 5 nm to about 20 nm.

[0037] At block 114, an exemplary method includes recessing fins in the source / drain region. Referring to the example of FIG8, in the embodiment of block 114, fin 220 is recessed in the source / drain region. Stacked epitaxial layers 214 and 216 are etched at the S / D region to form a recess 234. In various embodiments, the recess is performed via a suitable etching process (e.g., dry etching, wet etching, or RIE). Dry etching can be achieved using an etchant comprising a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or combinations thereof.

[0038] At block 116, exemplary method 100 includes removing the sacrificial epitaxial layer that forms a space between the channel epitaxial layers. Referring to the example of FIG9, in the embodiment of block 116, the sacrificial epitaxial layer 214 has been removed and a space 215 has been formed. The sacrificial epitaxial layer 214 can be removed or etched using an etchant that can selectively etch the sacrificial epitaxial layer 214 relative to the channel epitaxial layer 216.

[0039] When the sacrificial epitaxial layer 214 comprises Ge or SiGe and the channel epitaxial layer 216 comprises Si, the sacrificial epitaxial layer 214 can be selectively removed using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminetetraacetic acid (EDP), or potassium hydroxide (KOH) solution. In various embodiments, multiple sacrificial epitaxial layers 214 are selectively removed by a selective removal process, which includes oxidizing the multiple sacrificial epitaxial layers 214 using a suitable oxidant (e.g., ozone). Subsequently, the oxidized sacrificial epitaxial layers 214 are selectively removed by a dry etching process, for example, by applying HCl gas at a temperature of about 500 degrees Celsius to about 700 degrees Celsius, or by applying a gas mixture of CF4, SF6, and CHF3.

[0040] At block 118, exemplary method 100 includes forming a sacrificial oxide layer (e.g., using known deposition techniques such as chemical vapor deposition (CVD), or possibly thermal growth, or oxide layers using some other conventional techniques) in the area vacated by the removed sacrificial epitaxial layer 214. Referring to the example of FIG10, in the embodiment of block 118, a sacrificial oxide layer 217, such as silicon oxide, is formed in the area vacated by the removed sacrificial epitaxial layer 214. In various embodiments, forming the oxide layer includes depositing the sacrificial oxide layer over the semiconductor structure 200 and etching back the sacrificial oxide layer such that the sacrificial oxide layer 217 remains between the channel epitaxial layers 216.

[0041] At block 120, exemplary method 100 includes forming a groove in the sacrificial oxide layer. Referring to the example of FIG11, in the embodiment of block 120, the sacrificial oxide layer 217 has been etched to form an oxide layer groove 235, which is defined at the top and bottom by a channel epitaxial layer 216 and on the sides by a recessed oxide layer 217. The oxide layer 217 can be selectively etched using an etchant such as HF, NH3, or combinations thereof.

[0042] At block 122, exemplary method 100 includes forming an inner spacer layer in an oxide layer trench. Forming the inner spacer layer may include depositing an inner spacer material of a first material type in the oxide layer trench, and trimming the inner spacer layer (e.g., through an etching operation). Referring to the example of FIG12, in the embodiment of block 122, an inner spacer layer 238 is formed in an oxide layer trench 235. The inner spacer layer 238 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonitride, and / or other suitable dielectric materials. In some embodiments, the inner spacer layer 238 is deposited as a conformal layer. The inner spacer layer 238 may be formed by ALD or any other suitable method. In various embodiments, the inner spacer layer 238 is formed of the same material as the gate sidewall spacer layer 232. In various embodiments, the gate sidewall spacer layer 232 and the inner spacer layer 238 are formed of SiOCN.

[0043] At block 124, exemplary method 100 includes forming a source / drain (S / D) feature. Forming the S / D feature may include depositing pure silicon in a recess 234 in the source / drain region. Referring to the example of FIG13, in the embodiment of block 124, an epitaxial S / D feature 240 is formed in the recess 234. In some embodiments, the epitaxial S / D feature 240 includes silicon for NFET and SiGe for PFET. In some embodiments, the epitaxial S / D feature 240 is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). The epitaxial S / D feature 240 is formed to contact the channel epitaxial layer 216 and is separated from the oxide layer 217 by an inner spacer layer 238.

[0044] At block 126, exemplary method 100 includes forming a CESL layer. Referring to the example of FIG14, in the embodiment of block 126, a CESL layer 242 is formed over the S / D feature 240. The CESL layer 242 may include silicon nitride, silicon oxynitride, silicon nitride containing oxygen (O) or carbon (C), and / or other materials; and may be formed by CVD, PVD (physical vapor deposition), ALD, or other suitable methods. In various embodiments, the CESL layer 242 is formed of SiN.

[0045] At block 128, exemplary method 100 includes forming an ILD layer. Referring to the example of FIG15, in the embodiment of block 128, an interlayer dielectric layer (ILD layer 244) is formed over the CESL layer 242. The ILD layer 244 may include tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silica, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 244 may be formed by PECVD, flow CVD (FCVD), or other suitable methods. In some embodiments, forming the ILD layer 244 also includes performing a CMP process to planarize the top surface of the structure 200, thereby exposing the top surface of the sacrificial gate structure 224.

[0046] At block 130, exemplary method 100 includes removing the dummy gate stack to form a gate trench. Referring to the example of FIG16, in the embodiment of block 130, the sacrificial gate structure 224 has been removed to form a gate trench 254. The gate trench 254 exposes the fins 220 in the channel region. The ILD layer 244 and CESL layer 242 protect the epitaxial S / D features 240 during the removal of the sacrificial gate structure 224. The sacrificial gate structure 224 can be removed by plasma dry etching and / or wet etching. When the sacrificial gate electrode layer is polysilicon and the ILD layer 244 is oxide, the sacrificial gate electrode layer can be selectively removed using a wet etchant such as a TMAH solution. The sacrificial gate dielectric layer is then removed using plasma dry etching and / or wet etching.

[0047] At block 132, exemplary method 100 includes removing the sacrificial oxide layer and releasing the nanosheet. Referring to the example of FIG17, in the embodiment of block 132, oxide layer 217 has been removed, thereby releasing the channel member from the channel region of the GAA device. In the illustrated embodiment, the channel member is a channel epitaxial layer 216 in the form of a nanosheet. In various embodiments, the channel epitaxial layer 216 comprises silicon. In various embodiments, multiple sacrificial oxide layers 217 are selectively removed by a selective removal process using an etchant such as HF, NH3, or combinations thereof.

[0048] The removal of the sacrificial oxide layer is capable of (a) preventing notches / rounded corners on the top nanosheet, and (b) preventing residual oxides between the nanosheets of short-channel and long-channel elements, as well as damage to the dielectric film of the short-channel elements. In various embodiments, the removal of the sacrificial oxide layer includes a dry etching process for removing interlayer oxides (e.g., removing interlayer oxide 222) and a wet + chemical etching process for releasing oxides (e.g., removing sacrificial oxide 217), which will be described in more detail below with reference to Figures 19 through 26.

[0049] At block 134, exemplary method 100 includes forming a metal gate structure. Referring to the example of FIG18, in the embodiment of block 134, a gate structure 260 is formed. In various embodiments, the gate structure 260 is the gate of a multi-gate transistor. In various embodiments, the gate structure 260 is a high-k metal gate stack, but other compositions are also possible. In various embodiments, the high-k metal gate stack includes a gate dielectric layer comprising an interface layer and a high-k dielectric layer. The high-k dielectric layer encapsulates each nanosheet 216, and the interface layer is interposed between the high-k dielectric layer and the nanosheet 216. The interface layer may comprise a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON) and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, and / or other suitable methods. High-k dielectric layers may include hafnium oxide (HfO2), hafnium hafnium oxide (HMO), hafnium titanium oxide (HfTiO), hafnium oxide (HfZrO), other combinations of high-k dielectric materials, and their dielectric combinations. High-k materials may also be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3), or combinations thereof. High-k dielectric layers can be formed using any suitable process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), metal-organic CVD (MOCVD), sputtering, electroplating, other suitable processes, and / or combinations thereof. In one embodiment, a highly conformal deposition process (e.g., ALD) is used to form the gate dielectric layer to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer. High-k metal gate structures may include additional material layers.

[0050] At block 136, exemplary method 100 includes performing further fabrication. The semiconductor device may be further processed to form various features and regions known in the art. For example, subsequent processing may include filling openings above the source / drain regions with an ILD1 material to fill the ILD1 layer, and forming one or more intermetallic dielectric (IMD) layers above the ILD1 layer. Each IMD layer may include an etch stop layer (ESL) above the underlying layer and an ILD layer above the ESL. The ESL may be deposited using one or more low-temperature deposition processes (e.g., chemical vapor deposition, physical vapor deposition, or atomic layer deposition). Subsequent processing may also include forming contact openings, contact metals, and various contact / via / line and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features to form a functional circuit that may include one or more multi-gate elements. In this example, the multilayer interconnects may include vertical interconnects (e.g., vias or contacts) and horizontal interconnects (e.g., metal lines). The various interconnect features may employ various conductive materials, including copper, tungsten, and / or siliconides. In one example, damascene and / or dual damascene processes are used to form a copper-associated multilayer interconnect structure. Furthermore, additional process steps may be implemented before, during, and after method 100, and some of the aforementioned process steps may be replaced or eliminated depending on various embodiments of method 100.

[0051] Figures 19 to 22 illustrate embodiments of methods for removing the sacrificial oxide layer and releasing nanosheets during the fabrication of a GAA device. As shown in Figure 19, an example semiconductor structure 300 at an intermediate stage of fabrication is provided. This example semiconductor structure includes a substrate 302, silicon trench isolation features (STI features 304) disposed on the substrate 302 and separating multiple fin structures 306, a channel epitaxial layer 308 and an ILD layer 322 stacked between a sacrificial oxide layer 310, source / drain regions 312, a sacrificial gate structure (dummy gate structure 314), a gate sidewall spacer layer 316, an inner spacer layer 318, and a CESL 320.

[0052] Subsequently, the sacrificial gate structure is removed, as shown in Figure 20. The dummy gate structure 314 can be removed using a dry etching process, leaving the gate trench 324. In this example, after removing the sacrificial gate structure, a portion of the sacrificial oxide layer 310 located above the top channel epitaxial layer 308 remains.

[0053] This method includes removing interlayer oxides through a dry etching operation. In various embodiments, the dry etching operation for removing interlayer oxides includes using an etching gas including one or more of CF4, CHF3, CH2F2, or others; using a selective passivation gas including one or more of N2, O2, CO2, or others; using a dilution gas including one or more of He, Ar, N2, or others; a power between about 10 W and about 1000 W; a pressure between about 10 mTorr and about 800 mTorr; and a gas flow rate between about 20 sccm (standard cubic centimeters per minute) and about 2000 sccm. Figure 21 illustrates an exemplary embodiment of the semiconductor structure 300 after the removal of interlayer oxides through a dry etching operation. The sacrificial oxide layer 310 above the top channel epitaxial layer 308 has been removed.

[0054] This method also includes an oxide release operation to remove the sacrificial oxide layer between the channel layers. The oxide release operation includes wet and chemical etching operations. In various embodiments, the wet etching and chemical etching operations for oxide release include using an etching gas comprising one or more of HF, NH3, or others; using a selective passivation gas comprising one or more of N2, O2, CO2, or others; using a dilution gas comprising one or more of He, Ar, N2, or others; a power between about 10 W and about 2000 W; a pressure between about 10 mTorr and about 500 mTorr; and a gas flow rate between about 20 sccm and about 2000 sccm. Figure 22 illustrates an exemplary embodiment of the semiconductor structure 300 after the sacrificial oxide layer 310 is removed between the channel epitaxial layers 308. At this fabrication stage, the exemplary semiconductor structure 300 includes a square shape (e.g., having an angle of approximately 90 degrees) between the gate sidewall spacers 316 and the top of the top channel epitaxial layer 308.

[0055] Figures 23 through 26 illustrate various features of the exemplary semiconductor structure 300 after the sacrificial oxide layer is removed between the channel layers. Figure 23 shows an enlarged view of the exemplary semiconductor structure 300 of Figure 22, indicating the first region 350 around the top of the gate sidewall spacer 316 and the top of the top channel epitaxial layer 308, and indicating the cleavage line 360 ​​along the y-axis through the channel epitaxial layer 308. Figure 24 depicts an enlarged view of the first region 350, Figure 25 depicts a cross-sectional view of the long channel device along the cleavage line 360, and Figure 26 depicts a cross-sectional view of the short channel device along the cleavage line 360. As used herein, long channel elements include transistor elements with a channel length greater than 60 nm in the y-direction, while short channel elements include transistor elements with a channel length between about 19 nm and about 50 nm in the y-direction.

[0056] Figure 24 shows that the angle 352 at the intersection of the first gate sidewall spacer 316-L and the top 356 of the top channel epitaxial layer 308 has an angle of about 90 degrees, the angle 354 at the intersection of the second gate sidewall spacer 316-R and the top 356 of the top channel epitaxial layer 308 has an angle of about 90 degrees, and the area 358 defined on three sides by the first gate sidewall spacer 316-L, the top 356 and the second gate sidewall spacer 316-R has a rectangular shape.

[0057] Figure 25 shows that the long channel structure 362 formed using the techniques described herein can be fabricated without residual oxides between different layers of the channel epitaxial layer 308-L, which may occur when nanosheets are released using different techniques.

[0058] Similarly, Figure 26 illustrates a short-channel structure 364 formed using the techniques described herein, which can be fabricated without residual oxides between different layers of the channel epitaxial layers 308-S, whereas this could occur when the nanosheet is released using different techniques. Figure 26 also shows that the dielectric film 359 surrounding the channel region is not damaged when the nanosheet is released using different techniques.

[0059] Figures 27 and 28 illustrate various features of the exemplary semiconductor structure 400 (e.g., semiconductor structure 200 or semiconductor structure 300) after subsequent metal gate fabrication operations. The channel structure and metal gate structure are depicted. This channel structure includes a first nanosheet 402, a second nanosheet 404, and a third nanosheet 406. This metal gate structure includes a first metal gate region 408 disposed above the first nanosheet 402, a second metal gate region 410 disposed above the second nanosheet 404, a third metal gate region 412 disposed above the third nanosheet 406, and a fourth metal gate region 414 disposed below the third nanosheet 406. The first metal gate region 408 has a first length D1 in the x-direction along the contact region 416 and a second length D2 at a translational position 417, wherein the sidewalls 418 of the first metal gate region 408 begin to transition towards the contact region 416 (e.g., taper gradually). The semiconductor structure 400 also includes a first depth 420 measured from the transition position to the bottom of the second metal gate region 410, a second depth 422 measured from the transition position to the bottom of the third metal gate region 412, and a third depth 424 measured from the transition position to the bottom of the fourth metal gate region 414.

[0060] In various embodiments, the increment between the first length D1 (e.g., 13 nm) and the second length D2 (e.g., about 14 nm to about 15 nm) is less than 15% of the second length D2. In various embodiments, the increment between the first length D1 (e.g., 13 nm) and the second length D2 (e.g., about 14 nm to about 15 nm) is about 1 nm to about 2 nm or less. The lower increment is due to the larger contact area 416, which reduces DIBL degradation, increases current, can improve manufacturing yield, and can improve device performance.

[0061] The bend angle θb, measured at the corner between sidewall 418 and contact area 416, is close to 90 degrees. In various embodiments, angle θb is between approximately 95 degrees and approximately 100 degrees. An angle θb between approximately 95 degrees and approximately 100 degrees, or closer to 90 degrees, can reduce DIBL degradation, increase current, improve manufacturing yield, and improve device performance. In various embodiments, angle θb can be measured by the tangent line intersecting the sidewall 418 of the first metal gate region 408 at the height of the second length D2 and the edge of the contact area 416 intersecting the sidewall 418.

[0062] In various embodiments, the first depth 420 is less than 15 nm, the second depth 422 is less than 30 nm, and the third depth 424 is less than 45 nm. In various embodiments, the first depth 420 is about 13 nm to about 14 nm, the second depth 422 is about 28 nm to about 29 nm, and the third depth 424 is about 43 nm to about 44 nm. A first depth of less than 15 nm can indicate that no shape rounding has occurred and the contact area has sufficient length to reduce DIBL degradation, increase current, improve manufacturing yield, and improve device performance. A first depth 420, second depth 422, and third depth 424 above these ranges may indicate that shape rounding has occurred near the intersection between the first metal gate region 408 and the top of the first nanosheet 402, resulting in decreased DIBL performance, reduced current, reduced manufacturing yield, and decreased device performance.

[0063] Figures 29 and 30 illustrate various features of an example short-channel semiconductor structure 450 (e.g., semiconductor structure 200 or semiconductor structure 300) after the sacrificial oxide layer is removed between the channel layers. The figures show the channel structure, STI 452, and a dielectric hard mask (e.g., a nitride Si hard mask 454) disposed near the sidewalls of the bottom structure of the plurality of vertically spaced channel structures. This channel structure includes a first nanosheet 456, a second nanosheet 458, a third nanosheet 460, and a bottom channel region 462. The semiconductor structure 450 also includes a first depth 464 measured from the bottom of the first nanosheet 456 to the top of the nitride Si hard mask 454, a second depth 466 measured from the bottom of the second nanosheet 458 to the top of the nitride Si hard mask 454, a third depth 468 measured from the bottom of the third nanosheet 460 to the top of the nitride Si hard mask 454, and a bottom angle θS measured between the sidewall of the bottom channel region 462 and the top of the nitride Si hard mask 454.

[0064] In various embodiments, the bottom angle θS is between approximately 90° and approximately 99°. A bottom angle S less than 100° indicates that the silicon nitride hard mask 454 is not damaged during the removal of the sacrificial oxide layer from between the channel layers, thereby reducing DIBL degradation, increasing current, improving manufacturing yield, and enhancing device performance.

[0065] In various embodiments, the first depth 464 is approximately 45 nm, the second depth 466 is approximately 30 nm, and the third depth 468 is approximately 15 nm. These depths indicate that the silicon nitride hard mask 454 is not damaged during the removal of the sacrificial oxide layer between the channel layers, thereby reducing DIBL degradation, increasing current, improving manufacturing yield, and enhancing device performance. In various embodiments, the first depth 464 is greater than 43 nm, the second depth 466 is greater than 28 nm, and the third depth 468 is greater than 15 nm, indicating that the silicon nitride hard mask 454 is not damaged during the removal of the sacrificial oxide layer between the channel layers, thereby reducing DIBL performance, increasing current, improving manufacturing yield, and enhancing device performance.

[0066] Figures 31 and 32 illustrate various features of an example long-channel semiconductor structure 470 (e.g., semiconductor structure 200 or semiconductor structure 300) after the sacrificial oxide layer is removed between the channel layers. The figures show a channel structure STI 472 and a dielectric hard mask (e.g., a nitride Si hard mask 474) disposed above STI 472 and adjacent to the sidewalls of a bottom structure of multiple vertically spaced channel structures. This channel structure includes a first nanosheet 476, a second nanosheet 478, a third nanosheet 480, and a bottom channel region 482. The semiconductor structure 470 also includes a first depth 484 measured from the bottom of the first nanosheet 476 to the top of the silicon nitride hard mask 474, a second depth 486 measured from the bottom of the second nanosheet 478 to the top of the silicon nitride hard mask 474, a third depth 488 measured from the bottom of the third nanosheet 480 to the top of the silicon nitride hard mask 474, and a bottom angle θL measured between the sidewall of the bottom channel region 482 and the top of the silicon nitride hard mask 474.

[0067] In various embodiments, the bottom angle θL is between approximately 90° and approximately 95°. A bottom angle L less than 100° indicates that the silicon nitride hard mask 474 is not damaged during the removal of the sacrificial oxide layer from between the channel layers, thereby reducing DIBL degradation, increasing current, improving manufacturing yield, and enhancing device performance.

[0068] In various embodiments, the first depth 484 is approximately 44 nm, the second depth 486 is approximately 31 nm, and the third depth 488 is approximately 18 nm. These depths demonstrate that the silicon nitride hard mask 474 is not damaged during the removal of the sacrificial oxide layer from between the channel layers, thereby reducing DIBL degradation, increasing current, increasing manufacturing yield, and improving device performance.

[0069] Figures 33 and 34 show another example semiconductor structure 490 (e.g., semiconductor structure 200 or semiconductor structure 300) after subsequent metal gate fabrication operations. Figure 33 provides a cross-sectional schematic along the x-axis, and Figure 34 provides a three-dimensional schematic. The example semiconductor structure 490 includes a substrate 491, multiple fin structures 493 disposed on the substrate 491 and separating them, a channel nanosheet 494, a high-k (HK) metal gate structure 495 surrounding the channel nanosheet 494 (having HK dielectric, e.g., HfO, TaN, and metal, e.g., W, Cu, Co), source / drain regions 489, gate sidewall spacers 496 (e.g., SiCN, SiOCN, SiON, SiN), inner spacers 497 (e.g., SiCN, SiOCN, SiON, SiN), CESL 498, and an ILD layer 499.

[0070] Figure 35 is a flowchart illustrating a semiconductor manufacturing paradigm method 500 according to various aspects of this disclosure, including the fabrication of a multi-gate device. Figure 35 is described in conjunction with Figures 36-38, which show a semiconductor device 600 on a substrate 602 at various manufacturing stages according to some embodiments, and Figure 39 illustrates the etching sequence. Method 500 is merely an example and is not intended to limit the scope of this disclosure beyond what is expressly stated in the claims. Additional steps may be provided before, during, and after method 500, and some steps described may be moved, replaced, or eliminated for additional embodiments of method 500. Additional features may be added to the semiconductor device 600 depicted in the figures, and some features described below may be replaced, modified, or eliminated in other embodiments. In some figures, reference numerals for components or features shown may be omitted to avoid obscuring other components or features; this is for ease of drawing.

[0071] At block 502, exemplary method 500 includes providing a base. This block is similar to block 102 of method 100 and refers to the corresponding description of block 102, such as the description of block 502.

[0072] At block 504, exemplary method 500 includes forming an epitaxial stack comprising multiple epitaxial layers over a substrate. This block is similar to block 104 of method 100, and reference is made to the corresponding description of block 104, such as the description of block 504.

[0073] At block 506, exemplary method 500 includes patterning an epitaxial stack to form a semiconductor fin (also called a fin). This block is similar to block 106 of method 100 and refers to the corresponding description of block 106, such as the description of block 506.

[0074] At block 508, exemplary method 500 includes forming one or more sacrificial layers / features over a substrate. This block is similar to block 108 of method 100, and reference is made to the corresponding description of block 108, such as the description of block 508.

[0075] At block 510, exemplary method 500 includes patterning one or more sacrificial layers / features to form a dummy gate structure on the channel region of the fin. The patterning operations include operations similar to those discussed with respect to block 110, but also include operations to provide a higher level of smoothness to the sidewalls of the sacrificial gate structure. Smoothness can be measured by the bend ratio in the dummy gate structure. The bend ratio of the dummy gate structure defines the degree of deviation from a smooth surface and is based on the change in the horizontal position of the sidewall surface at a specific vertical location of the dummy gate structure and the change in the average position of the sidewall surface along its length. In various embodiments, an inflection point is defined as a location on the vertically extending sidewall of the dummy gate structure, wherein the specific sidewall location differs from the average position of the sidewall location at a predetermined distance (e.g., 2 nm) above the specific location by at least 0.5 nm in horizontal position, and the average position of the sidewall location at a predetermined distance (e.g., 2 nm) below the specific sidewall location is also at least 0.5 nm below the average position of the sidewall location. In various embodiments, the bending rate is based on the number of bends over the sidewall length.

[0076] In various embodiments, the patterning operation includes a bias reduction process comprising a main etching process, an O2 ashing process for removing residues from the main etching process, a breakthrough etching process for etching the dummy gate structure to the top of the epitaxial stack, repeating a smoothing etching operation, followed by multiple passivation operations (e.g., N2 passivation) (e.g., 3 times) to smooth the sidewalls of the dummy gate structure and reduce the bend rate, and an over-etching process. Referring to the example of FIG39, in an embodiment of the patterning operation, an exemplary bias reduction process 700 is provided for reducing the bend rate on the dummy gate structure. The exemplary formulation process 700 includes: at operation 702, a main etching process; at operation 704, an ashing process using O2 followed by a breakthrough etching process; at operation 706, a first soft-landing etching process that smooths the sidewalls of the dummy gate structure; at operation 708, a first N2 passivation process; at operation 710, a second soft-landing etching process to further smooth the sidewalls of the dummy gate structure; at operation 712, a second N2 passivation process; at operation 714, a third soft-landing etching process to further smooth the sidewalls of the dummy gate structure; at operation 716, a third N2 passivation process; and at operation 718, an over-etching process to further smooth the sidewalls of the dummy gate structure.

[0077] In various embodiments, the main etching process, smoothing etching operation, and over-etching process include plasma etching and are performed using an etching gas comprising one or more of CF4, CHF3, CH2F2, Cl2, HBr, O2, or others, with an HBr content of approximately 5% to approximately 10%; a selective passivation gas comprising one or more of N2, O2, CO2, or others; a dilution gas comprising one or more of He, Ar, N2, or others; a power between approximately 10 W and approximately 4000 W; a pressure between approximately 1 mTorr and approximately 800 mTorr; and a gas flow rate between approximately 20 sccm and approximately 3000 sccm. In various embodiments, the patterning operation can reduce the bend rate to below 10%.

[0078] At block 512, exemplary method 500 includes forming gate sidewall spacers on the sidewalls of the sacrificial gate structure. This block is similar to block 112 of method 100, and reference is made to the corresponding description of block 112, such as the description of block 512. Since the dummy gate 624 is formed to have a reduced deflection rate, the inner sidewalls of the inner spacer layer 638 are formed to have a smooth surface and a reduced deflection rate. In various embodiments, the smoothness level of the sidewalls of the sacrificial gate structure is transferred to the sidewalls of the gate sidewall spacers. In various embodiments, the deflection rate of the sidewalls of the sacrificial gate structure is transferred to the sidewalls of the gate sidewall spacers.

[0079] Smoothness can be measured by the bend ratio of the gate sidewall spacer. The bend ratio of the gate sidewall spacer defines the degree of deviation from a smooth surface and is based on the change in the horizontal position of the sidewall surface at a specific vertical location and the change in the average position of the sidewall surface along its length. In various embodiments, a bend is defined as a location on the vertically extending sidewall where the specific sidewall location differs from the average position of the sidewall location by at least 0.5 nanometers in the horizontal direction, the sidewall location being at least 2 nanometers above and below the specific sidewall location by a predetermined distance (e.g., 2 nanometers). In various embodiments, the bend ratio is based on the number of bends along the sidewall length.

[0080] At block 514, the exemplary method includes recessing the fins in the source / drain regions. This block is similar to block 114 of method 100, and, for example, the description of block 514 can be referenced to the corresponding description of block 114.

[0081] At block 516, exemplary method 500 includes forming a trench in a sacrificial epitaxial layer (e.g., SiGe) of an epitaxial stack. Referring to the example of FIG36, in the embodiment of block 516, the sacrificial epitaxial layer 614 has been etched back to form a sacrificial epitaxial layer trench 635, the top and bottom of which are bounded by the channel epitaxial layer 616, and the sides by the recessed sacrificial epitaxial layer 614. The sacrificial epitaxial layer 614 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. Alternatively, at block 516, the lateral ends of the sacrificial epitaxial layer 614 exposed in the trench 634 can be selectively oxidized to increase the etch selectivity between epitaxial layers 614 and 616. In some examples, the oxidation process can be performed by exposing the device 600 to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0082] At block 518, exemplary method 500 includes forming an inner spacer layer in a sacrificial epitaxial layer trench. Forming the inner spacer layer may include depositing an inner spacer material of a first material type in the sacrificial epitaxial layer trench, and trimming the inner spacer layer (e.g., through an etching operation). Referring to the example of FIG37, in the embodiment of block 518, an inner spacer layer 638 is formed in a sacrificial epitaxial layer trench 635. The inner spacer layer 638 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonitride, and / or other suitable dielectric materials. In some embodiments, the inner spacer layer 638 is deposited as a conformal layer. The inner spacer layer 638 may be formed by ALD or any other suitable method. In various embodiments, the inner spacer layer 638 is formed of the same material as the gate sidewall spacer layer 632 surrounding the dummy gate 624. In various embodiments, the gate sidewall spacer layer 632 and the inner spacer layer 638 are formed of SiOCN.

[0083] At block 520, exemplary method 500 includes forming source / drain (S / D) features. This block is similar to block 124 of method 100, and references the corresponding description of block 124, for example, the description of block 520.

[0084] At block 522, exemplary method 500 includes forming a CESL layer. This block is similar to block 126 of method 100 and refers to the corresponding description of block 126, for example, the description of block 522.

[0085] At block 524, exemplary method 500 includes forming an ILD layer. This block is similar to block 128 of method 100 and refers to the corresponding description of block 128, for example, the description of block 524.

[0086] At block 526, exemplary method 500 includes removing the dummy gate 624 to form a gate trench. This block is similar to block 130 of method 100, and reference is made to the corresponding description of block 130, such as the description of block 526. Because the formed dummy gate 624 has a reduced deflection rate, the inner sidewall of the inner spacer layer 638 maintains a smooth surface and a reduced deflection rate.

[0087] At block 528, exemplary method 500 includes removing the sacrificial epitaxial layer to form a nanosheet. Referring to the example of FIG38, in the embodiment of block 528, the sacrificial epitaxial layer 614 has been removed, thereby releasing the channel member from the channel region of the GAA device. In the illustrated embodiment, the channel member is a channel epitaxial layer 616 in the form of a nanosheet. In various embodiments, the channel epitaxial layer 616 comprises silicon, while the sacrificial epitaxial layer 614 comprises silicon germanium. In various embodiments, multiple sacrificial epitaxial layers 614 are selectively removed by a selective removal process, which includes oxidizing multiple sacrificial epitaxial layers 614 using a suitable oxidant (e.g., ozone). Subsequently, the oxidized sacrificial epitaxial layers 614 are selectively removed by a dry etching process, for example, by applying HCl gas at a temperature of about 500 degrees Celsius to about 700 degrees Celsius, or by applying a gas mixture of CF4, SF6, and CHF3.

[0088] At block 530, exemplary method 500 includes forming a metal gate structure. This block is similar to block 134 of method 100, and reference is made to the corresponding description of block 134, for example, the description of block 530. Since the dummy gate 624 is formed with a reduced bending rate, and the inner sidewall of the inner spacer layer 638 is formed with a smooth surface and a reduced bending rate, the sidewalls of the metal gate structure are formed with a smooth surface and a reduced bending rate.

[0089] In various embodiments, the smoothness of the sidewalls of the gate spacer is transferred to the sidewalls of the metal gate structure. Smoothness can be measured by the bend ratio in the metal gate structure. The bend ratio of the metal gate structure defines the degree of deviation from a smooth surface and is based on the change between the horizontal position of the sidewall surface at a specific vertical location of the metal gate structure and the average position of the sidewall surface along the length of the sidewall surface. In various embodiments, a bend is defined as a location on the vertically extending sidewall of the metal gate structure, wherein the horizontal position of the specific sidewall location differs from the average position of the sidewall location at a predetermined distance (e.g., 2 nm) above the specific location by at least 0.5 nm, and the average position of the sidewall location at a predetermined distance (e.g., 2 nm) below the specific sidewall location is also at least 0.5 nm below the average position of the sidewall location. In various embodiments, the bend ratio is based on the number of bends along the sidewall length.

[0090] At block 532, exemplary method 500 includes performing further manufacturing. This block is similar to block 136 of method 100, and reference is made to the corresponding description of block 136, for example, the description of block 532. The further manufacturing includes forming a metal drain (MD) contact. Because the sidewalls of the metal gate structure have smooth surfaces and reduced bending rates, the vertical profile of the MG is kept at a distance from the MD. This reduces MD-MG leakage and damage.

[0091] Figures 40 and 41 are cross-sectional views of a semiconductor structure 800, depicting multiple dummy gate structures 802 disposed above an epitaxial stack 804. As shown, the dummy gate structures have variable thicknesses, and due to the variable thickness of the gate structures, the sidewalls 806 are not smooth. Figure 41 is a schematic diagram of the semiconductor structure 800, showing the varying thickness of the dummy gate structures 802. In this example, the gate structure includes a first thickness Da at a first height level, a second thickness Db at a second height level, a third thickness Dc at a third height level, and a fourth thickness Dd at a fourth height level. Because a bias reduction process is used when patterning the dummy gate structures 802, the bending rate is 10% or less.

[0092] Figure 42 is a cross-sectional schematic diagram showing an example kink feature of a dummy gate on a semiconductor structure. Figure 43 is a graph illustrating an example formula for determining the kink ratio. Figure 44 is a graph illustrating an example calculation using the formula in Figure 43. As shown in Figure 42, the kink 820 provides a measurement of the difference in dummy gate width at different heights. As shown in Figure 43, the kink ratio is based on the number of kink increments with a difference greater than or equal to 0.5 nm, where the kink increment is the difference between the width at the kink center height and the average of the width at a height 2 nm above and below the kink. The kink ratio is equal to the number of kinks in the dummy gate structure with a kink increment greater than 0.5 nm divided by the length of the dummy gate structure.

[0093] In various embodiments, when a bias reduction process is used during dummy gate patterning operations, the number of bends with an increment greater than or equal to 0.5 nm can be 1E7 (10,000,000) or less, while when a bias reduction process is not used during dummy gate patterning operations, the increment is greater than or equal to 0.5 nm. Lower bend rates and lower bend counts can reduce the likelihood of leakage paths between the MG and MD and increase device yield during manufacturing.

[0094] In various embodiments, when a bias reduction process is used during the dummy gate patterning operation, the bend rate of the dummy gate structure can be 10% or less, while when a bias reduction process is not used during the dummy gate patterning operation, the bend rate can be 30% to 40%. Lower bend rates and lower bend counts can reduce the likelihood of leakage paths between the MG and MD and increase device yield during manufacturing.

[0095] Figure 45 is a cross-sectional schematic showing an exemplary metal gate structure (MG900) formed after a bias reduction process during the dummy gate patterning operation. In this example, a bottom angle θb is defined between the sidewalls and the contact surface of the MG900, a width 902 is defined at a gate height of 25 nm, a width 904 is defined at a gate height of 20 nm, a width 906 is defined at a gate height of 15 nm, and a width 908 is defined as a gate height of 3 nm. In this example, the gate structure has an M1 increment (the increment between width 902 and width 908) of approximately 3 nm to approximately 4 nm. The M2 increment (the increment between width 904 and width 908) is approximately 1 nm to approximately 2 nm, the M3 increment (the increment between width 906 and width 908) is less than 1 nm, and the bottom angle θb is between approximately 95 degrees and approximately 105 degrees. These ranges of M1 increments, M2 increments, M3 increments, and bottom angle b can reduce the likelihood of leakage paths between MG and MD and increase device yield during manufacturing. In various embodiments, a bottom angle b of less than 110 degrees can reduce the likelihood of leakage paths between MG and MD and increase device yield during manufacturing.

[0096] In various embodiments, an M1 increment of less than 5 nm can reduce the likelihood of a leakage path between the MG and MD, and increase device yield during manufacturing. In various embodiments, an M2 increment of less than 3 nm can reduce the likelihood of a leakage path between the MG and MD, and increase device yield during manufacturing. In various embodiments, an M3 increment of less than 2 nm can reduce the likelihood of a leakage path between the MG and MD, and increase device yield during manufacturing.

[0097] Figures 46 and 47 are schematic cross-sectional views showing an example metal gate structure (MG1000) formed after a bias reduction process during dummy gate patterning. In this example, a bottom angle θb is defined between the sidewalls of MG1000 and the contact surface of MG1000, width 1002 is defined at the top of MG1000, width 1004 is defined at the bottom of MG1000, and width 1006 is defined between MG1000 and MD1008. In this example, the T1 to T2 increment of the gate structure (the increment between widths 902 and 904) is less than 1 nm, the MG to MD distance is approximately 7.5 nm to approximately 9.5 nm, and the bottom angle θb is approximately 95 degrees to approximately 105 degrees. These ranges of T1 to T2 increment, MG to MD distance, and bottom angle θb can reduce the likelihood of leakage paths between MG and MD and improve device yield during manufacturing.

[0098] Figures 48 and 49 illustrate another example semiconductor structure 1100 using a bias reduction process after the metal gate fabrication operation and during the dummy gate patterning operation. Figure 48 provides a cross-sectional schematic along the x-axis, and Figure 49 provides a three-dimensional schematic. The example semiconductor structure 1100 includes a substrate 1102, STI features 1104 disposed on the substrate 1102 and separating multiple fin structures 1106, a channel nanosheet 1108, a high-k (HK) metal gate structure 1110 (with HK dielectric, e.g., HfO, TaN, and metal, e.g., W, Cu, Co), surrounding the channel nanosheet 1108, source / drain regions 1112, gate sidewall spacers 1114 (e.g., SiCN, SiOCN, SiON, SiN), inner spacer layers 1116 (e.g., SiCN, SiOCN, SiON, SiN), CESL 1118, ILD layer 1120, and MD 1122.

[0099] In some aspects, the technology described herein relates to a semiconductor structure comprising: a channel region including a plurality of vertically spaced channel structures, the channel region being surrounded by a gate structure including top vertically spaced channel structures; and a first metal gate region disposed above the gate structure of the top vertically spaced channel structures, the first metal gate region comprising: a vertically extending sidewall; a horizontally extending contact region located at the bottom of the first metal gate region, contacting the top vertically spaced channel structures, the contact region having a horizontally extending first length; a transition position on the sidewall, located at a position where the sidewall begins to transition towards the contact region; and a second length horizontally extending through the first metal gate region at the transition position; wherein the difference between the first length and the second length is less than 15% of the second length.

[0100] In some respects, the technology described herein relates to a semiconductor structure that also includes a corner measured at the corner between the sidewall and the contact area, wherein the corner is less than 100 degrees.

[0101] In some respects, the technology described herein relates to a semiconductor structure that also includes a first depth measured from a transition location to the bottom of a second metal gate region disposed below a channel structure vertically spaced at the top, wherein the first depth is less than 15 nm.

[0102] In some aspects, the technology described herein relates to a semiconductor structure that further includes a second depth measured from a transition location to the bottom of a third metal gate region disposed below a second vertically spaced channel structure disposed below the top of the second vertically spaced channel structure, wherein the second depth is less than 30 nm.

[0103] In some respects, the technology described herein relates to a semiconductor structure that further includes a third depth measured from a transition location to the bottom of a fourth metal gate region disposed below a third vertically spaced channel structure disposed below a second vertically spaced channel structure, wherein the third depth is less than 45 nm.

[0104] In some respects, the technology described herein relates to a semiconductor structure in which the difference between a first length and a second length is between about 1 nm and about 2 nm.

[0105] In some aspects, the technology described herein relates to a method comprising: providing a semiconductor structure including a plurality of vertically spaced channel structures, a plurality of vertically spaced interlayer oxide regions located between the plurality of vertically spaced channel structures, a sacrificial gate structure disposed above the plurality of vertically spaced channel structures, source features, and drain features; removing the gate structure by a dry etching operation; removing the interlayer oxide above the top channel structure of the plurality of vertically spaced channel structures by a dry etching operation; and removing the remaining portions of the plurality of vertically spaced interlayer oxide regions by a chemical etching operation.

[0106] In some respects, the techniques described herein relate to a method in which removing the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation includes removing all the remainder of the plurality of vertically spaced interlayer oxide regions by a chemical etching operation.

[0107] In some aspects, the techniques described herein relate to a method in which the removal of the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation includes the removal of the plurality of vertically spaced interlayer oxide regions without creating grooves between the bottom structure of the plurality of vertically spaced channel structures and the dielectric film adjacent to the sidewalls of the bottom structure.

[0108] In some respects, the techniques described herein relate to a method in which the angle between the sidewalls of the bottom structure of a semiconductor structure comprising a plurality of vertically spaced channel structures and a dielectric film disposed adjacent to the sidewalls, after the remaining portions of a plurality of vertically spaced interlayer oxide regions have been removed by a chemical etching operation, is less than 100 degrees.

[0109] In some respects, the technology described herein relates to a method in which, after removing the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation, the semiconductor structure further includes a dielectric film disposed near the sidewall of the bottom channel structure of the plurality of vertically spaced channel structures, and a first depth measured from the bottom of the top channel structure of the plurality of vertically spaced channel structures to the top of the dielectric film, wherein the first depth is approximately 45 nm.

[0110] In some respects, the technology described herein relates to a method in which, after removing the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation, the semiconductor structure further includes a dielectric film disposed near the sidewall of the bottom channel structure of the plurality of vertically spaced channel structures, and a second depth measured from the bottom of the second channel structure of the plurality of vertically spaced channel structures to the top of the dielectric film, wherein the second depth is approximately 30 nm.

[0111] In some respects, the technology described herein relates to a method in which, after removing the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation, the semiconductor structure further includes a dielectric film disposed near the sidewalls of the bottom channel structure of the plurality of vertically spaced channel structures and at a third depth measured from the bottom of the third channel structure of the plurality of vertically spaced channel structures to the top of the dielectric film, wherein the third depth is approximately 15 nm.

[0112] In some aspects, the technology described herein relates to a method comprising: providing a semiconductor structure including a plurality of vertically spaced channel structures, a plurality of vertically spaced interlayer oxide regions located between the plurality of vertically spaced channel structures, a sacrificial gate structure disposed above the plurality of vertically spaced channel structures, source features, and drain features; removing the sacrificial gate structure by a dry etching operation; removing the interlayer oxide above the top channel structure of the plurality of vertically spaced channel structures by a dry etching operation; removing the remainder of the plurality of vertically spaced interlayer oxide regions by a chemical etching operation; and forming a metal gate structure around the plurality of vertically spaced channel structures, the metal gate structure including a first metal gate region disposed above the top vertically spaced channel structure of the plurality of vertically spaced channel structures, the first metal gate region including: a vertically extending sidewall; a horizontally extending contact region located at the bottom of the first metal gate region, which contacts the top vertically spaced channel structure; and a corner measured at the corner between the sidewall and the contact region being less than 100 degrees.

[0113] In some respects, the technology described herein relates to a method in which: a contact region includes a first length extending horizontally; a first metal gate region also includes a transition location on a sidewall at which the sidewall begins to transition toward the contact region; the first metal gate region also includes a second length extending horizontally through the first metal gate region at the transition location; and the difference between the first length and the second length is less than 15% of the second length.

[0114] In some respects, the technique described herein relates to a method in which a first metal gate region further includes a first depth measured from a transition location to the bottom of a second metal gate region disposed below a channel structure at a top vertical spacing, wherein the first depth is less than 15 nm.

[0115] In some respects, the technology described herein relates to a method in which a first metal gate region further includes a second depth measured from a transition location to the bottom of a third metal gate region disposed below a second vertically spaced channel structure, wherein the second depth is less than 30 nm.

[0116] In some respects, the technology described herein relates to a method in which a first metal gate region further includes a third depth measured from a transition position to the bottom of a fourth metal gate region disposed below a third vertically spaced channel structure disposed below a second vertically spaced channel structure, wherein the third depth is less than 45 nm.

[0117] In some respects, the techniques described herein relate to a method in which removing the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation includes removing all the remainder of the plurality of vertically spaced interlayer oxide regions by a chemical etching operation.

[0118] In some respects, the techniques described herein relate to a method in which the removal of the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation includes the removal of the plurality of vertically spaced interlayer oxide regions without creating grooves between the bottom structure of the plurality of vertically spaced channel structures and the dielectric film adjacent to the sidewalls of the bottom structure.

[0119] In some aspects, the techniques described herein relate to a method comprising: providing a semiconductor structure including a plurality of vertically spaced channel structures and a plurality of vertically spaced sacrificial structures located between the plurality of vertically spaced channel structures; patterning a sacrificial gate structure over the plurality of vertically spaced channel structures, wherein the patterning provides a degree of smoothness to the sidewalls of the sacrificial gate structure, the patterning comprising: performing a master etch process; performing a breakthrough etch process; performing a plurality of smoothing etch processes; and performing an over-etch process; forming a gate spacer, wherein the smoothness of the sidewalls of the sacrificial gate structure is transferred to the sidewalls of the gate spacer; forming source and drain features; removing the sacrificial gate structure; and forming a metal gate structure, wherein the smoothness of the sidewalls of the gate spacer is transferred to the sidewalls of the metal gate structure, wherein the bend ratio in the metal gate structure is less than 10%, wherein the bend is defined as a location on a vertically extending sidewall of the metal gate structure, wherein a particular sidewall location differs at least 0.5 nanometers in a horizontal position from a first sidewall location at a predetermined distance above the particular sidewall location and an average level location at a predetermined distance below the particular sidewall location.

[0120] In some aspects, the techniques described herein relate to a method in which a semiconductor structure after forming a metal gate structure includes a base angle between the sidewall of the metal gate structure and the contact surface of the metal gate structure, and the base angle is less than 110 degrees.

[0121] In some respects, the technology described herein relates to a method in which a semiconductor structure following the formation of a metal gate structure includes a width difference of less than 5 nm between a second width at a gate height of 25 nm and a first width at a gate height of 3 nm.

[0122] In some respects, the technology described herein relates to a method in which a semiconductor structure following the formation of a metal gate structure includes a width difference of less than 3 nm between a third width at a gate height of 20 nm and a first width at a gate height of 3 nm.

[0123] In some respects, the technology described herein relates to a method in which a semiconductor structure following the formation of a metal gate structure includes a width difference of less than 2 nm between a fourth width at a gate height of 15 nm and a first width at a gate height of 3 nm.

[0124] In some aspects, the techniques described herein relate to a method in which a plurality of vertically spaced sacrificial structures include a plurality of vertically spaced interlayer oxide regions, further comprising: removing the sacrificial gate structure by a dry etching operation; removing the interlayer oxide above the top channel structure of the plurality of vertically spaced channel structures by a dry etching operation; and removing the remainder of the plurality of vertically spaced interlayer oxide regions by a chemical etching operation.

[0125] In some respects, the techniques described herein relate to a method in which removing the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation includes removing all the remainder of the plurality of vertically spaced interlayer oxide regions by a chemical etching operation.

[0126] In some respects, the techniques described herein relate to a method in which the removal of the remainder of a plurality of vertically spaced interlayer oxide regions by a chemical etching operation includes the removal of the plurality of vertically spaced interlayer oxide regions without creating grooves between the bottom structure of the plurality of vertically spaced channel structures and the dielectric film adjacent to the sidewalls of the bottom structure.

[0127] While at least one exemplary embodiment has been presented in the foregoing detailed description of this disclosure, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiments or multiple exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing exemplary embodiments of this disclosure. It should be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of this disclosure as set forth in the appended claims.

[0128] 100: Method 102: Block 104: Block 106: Block 108: Block 110: Block 112: Block 114: Block 116: Block 118: Block 120: Block 122: Block 124: Block 126: Block 128: Block 130: Block 132: Block 134: Block 136: Block 200: Structure 202:Substrate 212: Stacking 214: Epitaxial layer 215: Space 216: Epitaxial layer / nanosheet 217: Oxide layer 220: Fins 222: Oxides 224: Sacrificial gate structure 228: Gate electrode layer 232: Spacer / Spacer Layer 234: Groove 235: Groove 238: Inner Spacer Layer 240: S / D characteristics 242: CESL layer 244: ILD layer 254: Gate trench 260: Gate structure 300: Structure 302:Substrate 304: STI characteristics 306: Fin Structure 308: Channel epitaxial layer 308S: Channel epitaxial layer 308-L: Channel epitaxial layer 310: Oxide layer 312: Source / Leakage Zone 314: Gate structure 316: Spacer layer / spacer 316-L: First gate sidewall spacer 316-R: Second gate sidewall spacer 318: Inner Spacer Layer 320:CESL 322: ILD layer 324: Gate trench 350: Zone 1 352: Angle 354: Angle 356: Top 358: District 359: Dielectric film 360: Cutting line 362: Structure 364: Structure 400: Structure 402: The First Nanoparticle 404: Second Nanoparticle 406: The Third Nanoparticle 408: First metallic gate region 410: Second metallic gate region 412: Third Metal Gate Region 414: Fourth Metal Gate Region 416: Contact Area / Contact Surface Area 417: Location 418: Sidewall 420: First Depth 422: Second Depth 424: Third Depth 450: Structure 452:STI 454: Mask 456: The First Nanoparticle 458: Second Nanoparticle 460: The Third Nanoparticle 462: Bottom Channel Area 464: First Depth 466: Second Depth 468: Third Depth 470: Structure 472:STI 474: Mask 476: Nanoparticles 478: Nanoparticles 480: Nanoparticles 482: Passage Area 484: Depth 486: Depth 488: Depth 489: Source / Leakage Zone 490: Structure 491:Substrate 493: Fin Structure 494: Nanoparticles 495: Gate Structure 496: Spare layer 497: Spacer layer 499: ILD layer 500: Methods 502: Block 504: Block 506: Block 508: Block 510: Block 512: Block 514: Block 516: Block 518: Block 520: Block 522: Block 524: Block 526: Block 528: Block 530: Block 532: Block 600: Device 602:Substrate 614: Epitaxial layer 616: Epitaxial layer 624: Dummy gate 632: Spacer layer / spacer 634: Groove 635: Groove 638: Inner Spacer Layer D1: First Length D2: Second Length 700: Process 702: Operation 704: Operation 706: Operation 708: Operation 710: Operation 712: Operation 714: Operation 716: Operation 718: Operation 800: Structure 802: Gate structure 804: Stacking 806: Sidewall 802: Bending 900:MG (Metal Gate Structure) 902: Width 904: Width 906: Width 908: Width 1000:MG 1002: Width 1004: Width 1006: Width 1008:MD 1100: Structure 1102:Substrate 1104: STI Features 1106: Fin Structure 1108: Nanoparticles 1110: Structure 1112: Source / Leakage Zone 1114: Spacer 1116: Spacing layer 1118:CESL 1120: ILD layer 1122:MD θb: Angle θL: Angle θS: Angle

[0129] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor device, comprising: A semiconductor structure is provided, comprising a plurality of vertically spaced channel structures and a plurality of vertically spaced sacrificial structures located between the vertically spaced channel structures; a sacrificial gate structure is patterned over the vertically spaced channel structures, wherein the patterning provides a smoothness to one sidewall of the sacrificial gate structure, and the process includes: performing a master etching process; performing a breakthrough etching process; performing a plurality of smoothing etching processes; and performing an over-etching process; forming a plurality of gate spacers, wherein the smoothness of the sidewall of the sacrificial gate structure is transferred to one sidewall of the gate spacers; and forming a plurality of source features and a plurality of drain features. Remove the sacrificial gate structure; and form a metal gate structure, wherein a smoothness of the sidewall of the gate spacers is transferred to a sidewall of the metal gate structure, wherein a bend ratio in the metal gate structure is less than 10%, and wherein the bend is defined as a position on a vertically extending sidewall of the metal gate structure, wherein a particular sidewall position differs from an average of a first sidewall position at a predetermined distance above and below the particular sidewall position in a horizontal position by at least 0.5 nm.

2. The method as described in claim 1, wherein, The semiconductor structure after forming the metal gate structure includes: a bottom angle between a sidewall of the metal gate structure and a contact surface of the metal gate structure, the bottom angle being less than 110 degrees.

3. The method as described in claim 1, wherein, The semiconductor structure after forming the metal gate structure includes: a width difference of less than 5 nm between a second width at a gate height of 25 nm and a first width at a gate height of 3 nm; a width difference of less than 3 nm between a third width at a gate height of 20 nm and a first width at a gate height of 3 nm; and a width difference of less than 2 nm between a fourth width at a gate height of 15 nm and a first width at a gate height of 3 nm.

4. The method as described in claim 1, wherein, The sacrificial structures of the vertical spacings include a plurality of vertically spaced interlayer oxide regions, and further include: removing the sacrificial gate structure by dry etching; removing an interlayer oxide layer above a top channel structure of the vertically spaced channel structures by dry etching; and removing a remaining portion of the plurality of vertically spaced interlayer oxide regions by chemical etching.

5. A method for manufacturing a semiconductor device, comprising: A semiconductor structure is provided, including a plurality of vertically spaced channel structures, a plurality of vertically spaced interlayer oxide regions located between the vertically spaced channel structures, a sacrificial gate structure disposed above the vertically spaced channel structures, a source feature, and a drain feature; the sacrificial gate structure is removed by a dry etching operation; an interlayer oxide layer above a top channel structure of the vertically spaced channel structures is removed by a dry etching operation; and a remaining portion of the vertically spaced interlayer oxide regions is removed by a chemical etching operation.

6. The method as described in claim 5, wherein, Removing the remaining portion of the vertically spaced interlayer oxide regions through a chemical etching operation includes removing all remaining portions of the vertically spaced interlayer oxide regions through a chemical etching operation.

7. The method as described in claim 5, wherein, Removing the remaining portion of the vertically spaced interlayer oxide regions through a chemical etching operation includes removing the vertically spaced interlayer oxide regions without creating a groove between a bottom structure of the vertically spaced channel structure and a dielectric film adjacent to a sidewall of the bottom structure.

8. A method for manufacturing a semiconductor device, comprising: A semiconductor structure is provided, comprising a plurality of vertically spaced channel structures, a plurality of vertically spaced interlayer oxide regions located between the vertically spaced channel structures, a sacrificial gate structure disposed above the vertically spaced channel structures, a source feature, and a drain feature; the sacrificial gate structure is removed by dry etching; the interlayer oxide above a top channel structure of the vertically spaced channel structures is removed by dry etching; a remaining portion of the vertically spaced interlayer oxide regions is removed by chemical etching; and a metal gate structure is formed around the vertically spaced channel structures, the metal gate structure including a first metal gate region disposed above a top vertically spaced channel structure of the vertically spaced channel structures, the first metal gate region including: a vertically extending sidewall; a bottom horizontally extending contact region located in the first metal gate region, which contacts a top vertically spaced channel structure; and a corner angle of less than 100 degrees measured at a corner between the sidewall and the contact region.

9. The method as claimed in claim 8, wherein: the contact area includes a horizontally extending first length; the first metal gate region also includes a transition location on the sidewall at a location where the sidewall begins to transition into the contact area; the first metal gate region also includes a second length horizontally extending through the first metal gate region at the transition location; and a difference between the first length and the second length is less than 15% of the second length.

10. The method as described in claim 8, wherein, Removing the remaining portion of the vertically spaced interlayer oxide regions through a chemical etching operation includes removing the vertically spaced interlayer oxide regions without creating a groove between a bottom structure of the vertically spaced channel structure and a dielectric film adjacent to a sidewall of the bottom structure.

Images