Buffer and inverter transistors embedded in interconnect metal layers

Abstract

Integrated circuit devices with buffer transistors or inverter transistors formed between topside BEOL (back end of line) metal layers are described. The buffer or inverter transistors include active regions and source / drains that can be formed in the spaces between topside metal layers. In certain instances, the transistors are formed in between metal layers furthest away from substrate. The transistors connect to routing either above or below the transistors to buffer and / or invert signals passing through the routing. For instance, the transistors may include active regions positioned between power and ground routings and connect to signal routing between the power and ground routings to boost and / or to invert the signal propagating along the signal routing. In various instances, the active regions of the transistors are formed by thin channel materials.

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