Semiconductor devices and methods of formation

Abstract

A multiple-reticle exposure technique is used to manufacture monolithic superchips that have a greater amount of device area than if single-reticle exposures were used to manufacture the monolithic superchips. As described herein, different lateral regions of a semiconductor device (e.g., a monolithic superchip) may be patterned by different sets of lithography reticles. The multiple-reticle exposure technique may be expanded to manufacture a seal ring structure around the lateral regions of the semiconductor device. The multiple-reticle exposure technique may be used to manufacture the seal ring structure to have different attributes (e.g., different sizes, different shapes, different configurations) in different lateral regions of the semiconductor device, which provides for increased manufacturing flexibility in manufacturing monolithic superchips.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices and methods for forming the same. [Previous Technology]

[0002] The extreme ultraviolet (EUV) radiation source includes a collector comprising a curved mirror configured to collect EUV radiation and focus it to an intermediate focal point near an intermediate focal point cap (IF cap) of the EUV radiation source. EUV radiation is generated by laser-generated plasma (LPP), which is produced by exposing tin (Sn) droplets to a carbon dioxide (CO2) laser. The Sn droplets are generated by a droplet generator (DG) head, which feeds the Sn droplets into a vacuum chamber and then to the radiation position, where the Sn droplets are irradiated by a focused laser beam. [Summary of the Invention]

[0003] Some embodiments described herein provide a method of forming a semiconductor device. The method includes forming one or more integrated circuit elements in a device layer of the semiconductor device. This method includes forming an interconnect layer over the device layer. The interconnect layer includes one or more dielectric layers and one or more conductive structures located within the one or more dielectric layers. At least one integrated circuit element is coupled to at least one of the one or more conductive structures. This method includes forming a first segment of a multiple sealing ring structure around a first portion of the interconnect layer in a first region of the semiconductor device using a first set of photolithographic masks. This method includes forming a second segment of the multiple sealing ring structure around a second portion of the interconnect layer in a second region of the semiconductor device using a second set of photolithographic masks, wherein the first region and the second region are laterally adjacent in the semiconductor device, wherein the first portion and the second portion of the interconnect layer are laterally adjacent in the semiconductor device, and wherein the first segment and the second segment of the multiple sealing ring structure are coupled together such that the multiple sealing ring structure laterally and continuously surrounds the interconnect layer.

[0004] Some embodiments described herein provide a method for forming a semiconductor device. The method includes: forming one or more integrated circuit elements in a device layer of the semiconductor device; forming an interconnect layer above the device layer; wherein the interconnect layer includes one or more dielectric layers and one or more conductive structures located within the one or more dielectric layers, and wherein at least one integrated circuit element is coupled to at least one of the one or more conductive structures; using a first set of photolithographic masks, forming a first segment of a first sealing ring structure and a first segment of a second sealing ring structure of a multi-sealed ring structure around a first portion of the interconnect layer in a first region of the semiconductor device, wherein the first set of photolithographic masks is used to form the first segment of the first sealing ring structure, such that... A first segment of a first sealing ring structure includes a diced segment, and a first set of photolithographic masks is used to form a first segment of a second sealing ring structure such that the first segment of the second sealing ring structure includes a first terminal extending through the diced segment; and a second segment of a first sealing ring structure and a second segment of a second sealing ring structure of a multi-seal ring structure are formed around a second portion of an interconnect layer in a second region of a semiconductor element using a second set of photolithographic masks, wherein the second set of photolithographic masks is used to form a second segment of the first sealing ring structure such that the second segment of the first sealing ring structure includes a second terminal extending laterally from the second segment of the first sealing ring structure.

[0005] Some embodiments described herein provide a semiconductor element. The semiconductor element includes: a device layer including a semiconductor layer; one or more integrated circuit elements located in the semiconductor layer of the device layer; an interconnect layer located above the device layer and including: one or more dielectric layers; and one or more conductive structures located in the one or more dielectric layers, wherein at least one integrated circuit element is coupled to at least one of the one or more conductive structures; a first sealing ring structure located in the one or more dielectric layers, wherein a first segment of the first sealing ring structure has a first lateral width in a direction substantially perpendicular to the length of the first sealing ring structure, wherein a second segment of the first sealing ring structure has a second lateral width in a direction substantially perpendicular to the length of the first sealing ring structure, wherein the first lateral width and the second lateral width are different lateral widths; and a second sealing ring structure located in the one or more dielectric layers, wherein the second sealing ring structure laterally surrounds the first sealing ring structure, wherein a third segment of the second sealing ring structure has a third lateral width in a direction substantially perpendicular to the length of the second sealing ring structure, wherein a fourth segment of the second sealing ring structure has a fourth lateral width in a direction substantially perpendicular to the length of the second sealing ring structure, wherein the third lateral width and the fourth lateral width are different lateral widths.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another element or feature. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0008] A photolithography system may include a radiation source and an exposure tool. The radiation source (e.g., an extreme ultraviolet (EUV) radiation source or another type of radiation source) may be configured to generate radiation such as EUV radiation and / or another type of electromagnetic radiation (e.g., light). The exposure tool (e.g., an EUV scanner or other type of exposure tool) may be configured to focus the radiation onto a reflective mask (or photomask), thereby using the radiation to transfer a pattern from the mask onto a semiconductor substrate. Depending on the pattern of the mask, the radiation may be reflected from the mask. The radiation may be reflected onto the semiconductor substrate, such that the pattern of the mask is transferred onto the semiconductor substrate.

[0009] Various industries rely on advanced semiconductor equipment to achieve high-speed, low-power, and / or specialized operations. High-performance computing (HPC) devices can process large amounts of data at high speeds to perform complex calculations. HPC devices may include computer chips capable of performing multiple functions to perform parallel data processing. Internet of Things (IoT) devices may include computer chips with multiple functions (including processing, memory, wireless communication, and storage) while requiring high efficiency and sometimes relying on battery power. Communication equipment (e.g., radio frequency (RF) equipment, data center communication equipment) may include computer chips that perform high-speed and high-bandwidth communication.

[0010] Each dedicated computer chip may integrate multiple devices and contact structures that would otherwise only be found on multiple non-dedicated chips. Therefore, such a dedicated computer chip (e.g., a "superchip") may need to be larger than a non-dedicated chip to include the devices and / or contact structures required to perform multiple functions. However, the size of a computer chip (e.g., a semiconductor chip fabricated on a wafer) may be limited by the size of the mask used to pattern the layers of the computer chip. This may prevent the dedicated computer chip from achieving the device density required to perform multiple functions. Therefore, it may be necessary to interconnect multiple dedicated computer chips to achieve such a feature set, which could increase manufacturing complexity.

[0011] In some embodiments described herein, a multi-mask exposure technique is used to fabricate a single-crystal superwafer with a larger device area than that fabricated using a single-mask exposure technique. As described herein, different lateral regions of a semiconductor device (e.g., a single-crystal superwafer) can be patterned using different sets of photolithographic masks. For example, a first set of masks can be used to pattern a first lateral region of the semiconductor device, while a second set of masks can be used to pattern a second lateral region of the semiconductor device. This allows the lateral regions of the semiconductor device to be fabricated to have specific functional areas (e.g., memory, logic, analog, communication), which are integrated onto a single single-crystal superwafer, rather than distributed across multiple discrete computer chips fabricated using a single-mask exposure technique.

[0012] As further described herein, the multiple masking exposure technique can be extended to fabricate sealing ring structures around lateral regions of semiconductor devices. The multiple masking exposure technique can be used to fabricate sealing ring structures with different properties (e.g., different sizes, different shapes, different configurations) in different lateral regions of a semiconductor device, providing greater manufacturing flexibility for the fabrication of single-crystal super wafers.

[0013] Figure 1 is a diagram of an embodiment of the lithography system 100 described herein. The lithography system 100 includes an EUV lithography system or other types of lithography systems configured to transfer patterns onto a semiconductor substrate using mirror-based optical elements. The lithography system 100 can be configured for semiconductor process environments, such as semiconductor foundries or semiconductor manufacturing plants.

[0014] As shown in Figure 1, the photolithography system 100 includes a radiation source 102 and an exposure tool 104. The radiation source 102 (e.g., an EUV radiation source or other type of radiation source) is configured to generate radiation 106, such as EUV radiation and / or another type of electromagnetic radiation (e.g., light). The exposure tool 104 (e.g., an EUV scanner or other type of exposure tool) is configured to focus the radiation 106 onto a reflective mask 108 (or a photomask), such that a pattern is transferred from the mask 108 onto a semiconductor wafer 110 using the radiation 106.

[0015] Radiation source 102 includes a container 112 and a collector 114 located within the container 112. Collector 114 includes a curved mirror for collecting radiation 106 generated by radiation source 102 and focusing radiation 106 to an intermediate focal point 116. Radiation 106 is generated by plasma produced when droplets 118 (e.g., tin (Sn) droplets or other types of droplets) are exposed to laser beam 120. Droplet generator (DG) head 122 supplies droplets 118 to the front side of collector 114. DG head 122 is pressurized to provide a fine and controllable output of droplets 118.

[0016] A laser source (e.g., a pulsed carbon dioxide (CO2) laser) generates a laser beam 120. The laser beam 120 is provided (e.g., through a beam transmission system to a focusing lens) such that the laser beam 120 is focused through a viewing window 124 of a collector 114. The laser beam 120 is focused onto a droplet 118, thereby generating plasma. The plasma generates plasma emission, some of which is radiation 106. The laser beam 120 is time-pulsed in sync with the flow of the droplet 118 from the DG head 122.

[0017] Exposure tool 104 includes an illuminator 126 and a projection optics box (POB) 128. The illuminator 126 includes a plurality of mirrors configured to focus and / or direct radiation 106 onto a mask 108, thereby illuminating a pattern on the mask 108. The mirrors include, for example, mirrors 130a and 130b. Mirror 130a includes a field faceted mirror (FFM) or other types of mirrors including multiple field facets. Mirror 130b includes a pupil faceted mirror (PFM) or other types of mirrors also including multiple pupil facets. The facets of mirrors 130a and 130b are arranged to focus, polarize, and / or otherwise adjust radiation 106 from radiation source 102 to increase the uniformity of radiation 106 and / or increase specific types of radiation components (e.g., transversely electrically (TE) polarized radiation, transversely magnetically (TM) polarized radiation). Another mirror 132 (e.g., a relay mirror) is used to direct the radiation 106 of the illuminator 126 onto the shield 108.

[0018] The projection optics box 128 includes a plurality of mirrors configured to project radiation 106 onto the semiconductor wafer 110 after pattern modification radiation 106 based on mask 108. The plurality of mirrors includes, for example, mirrors 134a, 134b, 134c, 134d, 134e, and 134f. In some embodiments, mirrors 134a, 134b, 134c, 134d, 134e, and 134f are configured to focus or reduce radiation 106 into an exposure field that may include one or more bare die regions on the semiconductor wafer 110.

[0019] Exposure tool 104 includes a wafer platform 136 (e.g., a substrate platform) for supporting a semiconductor wafer 110. Furthermore, the wafer platform 136 is used to move (or step) the semiconductor wafer 110 through multiple exposure fields as radiation 106 transfers a pattern from a mask 108 onto the semiconductor wafer 110. The wafer platform 136 is included in a bottom module 138 of the exposure tool 104. The bottom module 138 includes a removable subsystem of the exposure tool 104. The bottom module 138 can slide out of and / or otherwise remove from the exposure tool 104 for cleaning and inspection of the wafer platform 136 and / or its components. The bottom module 138 isolates the wafer platform 136 from other areas in the exposure tool 104 to reduce and / or minimize contamination of the semiconductor wafer 110. Furthermore, the bottom module 138 can provide physical isolation for the wafer platform 136 by reducing vibrations transmitted to the wafer platform 136 and the semiconductor wafer 110 (e.g., vibrations in the semiconductor process environment where the lithography system 100 is located, and vibrations of the lithography system 100 during operation). This reduces movement and / or interference of the semiconductor wafer 110, thereby reducing the possibility of pattern misalignment caused by vibration.

[0020] The exposure tool 104 also includes a mask platform 140 for supporting and / or fixing the mask 108. Furthermore, the mask platform 140 is used to move or slide the mask through the radiation 106, allowing the mask 108 to be scanned by the radiation 106. In this way, a pattern of a field or beam larger than the radiation 106 can be transferred onto the semiconductor wafer 110.

[0021] The lithography system 100 includes a laser source 142. The laser source 142 is configured to generate a laser beam 120. The laser source 142 may include a CO2-based laser source or other types of laser sources. Since the wavelength of the laser beam generated by a CO2-based laser source is in the infrared (IR) region, the laser beam may be highly absorbed by tin, which enables the CO2-based laser source to achieve high power and energy to pump tin-based plasma. In some embodiments, the laser beam 120 includes multiple types of laser beams generated by the laser source 142 using multi-pulse technology (or multi-stage pumping technology), wherein the laser source 142 generates a pre-pulse laser beam and a main pulse laser beam to achieve higher heating efficiency of the tin (Sn)-based plasma, thereby improving conversion efficiency.

[0022] In an exemplary exposure operation (e.g., an EUV exposure operation), the DG head 122 provides a flow of water from droplets 118 through the front side of the collector 114. A laser beam 120 contacts the droplets 118, thereby generating plasma. A laser source 142 generates and provides a pre-pulsed laser beam to a target material droplet in the water flow of droplets 118, and this pre-pulsed laser beam is absorbed by the target material droplet. This transforms the target material droplet into a disk shape or a mist. Subsequently, the laser source 142 provides a main pulse laser beam of higher intensity and energy to the disk-shaped or mist-shaped target. Here, atoms of the target material are neutralized, and ions are generated through heat flux and shock waves. The main pulse laser beam pumps the ions to a higher charge state, causing the ions to radiate radiation 106 (e.g., EUV light).

[0023] Radiation 106 is collected by collector 114 and emitted from container 112 into exposure tool 104, toward mirror 130a of illuminator 126. Mirror 130a reflects radiation 106 onto mirror 130b, which in turn reflects it onto mirror 132, toward mask 108. The pattern in mask 108 modifies radiation 106. In other words, radiation 106 is reflected from mask 108 according to the pattern therein. The reflective mask 108 guides radiation 106 to mirror 134a in projection optics box 128, which in turn reflects radiation 106 onto mirror 134b. Radiation 106 continues to be reflected and attenuated by mirrors 134c, 134d, 134e, and 134f in projection optics box 128. Mirror 134f reflects radiation 106 onto semiconductor wafer 110, thereby transferring the pattern of mask 108 onto semiconductor wafer 110. The above exposure operation is merely an example; the lithography system 100 can operate according to other EUV technologies and radiation paths, including more mirrors, fewer mirrors, and / or mirrors with different configurations.

[0024] As stated above, Figure 1 is provided as an example only. Other examples may differ from those shown in Figure 1.

[0025] Figures 2A and 2B are figures of an exemplary embodiment 200 of the semiconductor element 202 described herein. Figure 2A shows a top view of the semiconductor element 202, and Figure 2B shows a cross-sectional view of the semiconductor element 202 along line A-A' in Figure 2A.

[0026] As shown in Figure 2A, the semiconductor element 202 may include an interface 204 between different lateral regions 206 and lateral regions 208 of the semiconductor element 202. The lateral regions 206 and 208 may be laterally adjacent in the x-direction and / or y-direction of the semiconductor element 202, and may contain different functional area top view layouts. For example, functional regions 210, 212, 214, and 216 may be laterally distributed on the lateral regions 206 and 208, wherein functional region 210 is contained in the lateral region 206, a portion of functional region 212 is contained in both the lateral regions 206 and 208, functional region 214 is contained in the lateral region 208, and a portion of functional region 216 is contained in both the lateral regions 206 and 208. The top-view layout of semiconductor element 202 and the number, size, shape and / or arrangement of functional areas 210, 212, 214 and 216 are merely examples, and other layouts, numbers, sizes, shapes and / or arrangements are within the scope of this disclosure.

[0027] Semiconductor element 202 may be a system-on-a-chip (SoC) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application-specific integrated circuit (ASIC) die, an image sensor die, an HPC die, and / or other types of semiconductor dies including multiple functional regions 210, 212, 214, and 216. Each of functional regions 210, 212, 214, and 216 may be fabricated to include integrated circuitry configured to perform a specific set of functions of semiconductor element 202. For example, functional region 210 may be a storage region (or storage core) of semiconductor element 202, which includes integrated circuitry configured to perform storage functions of semiconductor element 202. As another example, functional region 212 may be an analog circuitry region (or analog core) of semiconductor element 202, which includes integrated circuitry configured to perform analog functions of semiconductor element 202. As another example, functional area 214 may be an RF circuit region (or RF core) of semiconductor element 202, which includes integrated circuitry configured to perform RF communication functions of semiconductor element 202. As another example, functional area 216 may be a logic circuit region (or logic core) of semiconductor element 202, which includes integrated circuitry configured to perform logic functions of semiconductor element 202. In some implementations, semiconductor element 202 includes another type of functional area or a combination of different functional areas.

[0028] Lateral regions 206 and 208 are regions of the semiconductor element 202, which are patterned by different sets of masks 108 of the photolithography system 100 during the fabrication of the semiconductor element 202. For example, one or more layers and / or structures of the lateral region 206 can be patterned using a first set of masks 108, and one or more layers and / or structures of the lateral region 208 can be patterned using a second set of masks 108. The first and second sets of masks 108 can be used sequentially to form different layouts in the lateral regions 206 and 208 from the same layer formed on the semiconductor element 202. Interface 204 may correspond to the boundary between the region patterned using the first set of masks 108 (e.g., lateral region 206) and the region patterned using the second set of masks 108 (e.g., lateral region 208). Therefore, one or more of functional areas 210, 212, 214, and 216 (e.g., functional area 210) are formed using only the first set of masks 108. One or more of functional areas 210, 212, 214, and 216 (e.g., functional area 214) are formed using only the second set of masks 108. One or more of functional areas 210, 212, 214, and 216 (e.g., functional areas 212 and 216) are formed using both the first and second sets of masks 108. For example, the first set of masks 108 can be used to form portions of functional areas 212 and 216 located in the lateral region 206, while the second set of masks 108 can be used to form portions of functional areas 212 and 216 located in the lateral region 208.

[0029] This multiple masking exposure technique enables the use of multiple sets of masks 108 to form the lateral regions 206 and lateral regions 208 of the semiconductor device 202, thereby monolithically expanding the lateral coverage area of ​​the semiconductor device 202. In other words, instead of functional regions 210, 212, 214, and 216 being formed on separate workpieces and bonded together via wire bonding on the package substrate or otherwise integrated, functional regions 210, 212, 214, and 216 can be formed on the same substrate using multiple sets of masks 108, integrating functional regions 210, 212, 214, and 216 onto a single workpiece. In some embodiments, the multiple masking exposure technique enables the semiconductor device 202 to be formed as a single-crystal "super wafer" with a lateral dimension of approximately 25 mm x approximately 30 mm or larger.

[0030] As further shown in Figure 2A, the semiconductor element 202 may include a multi-ring sealing structure 218 laterally surrounding functional regions 210, 212, 214, and 216 of the semiconductor element 202. The multi-ring sealing structure 218 may include multiple sealing ring structures, each including multiple interconnected metallized structural layers and interconnect structures. These structures provide enhanced structural stiffness to the semiconductor element 202, thereby reducing the likelihood of cracking, warping, and / or other types of physical damage that might otherwise be caused by physical stresses applied to the semiconductor element 202. Additionally and / or alternatively, the multi-ring sealing structure 218 may be configured to provide a moisture-proof seal for the semiconductor element 202, which reduces the possibility of moisture intrusion into the semiconductor element 202.

[0031] The multi-ring sealing structure 218 may include multiple segments, including a first set of segments surrounding the periphery of the transverse region 206 and a second set of segments surrounding the periphery of the transverse region 208. The first set of segments and the second set of segments may be connected together to form a continuous seal around the periphery of the semiconductor element 202.

[0032] As further shown in Figure 2A, the multi-ring sealing structure 218 may include a sealing ring structure 218a that laterally surrounds functional regions 210, 212, 214, and 216, and a sealing ring structure 218b that laterally surrounds the sealing ring structure 218a. The sealing ring structure 218a may be referred to as the inner sealing ring structure, and the sealing ring structure 218b may be referred to as the outer sealing ring structure 218b. The sealing ring structures 218a and 218b may each include a closed-loop structure that completely and continuously surrounds the periphery of the semiconductor element 202.

[0033] As shown in the detailed view of Figure 2A, the sealing ring structure 218a may include a configuration of interconnect structure layers and metallization structure layers. One interconnect structure of the sealing ring structure 218a may include an inner interconnect structure 220a, an outer interconnect structure 220b, and an arrangement of a plurality of columnar interconnect structures 222 laterally located between the inner interconnect structure 220a and the outer interconnect structure 220b. The inner interconnect structure 220a and the outer interconnect structure 220b may each include a trench-like via extending continuously around the periphery of the semiconductor element 202, while the columnar interconnect structures 222 include vertically elongated interconnect structures spaced apart from each other. The columnar interconnect structures 222 may be arranged around the periphery of the semiconductor element 202 in a checkerboard pattern and / or other types of patterns.

[0034] The vertically adjacent interconnect structure layers of the sealing ring structure 218a can be coupled together through a metallization structure 224 located vertically between the adjacent interconnect structure layers. The metallization structure 224 may include a substantially flat metal line that extends continuously around the periphery of the semiconductor element 202.

[0035] The sealing ring structure 218a may have a lateral width (denoted as dimension D1 in Figure 2A) and a lateral spacing (denoted as dimension D2 in Figure 2A) between the inner interconnect structure 220a and the outer interconnect structure 220b of the sealing ring structure 218a. The lateral width may be in a direction substantially perpendicular to the length of the sealing ring structure 218a and may be in the range of about 4 micrometers to about 6 micrometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the lateral width of the sealing ring structure 218a may be in the range of about 3 micrometers to about 5 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0036] As further shown in the detailed view of Figure 2A, the sealing ring structure 218b may include a configuration of interconnect structure layers and metallization structure layers. One interconnect structure of the sealing ring structure 218b may include a configuration of inner pillar interconnect structure 226 and outer line interconnect structure 228. The outer line interconnect structure 228 may include trench-like vias extending continuously around the periphery of the semiconductor element 202, while the inner pillar interconnect structure 226 includes vertically elongated interconnect structures spaced apart from each other. The inner pillar interconnect structure 226 may be disposed around the periphery of the semiconductor element 202.

[0037] The vertically adjacent interconnect structure layers of the sealing ring structure 218b can be coupled together through a metallization structure 230 located vertically between the adjacent interconnect structure layers. The metallization structure 230 may include a substantially flat metal line extending continuously around the periphery of the semiconductor element 202.

[0038] The sealing ring structure 218b may have a lateral width (denoted as dimension D3 in Figure 2A) and a lateral spacing (denoted as dimension D4 in Figure 2A) between the inner post interconnection structure 226 and the outer line interconnection structure 228 of the sealing ring structure 218b. The lateral width may be in a direction substantially perpendicular to the length of the sealing ring structure 218 and may be in the range of about 1.5 micrometers to about 2.5 micrometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the lateral width of the sealing ring structure 218b may be in the range of about 1.0 micrometer to about 2 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0039] In some embodiments, the lateral width of the sealing ring structure 218a is greater than the lateral width of the sealing ring structure 218b (e.g., D1 > D3). In some embodiments, the lateral width of the sealing ring structure 218a is less than the lateral width of the sealing ring structure 218b (e.g., D1 < D3). In some embodiments, the lateral widths of the sealing ring structure 218a and the sealing ring structure 218b are approximately equal (e.g., D1 ≅ D3).

[0040] The sealing ring structure 218a may be spaced apart from the sealing ring structure 218b by a certain distance (denoted as dimension D5 in Figure 2A). In some embodiments, the distance between the sealing ring structure 218a and the sealing ring structure 218b is in the range of about 2 micrometers to about 3 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0041] As shown in Figure 2B, the semiconductor element 202 may include a device layer 232 and a front interconnect layer 234 located in front of the device layer 232. The device layer 232 and the front interconnect layer 234 may be arranged vertically along the z-direction in the semiconductor element 202.

[0042] Device layer 232 may include substrate layer 236. Substrate layer 236 may correspond to a portion of a semiconductor wafer on which semiconductor elements 202 are formed. Substrate layer 236 may include silicon (Si) substrate, substrate formed of a material including silicon, III-V compound semiconductor material substrate such as gallium arsenide (GaAs), silicon-on-insulator (SOI) substrate, or other types of semiconductor substrate.

[0043] Device layer 232 may further include one or more integrated circuit elements 238 located inside and / or on the front side of substrate layer 236. Each integrated circuit element 238 may include transistors (e.g., planar transistors, finFETs, gate-all-around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, diodes and / or other types of passive and / or active integrated circuit elements.

[0044] Lateral regions 206 and 208 may include different arrangements of integrated circuit elements 238 formed using different sets of masks 108. The integrated circuit elements 238 in lateral region 206 may be disposed in integrated circuits that implement the functions of functional areas 210, 212, and 216. Similarly, the integrated circuit elements 238 in lateral region 208 may be disposed in integrated circuits that implement the functions of functional areas 212, 214, and 216.

[0045] Isolation region 240 may also be included in substrate layer 236 to provide electrical isolation for integrated circuit element 238. One or more isolation regions 240 may include implantation regions of substrate layer 236, wherein dopants are implanted. Dopants may include, for example, n-type dopants (e.g., phosphorus (P) and / or arsenic (As)) and / or p-type dopants (e.g., boron (B)). Additionally and / or alternatively, one or more of isolation regions 240 may include shallow trench isolation (STI) structures. The STI structure may be a dielectric structure extending to the front side of substrate layer 236 and may include one or more dielectric materials, such as silicon oxide materials (SiOx, e.g., SiO2), silicon nitride materials (SixNy, e.g., Si3N4), and / or other suitable dielectric materials.

[0046] The front interconnect layer 234 includes one or more dielectric layers 242, which may be arranged in a direction approximately perpendicular to the substrate layer 236 (e.g., the z-direction). The dielectric layers 242 may include back-end dielectric layers (e.g., interlayer dielectric (ILD), intermetallic dielectric (IMD)) and etch stop layers (ESL) arranged alternately in the front interconnect layer 234. The dielectric layers 242 may each include oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), undoped silicate glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), extremely low dielectric constant (ELK) dielectric materials with a dielectric constant less than about 2.5, silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials.

[0047] The front interconnect layer 234 also includes one or more conductive structures 244 (e.g., electrically conductive structures) in the dielectric layer 242. The conductive structures 244 may be electrically coupled and / or physically coupled to one or more integrated circuit elements 238 in the device layer 232, and / or may be electrically interconnected together in the front interconnect layer 234. The conductive structures 244 correspond to circuit wiring that enables the supply of signals and / or power to and / or from the integrated circuit elements 238. The conductive structures 244 may include a combination of conductive structures (e.g., trenches, conductive lines) that extend primarily horizontally in the front interconnect layer 234, and these conductive structures are interconnected through interconnect structures (e.g., vias) that extend primarily vertically in the front interconnect layer 234. Each conductive structure 244 may include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, as well as other examples of conductive materials.

[0048] The conductive structures 244 of the front interconnect layer 234 may be vertically aligned to facilitate the transmission of electrical signals and / or power between the device layer 232 and an external connector coupled to the semiconductor element 202. The conductive structures 244 may be alternately arranged in metallization layers (referred to as "M" layers) and via layers (referred to as "V" layers). Each metallization layer may include one or more conductive structures laterally aligned in the front interconnect layer 234, and each via layer may include one or more interconnect structures interconnecting the metallization layers in the front interconnect layer 234. For example, a metal-0 (M0) layer may be located at the bottom of the front interconnect layer 234 (e.g., connected to the front of the device layer 232) and may be coupled to an integrated circuit element 238 in the substrate layer 236, wherein a via-0 (V0) layer may be located above and coupled to the M0 layer in the front interconnect layer 234, a metal-1 (M1) layer may be located above and coupled to the V0 layer in the front interconnect layer 234, a via-1 (V1) layer may be located above and coupled to the M1 layer in the front interconnect layer 234, a metal-2 (M2) layer may be located above and electrically coupled to the V1 layer in the front interconnect layer 234, and so on. In some embodiments, the front interconnect layer 234 includes nine (9) stacked metallization layers (e.g., M0-M8). In other embodiments, a contact layer (referred to as a "CO" layer) may be located at the bottom of the front interconnect layer 234 and may be coupled to the integrated circuit elements 238 in the substrate layer 236. For example, a metal-1 (M1) layer may be located above and coupled to the CO layer in the front interconnect layer 234, and so on. In some embodiments, the front interconnect layer 234 includes another number of stacked metallization layers.

[0049] Lateral regions 206 and 208 may include conductive structures 244 arranged in different configurations using different sets of masks 108. The conductive structures 244 in lateral region 206 may be configured to distribute signals and / or power to integrated circuits in functional regions 210, 212, and 216. Similarly, the conductive structures 244 in lateral region 208 may be configured to distribute signals and / or power to integrated circuits in functional regions 212, 214, and 216. In some embodiments, the conductive structures 244 in lateral regions 206 and / or lateral region 208 may be configured to distribute signals and / or power between two or more functional regions 210, 212, 214, and 216.

[0050] The multiple sealing ring structure 218 may also be located in the dielectric layer 242 of the front interconnect layer 234. The sealing ring structure 218 may include a plurality of vertically arranged conductive structure layers (e.g., in the z-direction) that laterally surround the semiconductor element 202. For example, the sealing ring structure 218a may include vertically alternating interconnect structure layers and metallization structure layers in the front interconnect layer 234. As another example, the sealing ring structure 218b may include vertically alternating interconnect structure layers and metallization structure layers in the front interconnect layer 234.

[0051] The one or more interconnect structures of the sealing ring structure 218a may include an inner interconnect structure 220a, an outer interconnect structure 220b, and a plurality of columnar interconnect structures 222 laterally located between the inner interconnect structure 220a and the outer interconnect structure 220b. In some embodiments, the lateral width of the inner interconnect structure 220a, the lateral width of the outer interconnect structure 220b, and / or the lateral width of the columnar interconnect structures 222 may increase progressively from the bottom of the front interconnect layer 234 (e.g., vertically adjacent to the device layer 232) to the top of the front interconnect layer 234. The vertically adjacent layers of the inner interconnect structure 220a, the outer interconnect structure 220b, and the columnar interconnect structures 222 may be interconnected through the metallization structure 224 layer. The inner interconnect structure 220a, the outer interconnect structure 220b, the columnar interconnect structure 222 and / or the metallization structure 224 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, as well as other examples of conductive materials.

[0052] The one or more interconnect structures of the sealing ring structure 218b may include a plurality of inner pillar interconnect structures 226 and outer wire interconnect structures 228 laterally adjacent to the inner pillar interconnect structures 226. In some embodiments, the lateral width of the inner pillar interconnect structures 226 and / or the lateral width of the outer wire interconnect structures 228 may increase progressively from the bottom of the front interconnect layer 234 (e.g., vertically adjacent to the device layer 232) to the top of the front interconnect layer 234. The vertically adjacent layers of the inner pillar interconnect structures 226 and the outer wire interconnect structures 228 may be interconnected through the metallization structure 230 layer. The inner pillar interconnect structures 226, the outer wire interconnect structures 228 and / or the metallization structure 230 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, and other examples of conductive materials.

[0053] In some embodiments, the multiple sealing ring structure 218 extends into the substrate layer 236 of the device layer 232 of the semiconductor element 202. For example, the multiple sealing ring structure 218 may further include one or more isolation regions 240 and / or one or more doped regions 246 in the substrate layer 236, such that the additional isolation regions 240 and doped regions 246 are perpendicularly adjacent to the conductive structure layer of the multiple sealing ring structure 218 in the front interconnect layer 234. This extends the electrical isolation provided by the multiple sealing ring structure 218 into the device layer 232.

[0054] At the top of the multiple sealing ring structure 218, sealing ring structure 218a and sealing ring structure 218b may each include a top through-hole 248 and a top pad 250. The top through-hole 248 and the top pad 250 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, as well as other examples of conductive materials.

[0055] Lateral regions 206 and 208 may include different conductive structure arrangements for segments of sealing ring structures 218a and / or sealing ring structures 218b, which are formed in lateral regions 206 and 208 using different sets of shields 108. For example, a first set of shields 108 may be used to form a layer of inner interconnect structure 220a, outer interconnect structure 220b, and a plurality of columnar interconnect structures 222 having a first size, a first shape, a first spacing, and / or a first arrangement in a segment of sealing ring structure 218a in lateral region 206. A second set of shields 108 may be used to form a layer of inner interconnect structure 220a, outer interconnect structure 220b, and a plurality of columnar interconnect structures 222 in a segment of sealing ring structure 218a in lateral region 208, which have a second size different from the first size, a second shape different from the first shape, a second spacing different from the first spacing, and / or a second arrangement different from the first arrangement.

[0056] As another embodiment, the first set of masks 108 can be used to form a metallized structure 224 in a segment of the sealing ring structure 218a in the transverse region 206, having a first width, a first thickness, and / or a first shape. The second set of masks 108 can be used to form a metallized structure layer 224 in a segment of the sealing ring structure 218a in the transverse region 208, the metallized structure layer having a second width different from the first width, a second thickness different from the first thickness, and / or a second shape different from the first shape.

[0057] As another embodiment, the first set of masks 108 can be used to form a layer of multiple inner pillar interconnect structures 226 and outer line interconnect structures 228 having a first size, a first shape, a first spacing and / or a first arrangement in a segment of the sealing ring structure 218b in the lateral region 206. The second set of masks 108 can be used to form a layer of multiple inner pillar interconnect structures 226 and outer line interconnect structures 228 having a second size different from the first size, a second shape different from the first shape, a second spacing different from the first spacing and / or a second arrangement different from the first arrangement.

[0058] As another embodiment, the first set of masks 108 can be used to form a metallized structure 230 in a segment of the sealing ring structure 218b in the transverse region 206, having a first width, a first thickness, and / or a first shape. The second set of masks 108 can be used to form a metallized structure 230 layer in a segment of the sealing ring structure 218b in the transverse region 208, the segment having a second width different from the first width, a second thickness different from the first thickness, and / or a second shape different from the first shape.

[0059] As described above, Figures 2A and 2B are provided as examples. Other examples may differ from those described in Figures 2A and 2B.

[0060] Figures 3A through 3L are diagrams illustrating an exemplary embodiment 300 of the semiconductor device 202 described herein. Exemplary embodiment 300 includes the use of a multiple mask exposure technique to form different layouts in different lateral regions 206 and lateral regions 208 on the front side of the semiconductor device 202 using different sets of masks 108. In some embodiments, one or more semiconductor process tools (e.g., deposition tools, exposure tools (e.g., lithography system 100), development tools, etching tools, ion implantation tools, bonding tools, planarization tools, and / or other types of semiconductor process tools) may be used to perform one or more operations described in conjunction with Figures 3A through 3L.

[0061] As shown in Figure 3A, semiconductor element 202 may be fabricated on semiconductor wafer 110 together with a plurality of other semiconductor elements 202. The operations and / or techniques described in conjunction with Figures 3A to 3L may be performed and / or used at the wafer layer, which means that the operations and / or techniques described in conjunction with Figures 3A to 3L may be performed and / or used to fabricate a plurality of semiconductor elements 202 formed on the same semiconductor wafer 110.

[0062] As shown in Figure 3B, the substrate layer 236 of the device layer 232 of the semiconductor element 202 may correspond to the portion of the semiconductor wafer 110 on which the semiconductor element 202 is fabricated.

[0063] As shown in Figures 3C to 3G, multiple masking exposure techniques can be used to pattern and form different integrated circuit layouts in the lateral regions 206 and 208 on the front side of the device layer 232 of the semiconductor device 202. For example, as shown in Figures 3C and 3D, a set of masks 108a can be used to pattern the front side of the device layer 232 in the lateral region 206 to form an integrated circuit element 238, isolation region 240, and / or doped region 246 in the front side of the device layer 232 of the semiconductor device 202 in the lateral region 206. As shown in Figures 3E and 3F, a set of masks 108b can be used to pattern the front side of the device layer 232 in the lateral region 208 to form an integrated circuit element 238, isolation region 240, and / or doped region 246 in the front side of the device layer 232 of the semiconductor device 202 in the lateral region 208.

[0064] In some embodiments, a deposition tool can be used to form a photoresist layer on the substrate layer 236 in the lateral regions 206 and lateral regions 208. The use of masks 108a and 108b can be continuous. For example, a semiconductor wafer 110 can be placed on the wafer platform 136 of the lithography system 100, as shown in Figure 3C. The first mask 108a can be loaded into the mask platform 140 of the lithography system 100, and the first mask 108a can be used to perform a first exposure operation to pattern the front side of the substrate layer 236 in the lateral region 206, thereby forming a groove arrangement for the isolation region 240 in the lateral region 206. The first mask 108a can be removed from the mask platform 140 and replaced with a first mask 108b, as shown in Figure 3E. The first mask 108b can be used to perform a second exposure operation (e.g., after the first exposure operation) to pattern the front side of the substrate layer 236 in the lateral region 208, thereby forming a groove arrangement for the isolation region 240 in the lateral region 208. In some embodiments, a developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern in the lateral regions 206 and 208. An etching tool can be used to etch the substrate layer 236 according to the pattern to form the grooves in the lateral regions 206 and 208. In some embodiments, the etching operation includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or other types of etching. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer in the lateral regions 206 and 208 (e.g., using chemical strippers, plasma ashing, and / or other techniques). Dielectric material can be deposited in the grooves of lateral regions 206 and 208 using deposition tools, wherein the deposition techniques include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition techniques to form isolation regions 240. Isolation regions 240 can be planarized using planarization tools.

[0065] As another example, a gate material layer can be deposited over the front side of the substrate layer 236 (e.g., through CVD, ALD, PVD, electroplating). The semiconductor wafer 110 can be placed on the wafer platform 136 of the lithography system 100, and the second mask 108a can be loaded into the mask platform 140 of the lithography system 100, as shown in Figure 3C. The second mask 108a can be used to perform a third exposure operation (e.g., after the second exposure operation) to pattern the gate material layer over the substrate layer 236 in the lateral region 206 to form a gate structure arrangement of integrated circuit elements 238 in the lateral region 206. The second mask 108a can be removed from the mask platform 140 and replaced with a second mask 108b, as shown in Figure 3E. The second mask 108b can be used to perform a fourth exposure operation (e.g., after the third exposure operation) to pattern the gate material layer on the substrate layer 236 in the lateral region 208 to form an arrangement of gate structures of integrated circuit elements 238 in the lateral region 208.

[0066] As another example, a photoresist layer can be deposited on the front side of substrate layer 236. Semiconductor wafer 110 can be placed on wafer platform 136 of photolithography system 100, and third mask 108a can be loaded into mask platform 140 of photolithography system 100, as shown in Figure 3C. Third mask 108a can be used to perform a fifth exposure operation (e.g., after a fourth exposure operation) to pattern the photoresist layer over substrate layer 236 in lateral region 206, thereby forming an injection mask in lateral region 206. Third mask 108a can be removed from mask platform 140 and replaced with third mask 108b, as shown in Figure 3E. Third mask 108b can be used to perform a sixth exposure operation (e.g., after a fifth exposure operation) to pattern the photoresist layer over substrate layer 236 in lateral region 208, thereby forming an injection mask in lateral region 208. The implantation masks in lateral regions 206 and 208 can be used to form source / drain regions of integrated circuit elements 238 and / or doped regions 246 of sealing ring structures 218a and / or sealing ring structures 218b on the front side of substrate layer 236 (e.g., through ion implantation).

[0067] As shown in Figures 3H to 3L, multiple masking exposure techniques can be used to pattern and form different metallization layouts in the lateral regions 206 and 208 above the device layer 232 of the semiconductor element 202. For example, as shown in Figures 3H and 3L, a set of masks 108a can be used to pattern the front side of the semiconductor element 202 in the lateral region 206 to form a first arrangement of conductive structures 244, and to form a first arrangement of sealing ring structures 218a and 218b of multiple sealing ring structures 218 in the front interconnect layer 234 of the semiconductor element 202 in the lateral region 206. As shown in Figures 3J and 3K, a set of masks 108b can be used to pattern the front side of the semiconductor element 202 in the lateral region 208 to form a second arrangement of conductive structure 244, and to form a second arrangement of sealing ring structure 218a and sealing ring structure 218b of multiple sealing ring structure 218 in the interconnect layer 234 on the front side of the semiconductor element 202 in the lateral region 208.

[0068] Masks 108a and 108b can be used consecutively to form the lateral regions 206 and 208 of the front interconnect layer 234. For example, the dielectric layer 242 of the front interconnect layer 234 can be deposited above the front side of the device layer 232 of the semiconductor device 202. The semiconductor wafer 110 can be placed on the wafer platform 136 of the lithography system 100, the fourth mask 108a can be loaded into the mask platform 140 of the lithography system 100, and the fourth mask 108a can be used to perform a seventh exposure operation (e.g., after the sixth exposure operation) to pattern the dielectric layer 242 in the lateral region 206. The fourth mask 108a can be removed from the mask platform 140 and replaced by the fourth mask 108b in the lithography system 100, and the fourth mask 108b can be used to perform an eighth exposure operation (e.g., after the seventh exposure operation) to pattern the dielectric layer 242 in the lateral region 208.

[0069] Patterning the dielectric layer 242 in the lateral regions 206 and 208 by performing the seventh and eighth exposure operations may include patterning a photoresist layer or other type of patterned layer, and then etching the dielectric layer 242 based on the pattern formed in the lateral regions 206 and 208 of the photoresist layer (e.g., using an etching tool) to form grooves in the dielectric layer 242. A metal material layer may be deposited in the corresponding patterns of the lateral regions 206 and 208 to form different arrangements in the conductive structures 244 in the lateral regions 206 and 208. Furthermore, a metal material layer may be deposited in the corresponding patterns of the lateral regions 206 and 208 to form different arrangements of the first layer interconnect structure in the sealing ring structures 218a and 218b in the lateral regions 206 and 208. Different arrangements in the first interconnect structure may include different arrangements of the inner interconnect structure 220a, different arrangements of the outer interconnect structure 220b, different arrangements of the column interconnect structure 222, different arrangements of the inner column interconnect structure 226, and / or different arrangements of the outer interconnect structure 228. Subsequent masks 108a and 108b may be used in a similar order for patterning the conductive structure 244, additional layers of the inner interconnect structure 220a, additional layers of the outer interconnect structure 220b, additional layers of the column interconnect structure 222, additional layers of the metallized structure 224, additional layers of the inner column interconnect structure 226, additional layers of the outer interconnect structure 228, additional layers of the metallized structure 230, additional layers of the top via 248, and / or additional layers of the top pad 250, etc.

[0070] As described above, Figures 3A to 3L are provided as examples. Other examples may differ from those described in Figures 3A to 3L.

[0071] Figures 4A and 4B are figures of an exemplary embodiment 400 of the semiconductor element 202 described herein. Figure 4A shows a top view of the semiconductor element 202, and Figure 4B shows a cross-sectional view of the semiconductor element 202 along line B-B' in Figure 4A. As shown in Figures 4A and 4B, the exemplary embodiment 400 of the semiconductor element 202 is similar to the exemplary embodiment 200 of the semiconductor element 202 shown in Figures 2A and 2B. However, the exemplary embodiment 400 of the semiconductor element 202 also includes one or more interconnect structures 402 through the substrate.

[0072] As shown in Figure 4A, the lateral regions 206 and 208 may include different arrangements of interconnect structures 402 through the substrate formed using different sets of masks 108, and one or more interconnect structures 402 through the substrate may be included in one or more functional regions 210, 212, 214 and 216 of the semiconductor element 202.

[0073] As shown in Figure 4B, the through-substrate interconnect structure 402 may extend through the substrate layer 236 of the semiconductor element 202 and may electrically connect to the front interconnect layer 234 of the semiconductor element 202. The through-substrate interconnect structure 402 may include through-silicon vias (TSVs), metal pillars, metal tubes, and / or other types of vertical (e.g., in the z-direction) elongated conductive structures. The through-substrate interconnect structure 402 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), aluminum copper (AlCu), one or more metals, one or more conductive ceramics, alloys thereof, and / or other types of conductive materials.

[0074] As further shown in Figure 4B, the exemplary embodiment 400 of the semiconductor element 202 may further include a back-side interconnect layer 404 located on the back side of the device layer 232 of the semiconductor element 202. The front-side interconnect layer 234 may be located on a first side (e.g., the front side) of the device layer 232, and the back-side interconnect layer 404 may be located on a second side (e.g., the back side) of the device layer 232 that is perpendicular to the first side. Therefore, the front-side interconnect layer 234, the device layer 232, and the back-side interconnect layer 404 may be arranged perpendicularly along the z-direction in the semiconductor element 202.

[0075] The through-substrate interconnect structure 402 extends through the substrate layer 236 and into the front interconnect layer 234 and the back interconnect layer 404. This enables the provision of signals and / or power between the front and back sides of the semiconductor element 202 through the through-substrate interconnect structure 402.

[0076] Material penetrating the substrate interconnect structure 402 may readily diffuse into the surrounding substrate layer 236. Therefore, isolation region 240 and one or more pads 406, pads 408 may be included between the penetrating substrate interconnect structure 402 and the substrate layer 236 to provide a diffusion barrier and / or promote adhesion between the penetrating substrate interconnect structure 402 and the substrate layer 236, etc. Furthermore, in some embodiments, an additional barrier layer is deposited on one or more pads 406, pads 408 to further and more effectively suppress metal diffusion from the penetrating substrate interconnect structure 402. One or more pads 406, pads 408 may include high-k dielectric pads, low-k dielectric pads, and / or other types of pads.

[0077] The high-k dielectric pad may include one or more high-k dielectric materials, such as silicon nitride (SixNy, e.g., Si3N4), aluminum oxide (AlxOy, e.g., Al2O3), tantalum oxide (TaxOy, e.g., Ta2O5), titanium oxide (TiOx, e.g., TiO2), zirconium oxide (ZrOx), strontium titanium oxide (SrTiOx, e.g., SrTiO3), hafnium silicon oxide (HfSiOx, e.g., HfSiO4), lanthanum oxide (LaxOy, e.g., La2O3), yttrium oxide (YxOy, e.g., Y2O3) and / or amorphous aluminum lanthanum oxide (a-LaAlOx, e.g., a-LaAlO3), etc. The low-k dielectric pad may include one or more low-k dielectric materials, such as silicon oxide (SiOx), undoped silicate glass (USG), borosilicate glass (BSG), and / or fluorinated silicate glass (FSG). If a barrier layer is included, the barrier layer may include a diffusion barrier material, such as tantalum (Ta) and / or tantalum nitride (TaN).

[0078] As further shown in Figure 4B, the back-side interconnect layer 404 may include one or more dielectric layers 410, which may be arranged in a direction approximately perpendicular to the substrate layer 236 (e.g., the z-direction). The dielectric layers 410 may include back-end dielectric layers (e.g., ILD layers, IMD layers) and ESLs arranged alternately in the back-side interconnect layer 404. Each dielectric layer 410 may include oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), undoped silicate glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), ELK dielectric materials with a dielectric constant less than about 2.5, silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials.

[0079] The back-side interconnect layer 404 may also include one or more conductive structures 412 (e.g., electrically conductive structures) in the dielectric layer 410. The conductive structures 412 may be electrically coupled and / or physically coupled to one or more through-substrate interconnect structures 402 extending through the device layer 232 between the front-side interconnect layer 234 and the back-side interconnect layer 404.

[0080] Lateral regions 206 and 208 may include conductive structures 412 arranged in different configurations using different sets of masks 108. The conductive structures 412 in lateral region 206 may be arranged to distribute signals and / or power to integrated circuits in functional regions 210, 212, and 216. Similarly, the conductive structures 412 in lateral region 208 may be arranged to distribute signals and / or power to integrated circuits in functional regions 212, 214, and 216. In some embodiments, the conductive structures 412 in lateral regions 206 and / or lateral region 208 may be arranged to distribute signals and / or power between two or more functional regions 210, 212, 214, and 216.

[0081] In this way, when manufacturing the semiconductor device 202, multiple mask exposure technology can be used for both the front-side and back-side processes. The front-side process of the semiconductor device 202 may include forming different circuit layouts in and / or above the device layer 232 (including the front interconnect layer 234) in the lateral region 206 and the lateral region 208 using different sets of masks 108. The back-side process of the semiconductor device 202 may include forming different circuit layouts in and / or above the device layer 232 (including the back interconnect layer 404 and the through-substrate interconnect structure 402) in the lateral region 206 and the lateral region 208 using different sets of masks 108. Therefore, the lateral region 206 may include a front-side region (or a front-side portion) and a back-side region (or a back-side portion), while the lateral region 208 may include a front-side region (or a front-side portion) and a back-side region (or a back-side portion).

[0082] As further shown in Figure 4B, one or more passivation layers 414 may be included on the back-side interconnect layer 404 above the dielectric layer 410. The passivation layer 414 may include silicon nitride (SixNy), tantalum nitride (TaN), silicon oxide (SiOx), and / or other suitable passivation materials. The passivation layer 414 may be used to passivate the back side of the semiconductor element 202 and / or pattern the back side of the semiconductor element 202 to form connection pads 416 and connection structures 418 on the back side of the semiconductor element 202. One or more conductive structures 412 in the back-side interconnect layer 404 may also be coupled to the connection pads 416 and connection structures 418. The connection pads 416 may include copper (Cu) pads, aluminum (Al) pads, aluminum-copper (AlCu) pads, and / or other types of metal pads providing surfaces on which the connection structures 418 may be formed. The connection structure 418 enables the semiconductor element 202 to be attached to a substrate (e.g., an interposer, a printed circuit board (PCB)), another semiconductor package, and / or to another structure. The connection structure 418 may include pads, solder balls, microbumps, and / or other types of connection structures.

[0083] As further shown in Figure 4B, the sealing ring structure 218a and / or sealing ring structure 218b may further include a through-substrate isolation structure 420 extending through the substrate layer 236 of the semiconductor element 202. The through-substrate isolation structure 420 of the sealing ring structure 218a may also be coupled to the metallization structure 224 of the sealing ring structure 218a in the front interconnect layer 234, and may be coupled to one or more conductive structures 412 in the back interconnect layer 404. One or more conductive structures 412 in the back interconnect layer 404 may also be coupled to the connection pad 416 and the connection structure 418, thereby allowing the sealing ring structure 218a to extend through the back interconnect layer 404.

[0084] Similarly, the through-substrate isolation structure 420 of the sealing ring structure 218b can also be coupled to the metallization structure 230 of the sealing ring structure 218b in the front interconnect layer 234, and can be coupled to one or more conductive structures 412 in the back interconnect layer 404. One or more conductive structures 412 in the back interconnect layer 404 can also be coupled to the connection pad 416 and the connection structure 418, so that the sealing ring structure 218b extends through the back interconnect layer 404.

[0085] In some embodiments, the sealing ring structure 218a includes a plurality of through-substrate isolation structures 420 arranged around the periphery of the semiconductor element 202 in a top view. A subset of the through-substrate isolation structures 420 may be located in the lateral region 206 and patterned using a first set of masks 108, and another subset of the through-substrate isolation structures 420 may be located in the lateral region 208 and patterned using a second set of masks 108. Similarly, the sealing ring structure 218b may include a plurality of through-substrate isolation structures 420 arranged around the periphery of the semiconductor element 202 in a top view. A subset of the through-substrate isolation structures 420 may be located in the lateral region 206 and patterned using a first set of masks 108, and another subset of the through-substrate isolation structures 420 may be located in the lateral region 208 and patterned using a second set of masks 108.

[0086] The through-substrate isolation structure 420 can block or suppress electrical effects (e.g., radio frequency interference, electromagnetic interference (EMI), current leakage) from entering and / or exiting portions of the substrate layer 236 in the device layer 232. In this way, the through-substrate isolation structure 420 protects the integrated circuit elements 238 in the device layer 232 from external electrical effects and / or the electrical effects of the semiconductor element 202. Furthermore, the through-substrate isolation structure 420 can block or suppress moisture, vibration, and / or other contaminants from entering the device layer 232 through the substrate layer 236, thereby protecting the integrated circuit elements 238 in the device layer 232 from such moisture, vibration, and / or other contaminants.

[0087] The through-substrate isolation structure 420 may include a TSV, a metal pillar, a metal tube, a through-substrate trench, and / or other types of conductive structures extending through the substrate layer 236. Figure 4B illustrates an exemplary embodiment in which the through-substrate isolation structure 420 has tapered sidewalls and is formed through a TSV process. In some embodiments, the through-substrate isolation structure 420 may have approximately vertical sidewalls and be formed through a back-side passivation (BPASS) process. In Figure 4B, the through-substrate isolation structure 420 may extend through the isolation region 240 included in the substrate layer 236. Alternatively, the isolation region 240 may be omitted, and the through-substrate isolation structure 420 may extend completely through the substrate layer 236.

[0088] The through-substrate isolation structure 420 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), aluminum copper (AlCu), one or more metals, one or more conductive ceramics, alloys thereof, and / or another type of conductive material. In some embodiments, one or more pads 406 and pads 408 may be included on the sidewalls of the through-substrate isolation structure 420.

[0089] As described above, Figures 4A and 4B are provided as examples. Other examples may differ from those described in Figures 4A and 4B.

[0090] Figures 5A through 5K are diagrams forming an exemplary embodiment 500 of the stacked semiconductor device described herein. Exemplary embodiment 500 includes using a similar multiple mask exposure technique as associated with Figures 3A through 3L to form different layouts on the front and back sides of the semiconductor device 202 using different sets of masks 108. In some embodiments, one or more semiconductor process tools (e.g., deposition tools, exposure tools (e.g., lithography system 100), development tools, etching tools, ion implantation tools, bonding tools, planarization tools, and / or other types of semiconductor process tools) may be used to perform one or more operations associated with Figures 5A through 5K.

[0091] As shown in Figure 5A, the semiconductor element 202 can be flipped (e.g., after the operations described in conjunction with Figures 3A to 3L) to allow back-side processing to be performed on the back side of the device layer 232 of the semiconductor element 202. The semiconductor wafer 110 on which the semiconductor element 202 is fabricated can be bonded to the carrier substrate 502 to protect the front side of the semiconductor element 202 formed on the semiconductor wafer 110. The semiconductor wafer 110 can be bonded to the carrier substrate 502 using one or more bonding dielectric layers 504 to form face-to-face dielectric bonds between the bonding dielectric layer 504 and the dielectric region 242.

[0092] As shown in Figures 5B to 5F, a multi-mask exposure technique can be used to pattern the sealing ring structures 218a and / or 218b in the lateral regions 206 and 208 from the back side of the device layer 232 of the semiconductor device 202, forming through-substrate interconnect structures 402 and / or through-substrate isolation structures 420 with different arrangements. For example, as shown in Figures 5B and 5C, a set of masks 108a can be used to pattern the back side of the device layer 232 in the lateral region 206 to form the arrangement of through-substrate interconnect structures 402 and through-substrate isolation structures 420 for the segments of the sealing ring structures 218a and 218b in the lateral region 206 of the semiconductor device 202. As shown in Figures 5D and 5E, a set of masks 108b can be used to pattern the back side of the device layer 232 in the lateral region 208 to form an arrangement of through-substrate interconnect structures 402 and through-substrate isolation structures 420 for the segments of sealing ring structures 218a and 218b in the lateral region 208.

[0093] Masks 108a and 108b can be used consecutively to form arrangements of through-substrate interconnect structures 402 and through-substrate isolation structures 420 in lateral regions 206 and 208, starting from the back side of device layer 232. For example, one or more patterned layers can be deposited on the back side of device layer 232 of semiconductor element 202. Semiconductor wafer 110 can be placed on wafer platform 136 of lithography system 100, first mask 108a can be loaded into mask platform 140 of lithography system 100, and first mask 108a can be used to perform a first exposure operation to form a pattern in a pattern in lateral region 206. First mask 108a can be removed from mask platform 140 and replaced with first mask 108b in lithography system 100, and first mask 108b can be used to perform a second exposure operation (e.g., after the first exposure operation) to form a pattern in one or more patterned layers in lateral region 208. An etching tool can be used to etch the substrate layer 236 in the lateral regions 206 and 208 according to the corresponding pattern formed in the pattern layer in the lateral regions 206 and 208, so as to form a groove extending through the substrate layer 236 and into the front interconnect layer 234.

[0094] Pads 406 and 408 may be formed on the sidewalls of the groove, and the groove may be filled with conductive material (e.g., by CVD, PVD, ALD and / or by electroplating using a deposition tool) to form a through-substrate interconnect structure 402 and a through-substrate isolation structure 420 in the groove.

[0095] As shown in Figures 5G to 5K, multiple masking exposure techniques can be used to pattern and form different metallization layouts in the lateral regions 206 and 208 above the back side of the device layer 232 of the semiconductor device 202. For example, as shown in Figures 5G and 5H, a set of masks 108a can be used to pattern the back-side interconnect layer 404 in the lateral region 206 to form a configuration of conductive structures 412, connection pads 416, and connection structures 418 in the back-side interconnect layer 404 of the semiconductor device 202 in the lateral region 206. As shown in Figures 5I and 5J, a set of masks 108b can be used to pattern the back-side interconnect layer 404 in the lateral region 208 to form a configuration of conductive structures 412, connection pads 416, and connection structures 418 in the back-side interconnect layer 404 of the semiconductor device 202 in the lateral region 208.

[0096] Masks 108a and 108b can be used consecutively to form lateral regions 206 and 208 of the back-side interconnect layer 404. For example, the dielectric layer 410 of the back-side interconnect layer 404 can be deposited over the back side of the device layer 232 of the semiconductor device 202. The semiconductor wafer 110 can be placed on the wafer platform 136 of the lithography system 100, the second mask 108a can be loaded into the mask platform 140 of the lithography system 100, and the second mask 108a can be used to perform a third exposure operation (e.g., after the second exposure operation) to pattern the first dielectric layer 410 in the lateral region 206. The second mask 108a can be removed from the mask platform 140 and replaced with the second mask 108b in the lithography system 100, and the second mask 108b can be used to perform a fourth exposure operation (e.g., after the third exposure operation) to pattern the first dielectric layer in the lateral region 208.

[0097] Patterning the first dielectric layer 410 in lateral regions 206 and 208 may include: patterning a photoresist layer or other type of patterned layer by performing a third exposure operation and a fourth exposure operation, and then etching the first dielectric layer 410 (e.g., using an etching tool) based on the pattern formed in lateral regions 206 and 208 in the photoresist layer to form grooves in the first dielectric layer 410. A layer of metal material may be deposited in the grooves of lateral regions 206 and 208 to form different arrangements in the conductive structures 412 in lateral regions 206 and 208. Subsequent masks 108a and 108b may be used in a similar order to pattern additional layers of the conductive structures 412 in the back-side interconnect layer 404.

[0098] As described above, Figures 5A to 5K are provided as examples. Other examples may differ from those described in Figures 5A to 5K.

[0099] Figures 6A and 6B are diagrams of the exemplary stacked semiconductor device 600 described herein. Figure 6A shows a top view of the stacked semiconductor device 600, and Figure 6B shows a cross-sectional view of the stacked semiconductor device 600 along line C-C' in Figure 6A.

[0100] As shown in Figure 6A, the stacked semiconductor device 600 includes a plurality of semiconductor devices 202, such as semiconductor device 202a and semiconductor device 202b. Semiconductor devices 202a and 202b can be stacked and arranged vertically along the z-direction. The stacked semiconductor device 600 may include lateral regions 206 and lateral regions 208, which may include corresponding lateral portions of semiconductor device 202a and corresponding lateral portions of semiconductor device 202b. Therefore, lateral region 206 of the stacked semiconductor device 600 may include a first portion of semiconductor device 202a stacked together with a first portion of semiconductor device 202b, and lateral region 208 of the stacked semiconductor device 600 may include a second portion of semiconductor device 202a stacked together with a second portion of semiconductor device 202b. Functional regions 210, 212, 214, and 216 of the stacked semiconductor device 600 may be distributed on semiconductor devices 202a and 202b.

[0101] As shown in Figure 6B, semiconductor elements 202a and 202b can be directly bonded together at the bonding interface 602. Semiconductor element 202a may include a layer and / or structural arrangement similar to that shown in Figure 4B. Specifically, the integrated circuit elements 238 in the device layer 232 through the substrate isolation structure 420 are protected from external electrical effects and / or electrical effects from semiconductor element 202b, and / or the integrated circuit elements 610 in the device layer 604 are protected from external electrical effects and / or electrical effects from semiconductor element 202a. Semiconductor element 202b may include device layer 604 and an interconnect layer 606 located above device layer 604. Semiconductor elements 202a and 202b may be bonded together such that the front interconnect layer 234 and interconnect layer 606 face each other. Alternatively, semiconductor elements 202a and 202b may be combined such that the back interconnect layer 404 and interconnect layer 606 face each other.

[0102] Device layer 604 may include a substrate layer (e.g., similar to substrate layer 236), an isolation region 608 (e.g., similar to isolation region 240), and integrated circuit elements 610 (e.g., similar to integrated circuit element 238) located in and / or on the substrate layer. Interconnect layer 606 may include one or more dielectric layers 612 (e.g., similar to dielectric layer 242) and one or more conductive structure layers 614 (e.g., similar to conductive structure 244) in the dielectric layers 612.

[0103] The multiple sealing ring structure 218 may extend through the interconnect layer 606. A portion of the sealing ring structure 218a in the semiconductor device 202b may include an arrangement layer similar to the sealing ring structure 218a in the semiconductor device 202a, comprising an inner interconnect structure 220a, an outer interconnect structure 220b, a pillar interconnect structure 222, a metallization structure 224, a doped region 246, a top via 248, and a pad 250. A portion of the sealing ring structure 218b in the semiconductor device 202b may include a similar layer arrangement to the inner pillar interconnect structure 226, an outer interconnect structure 228, a metallization structure 230, a doped region 246, a top via 248, and a top pad 250 as a portion of the sealing ring structure 218b in the semiconductor device 202a.

[0104] The interconnect layer 606 may also include a plurality of bonding pads 616. The bonding pads 616 may be electrically coupled to the conductive structures 614 in the interconnect layer 606 through bonding vias 618 and / or other types of conductive structures. The bonding pads 616 and bonding vias 618 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, as well as examples of other conductive metals. In some embodiments, one or more bonding pads 616 are each coupled to a single bonding via 618. In some embodiments, one or more bonding pads 616 are each coupled to two or more bonding vias 618.

[0105] At the bonding interface 602, the bonding pad 616 of the semiconductor device 202b can be directly bonded to the bonding pad 620 in the front interconnect layer 234 of the semiconductor device 202a via metal-to-metal bonding. Furthermore, the dielectric layer 612 of the interconnect layer 606 of the semiconductor device 202b can be directly bonded to the dielectric layer 242 of the front interconnect layer 234 of the semiconductor device 202a via dielectric-to-dielectric bonding.

[0106] The bonding pads 620 of the semiconductor device 202a can be electrically coupled to the conductive structure 244 of the front interconnect layer 234 through the bonding vias 622. The bonding pads 620 and the bonding vias 622 may respectively include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, as well as examples of other conductive metals.

[0107] As described above, Figures 6A and 6B are provided as examples. Other examples may differ from those described in Figures 6A and 6B.

[0108] Figures 7A through 7P are diagrams of an exemplary embodiment 700 forming the stacked semiconductor device described herein. Exemplary embodiment 700 includes using a similar multiple mask exposure technique as associated with Figures 3A through 3L and / or Figures 5A through 5K, forming different layouts on the front side of semiconductor device 202a and semiconductor device 202b and on the back side of semiconductor device 202a using different sets of masks 108. In some embodiments, one or more semiconductor process tools (e.g., deposition tools, exposure tools (e.g., lithography system 100), development tools, etching tools, ion implantation tools, bonding tools, planarization tools, and / or other types of semiconductor process tools) may be used to perform one or more operations associated with Figures 7A through 7P.

[0109] As shown in Figure 7A, semiconductor element 202a and semiconductor element 202b can be fabricated on different semiconductor wafers 110. For example, semiconductor element 202a can be fabricated on semiconductor wafer 110a, while semiconductor element 202b can be fabricated on semiconductor wafer 110b. This enables the use of multiple masking exposure technology to pattern the lateral regions 206 and 208 on semiconductor element 202a and semiconductor element 202b, respectively. Specifically, this enables the use of multiple masking exposure technology to pattern the lateral regions 206a and 208a separately on semiconductor element 202a, and enables the use of multiple masking exposure technology to pattern the lateral regions 206b and 208b separately on semiconductor element 202b.

[0110] As shown in Figures 7B to 7L, multiple masking exposure techniques can be used to form patterns and / or structures on the front side of semiconductor device 202a and semiconductor device 202b, respectively formed on semiconductor wafers 110a and 110b. The front-side processes of semiconductor device 202a and semiconductor device 202b may include a set of similar operations, including the use of multiple masking exposure techniques, as shown and described in conjunction with Figures 3A to 3L and / or Figures 5A to 5K.

[0111] As shown in Figures 7B and 7C, a set of masks 108a can be used to pattern the lateral region 206a of the semiconductor element 202a on the semiconductor wafer 110a to form a circuit layout on the front side (e.g., front region) of the lateral region 206a inside and / or above the device layer 232 of the semiconductor element 202a. This may include forming integrated circuit elements 238 on the front side and / or inside the device layer 232 in the lateral region 206a, forming an isolation region 240 on the front side and / or inside the device layer 232, forming a conductive structure layer 244 in a front interconnect layer 234 above the device layer 232 of the semiconductor element 202a, and / or forming a layer of sealing ring structures 218a and sealing ring structures 218b of a plurality of sealing ring structures 218 in the front interconnect layer 234 above the device layer 232 of the semiconductor element 202a, etc.

[0112] As shown in Figures 7D and 7E, a set of masks 108b can be used to pattern the lateral region 208a of the semiconductor element 202a on the semiconductor wafer 110a to form a circuit layout on the front side (e.g., the front region) of the lateral region 208a within and / or above the device layer 232 of the semiconductor element 202a. This may include forming integrated circuit elements 238 on the front side and / or the front side of the device layer 232 in the lateral region 208a, forming an isolation region 240 in and / or on the front side of the device layer 232, forming a conductive structure layer 244 in a front interconnect layer 234 above the device layer 232 of the semiconductor element 202a, and / or forming a layer of sealing ring structures 218a and sealing ring structures 218b of a plurality of sealing ring structures 218 in the front interconnect layer 234 above the device layer 232 of the semiconductor element 202a, and so on.

[0113] The use of masks 108a and 108b can be sequential. For example, a semiconductor wafer 110a can be placed on a wafer platform 136 of a photolithography system 100, and a first mask 108a can be loaded into a mask platform 140 of the photolithography system 100. The first mask 108a can be used to perform a first exposure operation to pattern the front side of the device layer 232 in the lateral region 206a, thereby forming an arrangement of integrated circuit elements 238 in the lateral region 206a. The first mask 108a can be removed from the mask platform 140 and replaced with a first mask 108b, and the first mask 108b can be used to perform a second exposure operation (e.g., after the first exposure operation) to pattern the front side of the device layer 232 in the lateral region 208a to form an arrangement of integrated circuit elements 238 in the lateral region 208a. The subsequent masks 108a and 108b can be used to form patterns and / or structures in the lateral regions 206a and 208a of the device layer 232 of the semiconductor element 202a, respectively.

[0114] As another example, the dielectric layer 242 of the front interconnect layer 234 can be deposited above the front side of the device layer 232 of the semiconductor device 202a. The semiconductor wafer 110a can be placed on the wafer platform 136 of the lithography system 100, and the second mask 108a can be loaded into the mask platform 140 of the lithography system 100. The second mask 108a can be used for a third exposure operation (e.g., after the second exposure operation) to pattern the dielectric layer 242 in the lateral region 206a. The second mask 108a can be removed from the mask platform 140 and replaced by a second mask 108b in the lithography system 100. The second mask 108b can be used for a fourth exposure operation (e.g., after the third exposure operation) to pattern the dielectric layer 242 in the lateral region 208a.

[0115] As shown in Figures 7F and 7G, a set of masks 108c can be used to pattern the lateral regions 206b of the semiconductor element 202b on the semiconductor wafer 110b to form a circuit layout on the front side (e.g., the front region) of the lateral regions 206b within and / or above the device layer 604 of the semiconductor element 202b. This may include forming integrated circuit elements 610 in and / or on the front side of the device layer 604 in the lateral regions 206b, forming conductive structure layers 614 in interconnect layers 606 above the device layer 604 of the semiconductor element 202b, and / or forming layers of sealing ring structures 218a and 218b of a plurality of sealing ring structures 218 in interconnect layers 606 above the device layer 604 of the semiconductor element 202b, etc.

[0116] As shown in Figures 7H and 7I, a set of masks 108d can be used to pattern the lateral regions 208b of the semiconductor element 202b on the semiconductor wafer 110b to form a circuit layout on the front side (e.g., the front region) of the lateral regions 208b within and / or above the device layer 604 of the semiconductor element 202b. This may include forming integrated circuit elements 610 in and / or on the front side of the device layer 604 in the lateral regions 208b, forming conductive structure layers 614 in interconnect layers 606 above the device layer 604 of the semiconductor element 202b, and / or forming layers of sealing ring structures 218a and sealing ring structures 218b of a plurality of sealing ring structures 218 in interconnect layers 606 above the device layer 604 of the semiconductor element 202b, etc.

[0117] The use of masks 108c and 108d can be sequential. For example, a semiconductor wafer 110b can be placed on a wafer platform 136 of a photolithography system 100, a first mask 108c can be loaded into a mask platform 140 of the photolithography system 100, and the first mask 108c can be used to perform a first exposure operation to pattern the front side of the device layer 604 in the lateral region 206b, thereby forming an arrangement of integrated circuit elements 610 in the lateral region 206b. The first mask 108c can be removed from the mask platform 140 and replaced with a first mask 108d, and the first mask 108d can be used to perform a second exposure operation (e.g., after the first exposure operation) to pattern the front side of the device layer 604 in the lateral region 208b to form an arrangement of integrated circuit elements 610 in the lateral region 208b. The subsequent masks 108c and 108d can be used to form patterns and / or structures in the lateral regions 206b and 208b of the device layer 604 of the semiconductor element 202b, respectively.

[0118] As another example, the dielectric layer 612 of the interconnect layer 606 may be deposited above the front side of the device layer 604 of the semiconductor device 202b. The semiconductor wafer 110b may be placed on the wafer platform 136 of the lithography system 100, and the second mask 108c may be loaded into the mask platform 140 of the lithography system 100. The second mask 108c may be used to perform a third exposure operation (e.g., after the second exposure operation) to pattern the first dielectric layer 612 in the lateral region 206b. The second mask 108c may be removed from the mask platform 140 and replaced by a second mask 108d in the lithography system 100, and the second mask 108d may be used to perform a fourth exposure operation (e.g., after the third exposure operation) to pattern the first dielectric layer 612 in the lateral region 208b. A layer of metallic material can be deposited in the corresponding patterns of lateral regions 206b and 208b to form different arrangements in the first layer of conductive structure 614 in lateral regions 206b and 208b, and in the first layer of metallization structures 224 and 230 of the sealing ring structures 218a and 218b of the multi-sealing ring structure 218. Subsequent masks 108c and 108d can be used in a similar order for additional layers of patterned conductive structure 614 and additional layers of sealing ring structures 218a and 218b of the multi-sealing ring structure 218.

[0119] As shown in Figures 7J and 7K, after front-side processing of semiconductor elements 202a and 202b, semiconductor elements 202a and 202b can be bonded together at bonding interface 602 to form a plurality of stacked semiconductor elements 600. The bonding between semiconductor elements 202a and 202b can be formed by bonding semiconductor wafers 110a and 110b together (e.g., inter-wafer bonding), bonding bare dies together (inter-die bonding), and / or by bonding bare dies to wafers (e.g., bare die to wafer bonding), and other examples of bonding configurations.

[0120] As shown in Figure 7J, semiconductor wafers 110a and 110b are bonded together to form a wafer stack 702 including the bonded semiconductor wafers 110a and 110b. The wafer stack 702 includes a plurality of stacked semiconductor elements 600, which are formed by bonding semiconductor elements 202a of semiconductor wafer 110a to semiconductor elements 202b of semiconductor wafer 110b.

[0121] As shown in Figure 7K, a bonding operation can be performed using a bonding tool to bond semiconductor elements 202a and 202b, and / or dielectric-to-dielectric bonds between the dielectric layer 242 of semiconductor element 202a and the dielectric layer 612 of semiconductor element 202b, by forming metal-to-metal bonds between the bonding pads 616 of semiconductor element 202b and the bonding pads 620 of semiconductor element 202a.

[0122] As further shown in Figure 7K, semiconductor elements 202a and 202b are bonded in a stacked manner, and the lateral regions 206a and 206b of semiconductor elements 202a and 202b are connected together, and the lateral regions 208a and 208b of semiconductor elements 202a and 202b are connected together. Therefore, the integrated circuits of functional regions 210, 212, and 216 may include combinations of integrated circuit elements 238 and 610 that are electrically connected to semiconductor elements 202a and 202b in the lateral regions 206 (including lateral regions 206a and 206b) of the stacked semiconductor elements 600. The integrated circuits of functional regions 212, 214 and 216 may include combinations of integrated circuit elements 238 and 610 that are electrically connected to semiconductor elements 202a and 202b in the lateral regions 208 (including lateral regions 208a and lateral regions 208b) of the stacked semiconductor elements 600, respectively.

[0123] Furthermore, semiconductor elements 202a and 202b are bonded in a stacked manner, connecting portions of the sealing ring structures 218a formed on semiconductor elements 202a and 202b together, and joining portions of the sealing ring structures 218b formed on semiconductor elements 202a and 202b together. Therefore, the sealing ring structures 218a and 218b of the multiple sealing ring structures 218 extend vertically through semiconductor elements 202a and 202b.

[0124] As shown in Figures 7L and 7P, a back-side process can be performed on the semiconductor device 202a. The back-side process of the semiconductor device 202a may include a set of similar operations, including the use of multiple mask exposure techniques, as shown and described in Figures 5A and 5K. For example, as shown in Figures 7L and 7M, a set of masks 108e can be used to pattern the lateral region 206 of the stacked semiconductor device 600 to form a circuit layout from the back side of the device layer 232 to the front interconnect layer 234, and to form the circuit layout in the back-side interconnect layer 404 (e.g., the back-side region) of the lateral region 206 above the back side of the semiconductor device 202a. As shown in Figures 7N and 7O, different sets of masks 108f can be used to pattern the lateral regions 208 of the stacked semiconductor elements 600 to form a circuit layout from the back side of the device layer 232 to the front interconnect layer 234, and to form a circuit layout in the back interconnect layer 404 (e.g., the back region) of the lateral regions 208 above the back side of the semiconductor elements 202a.

[0125] The use of masks 108e and 108f can be sequential. For example, the dielectric layer 410 of the back-side interconnect layer 404 can be deposited over the back side of the device layer 232 of the semiconductor device 202a. The stacked semiconductor device 600 can be placed on the wafer platform 136 of the lithography system 100, the first mask 108e can be loaded into the mask platform 140 of the lithography system 100, and the first mask 108e can be used to perform a first exposure operation to pattern the first dielectric layer 410 in the lateral region 206. The first mask 108e can be replaced by the first mask 108f of the lithography system 100, and the first mask 108f can be used to perform a second exposure operation to pattern the first dielectric layer 410 in the lateral region 208. A layer of metal material can be deposited in the corresponding patterns of the lateral regions 206 and 208 to form different arrangements in the conductive structures 412 in the lateral regions 206 and 208. Additional conductive structure layers 412 can be patterned using subsequent masks 108e and 108f in a similar order.

[0126] The above-described sequential process can be performed on a wafer layer for multiple stacked semiconductor elements 600 formed by the wafer stack 702. For example, as shown in Figures 7L and 7M, this set of masks 108e can be used to pattern the lateral regions 206 of the stacked semiconductor elements 600 of the wafer stack 702, forming a circuit layout in the back-side interconnect layer 404 (e.g., the back-side region) of the lateral regions 206 of the stacked semiconductor elements 600. As shown in Figures 7N and 7O, different sets of masks 108f can be used to pattern the lateral regions 208 of the stacked semiconductor elements 600 of the wafer stack 702, forming a circuit layout in the back-side interconnect layer 404 (e.g., the back-side region) of the lateral regions 208 of the stacked semiconductor elements 600.

[0127] As shown in Figure 7P, a back-side process can be performed to form one or more through-substrate interconnect structures 402 (and associated pads 406, pads 408) through the substrate layer 236 of the semiconductor element 202a, to form one or more through-substrate isolation structures 420 (and associated pads 406, pads 408) through the substrate layer 236 of the semiconductor element 202a, to form a dielectric layer 410 of the back-side interconnect layer 404, to form a conductive structure 412 of the back-side interconnect layer 404, to form a passivation layer 414, and / or to form a connection pad 416 and a connection structure 418, etc.

[0128] After combining semiconductor element 202a and semiconductor element 202b to form stacked semiconductor element 600, stacked semiconductor element 600 can be cut or diced from wafer stack 702 using a die dicing tool, so that stacked semiconductor element 600 can be further packaged and processed.

[0129] As described above, Figures 7A to 7P are provided as examples. Other examples may differ from those described in Figures 7A to 7P.

[0130] Figure 8 is a diagram of an exemplary embodiment 800 of the mask for the multiple mask exposure technique described herein. Figure 8 illustrates the circuit pattern layouts of masks 108a and 108b for patterning lateral regions 206 and 208 of the semiconductor element 202 described herein, respectively. Specifically, the circuit pattern layouts of masks 108a and 108b are configured such that a plurality of sealing ring structures 218 in the circuit pattern layout, including sealing ring structure 218a and / or the segment of sealing ring structure 218 at interface 204, have different properties than other segments away from interface 204. Interface 204 corresponds to the edge of the circuit pattern layout of masks 108a and 108b for lateral regions 206 and 208. Due to pattern misalignment, pattern density, and / or other factors, a higher defect rate may occur near interface 204. The different properties of the segments of the sealing ring structure 218a and / or sealing ring structure 218b near the interface 204 can reduce the likelihood and / or defect rate of defects occurring at the interface 204 in the semiconductor device 202 formed using the mask 108a and mask 108b.

[0131] As shown in Figure 8, mask 108a may include buffer 802, and mask 108b may include buffer 804. Buffer 802 and buffer 804 may be located at corresponding edges of mask 108a and mask 108b, which may be located on opposite sides of interface 204. Buffer 802 may be used to pattern a portion of lateral region 206 on semiconductor element 202, wherein patterning rules and / or parameters of a first set of masks are selected to reduce and / or minimize the likelihood of defects forming at interface 204. Similarly, buffer 804 may be used to pattern a portion of lateral region 208 of semiconductor element 202, wherein patterning rules and / or parameters of a second set of masks are selected to reduce and / or minimize the likelihood of defects forming at interface 204.

[0132] Buffers 802 and 804 may be referred to as Optical Proximity Correction (OPC) regions for masks 108a and 108b, respectively. In the OPC regions, an OPC design flow is performed to adjust (e.g., correct or optimize) the layout design of masks 108a and 108b, thereby improving lithographic imaging. The purpose of the OPC process is to accurately transfer a specified circuit layout design onto semiconductor device 202. For example, OPC can be used to compensate for image errors caused by diffraction, distortion, process effects, and / or other types of aberrations. OPC can improve the edge placement integrity of the circuit layout design. For example, after processing, the pattern image transferred onto semiconductor device 202 may exhibit irregularities, such as linewidths that are narrower or wider than designed. OPC can compensate for such irregularities by changing (e.g., correcting) or modifying the original circuit layout design to achieve this in the circuit pattern layout of masks 108a and 108b.

[0133] In buffer 802, segment 806a of the mask 108a used for patterning the sealing ring structure 218a may have a lateral width (denoted as dimension D6 in Figure 8) that is substantially perpendicular to the length of segment 806a, and the lateral width of segment 806a may be smaller than the lateral width of another segment 810a of the mask 108a used for patterning the sealing ring structure 218a outside buffer 802 and buffer 804 (denoted as dimension D7 in Figure 8). In buffer 804, segment 806b of the mask 108b used for patterning the sealing ring structure 218a may have a lateral width (denoted as dimension D8 in Figure 8) that is substantially perpendicular to the length of segment 806b, and the lateral width of segment 806b may be smaller than the lateral width of segment 810b of the mask 108b used for patterning the sealing ring structure 218a outside buffer 802 and buffer 804 (denoted as dimension D8 in Figure 8).

[0134] In buffer 802, segment 808a of the mask 108a for patterning the sealing ring structure 218b may have a lateral width (denoted as dimension D9 in Figure 8) that is substantially perpendicular to the length of segment 808a, and the lateral width of segment 808a may be smaller than the lateral width of another segment 812a (denoted as dimension D10 in Figure 8) of the mask 108a for patterning the sealing ring structure 218b outside buffer 802 and buffer 804. In buffer 804, segment 808b of the mask 108b for patterning the sealing ring structure 218b in buffer 804 may have a lateral width (denoted as dimension D11 in Figure 8) that is substantially perpendicular to the length of segment 808b, and the lateral width of segment 808b may be smaller than the lateral width of segment 812b (denoted as dimension D10 in Figure 8) of the mask 108b for patterning the sealing ring structure 218b outside buffer 802 and buffer 804.

[0135] The smaller lateral widths of segments 806a, 806b, 808a, and 808b near interface 204 in buffers 802 and 804 (e.g., in the OPC region) can be implemented as OPCs to compensate for linewidth distortion in sealing ring structures 218a and 218b at the edges of lateral regions 206 and 208. The lateral widths of segments 806a, 806b, 808a, and 808b can be determined by logic operations (LOPs) as part of the OPC process to generate the circuit layout of masks 108a and 108b.

[0136] As shown in Figure 8, buffer 802 may have a lateral width in the x-direction (denoted as dimension D12 in Figure 8), and buffer 804 may have a lateral width in the x-direction (denoted as dimension D13 in Figure 8). The lateral widths of buffer 802 and buffer 804 may each be in the range of approximately 2 micrometers to approximately 10 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0137] As stated above, Figure 8 is provided as an example only. Other examples may differ from those shown in Figure 8.

[0138] Figures 9A and 9B are diagrams of an exemplary embodiment of the semiconductor device 202 described herein. In the embodiment shown in Figures 9A and 9B, the semiconductor device 202 includes a plurality of sealing ring structures 218, wherein sealing ring structures 218a and / or sealing ring structures 218b include segments located at interface 204 that have different properties than other segments farther from interface 204. Interface 204 corresponds to the edge of a pattern implemented by different sets of masks 108 for lateral regions 206 and lateral regions 208. Therefore, a higher defect rate may occur near interface 204 due to pattern misalignment, pattern density, and / or other factors. The different properties of the segments of sealing ring structures 218a and / or sealing ring structures 218b near interface 204 can reduce the likelihood and / or defect rate of defects at interface 204.

[0139] Specifically, in the exemplary embodiment of the semiconductor element 202 shown in Figures 9A and 9B, the lateral width of the sealing ring structure 218a and / or sealing ring structure 218b near the interface 204 is increased relative to the lateral width of other segments of the sealing ring structure 218a and / or sealing ring structure 218b to compensate for the masking misalignment between the lateral regions 206 and 208 at the interface 204. The masking misalignment between the lateral regions 206 and 208 at the interface 204 may cause segmental misalignment of the sealing ring structure 218a in the lateral regions 206 and 208 at the interface 204, and / or may cause segmental misalignment of the sealing ring structure 218b in the lateral regions 206 and 208 at the interface 204. Misalignment between portions of the sealing ring structure 218a in lateral regions 206 and 208 may prevent segments of the sealing ring structure 218a from connecting at interface 204, thus preventing the formation of a continuous sealing ring structure 218a around the semiconductor element 202. Similarly, misalignment between segments of the sealing ring structure 218b in lateral regions 206 and 208 may prevent segments of the sealing ring structure 218b from connecting at interface 204, thus preventing the formation of a continuous sealing ring structure 218b around the semiconductor element 202. Discontinuities in the sealing ring structures 218a and / or 218b may reduce their ability to protect functional regions 210, 212, 214, and 216 of the semiconductor element 202.

[0140] As shown in Figure 9A, an exemplary embodiment 900 of the semiconductor element 202 may include buffers 902 and 904 located in lateral regions 206 and 208, respectively, on opposite sides of interface 204. In buffer 902, a segment 906a of the sealing ring structure 218a may have a lateral width (dimension D14 shown in Figure 9A) in a direction substantially perpendicular to the length of segment 906a, which is greater than the lateral width (dimension D1) of the sealing ring structure 218a outside buffers 902 and 904. Similarly, in buffer 904, a segment 906b of the sealing ring structure 218a may have a lateral width (dimension D15 shown in Figure 9A) in a direction substantially perpendicular to the length of segment 906b, which is greater than the lateral width (dimension D1) of the sealing ring structure 218a outside buffers 902 and 904. The lateral widths of segments 906a and 906b are greater than those of the other segments of the sealing ring structure 218a. This increases the likelihood that the segments of the sealing ring structure 218a formed in the lateral regions 206 and 208 will connect together at interface 204, and provides a wider process window for patterning the sealing ring structure 218a using a multi-mask exposure technique. In some embodiments, the lateral widths of segments 906a and 906b may be approximately 20% to 30% larger than the lateral width of the sealing ring structure 218a (e.g., dimension D1). However, other values ​​and ranges are also within the scope of this disclosure.

[0141] In buffer 902, the lateral width (dimension D16 shown in Figure 9A) of segment 908a of sealing ring structure 218b in the direction perpendicular to the length of segment 908a is greater than the lateral width (dimension D3) of sealing ring structure 218b located outside buffer 902 and buffer 904. Similarly, in buffer 904, the lateral width (dimension D17 shown in Figure 9A) of segment 908b of sealing ring structure 218b in the direction perpendicular to the length of segment 908b is greater than the width (lateral dimension D3) of sealing ring structure 218b located outside buffer 902 and buffer 904. The lateral widths of segments 908a and 908b are greater than those of the other segments of the sealing ring structure 218b. This increases the likelihood that the segments of the sealing ring structure 218b formed in the lateral regions 206 and 208 will connect together at interface 204, and provides a wider process window for patterning the sealing ring structure 218b using a multiple mask exposure technique. In some embodiments, the lateral widths of segments 908a and 908b may be approximately 20% to approximately 30% greater than the lateral width of the sealing ring structure 218b (e.g., dimension D3). However, other values ​​and ranges are also within the scope of this disclosure.

[0142] As further shown in Figure 9A, buffer 902 may have a lateral width in the x-direction (denoted as dimension D18 in Figure 9A), and buffer 904 may have a lateral width in the x-direction (denoted as dimension D19 in Figure 9A). The lateral widths of buffer 902 and buffer 904 may each range from approximately 2 micrometers to approximately 10 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0143] A multi-mask exposure technique described in conjunction with Figures 3A to 3L, Figures 5A to 5K, and / or Figures 7A to 7P can be performed to form segments of sealing ring structures 218a and 218b of the multi-sealing ring structure 218, incorporating segments 906a and 908a into the lateral region 206, and segments 906b and 908b into the lateral region 208. For example, a first set of masks 108 can be used to pattern the lateral region 206 to form segments 906a and 908a in the buffer 902 of the lateral region 206, and a second set of masks 108 can be used to pattern the lateral region 208 to form segments 906b and 908b in the buffer 904 of the lateral region 208.

[0144] As shown in Figure 9B, an exemplary embodiment 910 of the semiconductor element 202 may include sealing ring structures 218a and 218b, the lateral width of the segments within buffers 902 and 904 being greater than the lateral width of the segments outside buffers 902 and 904. This increased lateral width of the segments of sealing ring structures 218a and 218b causes them to merge together within buffers 902 and 904. Therefore, the multiple sealing ring structure 218 may include a merged segment 912 in buffers 902 and 904 extending across the interface 204 between lateral regions 206 and 208.

[0145] The multi-mask exposure technique described in conjunction with Figures 3A to 3L, Figures 5A to 5K, and / or Figures 7A to 7P can be performed to form segments of sealing ring structures 218a and 218b of the multi-sealing ring structure 218, including portions of the merged segment 912 in the lateral regions 206 and 208. For example, the lateral region 206 can be patterned using a first set of masks 108 to form a first portion of the merged segment 912 in a buffer 902 of the lateral region 206, and the lateral region 208 can be patterned using a second set of masks 108 to form a second portion of the merged segment 912 in a buffer 904 of the lateral region 208.

[0146] As described above, Figures 9A and 9B are provided as examples. Other examples may differ from those described in Figures 9A and 9B.

[0147] Figure 10 is a diagram of an exemplary embodiment 1000 of the semiconductor device 202 described herein. In exemplary embodiment 1000, sealing ring structures 218a and 218b of the multiple sealing ring structure 218 are configured as capacitor electrodes, and these elements are physically isolated through a dielectric layer 242 in the front interconnect layer 234 of the semiconductor device 202. In this way, the combination of sealing ring structures 218a and 218b and the dielectric layer 242 located between sealing ring structures 218a and 218b enables the multiple sealing ring structure 218 to act as a capacitor, which can absorb leakage current around functional regions 210, 212, 214, and 216 of the semiconductor device 202 to enhance electrical isolation.

[0148] As shown in Figure 10, the exemplary embodiment 1000 of the semiconductor device 202 includes a top-view layout similar to that of the exemplary embodiment 200 of the semiconductor device 202 shown in Figure 2A. However, the sealing ring structure 218b in the exemplary embodiment 1000 of the semiconductor device 202 includes a terminal 1002 extending through a cut segment 1004 of the sealing ring structure 218a. Similarly, the sealing ring structure 218a includes a terminal 1006 extending inward toward the center of the semiconductor device 202. The terminal 1002 may be a lateral extension of the sealing ring structure 218b, and the terminal 1006 may be a lateral extension of the sealing ring structure 218a.

[0149] Terminal 1002 may be grounded (e.g., electrically coupled to the electrical ground of semiconductor element 202), and terminal 1006 may be electrically coupled to a bias input to bias the multiple sealing ring structure 218. The bias causes sealing ring structures 218a and 218b to absorb charge carriers around the multiple sealing ring structure 218 to prevent or minimize the possibility of charge carriers interfering with the operation of functional regions 210, 212, 214, and 216 of semiconductor element 202.

[0150] A multi-mask exposure technique combined with that described in Figures 3A to 3L, 5A to 5K, and / or 7A to 7P can be performed to form segments of sealing ring structures 218a and 218b of the multi-sealed ring structure 218, including terminals 1002 and cut segments 1004 in the lateral region 206, and to form segments of sealing ring structures 218a and 218b of the multi-sealed ring structure 218, including terminals 1006 in the lateral region 208. For example, the lateral region 206 can be patterned using a first set of masks 108 to form a first portion of the sealing ring structure 218b in the lateral region 206, including terminals 1002, and to form a first portion of the sealing ring structure 218a, including cut segments 1004 in the lateral region 206. The second set of shields 108 can be used to pattern the lateral region 208 to form a second part of the sealing ring structure 218a to include the terminal 1006 in the lateral region 208.

[0151] As described above, Figure 10 is provided as an example. Other examples may differ from those shown in Figure 10.

[0152] Figure 11 is a diagram of an exemplary embodiment 1100 of the semiconductor device 202 described herein. The exemplary embodiment 1100 of the semiconductor device 202 is similar to the exemplary embodiment 1000 of the semiconductor device 202, wherein the multiple sealing ring structure 218 in the exemplary embodiment 1100 of the semiconductor device 202 is configured to function as a capacitor, which can absorb leakage current around the functional regions 210, 212, 214, and 216 of the semiconductor device 202 to enhance electrical isolation. However, in the exemplary embodiment 1100 of the semiconductor device 202, the multiple sealing ring structure 218 is segmented to include multiple discontinuous capacitor segments surrounding the periphery of the semiconductor device 202.

[0153] As shown in Figure 11, the sealing ring structure 218b may include a terminal 1002a coupled to a first segment of the sealing ring structure 218b, and the sealing ring structure 218a may include a terminal 1006a coupled to a first segment of the sealing ring structure 218a. The first segments of the sealing ring structures 218a and 218b, as well as the terminals 1002a and 1006a, may correspond to the capacitor segments of the multiple sealing ring structure 218.

[0154] The sealing ring structure 218b may include a terminal 1002b coupled to a second segment of the sealing ring structure 218b, and the sealing ring structure 218a may include a terminal 1006b coupled to a second segment of the sealing ring structure 218a. The second segments of the sealing ring structures 218a and 218b, as well as the terminals 1002b and 1006b, may correspond to the capacitor segments of the multiple sealing ring structure 218.

[0155] The sealing ring structure 218b may include a terminal 1002c coupled to the third segment of the sealing ring structure 218b, and the sealing ring structure 218a may include a terminal 1006c coupled to the third segment of the sealing ring structure 218a. The third segments of the sealing ring structures 218a and 218b, as well as the terminals 1002c and 1006c, may correspond to the capacitor segments of the multiple sealing ring structure 218.

[0156] The sealing ring structure 218b may include a terminal 1002d coupled to the fourth segment of the sealing ring structure 218b, and the sealing ring structure 218a may include a terminal 1006d coupled to the fourth segment of the sealing ring structure 218a. The fourth segments of the sealing ring structures 218a and 218b, as well as the terminals 1002d and 1006d, may correspond to the capacitor segments of the multiple sealing ring structure 218.

[0157] The capacitor segments of the multi-ring structure 218 can be separated by the dielectric layer 242 of the front interconnect layer 234 of the semiconductor element 202. Cut sections 1004a, 1004b, 1004c, 1004d and 1102a, 1102b, 1102c, 1102d provide spacing between the capacitor segments of the multi-ring structure 218. Cut sections 1004a-1004d and 1102a-1102d can be used to provide stress relief at the edges or periphery of the semiconductor element 202.

[0158] Cutting segment 1004a may be located between the first and second segments of sealing ring structure 218a, cutting segment 1004b may be located between the second and third segments of sealing ring structure 218a, cutting segment 1004c may be located between the third and fourth segments of sealing ring structure 218a, and cutting segment 1004d may be located between the fourth and first segments of sealing ring structure 218a. Cutting segment 1102a may be located between the first and second segments of sealing ring structure 218b, cutting segment 1102b may be located between the second and third segments of sealing ring structure 218b, for example, cutting segment 1102c may be located between the third and fourth segments of sealing ring structure 218b, and cutting segment 1102d may be located between the fourth and first segments of sealing ring structure 218b.

[0159] Terminal 1002a can extend laterally through the cutting section 1004a. Terminal 1002b can extend laterally through the cutting section 1004b. Terminal 1002c can extend laterally through the cutting section 1004c. Terminal 1002d can extend laterally through the cutting section 1004d.

[0160] As described above, Figure 11 is provided as an example. Other examples may differ from those shown in Figure 11.

[0161] Figure 12 is a diagram of an exemplary embodiment 1200 of the semiconductor device 202 described herein. The exemplary embodiment 1200 of the semiconductor device 202 is similar to exemplary embodiment 1100, wherein the multiple sealing ring structure 218 in the exemplary embodiment 1200 of the semiconductor device 202 is configured to function as a capacitor, which can absorb leakage current around functional regions 210, 212, 214, and 216 of the semiconductor device 202 to enhance electrical isolation. However, in the exemplary embodiment 1200 of the semiconductor device 202, the multiple sealing ring structure 218 also includes another sealing ring structure 218c laterally surrounding the periphery of the semiconductor device 202.

[0162] As shown in Figure 12, the sealing ring structure 218c may be included around the sealing ring structure 218b. Therefore, in the exemplary embodiment 1200 of the semiconductor element 202, the sealing ring structure 218a is the inner sealing ring structure of the multiple sealing ring structure 218, the sealing ring structure 218b is the middle sealing ring structure of the multiple sealing ring structure 218, and the sealing ring structure 218c is the outer sealing ring structure of the multiple sealing ring structure 218.

[0163] As further shown in Figure 12, the sealing ring structure 218c may include a closed-loop structure that extends continuously to the periphery of the semiconductor element 202. The sealing ring structure 218c may include vertically arranged inner pillar interconnect structures 1202, outer line interconnect structures 1204, and metallization structures 1206. Each interconnect structure of the sealing ring structure 218c may include an arrangement of inner pillar interconnect structures 1202 and outer line interconnect structures 1204. The two interconnect structures of the sealing ring structure 218c may be coupled together through the metallization structure 1206 located vertically between the two interconnect structures.

[0164] The sealing ring structure 218c may have a lateral width (denoted as dimension D20 in Figure 12) and a lateral spacing (denoted as dimension D21 in Figure 12) between the inner post interconnection structure 1202 and the outer line interconnection structure 1204 of the sealing ring structure 218c. In some embodiments, the lateral width of the sealing ring structure 218c may be smaller than the lateral width of the sealing ring structure 218b (e.g., D20 < D3). For example, the lateral width of the sealing ring structure 218c may be from about 1.5 micrometers to about 2 micrometers, while the lateral width of the sealing ring structure 218b may be from about 2.5 micrometers to about 3 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0165] The sealing ring structure 218c may be spaced apart from the sealing ring structure 218b by a certain distance (denoted as dimension D22 in Figure 12). In some embodiments, the distance between the sealing ring structure 218c and the sealing ring structure 218b is greater than the distance between the sealing ring structure 218b and the sealing ring structure 218a (e.g., D22 > D5). In some embodiments, the distance between the sealing ring structure 218c and the sealing ring structure 218b is less than the distance between the sealing ring structure 218b and the sealing ring structure 218a (e.g., D22 < D5). In some embodiments, the distance between the sealing ring structure 218c and the sealing ring structure 218b and the distance between the sealing ring structure 218b and the sealing ring structure 218a are approximately equal (e.g., D22 ≅ D5).

[0166] As described above, Figure 12 is provided as an example. Other examples may differ from those shown in Figure 12.

[0167] Figure 13 is a diagram of an exemplary embodiment of the semiconductor package 1300 described herein. The semiconductor package 1300 includes a package substrate 1302 and a plurality of semiconductor elements 1304 and 1306 mounted or attached to a first side (e.g., the top side) of the package substrate 1302. The semiconductor elements 1304 and 1306 may be arranged horizontally in the semiconductor package 1300 (e.g., in the x-direction, in the y-direction) and / or vertically in the semiconductor package 1300 in the z-direction.

[0168] In some embodiments, semiconductor element 1304 may include one or more single-crystal super wafers, such as one or more exemplary embodiments of semiconductor element 202 shown and described herein. In some embodiments, semiconductor element 1304 may include one or more stacked semiconductor elements 600, which include a plurality of vertically stacked single-crystal super wafers (e.g., vertically stacked semiconductor elements 202a and semiconductor elements 202b).

[0169] In some embodiments, semiconductor element 1306 may include a SoC die, such as a logic die, CPU die, GPU die, DSP die, ASIC die, and / or another type of SoC die. In some embodiments, semiconductor element 1306 includes a memory die, input / output (I / O) die, pixel sensor die, high voltage (HV) die, and / or another type of semiconductor die. Examples of such memory dies include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, NAND dies, high bandwidth memory (HBM) dies, and / or other types of memory dies. In some embodiments, semiconductor element 1306 includes an integrated passive device (IPD) that includes one or more passive semiconductor elements, such as resistors, capacitors, inductors, and / or diodes.

[0170] The package substrate 1302 includes a plurality of conductive lines 1308 that are interconnected and can electrically connect semiconductor elements 1304 and 1306 to the package connector 1310 of the semiconductor package 1300. Additionally, the package substrate 1302 may include conductive lines 1312 that electrically connect semiconductor elements 1304 and 1306 together. The conductive lines 1308 and 1312 enable the transmission of signals and / or power between semiconductor elements 1304 and 1306, and / or between semiconductor elements 1304 and 1306 and devices outside the semiconductor package 1300.

[0171] In some embodiments, the package substrate 1302 is an interposer and includes a silicon (Si) interposer, an organic interposer (e.g., an organic polymer interposer), a dielectric interposer (e.g., silicon oxide (SiOx) or a glass interposer), and / or other types of interposers. Conductive lines 1308 and 1312 in the package substrate 1302 may be arranged in interconnect layers called redistribution layers (RDLs). Each RDL may include trenches, conductive lines, and / or other types of conductive structures that extend primarily laterally or horizontally (e.g., in the x-direction, in the y-direction) in the package substrate 1302. The RDLs in the package substrate 1302 may be interconnected through interconnect layers, which include vias, conductive tubes, conductive pillars, and / or other types of interconnect structures that extend primarily vertically (e.g., in the z-direction) in the package substrate 1302. The conductive lines 1308 and 1312 in the packaging substrate 1302 may include one or more conductive materials, such as gold (Au), copper (Cu), silver (Ag), nickel (Ni), aluminum (Al), ruthenium (Ru), cobalt (Co), titanium (Ti), tungsten (W), tin (Sn), lead (Pb), and / or palladium (Pd).

[0172] The use of the multimask exposure technique described herein to fabricate semiconductor element 1304 allows the functionality of semiconductor package 1300 to be distributed across fewer semiconductor elements, which reduces the number and / or density of conductive lines 1312 used to interconnect semiconductor elements of semiconductor package 1300. This can provide greater I / O density in package substrate 1302 and / or provide faster, lower latency communication between functional regions 210, 212, 214, and 216 of semiconductor element 1304 (e.g., if functional regions 210, 212, 214, and 216 are contained on separate semiconductor elements 1306 and interconnected via conductive lines 1312).

[0173] The package connector 1310 of the semiconductor package 1300 enables the semiconductor package 1300 to be mounted or attached to the system substrate 1316 via a mounting structure 1314. The package connector 1310 may include bonding pads, solder balls arranged in a ball gate array package (BGA), microbumps, controllable melt-collapse chip connection (C4) bumps, metal pads arranged in a planar grid array package (LGA), conductive pins arranged in a pin grid array (PGA), and / or other types of connection structures.

[0174] Mounting structure 1314 may include sockets, solder pads, connectors, and / or other types of mounting structures. System board 1316 may include printed circuit boards, such as system boards, motherboards, adapter boards, and / or other types of printed circuit boards.

[0175] As further shown in Figure 13, semiconductor elements 1304 and 1306 may be surrounded by an encapsulation layer 1318. The encapsulation layer 1318 may include an underfill layer, a molding compound layer, and / or other types of encapsulation layers to provide electrical isolation for semiconductor elements 1304 and 1306 and to protect them from vibration and moisture intrusion. The encapsulation layer 1318 may include an underfill material, such as a polymer, one or more fillers dispersed in a resin, an epoxy resin, and / or another type of electrically insulating material. In some embodiments, the encapsulation layer 1318 may include a molding compound and / or another type of encapsulation material.

[0176] The semiconductor package 1300 may include a heat cap structure 1320 mounted or attached to semiconductor elements 1304 and 1306. The heat cap structure 1320 may be thermally coupled to semiconductor elements 1304 and 1306 through a thermal interface material layer 1322. This enables the heat cap structure 1320 to provide thermal management for semiconductor elements 1304 and 1306. Specifically, the heat cap structure 1320 may remove heat from semiconductor elements 1304 and 1306 and / or their surroundings, thereby providing cooling for semiconductor elements 1304 and 1306. The heat cap structure 1320 may include a heat sink, a vapor chamber, a heat pipe, and / or other types of heat cap structures.

[0177] The thermal interface material layer 1322 may include a layer of thermal interface material. The thermal interface material may include thermal interface paste, thermal interface sheet, and / or other types of thermal interface materials. In some embodiments, the thermal interface material of the thermal interface material layer 1322 includes a paste comprising metal particles (e.g., gold particles, silver particles) suspended in a liquid compound. In some embodiments, the thermal interface material of the thermal interface material layer 1322 includes graphene sheets and / or another type of carbon-based thermal interface material. In some embodiments, the thermal interface material of the thermal interface material layer 1322 includes a phase change material, such as a polymer-based phase change material. In some embodiments, the thermal interface material of the thermal interface material layer 1322 includes a liquid metal thermal interface material, which may include one or more metals (e.g., gallium (Ga), indium (In), tin (Sn)) suspended in a liquid form in a compound.

[0178] As described above, Figure 13 is provided as an example. Other examples may differ from those shown in Figure 13.

[0179] Figure 14 is a flowchart of an exemplary process 1400 associated with forming the semiconductor device described herein. In some embodiments, one or more semiconductor process tools are used to perform one or more process blocks of Figure 14, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools and / or other types of semiconductor process tools.

[0180] As shown in Figure 14, process 1400 may include forming one or more integrated circuit elements (block 1410) in a device layer of a semiconductor element. For example, one or more semiconductor process tools may be used to form one or more integrated circuit elements (e.g., integrated circuit element 238) in a device layer (e.g., device layer 232) of a semiconductor element (e.g., semiconductor element 202), as described herein.

[0181] As further shown in Figure 14, process 1400 may include forming an interconnect layer (block 1420) over the device layer. For example, an interconnect layer (e.g., front-side interconnect layer 234) may be formed over the device layer using one or more semiconductor process tools, as described herein. In some embodiments, the interconnect layer includes one or more dielectric layers (e.g., one or more dielectric layers 242) and one or more conductive structures (e.g., one or more conductive structures 244) within the one or more dielectric layers. In some embodiments, at least one integrated circuit element is coupled to at least one of the one or more conductive structures.

[0182] As further shown in Figure 14, process 1400 may include a first segment (block 1430) forming a multi-ring structure around a first portion of the interconnect layer in a first region of the semiconductor element using a first set of photolithographic masks. For example, one or more semiconductor process tools may be used to form a first segment (e.g., multi-ring structure 218) of the multi-ring structure around a first portion of the interconnect layer in a first region (e.g., lateral region 206) of the semiconductor element using a first set of photolithographic masks (e.g., first set of masks 108a), as described herein.

[0183] As further shown in Figure 14, process 1400 may include forming a second segment (block 1440) of a multiple sealing ring structure around a second portion of an interconnect layer in a second region of a semiconductor device using a second set of photolithographic masks. For example, one or more semiconductor process tools may be used to form the second segment of the multiple sealing ring structure around a second portion of an interconnect layer in a second region (e.g., lateral region 208) of a semiconductor device using a second set of photolithographic masks (e.g., second set of masks 108b), as described herein. In some embodiments, the first region and the second region are laterally adjacent in the semiconductor device. In some embodiments, the first portion and the second portion of the interconnect layer are laterally adjacent in the semiconductor device. In some embodiments, the first segment and the second segment of the multiple sealing ring structure are coupled together such that the multiple sealing ring structure laterally and continuously surrounds the interconnect layer.

[0184] Process 1400 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or embodiments related to one or more other processes described elsewhere herein.

[0185] In a first embodiment, a first set of photolithography masks is used to pattern a first region of a semiconductor element and an additional first region of an additional semiconductor element on a semiconductor wafer (e.g., semiconductor wafer 110), and a second set of photolithography masks is used to pattern a second region of a semiconductor element and an additional second region of an additional semiconductor element on a semiconductor wafer.

[0186] In the second embodiment, the first segment forming the multiple sealing ring structure, alone or in combination with the first embodiment, includes performing a first exposure operation using a first photolithographic mask (e.g., mask 108a) in the first set of photolithographic masks to expose a first region, thereby forming the first segment of the multiple sealing ring structure in the first region. The second segment forming the multiple sealing ring structure includes performing a second exposure operation using a first photolithographic mask (e.g., mask 108b) in the second set of photolithographic masks after the first exposure operation to expose a second region, thereby forming the second segment of the multiple sealing ring structure in the second region.

[0187] In the third embodiment, forming a first segment of the multiple sealing ring structure, either alone or in combination with one or more of the first and second embodiments, includes performing a third exposure operation after a second exposure operation using a second photolithographic mask (e.g., mask 108a) from a first set of photolithographic masks to expose a first region, thereby forming a first segment of the multiple sealing ring structure in the first region. Forming a second portion of the multiple sealing ring structure includes performing a fourth exposure operation after the third exposure operation using a second photolithographic mask (e.g., mask 108b) from a second set of photolithographic masks to expose a second region, thereby forming a second segment of the multiple sealing ring structure in the second region.

[0188] In the fourth embodiment, the first segment forming the multiple sealing ring structure, either alone or in combination with one or more of the first to third embodiments, includes a first segment (e.g., segment 906a, segment 908a) of the first segment forming the multiple sealing ring structure in a first buffer (e.g., buffer 902) at the interface (e.g., interface 204) between the first region and the second region using a first set of photolithographic masks. This first segment extends to a first lateral width. The second segment forming the multi-ring structure includes forming a second buffer (e.g., buffer 904) at the interface between the first and second regions using a second set of photolithographic masks, extending the second segment (e.g., segment 906b, segment 908b) of the second segment of the multi-ring structure (e.g., the segment of ring structure 218a in the lateral region 208, the segment of ring structure 218b in the lateral region 208) to a second lateral width, wherein the first segment of the first segment of the multi-ring structure and the second segment of the second segment of the multi-ring structure are coupled together at the interface.

[0189] In the fifth embodiment, the first pattern segment for patterning the first pattern segment (e.g., pattern segment 806a) of the first photolithography mask (e.g., mask 108a) in the first set of photolithography masks has a third lateral width (dimension D6), which is smaller than the fourth lateral width (dimension D7) of the second pattern segment in the first photolithography mask. The second pattern segment is used to pattern the third segment of the first segment of the multi-sealing ring structure outside the first buffer.

[0190] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the first lateral width of the first segment of the first section of the multi-seal ring structure is greater than the third lateral width of the third segment outside the first buffer zone of the first section of the multi-seal ring structure, and the second lateral width of the second segment of the second section of the multi-seal ring structure is greater than the fourth lateral width of the fourth segment outside the second buffer zone of the second section of the multi-seal ring structure.

[0191] In the seventh embodiment, the first segment forming the multi-seal ring structure, either alone or in combination with one or more of the first to sixth embodiments, includes a first segment of the inner sealing ring structure (e.g., sealing ring structure 218a) and a first segment of the outer sealing ring structure (e.g., sealing ring structure 218b) of the multi-seal ring structure, formed using a first set of photolithographic masks. The first segment of the inner sealing ring structure and the first segment of the outer sealing ring structure are merged together at the first segment of the first segment of the multi-seal ring structure within a first buffer zone.

[0192] In the eighth embodiment, the second segment forming the multi-seal ring structure, either alone or in combination with one or more of the first to seventh embodiments, includes a second segment of the inner sealing ring structure formed by using a second set of photolithographic masks to form the multi-seal ring structure and a second segment of the outer sealing ring structure of the multi-seal ring structure, wherein the second segment of the inner sealing ring structure and the second segment of the outer sealing ring structure are merged together at the second segment of the second segment of the multi-seal ring structure within the second buffer zone.

[0193] Although Figure 14 shows an example block of process 1400, in some embodiments, process 1400 includes more blocks, fewer blocks, different blocks, or blocks arranged differently than those shown in Figure 14. Alternatively, two or more blocks of process 1400 may be executed in parallel.

[0194] Figure 15 is a flowchart of an exemplary process 1500 associated with forming the semiconductor device described herein. In some embodiments, one or more process blocks of Figure 15 are performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0195] As shown in Figure 15, process 1500 may include forming one or more integrated circuit elements (block 1510) in a device layer of a semiconductor element. For example, one or more semiconductor process tools may be used to form one or more integrated circuit elements (e.g., integrated circuit element 238) in a device layer (e.g., device layer 232) of a semiconductor element (e.g., semiconductor element 202), as described herein.

[0196] As further shown in Figure 15, process 1500 may include forming an interconnect layer (block 1520) over the device layer. For example, an interconnect layer (e.g., front-side interconnect layer 234) may be formed over the device layer using one or more semiconductor process tools, as described herein. In some embodiments, the interconnect layer includes one or more dielectric layers (e.g., dielectric layer 242) and one or more conductive structures (e.g., conductive structure 244) within the one or more dielectric layers. In some embodiments, at least one integrated circuit element is coupled to at least one of the one or more conductive structures.

[0197] As further shown in Figure 15, process 1500 may include a first segment of a first sealing ring structure and a first segment of a second sealing ring structure (block 1530) of a multi-sealed ring structure formed around a first portion of an interconnect layer in a first region of a semiconductor element using a first set of photolithographic masks. For example, one or more semiconductor process tools may be used to form a first segment of a first sealing ring structure (e.g., sealing ring structure 218a) of a multi-sealed ring structure (e.g., multi-sealed ring structure 218) and a first segment of a second sealing ring structure (e.g., sealing ring structure 218b) of a multi-sealed ring structure around a first portion of an interconnect layer in a first region (e.g., lateral region 206) of a semiconductor element, as described herein. In some embodiments, the first set of photolithographic masks is used to form the first segment of the first sealing ring structure such that the first segment of the first sealing ring structure includes a diced segment (e.g., diced segment 1004). In some embodiments, a first set of photolithographic masks is used to form a first segment of the second sealing ring structure, such that the first segment of the second sealing ring structure includes a first terminal (e.g., terminal 1002) extending through the cut segment.

[0198] As further shown in Figure 15, process 1500 may include forming a second segment of a first sealing ring structure and a second segment of a second sealing ring structure (block 1540) around a second portion of an interconnect layer in a second region of a semiconductor element using a second set of photolithographic masks. For example, one or more semiconductor process tools may be used to form a second set of photolithographic masks (e.g., second set of masks 108b) surrounding a second portion of an interconnect layer in a second region of a semiconductor element (e.g., lateral region 208), as described herein. In some embodiments, the second set of photolithographic masks is used to form a second segment of the first sealing ring structure such that the second segment of the first sealing ring structure includes a second terminal (e.g., terminal 1002) extending laterally from the second segment of the first sealing ring structure.

[0199] Process 1500 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or embodiments related to one or more other processes described elsewhere herein.

[0200] In the first embodiment, the first region and the second region are laterally adjacent in the semiconductor element, wherein the first portion of the interconnect layer and the second portion of the interconnect layer are laterally adjacent in the semiconductor element, and the multiple sealing ring structure laterally surrounds the interconnect layer.

[0201] In the second embodiment, alone or in combination with the first embodiment, the cutting segment is a first cutting segment, the first segment forming the second sealing ring structure includes the first segment forming the second sealing ring structure using a first set of photolithographic masks, such that the first segment of the second sealing ring structure includes a second cutting segment (e.g., cutting segment 1102a), and the second segment forming the second sealing ring structure includes the second segment forming the second sealing ring structure using a second set of photolithographic masks, such that the second segment of the second sealing ring structure includes a third cutting segment (e.g., cutting segment 1102c).

[0202] In the third embodiment, either alone or in combination with the first and second embodiments, process 1500 includes forming a first segment of a third sealing ring structure (e.g., sealing ring structure 218c) around a first portion of an interconnect layer in a first region of a semiconductor element using a first set of photolithographic masks, and forming a second segment of the third sealing ring structure around a second portion of an interconnect layer in a second region of a semiconductor element using a second set of photolithographic masks, wherein the first segment of the third sealing ring structure and the second segment of the third sealing ring structure are coupled together such that the third sealing ring structure is laterally continuous around the interconnect layer.

[0203] Although Figure 15 shows an example block of process 1500, in some embodiments, process 1500 includes more blocks, fewer blocks, different blocks, or blocks arranged differently than those shown in Figure 15. Alternatively, two or more blocks of process 1500 may be executed in parallel.

[0204] As a result, single-crystal super wafers fabricated using multi-mask exposure technology have a larger device area than those fabricated using single-mask exposure technology. As described herein, different lateral regions of a semiconductor device (e.g., a single-crystal super wafer) can be patterned using different sets of photolithographic masks. Multi-mask exposure technology can be extended to fabricate sealing ring structures around the lateral regions of a semiconductor device. Multi-mask exposure technology can be used to fabricate sealing ring structures with different properties (e.g., different sizes, different shapes, different configurations) in different lateral regions of a semiconductor device, which provides greater manufacturing flexibility for single-crystal super wafers.

[0205] As described in more detail above, some embodiments described herein provide a method. This method includes forming one or more integrated circuit elements in a device layer of a semiconductor device. This method includes forming an interconnect layer over the device layer. The interconnect layer includes one or more dielectric layers and one or more conductive structures located within the one or more dielectric layers. At least one integrated circuit element is coupled to at least one of the one or more conductive structures. This method includes forming a first segment of a multiple sealing ring structure around a first portion of the interconnect layer in a first region of the semiconductor device using a first set of photolithographic masks. This method includes forming a second segment of the multiple sealing ring structure around a second portion of the interconnect layer in a second region of the semiconductor device using a second set of photolithographic masks, wherein the first region and the second region are laterally adjacent in the semiconductor device, wherein the first portion and the second portion of the interconnect layer are laterally adjacent in the semiconductor device, and wherein the first segment and the second segment of the multiple sealing ring structure are coupled together such that the multiple sealing ring structure laterally and continuously surrounds the interconnect layer.

[0206] In some embodiments, a first set of photolithographic masks is used to pattern a first region of a semiconductor element and a plurality of additional first regions of a plurality of additional semiconductor elements on a semiconductor wafer; and a second set of photolithographic masks is used to pattern a second region of a semiconductor element and a plurality of additional second regions of additional semiconductor elements on a semiconductor wafer.

[0207] In some embodiments, the first segment forming the multiple sealing ring structure includes: performing a first exposure operation using a first photolithographic mask in a first set of photolithographic masks to expose a first region, thereby forming the first segment of the multiple sealing ring structure in the first region; and wherein the second segment forming the multiple sealing ring structure includes: after the first exposure operation, performing a second exposure operation using a first photolithographic mask in a second set of photolithographic masks to expose a second region, thereby forming the second segment of the multiple sealing ring structure in the second region.

[0208] In some embodiments, forming the first segment of the multiple sealing ring structure includes: after the second exposure operation, performing a third exposure operation using a second photolithographic mask in a first set of photolithographic masks to expose a first region, thereby forming the first segment of the multiple sealing ring structure in the first region; and wherein forming the second segment of the multiple sealing ring structure includes: after the third exposure operation, performing a fourth exposure operation using a second photolithographic mask in a second set of photolithographic masks to expose a second region, thereby forming the second segment of the multiple sealing ring structure in the second region.

[0209] In some embodiments, the first segment forming the multi-sealing ring structure includes: forming a first segment of the first segment of the multi-sealing ring structure having a first lateral width in a first buffer zone at the interface between the first region and the second region using a first set of photolithographic masks; and wherein the second segment forming the multi-sealing ring structure includes: forming a second segment of the second segment of the multi-sealing ring structure having a second lateral width in a second buffer zone at the interface between the first region and the second region using a second set of photolithographic masks, wherein the first segment of the first segment of the multi-sealing ring structure and the second segment of the second segment of the multi-sealing ring structure are coupled together at the interface.

[0210] In some embodiments, the first pattern segment in the first photolithography mask of the first group of photolithography masks used for patterning the first segment has a third lateral width, which is smaller than the fourth lateral width of the second pattern segment in the first photolithography mask used for patterning the third segment of the first segment of the multi-sealing ring structure outside the first buffer zone.

[0211] In some embodiments, the first lateral width of the first segment of the first section of the multi-seal ring structure is greater than the third lateral width of the third segment of the first section of the multi-seal ring structure located outside the first buffer zone; and the second lateral width of the second segment of the second section of the multi-seal ring structure is greater than the fourth lateral width of the fourth segment of the second section of the multi-seal ring structure located outside the second buffer zone.

[0212] In some embodiments, the first segment forming the multi-seal ring structure includes: a first segment of an inner sealing ring structure and a first segment of an outer sealing ring structure of the multi-seal ring structure formed using a first set of photolithographic masks, wherein the first segment of the inner sealing ring structure and the first segment of the outer sealing ring structure are merged together in a first buffer zone.

[0213] In some embodiments, the second segment forming the multi-seal ring structure includes: a second segment of the inner sealing ring structure and a second segment of the outer sealing ring structure of the multi-seal ring structure formed using a first set of photolithographic masks, wherein the second segment of the inner sealing ring structure and the second segment of the outer sealing ring structure are merged together in the second buffer zone.

[0214] As described in more detail above, some embodiments described herein provide a method. This method includes forming one or more integrated circuit elements in a device layer of a semiconductor device; forming an interconnect layer above the device layer; wherein the interconnect layer includes one or more dielectric layers and one or more conductive structures located within the one or more dielectric layers, and wherein at least one integrated circuit element is coupled to at least one of the one or more conductive structures; using a first set of photolithographic masks, forming a first segment of a first sealing ring structure of a first sealing ring structure and a first segment of a second sealing ring structure of a multiple sealing ring structure around a first portion of the interconnect layer in a first region of the semiconductor device, wherein the first set of photolithographic masks is used to form the first segment of the first sealing ring structure, such that... A first segment of a first sealing ring structure includes a diced segment, and a first set of photolithographic masks is used to form a first segment of a second sealing ring structure such that the first segment of the second sealing ring structure includes a first terminal extending through the diced segment; and a second segment of a first sealing ring structure and a second segment of a second sealing ring structure of a multi-seal ring structure are formed around a second portion of an interconnect layer in a second region of a semiconductor element using a second set of photolithographic masks, wherein the second set of photolithographic masks is used to form a second segment of the first sealing ring structure such that the second segment of the first sealing ring structure includes a second terminal extending laterally from the second segment of the first sealing ring structure.

[0215] In some embodiments, the first region and the second region are laterally adjacent in the semiconductor element; wherein the first portion of the interconnect layer and the second portion of the interconnect layer are laterally adjacent in the semiconductor element; and wherein the multiple sealing ring structure laterally surrounds the interconnect layer.

[0216] In some embodiments, the cutting segment is a first cutting segment; wherein the first segment forming the second sealing ring structure includes: forming the first segment of the second sealing ring structure using a first set of photolithographic masks, such that the first segment of the second sealing ring structure includes the second cutting segment; and wherein the second segment forming the second sealing ring structure includes: forming the second segment of the second sealing ring structure using a second set of photolithographic masks, such that the second segment of the second sealing ring structure includes the third cutting segment.

[0217] In some embodiments, the method further includes: forming a first segment of a third sealing ring structure with a multiple sealing ring structure around a first portion of an interconnect layer in a first region of a semiconductor element using a first set of photolithographic masks; and forming a second segment of a third sealing ring structure with a multiple sealing ring structure around a second portion of an interconnect layer in a second region of a semiconductor element using a second set of photolithographic masks; and wherein the first segment of the third sealing ring structure and the second segment of the third sealing ring structure are coupled together such that the third sealing ring structure is laterally continuous around the interconnect layer.

[0218] As described in more detail above, some embodiments described herein provide a semiconductor element. The semiconductor element includes: a device layer comprising a semiconductor layer; one or more integrated circuit elements located within the semiconductor layer of the device layer; an interconnect layer located above the device layer and comprising: one or more dielectric layers; and one or more conductive structures located within the one or more dielectric layers, wherein at least one integrated circuit element is coupled to at least one of the one or more conductive structures; a first sealing ring structure located within the one or more dielectric layers, wherein a first segment of the first sealing ring structure has a first lateral width in a direction substantially perpendicular to the length of the first sealing ring structure, wherein a second segment of the first sealing ring structure has a second lateral width in a direction substantially perpendicular to the length of the first sealing ring structure, wherein the first lateral width and the second lateral width are different lateral widths; and a second sealing ring structure located within the one or more dielectric layers, wherein the second sealing ring structure laterally surrounds the first sealing ring structure, wherein a third segment of the second sealing ring structure has a third lateral width in a direction substantially perpendicular to the length of the second sealing ring structure, wherein a fourth segment of the second sealing ring structure has a fourth lateral width in a direction substantially perpendicular to the length of the second sealing ring structure, wherein the third lateral width and the fourth lateral width are different lateral widths.

[0219] In some embodiments, the first segment of the first sealing ring structure and the third segment of the second sealing ring structure are spaced apart from each other; wherein the first segment of the first sealing ring structure and the third segment of the second sealing ring structure are substantially parallel to each other; wherein the second segment of the first sealing ring structure and the fourth segment of the second sealing ring structure are spaced apart from each other; and wherein the second segment of the first sealing ring structure and the fourth segment of the second sealing ring structure are substantially parallel to each other.

[0220] In some embodiments, the first horizontal width is greater than the second horizontal width; and the third horizontal width is greater than the fourth horizontal width.

[0221] In some embodiments, the second horizontal width is greater than the first horizontal width; wherein the fourth horizontal width is greater than the second horizontal width.

[0222] In some embodiments, a second segment of the first sealing ring structure extends laterally toward the second sealing ring structure in a direction substantially perpendicular to the length of the first sealing ring structure; and a fourth segment of the second sealing ring structure extends laterally toward the first sealing ring structure in a direction substantially perpendicular to the length of the second sealing ring structure.

[0223] In some embodiments, the second segment of the first sealing ring structure is combined with the fourth segment of the second sealing ring structure.

[0224] In some embodiments, the first horizontal width is greater than the third horizontal width.

[0225] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0226] The nature of this disclosure is best understood from the following detailed description when read with reference to the accompanying drawings. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a diagram of an embodiment of the lithography system described herein. Figures 2A and 2B are diagrams of exemplary embodiments of the semiconductor element described herein. Figures 3A to 3L are diagrams of exemplary embodiments of the semiconductor element described herein. Figures 4A and 4B are diagrams of exemplary embodiments of the semiconductor element described herein. Figures 5A to 5K are diagrams of exemplary embodiments of the semiconductor element described herein. Figures 6A and 6B are diagrams of exemplary stacked semiconductor elements described herein. Figures 7A to 7P are diagrams of exemplary embodiments of stacked semiconductor elements described herein. Figure 8 illustrates an exemplary implementation of the mask in the multiple mask exposure technique described herein. Figures 9A and 9B are diagrams of exemplary embodiments of the semiconductor element described herein. Figure 10 is a diagram of an exemplary embodiment of the semiconductor device described herein. Figure 11 is a diagram of an exemplary embodiment of the semiconductor device described herein. Figure 12 is a diagram of an exemplary embodiment of the semiconductor device described herein. Figure 13 is a diagram of an exemplary embodiment of the semiconductor package described herein. Figure 14 is a flowchart of an exemplary process related to forming the semiconductor device described herein. Figure 15 is a flowchart of an exemplary process related to forming the semiconductor device described herein. [Biomaterial Storage]

[0228] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of forming a semiconductor device, comprising: forming one or more integrated circuit elements in a device layer of a semiconductor device; forming an interconnect layer above the device layer, wherein the interconnect layer includes one or more dielectric layers and one or more conductive structures located in the one or more dielectric layers, and wherein at least one of the integrated circuit elements is coupled to at least one of the one or more conductive structures; forming a first segment of a multi-ring structure around a first portion of the interconnect layer in a first region of the semiconductor device using a first set of photolithographic masks; and forming a second segment of the multi-ring structure around a second portion of the interconnect layer in a second region of the semiconductor device using a second set of photolithographic masks, wherein the first region and the second region are laterally adjacent in the semiconductor device, wherein the first portion and the second portion of the interconnect layer are laterally adjacent in the semiconductor device, and wherein the first segment and the second segment of the multi-ring structure are coupled together such that the multi-ring structure laterally and continuously surrounds the interconnect layer.

2. The method of claim 1, wherein the first set of photolithographic masks is used to pattern the first region of the semiconductor element and a plurality of additional first regions of a plurality of additional semiconductor elements on a semiconductor wafer; and wherein the second set of photolithographic masks is used to pattern the second region of the semiconductor element and a plurality of additional second regions of the additional semiconductor elements on the semiconductor wafer.

3. The method of claim 1, wherein forming the first segment of the multiple sealing ring structure comprises: performing a first exposure operation using a first photolithographic mask in a first set of photolithographic masks to expose the first region, thereby forming the first segment of the multiple sealing ring structure in the first region; and wherein forming the second segment of the multiple sealing ring structure comprises: after the first exposure operation, performing a second exposure operation using the first photolithographic mask in a second set of photolithographic masks to expose the second region, thereby forming the second segment of the multiple sealing ring structure in the second region.

4. The method of claim 3, wherein forming the first segment of the multiple sealing ring structure comprises: after the second exposure operation, performing a third exposure operation using a second photolithographic mask from the first set of photolithographic masks to expose the first region, thereby forming the first segment of the multiple sealing ring structure in the first region; and wherein forming the second segment of the multiple sealing ring structure comprises: after the third exposure operation, performing a fourth exposure operation using a second photolithographic mask from the second set of photolithographic masks to expose the second region, thereby forming the second segment of the multiple sealing ring structure in the second region.

5. The method of claim 1, wherein forming the first segment of the multi-ring structure comprises: forming a first segment of the first segment of the multi-ring structure having a first lateral width in a first buffer at an interface between the first region and the second region using a first set of photolithographic masks; and wherein forming the second segment of the multi-ring structure comprises: forming a second segment of the second segment of the multi-ring structure having a second lateral width in a second buffer at an interface between the first region and the second region using a second set of photolithographic masks, wherein the first segment of the first segment of the multi-ring structure and the second segment of the second segment of the multi-ring structure are coupled together at the interface.

6. A method of forming a semiconductor device, comprising: forming one or more integrated circuit elements in a device layer of a semiconductor device; forming an interconnect layer above the device layer; wherein the interconnect layer includes one or more dielectric layers and one or more conductive structures located in the one or more dielectric layers, and wherein at least one of the integrated circuit elements is coupled to at least one of the one or more conductive structures; using a first set of photolithographic masks, forming a first segment of a first sealing ring structure and a first segment of a second sealing ring structure of a multi-ring structure around a first portion of the interconnect layer in a first region of the semiconductor device. The first set of photolithographic masks is used to form the first segment of the first sealing ring structure, such that the first segment of the first sealing ring structure includes a diced segment; and the first set of photolithographic masks is used to form the first segment of the second sealing ring structure, such that the first segment of the second sealing ring structure includes a first terminal extending through the diced segment; and a second set of photolithographic masks is used to form a second segment of the first sealing ring structure and a second segment of the second sealing ring structure of the multi-sealing ring structure around a second portion of the interconnect layer in a second region of the semiconductor element, wherein the second set of photolithographic masks is used to form the second segment of the first sealing ring structure, such that the second segment of the first sealing ring structure includes a second terminal extending laterally from the second segment of the first sealing ring structure.

7. The method of claim 6, wherein the first region and the second region are laterally adjacent in the semiconductor element; wherein the first portion and the second portion of the interconnect layer are laterally adjacent in the semiconductor element; and wherein the multiple sealing ring structure laterally surrounds the interconnect layer.

8. A semiconductor element comprising: a device layer including a semiconductor layer; one or more integrated circuit elements located in the semiconductor layer of the device layer; an interconnect layer located above the device layer, including: one or more dielectric layers; and one or more conductive structures located in the one or more dielectric layers, wherein at least one of the integrated circuit elements is coupled to at least one of the one or more conductive structures; a first sealing ring structure located in the one or more dielectric layers, wherein a first segment of the first sealing ring structure has a first lateral width in a direction substantially perpendicular to a length of the first sealing ring structure, wherein a second segment of the first sealing ring structure has a second lateral width in the same direction substantially perpendicular to the length of the first sealing ring structure, wherein the first lateral width and the second lateral width are different lateral widths; and a second sealing ring structure located in the one or more dielectric layers, wherein the second sealing ring structure laterally surrounds the first sealing ring structure, wherein a third segment of the second sealing ring structure has a third lateral width in a direction substantially perpendicular to a length of the second sealing ring structure. The fourth segment of the second sealing ring structure has a fourth lateral width in a direction substantially perpendicular to the length of the second sealing ring structure, wherein the third lateral width and the fourth lateral width are different lateral widths.

9. The semiconductor element of claim 8, wherein the first segment of the first sealing ring structure and the third segment of the second sealing ring structure are spaced apart from each other; wherein the first segment of the first sealing ring structure and the third segment of the second sealing ring structure are substantially parallel to each other; wherein the second segment of the first sealing ring structure and the fourth segment of the second sealing ring structure are spaced apart from each other; and wherein the second segment of the first sealing ring structure and the fourth segment of the second sealing ring structure are substantially parallel to each other.

10. The semiconductor element as claimed in claim 8, wherein the first lateral width is greater than the second lateral width; and wherein the third lateral width is greater than the fourth lateral width.

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