Semiconductor device including a buried pattern
TW202643004APending Publication Date: 2026-10-16SAMSUNG ELECTRONICS CO LTD
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Patent Information
- Application Number
- TW114145989
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-04-01
- Filing Date
- 2025-11-25
- Publication Date
- 2026-10-16
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Abstract
There is a semiconductor device in which a logical element region and a passive element region are easily integrated. The semiconductor device which includes a first region and a second region that are different from one another, the semiconductor device including a substrate which includes an insulating pattern in the first region, and a first semiconductor pattern in the second region, a separation pattern which separates the insulating pattern and the first semiconductor pattern, between the insulating pattern and the first semiconductor pattern, a first active pattern on an upper surface of the insulating pattern, a first gate structure which intersects the first active pattern, a first source / drain region which is connected to the first active pattern, on a sidewall of the first gate structure, a second active pattern on an upper surface of the first semiconductor pattern, a second gate structure which intersects the second active pattern, a buried pattern on a lower surface of the first semiconductor pattern, a backside wiring structure on a lower surface of the insulating pattern and on a lower surface of the buried pattern and a back source / drain contact which penetrates the insulating pattern, and connects the first source / drain region and the backside wiring structure, wherein the buried pattern includes a liner film extending along profiles of the lower surface of the first semiconductor pattern and the sidewall of the separation pattern, and a buried insulating film on the liner film.
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