Package substrate and manufacturing method thereof

Abstract

A package substrate and manufacturing method thereof, the method comprises: providing a carrying element, two package structures and a plurality of isolation layers; forming symmetrically the package structures and the isolation layer on two opposite sides of the carrying element by using a lamination process; and removing the carrying element.

Description

Technical Field

[0001] This disclosure relates to a packaging substrate and its manufacturing method, and more particularly to a packaging substrate and its manufacturing method that can improve production capacity. Prior Technology

[0002] With the booming development of the electronics industry, electronic products are trending towards thinner, lighter, and smaller forms, while focusing on high performance, high functionality, and high speed. Therefore, to meet the demands for high integration and miniaturization in semiconductor devices, packaging substrates with high-density and fine-pitch circuitry are frequently used in the packaging process. However, the production capacity of existing packaging substrate manufacturing methods still cannot meet the demand, and the thickness of packaging substrates cannot be further reduced, leaving room for further improvement.

[0003] Therefore, how to overcome the problems of the aforementioned conventional methods has become an urgent issue that needs to be addressed. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a packaging substrate, comprising: providing a carrier, two packaging structures, and a plurality of insulating layers, wherein two first trace layers are formed on opposite sides of the carrier, and each of the packaging structures has two opposite wiring layers; positioning the packaging structures on opposite sides of the carrier, with the insulating layers located outside the packaging structures and between the packaging structures and the carrier, respectively; and symmetrically bonding the packaging structures and the insulating layers to opposite sides of the carrier using a lamination process, such that the first trace layers and the wiring layers are embedded in the insulating layers; and removing the carrier.

[0005] The aforementioned method for manufacturing a packaging substrate further includes forming a plurality of openings in the insulating layer after removing the carrier to expose the wiring layer.

[0006] The aforementioned method for manufacturing a packaging substrate further includes forming a plurality of conductive pillars and a circuit layer in the opening and on the insulating layer respectively using a patterning process, and electrically connecting the conductive pillars to the wiring layer, and electrically connecting the circuit layer to the first trace layer.

[0007] The aforementioned method for manufacturing a packaging substrate further includes providing two carrier units, wherein a second trace layer is formed on one side of each carrier unit.

[0008] In the aforementioned method for manufacturing a packaging substrate, the carrier units are respectively located outside the packaging structure, and the insulating layers are respectively located between the packaging structure and the carrier and between the packaging structure and the carrier units. The carrier units, the packaging structure and the insulating layers are symmetrically bonded to opposite sides of the carrier by the lamination process, so that the first trace layer, the second trace layer and the wiring layer are embedded in the insulating layer.

[0009] The aforementioned method for manufacturing a packaging substrate further includes forming a plurality of openings in the insulating layer after removing the carrier to expose the wiring layer.

[0010] In the aforementioned method of manufacturing the packaging substrate, the first trace layer or the second trace layer is further exposed outside the opening.

[0011] The aforementioned method for manufacturing a packaging substrate further includes forming a plurality of conductive pillars in the openings, and forming a circuit layer on the insulating layer and the conductive pillars, so that the conductive pillars are electrically connected to the wiring layer, and the circuit layer is electrically connected to the first trace layer and the conductive pillars, or electrically connected to the second trace layer and the conductive pillars.

[0012] The aforementioned method for manufacturing a packaging substrate further includes, after forming the conductive pillars and the circuit layer, removing the circuit layer to expose the first trace layer, the second trace layer, and the conductive pillars, so that the conductive pillars are flush with the insulating layer.

[0013] In the aforementioned method for manufacturing the packaging substrate, a portion of the first trace layer and the second trace layer are removed by an etching process, so that the height of the first trace layer and the second trace layer is lower than that of the insulating layer.

[0014] In the aforementioned method for manufacturing a packaging substrate, the packaging structure includes a core plate, an inner circuit layer and a dielectric layer disposed on opposite sides of the core plate, and a plurality of conductive vias penetrating the core plate and electrically connected to the inner circuit layer, wherein the wiring layer is disposed on the dielectric layer and electrically connected to the inner circuit layer.

[0015] This disclosure further provides a packaging substrate, comprising: a packaging structure including a core plate, an inner circuit layer and a dielectric layer disposed on opposite sides of the core plate, a plurality of conductive vias penetrating the core plate and electrically connected to the inner circuit layer, and a wiring layer disposed on the dielectric layer and electrically connected to the inner circuit layer; two insulating layers formed on opposite sides of the packaging structure and embedded therein, a plurality of conductive pillars embedded in the insulating layers and electrically connected to the wiring layers; and a first trace layer embedded in one of the insulating layers and exposed thereout.

[0016] The aforementioned packaging substrate further includes a circuit layer formed on the insulating layer and the conductive pillars and electrically connected to the first trace layer.

[0017] The aforementioned packaging substrate further includes a second trace layer embedded in the other of the insulating layer and exposed outside the insulating layer.

[0018] In the aforementioned packaging substrate, the conductive pillars are electrically connected to the first trace layer or the second trace layer.

[0019] In the aforementioned packaging substrate, the conductive pillars are flush with the insulating layer.

[0020] In the aforementioned packaging substrate, the height of the first trace layer and the second trace layer is lower than that of the insulating layer. Simple Explanation of the Diagram

[0021] Figures 1A to 1J are cross-sectional schematic diagrams of the manufacturing method of the packaging substrate disclosed herein.

[0022] Figures 2A to 2J are cross-sectional schematic diagrams of another embodiment of the method for manufacturing the packaging substrate disclosed herein. Implementation

[0023] The following specific embodiments illustrate the implementation of this disclosure. Those skilled in the art can easily understand the other advantages and effects of this disclosure from the content disclosed in this specification.

[0024] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying diagrams of this specification are merely for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which this disclosure can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," and "second" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0025] Figures 1A to 1J are cross-sectional schematic diagrams of the manufacturing method of the packaging substrate 100 disclosed herein.

[0026] As shown in Figure 1A, a carrier 9, two encapsulation structures 2, and four insulating layers 3 are provided. The two encapsulation structures 2 are respectively disposed on opposite sides of the carrier 9, and two of the insulating layers 3 are disposed between one side of the encapsulation structure 2 and the carrier 9, and the other two insulating layers 3 are respectively disposed on the other side of the encapsulation structure 2.

[0027] The carrier 9 has a plate 90, two release layers 91 and two metal layers 92. The release layers 91 are formed on two opposite surfaces of the plate 90, and the metal layers 92 are formed on the release layers 91. A first trace layer 11 is formed on the metal layers 92.

[0028] In this embodiment, the carrier 9 is a temporary carrier plate, and its plate body 90 may be, for example, an organic polymer plate containing bis(cis-butadiene)imide / triazine (BT), glass fiber prepreg (PP), or other plates. The release layer 91 may be, for example, a thick copper layer of copper foil, and the metal layer 92 may be, for example, a thin copper layer, which is formed on the release layer 91 by electroplating or deposition.

[0029] The package structure 2 includes a core board 20, an inner circuit layer 21, a dielectric layer 22, a wiring layer 23, and conductive vias 200. The conductive vias 200 extend through opposite sides of the core board 20. The inner circuit layer 21 and the dielectric layer 22 are formed on opposite sides of the core board 20, and the inner circuit layer 21 is electrically connected to the conductive vias 200. The wiring layer 23 is formed on the dielectric layer 22 and is electrically connected to the inner circuit layer 21.

[0030] In this embodiment, a patterned resist layer with openings is first formed on opposite sides of the core board 20, and an inner circuit layer 21 is formed within these openings by electroplating metal (such as copper) or other methods. The patterned resist layer is then removed. Next, a dielectric layer 22 is formed on opposite sides of the core board 20, and a plurality of blind vias exposing the inner circuit layer 21 are formed on the dielectric layer 22 using a laser. Finally, copper is electroplated in the dielectric layer 22 and the blind vias to form a wiring layer 23, which adopts a redistribution layer (RDL) specification.

[0031] The dielectric layer 22 is an Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP), or other dielectric materials.

[0032] Furthermore, the conductive via 200 is a hollow column, and the hollow portion can be filled with a plugging material 201. The plugging material 201 can be of various types, such as conductive adhesives or inks, and is not particularly limited. It should be understood that in other embodiments, the conductive via 200 can also be a solid metal column without the need to fill it with plugging material 201. For example, the material forming the ink mainly comprises epoxy ink composites, which have a viscosity of 25 to 55 Pa·s, a glass transition temperature (Tg) of 145 to 180°C, and / or a Young's modulus of 3-10 GPa.

[0033] The insulating layer 3 is a dielectric layer, such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials. A metal layer 31, which is copper, is also formed on one of the outermost insulating layers 3.

[0034] As shown in Figure 1B, the packaging structure 2 and the insulating layer 3 are symmetrically bonded to the opposite sides of the carrier 9 by a lamination process, so that the first trace layer 11 and the wiring layer 23 are embedded in the insulating layer 3, and the metal layer 31 is located on the outermost side.

[0035] As shown in Figure 1C, the carrier 9 is removed to obtain the two intermediate structures 1. Specifically, the release layer 91 can be used to separate the plate 90 and the metal layer 92, leaving the metal layer 92 on one of the surfaces of the insulating layer 3.

[0036] As shown in Figure 1D, a plurality of openings 32 are formed by laser in the insulating layers 3 on both sides of the intermediate structure 1, and the openings 32 expose the wiring layer 23.

[0037] As shown in Figure 1E, copper is electroplated into the opening 32, so that the copper and metal layers 31 and 92 together serve as the seed layer 33.

[0038] As shown in Figure 1F, a patterned resist layer 34, resembling a dry film, is formed on the seed layer 33.

[0039] As shown in Figure 1G, copper is electroplated onto the patterned resist layer 34 and the seed layer 33 in the opening 32 to form conductive pillars 35 and circuit layer 36. The conductive pillars 35 are electrically connected to the wiring layer 23, and the circuit layer 36 is located on the conductive pillars 35 and the insulating layer 3, and is electrically connected to the first trace layer 11.

[0040] As shown in Figure 1H, the patterned resist layer 34 is removed, exposing the seed layer 33, and the circuit layer 36 protrudes from the surface of the insulating layer 3.

[0041] As shown in Figure 1I, a portion of the seed layer 33 on the insulating layer 3 is removed by a double-sided etching process, exposing the insulating layer 3, while retaining the seed layer 33 under the circuit layer 36 and in the opening 32.

[0042] As shown in Figure 1J, a solder resist layer 37, which is like a solder resist material, is formed on the insulating layer 3. The solder resist layer 37 has an opening to expose a portion of the circuit layer 36, so that the exposed circuit layer 36 can serve as an electrical contact pad, thereby obtaining the package substrate 100 disclosed herein.

[0043] Figures 2A to 2J are cross-sectional schematic diagrams of another embodiment of the manufacturing method of the packaged substrate 100' disclosed herein. The following only describes the differences between this embodiment and the embodiments described in Figures 1A to 1J above; the same technical content will not be repeated here.

[0044] As shown in Figure 2A, a carrier element 9, two encapsulation structures 2, four insulating layers 3, and two carrier units 4 are provided. The two encapsulation structures 2 are respectively disposed on opposite sides of the carrier element 9, and two of the insulating layers 3 are disposed between the encapsulation structure 2 and the carrier element 9. The two carrier units 4 are respectively disposed on the outer side of the encapsulation structure 2, and the other two of the insulating layers 3 are respectively disposed between the encapsulation structure 2 and the carrier unit 4.

[0045] The carrier 9 has a plate 90, two release layers 91 and two metal layers 92. The release layers 91 are formed on two opposite surfaces of the plate 90, and the metal layers 92 are formed on the release layers 91. A first trace layer 11 is formed on the metal layers 92.

[0046] The package structure 2 includes a core board 20, an inner circuit layer 21, a dielectric layer 22, a wiring layer 23, and conductive vias 200. The conductive vias 200 extend through opposite sides of the core board 20. The inner circuit layer 21 and the dielectric layer 22 are formed on opposite sides of the core board 20, and the inner circuit layer 21 is electrically connected to the conductive vias 200. The wiring layer 23 is formed on the dielectric layer 22 and is electrically connected to the inner circuit layer 21.

[0047] In this embodiment, a patterned resist layer with openings is first formed on opposite sides of the core board 20, and an inner circuit layer 21 is formed within these openings by electroplating metal (such as copper) or other methods. The patterned resist layer is then removed. Next, a dielectric layer 22 is formed on opposite sides of the core board 20, and a plurality of blind vias exposing the inner circuit layer 21 are formed on the dielectric layer 22 using a laser. Finally, copper is electroplated in the dielectric layer 22 and the blind vias to form a wiring layer 23, which adopts a redistribution layer (RDL) specification.

[0048] The dielectric layer 22 is an Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP), or other dielectric materials.

[0049] Furthermore, the conductive via 200 is a hollow column, and the hollow space can be filled with a plugging material 201. The plugging material 201 can be of various types, such as conductive adhesive or ink, and is not particularly limited. It should be understood that in other embodiments, the conductive via 200 can also be a solid metal column, without the need to fill it with plugging material 201.

[0050] Insulating layer 3 is a dielectric layer, such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0051] The carrier unit 4 has a plate 40, a release layer 41, and a metal layer 42. The release layer 41 is formed on one surface of the plate 40, and the metal layer 42 is formed on the release layer 41. A second trace layer 12 is formed on the metal layer 42. The carrier unit 4 is located outside the insulating layer 3 with the second trace layer 12 facing the insulating layer 3.

[0052] In this embodiment, the support unit 4 and the support member 9 are temporary carrier plates. The plates 40 and 90 can be, for example, organic polymer plates containing bis(maleimide) triazine (BT), glass fiber prepreg (PP), or other plates. The release layers 41 and 91 can be, for example, thick copper layers of copper foil, and the metal layers 42 and 92 can be, for example, thin copper layers, which are formed on the release layers 41 and 91 by electroplating or deposition.

[0053] As shown in Figure 2B, the packaging structure 2, the insulating layer 3, and the carrier unit 4 are symmetrically bonded to opposite sides of the carrier 9 using a lamination process, so that the first trace layer 11 and the wiring layer 23 are embedded in the insulating layer 3 located between the packaging structure 2 and the carrier 9, and the second trace layer 12 and the wiring layer 23 on the other side are embedded in the insulating layer 3 located between the packaging structure 2 and the carrier unit 4.

[0054] As shown in Figure 2C, the carrier 9 is removed to obtain the two intermediate structures 1'. Specifically, the release layer 91 can be used to separate the plate 90 and the metal layer 92, leaving the metal layer 92 on one of the surfaces of the insulating layer 3.

[0055] As shown in Figure 2D, a plurality of openings 32 can be laser-formed in the insulating layer 3 above the intermediate structure 1', exposing the wiring layer 23 and the first trace layer 11. Then, the plate 40 and the metal layer 42 can be separated by the release layer 41, leaving the metal layer 42 on one surface of the other insulating layer 3. Finally, a plurality of openings 32 are laser-formed in the insulating layer 3 below the intermediate structure 1', exposing the wiring layer 23 and the second trace layer 12. Forming the upper opening 32 on the carrier unit 4 first facilitates the laser alignment of the lower opening 32, making it suitable for small-sized laser apertures.

[0056] As shown in Figure 2E, copper is electroplated into the opening 32 to form a seed layer 33, and the seed layer 33 is connected to the first trace layer 11 and the second trace layer 12.

[0057] As shown in Figure 2F, copper is electroplated onto the seed layer 33 and metal layers 42 and 92 in the opening 32 to form conductive pillars 35 and circuit layers 36. The conductive pillars 35 are electrically connected to the wiring layer 23, the upper circuit layer 36 is electrically connected to the first trace layer 11 and the conductive pillars 35, and the lower circuit layer 36 is electrically connected to the second trace layer 12 and the conductive pillars 35.

[0058] As shown in Figure 2G, the circuit layer 36 and metal layers 42 and 92 are removed by a double-sided etching process, exposing the first trace layer 11, the second trace layer 12, the conductive pillar 35 and the insulating layer 3. The conductive pillar 35, the first trace layer 11 and the insulating layer 3 are made flush, and the conductive pillar 35, the second trace layer 12 and the insulating layer 3 are made flush.

[0059] As shown in Figure 2H, a patterned resist layer 34, resembling a dry film, is formed on the insulating layer 3 and the conductive pillar 35. The patterned resist layer 34 exposes only the first trace layer 11 and the second trace layer 12 adjacent to the conductive pillar 35.

[0060] As shown in Figure 2I, the first trace layer 11 and the second trace layer 12 are partially removed by a double-sided etching process, so that the height of the first trace layer 11' and the second trace layer 12' adjacent to the conductive pillar 35 is lower than that of the insulating layer 3.

[0061] As shown in Figure 2J, the patterned resist layer 34 is first removed, and a solder resist layer 37, which is like a solder resist material, is formed on the insulating layer 3. The solder resist layer 37 has openings to expose the first trace layer 11', the second trace layer 12', and the conductive pillars 35, thereby obtaining the package substrate 100' disclosed herein.

[0062] In summary, the packaging substrate 100 disclosed herein allows the first trace layer 11 to be embedded within the insulating layer 3, and the circuit layer 36, serving as an electrical contact pad, to protrude from the insulating layer 3. This is suitable for designs where solder balls are placed on electrical contact pads, and it offers better copper adhesion compared to conventional substrates of the prior art. It is also suitable for small-sized ball placement operations within the solder mask layer 37. Furthermore, this disclosure involves first forming the first trace layer 11 on both sides of the carrier 9, then stacking and laminating the insulating layer 3 and the packaging structure 2, and finally removing the carrier 9 to obtain twice the amount of the intermediate structure 1, effectively doubling the production capacity.

[0063] Furthermore, the packaging substrate 100' disclosed herein allows the first trace layer 11', the second trace layer 12', and the conductive pillar 35 to be embedded within the insulating layer 3, making it suitable for bump-on-trace designs and offering a thinner profile compared to conventional substrates or the aforementioned packaging substrate 100. Moreover, since the height of the first trace layer 11' and the second trace layer 12' adjacent to the conductive pillar 35 is lower than the insulating layer 3, and the conductive pillar 35 protrudes from the first trace layer 11' and the second trace layer 12', the electrical contact pads formed by the conductive pillar 35, the first trace layer 11', and the second trace layer 12' have a larger specific surface area, which improves the adhesion of solder balls after reflow and avoids reliability risks. Furthermore, this disclosure involves first forming a first trace layer 11 on both sides of the carrier 9 and a second trace layer 12 on one side of the carrier unit 4, then stacking and pressing the insulating layer 3 and the encapsulation structure 2 together, and then removing the carrier 9 and the carrier unit 4 to obtain twice the amount of intermediate structure 1', effectively doubling the production capacity.

[0064] The above embodiments are illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be as set forth in the following patent application claims.

[0065]

[0066] 100,100': Packaging substrate

[0067] 1,1': Mediation Structure

[0068] 11,11': First trace layer

[0069] 12,12': Second trace layer

[0070] 2: Packaging Structure

[0071] 20: Core Plate

[0072] 200: Conductive via

[0073] 201: Pore plugging material

[0074] 21: Inner Circuit Layer

[0075] 22: Dielectric layer

[0076] 23: Wiring Layer

[0077] 3: Insulation layer

[0078] 31,42,92: Metallic layer

[0079] 32: Opening

[0080] 33: Seed layer

[0081] 34: Patterned resist layer

[0082] 35: Conductive column

[0083] 36: Line Layer

[0084] 37: Solder resist layer

[0085] 4: Bearing unit

[0086] 40,90: plate body

[0087] 41,91: Release layer

[0088] 9: Load-bearing components

Claims

1. A method for manufacturing a packaging substrate, comprising: A carrier, two encapsulation structures, two carrier units, and a plurality of insulating layers are provided. Two first trace layers are formed on opposite sides of the carrier, a second trace layer is formed on one side of each carrier unit, and each encapsulation structure has two opposite wiring layers. The encapsulation structures are positioned on opposite sides of the carrier, the carrier units are positioned outside the encapsulation structures, and the insulating layers are positioned between the encapsulation structure and the carrier units, and between the encapsulation structure and the carrier. The carrier units, the encapsulation structure, and the insulating layers are symmetrically bonded to opposite sides of the carrier using a lamination process, such that the first trace layers, the second trace layers, and the wiring layers are embedded in the insulating layers. The carrier is then removed.

2. The method of manufacturing the packaging substrate as described in claim 1 further includes forming a plurality of openings in the insulating layer after removing the carrier to expose the wiring layer.

3. The method for manufacturing the packaging substrate as described in claim 2 further includes forming a plurality of conductive pillars and a circuit layer in the opening and on the insulating layer respectively by a patterning process, and electrically connecting the conductive pillars to the wiring layer, and electrically connecting the circuit layer to the first trace layer.

4. The method of manufacturing the packaging substrate as described in claim 1 further includes forming a plurality of openings in the insulating layer after removing the carrier to expose the wiring layer.

5. The method for manufacturing the packaging substrate as described in claim 4, wherein, The first trace layer or the second trace layer is further exposed outside the opening.

6. The method of manufacturing the packaging substrate as described in claim 4 further includes forming a plurality of conductive pillars in the openings, and forming a circuit layer on the insulating layer and the conductive pillars, such that the conductive pillars are electrically connected to the wiring layer, and the circuit layer is electrically connected to the first trace layer and the conductive pillars, or electrically connected to the second trace layer and the conductive pillars.

7. The method of manufacturing a packaging substrate as described in claim 6 further includes, after forming the conductive pillars and the circuit layer, removing the circuit layer to expose the first trace layer, the second trace layer and the conductive pillars, and making the conductive pillars flush with the insulating layer.

8. The method for manufacturing the packaging substrate as described in claim 7, further comprising removing a portion of the first trace layer and the second trace layer by an etching process, such that the height of the first trace layer and the second trace layer is lower than that of the insulating layer.

9. A method for manufacturing the packaging substrate as described in claim 1, wherein, The packaging structure includes a core board, an inner circuit layer and a dielectric layer disposed on opposite sides of the core board, and a plurality of conductive vias penetrating the core board and electrically connected to the inner circuit layer, wherein the wiring layer is disposed on the dielectric layer and electrically connected to the inner circuit layer.

10. A packaging substrate, comprising: The packaging structure includes a core board, an inner circuit layer and a dielectric layer disposed on opposite sides of the core board, a plurality of conductive vias penetrating the core board and electrically connected to the inner circuit layer, and a wiring layer disposed on the dielectric layer and electrically connected to the inner circuit layer; two insulating layers formed on opposite sides of the packaging structure and embedded with the wiring layer; a plurality of conductive pillars embedded in the insulating layers and electrically connected to the wiring layer; a first trace layer embedded in one of the insulating layers and exposed outside the insulating layer; and a second trace layer embedded in the other of the insulating layers and exposed outside the insulating layer; wherein a portion of the first trace layer and a portion of the second trace layer are flush with the insulating layer.

11. The packaging substrate as claimed in claim 10 further includes a circuit layer formed on the insulating layer and the conductive pillars and electrically connected to the first trace layer.

12. The packaging substrate as described in claim 10, wherein, The conductive pillar is electrically connected to the first trace layer or the second trace layer.

13. The packaging substrate as described in claim 10, wherein, The conductive post is flush with the insulating layer.

14. The packaging substrate as described in claim 10, wherein, The height of a portion of the first trace layer and a portion of the second trace layer is lower than that of the insulating layer.

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