Sequential read mode static random access memory (SRAM)

Abstract

This invention discloses a structure including a sequential read controller configured to receive a sequential read enable burst signal and an initial word line address, identify sequential read operations from a memory cell array accessed via a plurality of word lines, precharge the plurality of bit lines of the memory cell no more than once during the sequential read operation, and keep one word line active throughout the sequential read operation. The sequential read enable burst signal and the initial word line address are decoded to select a column of addresses and initiate the corresponding word line from the plurality of word lines in the array.

Description

[Technical Field] This invention relates to sequential read modes in static random access memory (SRAM), and more specifically, to circuits and methods for using burst mode in SRAM to save power and improve performance associated with address switching and decoding. [Previous Technology] Memory devices are used as internal storage areas in computers or other electronic devices. A specific type of memory used to store data in a computer is random access memory (RAM). RAM is usually used as the main memory in a computer environment and is typically volatile because all data stored in RAM will be lost once the power is turned off. Static random access memory (SRAM) is a type of RAM that has the advantage of storing data without needing to be refreshed. A typical SRAM device consists of an array of SRAM cells. Each SRAM cell can store a binary voltage value representing a logical data bit (e.g., "0" or "1"). Energy efficiency, requiring lower power consumption within SRAM, is a challenge; for example, typical machine learning applications demand lower power consumption and faster memory access. In typical deep neural network hardware, memory is used to store weight parameters and startup as input propagates through the network. Typical neural network applications use SRAM to store weights and startup, with these weights stored in contiguous (i.e., adjacent) locations to address spatial locality. Furthermore, typical deep learning architectures read the entire layer matrix linearly and use this data to generate the next layer. Applications employing sequential access instead of fully random access achieve power savings and performance enhancements (higher bandwidth), where signals are generated in parallel across multiple adjacent words (i.e., multiple columns connected to a single sense amplifier), and control circuitry can continuously sense these words in burst patterns. [Summary of the Invention] In one embodiment of the invention, a structure includes a sequential read controller configured to receive a sequential read enable burst signal and an initial word line address, identify sequential read operations from a memory cell array accessed via a plurality of word lines, precharge the plurality of bit lines of the memory cells no more than once during the sequential read operation, and keep one word line active throughout the sequential read operation. The sequential read enable burst signal and the initial word line address are decoded to select a column of addresses and initiate the corresponding word line from the plurality of word lines in the array. In another embodiment of the invention, a circuit includes a memory cell array disposed in a plurality of columns and a plurality of fields, and a read controller configured to operate in a burst mode, precharge a plurality of bit lines of the memory cells no more than once during a sequential read operation, and keep one word line among the plurality of word lines active throughout the sequential read operation. The word lines correspond to the columns, and the bit lines correspond to the fields. In another embodiment of the present invention, a method includes operating a static random access memory (SRAM) in a burst mode, precharging a plurality of bit lines in the SRAM no more than once during a successive sequential read operation, and keeping one of the plurality of word lines active throughout the successive sequential read operation. [Simplified Explanation of the Diagram] The invention is described in the following detailed description with reference to numerous figures, using non-limiting examples of specific embodiments of the invention. Figure 1A shows a static random access memory read operation of a multiplexer according to the present invention. Figure 1B shows another multiplexer static random access memory read operation according to the present invention. Figure 2 shows a comparison between the timing diagram of the static random access memory read operation of the multiplexer according to the present invention and a conventional timing diagram. Figure 3 shows a control block system within the static random access memory of the multiplexer according to the present invention. Figure 4 shows the waveform of the static random access memory read operation of the multiplexer according to the present invention. Figure 5 illustrates a high-decoding domino sensing operation according to the present invention. Figure 6 shows a circuit diagram of the high-decoding domino sensing operation according to the present invention.

Implementation Method

Claims

1. A memory architecture including a sequential read controller configured to receive a sequential read enable burst signal and a start word line address, identify sequential read operations from a memory cell array accessed via a plurality of word lines, precharge a plurality of bit lines of the memory cells no more than once during the sequential read operations, and keep one of the word lines active throughout the sequential read operations, wherein the sequential read enable burst signal and the start word line address are decoded to select a column of addresses and initiate corresponding word lines from the plurality of word lines in the memory cell array, wherein the sequential read controller includes an SR (set reset) latch that receives a burst enable signal and an inverting set amplifier set signal and outputs an SR output signal to a multiplexer that receives the SR output signal and the burst enable signal and outputs a multiplexer output signal to enable a path selector.

2. The structure as described in claim 1, wherein the continuous read operations include a burst mode.

3. The structure as described in claim 2, wherein the sequential read operations include reading a plurality of adjacent column addresses.

4. The structure as described in claim 3, wherein the plurality of adjacent field addresses are read sequentially.

5. The structure as described in claim 4, wherein the sequential mode read controller is configured to save power associated with field address switching.

6. The structure of claim 5, wherein the power associated with column address switching includes power associated with word line switching and power associated with bit line restoration.

7. The structure of claim 6, wherein the sequential mode read controller is configured to iterate through the field addresses during the burst mode.

8. The structure of claim 1, wherein the read controller is configured to prevent the bit lines from floating by keeping the word lines active throughout the continuous read operations.

9. The structure as described in claim 1, wherein the structure is a static random access memory (SRAM).

10. A memory circuit, comprising: An array of storage cells is arranged in a plurality of columns and a plurality of fields; a read controller is configured to operate in a burst mode, precharge a plurality of bit lines of the storage cells no more than once during a series of sequential read operations, and keep one word line of a plurality of word lines active throughout the series of sequential read operations, wherein the word lines correspond to the columns and the bit lines correspond to the fields, wherein the read controller includes an SR (set reset) latch that receives a burst enable signal and an inverting set amplifier setting signal and outputs an SR output signal to a multiplexer that receives the SR output signal and the burst enable signal and outputs a multiplexer output signal to enable a path selector.

11. The circuit of claim 10, wherein the read controller is further configured to receive a precharge signal and a word line pulse signal.

12. The circuit of claim 11, wherein the read controller is further configured to identify the sequential read operations from the array of memory cells accessed through the plurality of word lines.

13. The circuit of claim 12, wherein the read controller is configured to save power associated with field address switching.

14. The circuit of claim 10, wherein the read controller is configured to prevent the bit lines from floating by keeping the word lines active throughout the entire sequence of read operations.

15. The circuit of claim 10, wherein the circuit is a static random access memory (SRAM).

16. A method for operating a static random access memory, comprising: Operating the static random access memory (SRAM) in a burst mode; precharging a plurality of bit lines in the SRAM no more than once during consecutive sequential read operations; and maintaining one word line active throughout the entire series of consecutive sequential read operations, wherein operating the SRAM in the burst mode further includes: receiving a burst enable signal and an inverting set amplifier setting signal from an SR latch of one of the SRAMs; outputting an SR output signal from the SR latch to a multiplexer of the SRAMs; receiving the SR output signal and the burst enable signal from the multiplexer; and outputting a multiplexer output signal from the multiplexer to a path selector to enable the path selector.

17. The method of claim 16, wherein the operation of the SRAM within the burst mode further includes: Using a single address to set the timing, a first read operation is performed in the first column of the SRAM array; And when the address setting timing is cleared, a second read operation is performed in the second column of the array adjacent to the first column of the SRAM array, wherein the second read operation is a domino sensing read that provides lower power and faster read operation than the first read operation.

18. The method of claim 17 further includes performing a third read operation in the third column of the array adjacent to the second column of the SRAM array when the address setting timing is eliminated.

19. The method of claim 18, wherein the third read operation is another domino sensing read that provides lower power consumption and faster read operation than the first read operation.

20. The method of claim 17, wherein the domino sensing readout establishes a bit line differential by inverting a bit line value to provide lower power consumption and faster readout operation.

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