Signal conversion circuit utilizing switched capacitors

Abstract

A signal conversion circuit includes a first capacitor pair and a comparator. The first capacitor pair includes a first capacitor and a second capacitor having the same capacitance value. Both the first capacitor and the second capacitor are coupled to an input signal during a first sampling phase, and are not coupled to the input signal during a first conversion phase following the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, and the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal. The comparator is used to compare the signal level of the first input terminal with the signal level of the second input terminal to convert the input signal.

Description

[Technical Field]

[0001] This disclosure relates to signal conversion, and more particularly to a signal conversion circuit employing a switching capacitor. [Previous Technology]

[0002] Due to their low power consumption, simple structure, and small form factor, successive-approximation register analog-to-digital converters (SAR ADCs) are favored in system-on-chip (SoC) designs. The basic operating principle of a successive-approximation register analog-to-digital converter is to use a series of comparison operations to implement a binary search algorithm, thereby determining each bit of the digital output converted from an analog input. For example, before the conversion result of the successive-approximation register analog-to-digital converter converges to the digital output, the signal level of the analog input can be compared with multiple different quantization levels, which are generated for different digital codes. The number of bit cycles required to convert the analog input can be determined based on the resolution of the successive-approximation register analog-to-digital converter. [Summary of the Invention]

[0003] The embodiments disclosed herein provide a signal conversion circuit comprising a switched-capacitor digital-to-analog converter (switched-capacitor DAC) structure. This signal conversion circuit can perform signal conversion using either bottom-board sampling or top-board sampling. Furthermore, this signal conversion circuit can be used to implement at least a portion of an analog-to-digital converter. The analog-to-digital converter can be (but is not limited to) a successive approximation analog-to-digital converter, a pipeline analog-to-digital converter (ADC), or a delta-Sigma analog-to-digital converter (ADC).

[0004] Some embodiments of this disclosure include a signal conversion circuit comprising a first capacitor pair and a comparator. The first capacitor pair comprises a first capacitor and a second capacitor having the same capacitance value. Both the first capacitor and the second capacitor are coupled to an input signal during a first sampling stage, and are not coupled to the input signal during a first conversion stage following the first sampling stage. The comparator has a first input terminal and a second input terminal. During the first conversion stage, the first capacitor is coupled between the first input terminal and a first reference signal, and the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal. The comparator is used to compare the signal level of the first input terminal with the signal level of the second input terminal to convert the input signal.

[0005] Some embodiments of this disclosure include a signal conversion circuit comprising a first capacitor pair and a comparator. The first capacitor pair comprises a first capacitor and a second capacitor having the same capacitance value. In a first sampling phase, the first capacitor is coupled between an input signal and a first reference signal, and the second capacitor is coupled between the input signal and a second reference signal different from the first reference signal. The comparator has a first input terminal and a second input terminal. In a first conversion phase following the first sampling phase, both the first capacitor and the second capacitor are coupled to the first input terminal but not coupled to the input signal, and the comparator is used to compare the signal level of the first input terminal with the signal level of the second input terminal to convert the input signal.

[0006] The signal conversion scheme provided in this disclosure can significantly reduce the power consumption caused by the high-power register used to store common-mode voltage. In addition, the signal conversion scheme provided in this disclosure can exchange the reference signals applied to the two capacitors in the same capacitor pair according to different conversion cycles, so as to reduce the impact of capacitor mismatch. [Simplified Explanation of the Diagram]

[0075] The various embodiments disclosed herein can be clearly understood by reading the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of certain features may be arbitrarily enlarged or reduced for clear description.

[0076] FIG1 is a functional block diagram of an exemplary signal conversion circuit according to certain embodiments of the present disclosure.

[0077] FIG2 is a schematic diagram of an embodiment of the digital-to-analog converter shown in FIG1 according to certain embodiments of the present disclosure.

[0078] Figures 3A and 3B are schematic diagrams of the operation of the digital-to-analog converter shown in Figure 2 according to certain embodiments of the present disclosure.

[0079] Figures 3C and 3D are schematic diagrams of the operation of the digital-to-analog converter shown in Figure 2 according to certain embodiments of the present disclosure.

[0080] FIG4 is a schematic diagram of another embodiment of the digital-to-analog converter shown in FIG1 according to certain embodiments of the present disclosure.

[0081] Figures 5A and 5B are schematic diagrams of the operation of the digital-to-analog converter shown in Figure 4 according to certain embodiments of the present disclosure.

[0082] FIG6 is a schematic diagram of another embodiment of the digital-to-analog converter shown in FIG1 according to certain embodiments of the present disclosure.

[0083] FIG7 is a schematic diagram of the operation of the digital-to-analog converter shown in FIG6 according to certain embodiments of the present disclosure.

[0084] FIG8 is a schematic diagram of another embodiment of the digital-to-analog converter shown in FIG1 according to certain embodiments of the present disclosure.

[0085] FIG9 is a schematic diagram of the operation of the digital-to-analog converter shown in FIG8 according to certain embodiments of the present disclosure.

[0086] FIG10 is a schematic diagram of another embodiment of the digital-to-analog converter shown in FIG1 according to certain embodiments of the present disclosure.

[0087] FIG11 is a schematic diagram of the operation of the digital-to-analog converter shown in FIG10 according to certain embodiments of the present disclosure.

[0088] FIG12 is a schematic diagram of the operation of the digital-to-analog converter shown in FIG10 according to certain embodiments of the present disclosure.

[0089] FIG13 is a schematic diagram of the operation of the digital-to-analog converter shown in FIG2 according to certain embodiments of the present disclosure at different conversion cycles.

Implementation Method

[0007] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of parameter values, components, and configurations described below are used to simplify this disclosure. It is understood that these descriptions are merely illustrative and are not intended to limit the scope of this disclosure. For example, component symbols and / or reference numerals may be reused in embodiments. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0008] Furthermore, it is understood that if a component is described as being "connected to" or "coupled to" another component, then the two components may be directly connected or coupled, or there may be other intervening components between them.

[0009] An N-bit successive approximation analog-to-digital converter (DTC) can utilize a conversion cycle (which includes a sampling phase and a conversion phase) to convert an analog input to produce an N-bit digital output. The analog input is acquired in the sampling phase, while the N bits of the digital output can be determined separately over N bit cycles in the conversion phase. To further reduce power consumption, the digital-to-analog converter in an N-bit successive approximation DTC can be implemented using a capacitive digital-to-analog converter (CDAC). For example, an N-bit successive approximation analog-to-digital converter can be an N-bit analog-to-digital converter with multiple differential inputs. This capacitive CDAC can convert the multiple differential inputs in the conversion phase using a common-mode voltage of the multiple differential inputs. The common-mode voltage should stabilize at the end of each bit cycle in the conversion phase. However, as the resolution of N-bit approximation analog-to-digital converters increases, the time allotted for stabilizing the common-mode voltage becomes insufficient. Therefore, a high-power-hungry register is needed to store this common-mode voltage.

[0010] This disclosure provides exemplary signal conversion circuits, wherein each exemplary signal conversion circuit includes a pair of capacitors having the same capacitance value (or weighted value) to perform signal conversion operations. The capacitor pair may be electrically connected to a first reference signal and a second reference signal different from the first reference signal. When an exemplary signal conversion circuit is at least part of a successive approximation analog-to-digital converter, the exemplary signal conversion circuit may utilize the capacitor pair (instead of utilizing a capacitor electrically connected to a common-mode voltage) to perform a binary search algorithm in at least one of a sampling phase and a conversion phase in a conversion cycle. That is, the capacitor pair can replace the capacitor electrically connected to the common-mode voltage. Therefore, a high-power register for storing the common-mode voltage is unnecessary.

[0011] In some embodiments, both the first reference signal and the second reference signal are different from the common-mode voltage. For example, the first reference signal and the second reference signal may be two supply voltages supplied to a successive approximation analog-to-digital converter. In some embodiments, the capacitor pair may be provided by splitting the capacitor (which is electrically connected to the common-mode voltage). For example, the capacitance value of each capacitor in the capacitor pair may be equal to half the capacitance value of the capacitor electrically connected to the common-mode voltage. In some embodiments, the capacitor pair may be switched to perform signal conversion operations using a bottom-plate sampling scheme or a top-plate sampling scheme. In some embodiments, when the exemplary signal conversion circuit operates at different conversion cycles, the signals coupled to a first capacitor and a second capacitor in the capacitor pair may be swapped to reduce the effects of capacitor mismatch.

[0012] The signal conversion scheme provided in this disclosure can be applied to a switched-capacitor circuit, wherein the switched-capacitor circuit originally required a third reference signal different from the first reference signal and the second reference signal. Furthermore, the signal conversion scheme provided in this disclosure can operate in differential mode or single-ended mode to perform the signal conversion operation. Further explanation follows.

[0013] FIG1 is a functional block diagram of an exemplary signal conversion circuit according to certain embodiments of the present disclosure. The signal conversion circuit 100 is used to convert an input signal AIN into an output signal DOUT. In this embodiment, the signal conversion circuit 100 may be implemented as an N-bit successive approximation analog-to-digital converter, where N is a positive integer. The input signal AIN may be an analog voltage, and the output signal DOUT may be an N-bit digital word. The signal conversion circuit 100 may sample the input signal AIN in a sampling phase during a conversion cycle, and convert the input signal AIN into the input signal DOUT in a conversion phase after the sampling phase during the conversion cycle.

[0014] The input signal AIN can be a differential signal or a single-ended signal. The signal conversion circuit 100 can use differential mode or single-ended mode to convert the input signal AIN. In this embodiment, the input signal AIN can be implemented as a differential signal comprising a plurality of voltage signals VIP and VIN. One of the plurality of voltage signals VIP and VIN can be the positive component of the differential signal, and the other of the plurality of voltage signals VIP and VIN can be the negative component of the differential signal. The signal conversion circuit 100 can operate in differential mode to perform the signal conversion operation. However, this is not intended to limit the scope of this disclosure. In some embodiments where the input signal AIN is implemented as a single-ended signal, the signal conversion circuit 100 can use single-ended mode to perform the signal conversion operation without departing from the scope of this disclosure.

[0015] The signal conversion circuit 100 includes (but is not limited to) a comparator 110, a controller 120, and a digital-to-analog converter 130. The comparator 110 has an input terminal TM, an input terminal TP, and an output terminal TC, and is used to compare the signal level of the input terminal TM with the signal level of the input terminal TP to output a comparison result CR from the output terminal TC. The controller 120 is coupled to the comparator 110 and is used to generate an output signal DOUT based on the comparison result CR. The controller 120 is also used to generate a plurality of digital signals SD1 and SD2 based on the comparison result CR, wherein the plurality of digital signals SD1 and SD2 can both be multi-bit digital signals.

[0016] A digital-to-analog converter 130 is coupled to comparator 110 and controller 120 to convert a plurality of digital signals SD1 and SD2 and generate an analog output accordingly, wherein the analog output may include a voltage signal VXM at input terminal TM and a voltage signal VXP at input terminal TP. In this embodiment, the digital-to-analog converter 130 may be an (N-1)-bit digital-to-analog converter implemented using a switched-capacitor structure. The digital-to-analog converter 130 may include a plurality of switched capacitor arrays 132 and 134, and a plurality of switching circuits 136.1, 136.2, 138.1, and 138.2.

[0017] The switchable capacitor array 132 includes (N-1) capacitor pairs CPM1 to CPM(N-1), wherein each capacitor pair includes a plurality of capacitors (i.e., one of the plurality of capacitors CM11 to CM1(N-1) and one of the plurality of capacitors CM21 to CM2(N-1)). Each capacitor includes a terminal N11 and a terminal N12. The plurality of capacitors in the same capacitor pair may have the same or substantially the same capacitance value. In addition, the (N-1) capacitor pairs CPM1 to CPM(N-1) may have binary weighted capacitance values. For example, the signal level of each of the multiple terminals N11 of capacitor pair CPM(N-1) can correspond to the bit value of the most significant bit (MSB) of the output signal DOUT, while the signal level of each of the multiple terminals N11 of capacitor pair CPM1 can correspond to the bit value of the least significant bit (LSB) of the output signal DOUT. Each of capacitors CM1i and CM2i can have a capacitance value equal to half the capacitance value of each of capacitors CM1(i+1) and CM2(i+1), where i is an integer between 1 and (N-2).

[0018] Similarly, the switching capacitor array 134 includes (N-1) capacitor pairs CPP1 to CPP(N-1), wherein each capacitor pair includes a plurality of capacitors (i.e., one of the plurality of capacitors CP11 to CP1(N-1) and one of the plurality of capacitors CP21 to CP2(N-1)). Each capacitor includes a terminal N21 and a terminal N22. The plurality of capacitors in the same capacitor pair may have the same or substantially the same capacitance value. In addition, the (N-1) capacitor pairs CPP1 to CPP(N-1) may have binary weighted capacitance values.

[0019] Switching circuit 136.1 is used to allow, according to digital signal SD1, to switchably couple terminal N11 of each of (N-1) capacitors CPM1 to CPM(N-1) to a plurality of reference signals VR1 and VR2. Switching circuit 136.2 is used to allow, according to digital signal SD1, to selectively couple terminal N12 of each of (N-1) capacitors CPM1 to CPM(N-1) to input terminal TM. Similarly, switching circuit 138.1 is used to allow, according to digital signal SD2, to switchably couple terminal N21 of each of (N-1) capacitors CPP1 to CPP(N-1) to a plurality of reference signals VR1 and VR2. The switching circuit 138.2 is used to allow the terminals N22 of each of the (N-1) capacitors CPP1 to CPP(N-1) to be selectively coupled to the input terminal TP according to the digital signal SD2.

[0020] Each of the plurality of reference signals VR1 and VR2 is different from the common-mode voltage VCM of the plurality of voltage signals VIP and VIM. For example (but this disclosure is not limited to this), each of the plurality of reference signals VR1 and VR2 can be a supply voltage supplied to the signal conversion circuit 100, wherein reference signal VR1 can be the power supply voltage, and reference signal VR2 can be ground voltage. As another example, the signal level of the common-mode voltage VCM can be equal to the average of the signal levels of reference signal VR1 and reference signal VR2.

[0021] During operation. The digital-to-analog converter 130 may be coupled to the input signal AIN during the sampling phase, but not coupled to the input signal AIN during the conversion phase. For example, each capacitor in the switched capacitor array 132 may be coupled to the voltage signal VIP during the sampling phase, but not coupled to the voltage signal VIP during the conversion phase. Each capacitor in the switched capacitor array 134 may be coupled to the voltage signal VIM during the sampling phase, but not coupled to the voltage signal VIM during the conversion phase.

[0022] Furthermore, during this conversion stage, the capacitor CM1k (k is an integer between 1 and (N-1)) in the capacitor pair CPMk can be coupled between the input terminal TM and the reference signal VR1, and the capacitor CM2k in the capacitor pair CPMk can be coupled between the input terminal TM and the reference signal VR2. Similarly, during this conversion stage, the capacitor CP1k in the capacitor pair CPPk can be coupled between the input terminal TP and the reference signal VR1, and the capacitor CP2k in the capacitor pair CPPk can be coupled between the input terminal TP and the reference signal VR2. The comparator 110 can compare the signal level of the input terminal TM with the signal level of the input terminal TP during this conversion stage to convert the input signal AIN.

[0023] When the comparison result CR indicates that the signal level of input terminal TM is less than the signal level of input terminal TP, capacitor CM2k can be coupled between input terminal TM and reference signal VR1. When the comparison result CR indicates that the signal level of input terminal TM is greater than the signal level of input terminal TP, capacitor CM1k can be coupled between input terminal TM and reference signal VR2. Alternatively, when the comparison result CR indicates that the signal level of input terminal TM is less than the signal level of input terminal TP, capacitor CP1k can be coupled between input terminal TP and reference signal VR2. When the comparison result CR indicates that the signal level of input terminal TM is greater than the signal level of input terminal TP, capacitor CP2k can be coupled between input terminal TP and reference signal VR1.

[0024] For example, in a conversion step of this conversion stage (which may correspond to a single bit cycle), capacitor CM1 (N-1) may be coupled between input terminal TM and reference signal VR1, and capacitor CM2 (N-1) may be coupled between input terminal TM and reference signal VR2. Furthermore, capacitor CP1 (N-1) may be coupled between input terminal TP and reference signal VR1, and capacitor CP2 (N-1) may be coupled between input terminal TP and reference signal VR2. Comparator 110 may compare the signal level of input terminal TM with the signal level of input terminal TP to generate a comparison result CR. When the comparison result CR indicates that the signal level of input terminal TM is less than the signal level of input terminal TP, switching circuit 136.1 may couple reference voltage VR1 to capacitor CM2 (N-1) according to digital signal SD1, and switching circuit 138.1 may couple reference voltage VR2 to capacitor CP1 (N-1) according to digital signal SD2. When the comparison result CR indicates that the signal level of the input terminal TM is greater than the signal level of the input terminal TP, the switching circuit 136.1 can couple the reference voltage VR2 to the capacitor CM1(N-1) according to the digital signal SD1, and the switching circuit 138.1 can couple the reference voltage VR1 to the capacitor CP2(N-1) according to the digital signal SD2.

[0025] Similarly, the reference signal coupled to capacitor pair CPM(N-2) can be changed according to the comparison result CR obtained in the next conversion step of this conversion stage. The reference signal coupled to capacitor pair CPP(N-2) can be changed according to the comparison result CR obtained in the next conversion step of this conversion stage.

[0026] With the signal conversion scheme provided in this disclosure, a single capacitor coupled to the common-mode voltage VCM can be replaced by a capacitor pair coupled to a plurality of reference signals VR1 and VR2. Compared to a digital-to-analog converter (which includes a plurality of capacitors coupled to the common-mode voltage VCM in a conversion stage), since the number of times the digital-to-analog converter 130 accesses the common-mode voltage VCM from a register can be reduced to zero, the power consumption caused by the register used to store the common-mode voltage VCM (i.e., the high-power register) can be significantly reduced.

[0027] To facilitate understanding of the contents of this disclosure, certain embodiments are provided below to further illustrate the signal conversion scheme disclosed herein. Those skilled in the art will understand that other embodiments employing the switching capacitor structure shown in Figure 1 follow the spirit of this disclosure and fall within its scope.

[0028] FIG2 is a schematic diagram of an embodiment of the digital-to-analog converter 130 shown in FIG1 according to certain embodiments of the present disclosure. In this embodiment, for ease of explanation, the digital-to-analog converter 230 may be implemented as a 2-bit digital-to-analog converter employing a bottom-sampling scheme. The digital-to-analog converter 230 includes a plurality of switched capacitor arrays 232 and 234, and a plurality of switching circuits 236.1, 236.2, 238.1, and 238.2. The plurality of switched capacitor arrays 232 and 234 may be embodiments of the plurality of switched capacitor arrays 132 and 134 shown in FIG1, respectively. The plurality of switching circuits 236.1, 236.2, 238.1, and 238.2 may be embodiments of the plurality of switching circuits 136.1, 136.2, 138.1, and 138.2 shown in FIG1, respectively.

[0029] The switching capacitor array 232 includes a plurality of capacitor pairs CPM1 and CPM2. The switching capacitor array 234 includes a plurality of capacitor pairs CPP1 and CPP2. The switching circuit 236.1 is used to selectively couple the terminal N11 of each capacitor in the switching capacitor array 232 to one of the voltage signal VIP, the power supply voltage VDD, and the ground voltage GND according to the digital signal SD1. The power supply voltage VDD and the ground voltage GND can be used as embodiments of the reference voltage VR1 and reference voltage VR2 shown in FIG1, respectively. The switching circuit 236.1 may include (but is not limited to) a plurality of switches SM11, SM21, SM12, and SM22. The switching circuit 236.2 is used to selectively couple the terminal N12 of each capacitor in the switching capacitor array 232 to the common-mode voltage VCM. The switching circuit 236.2 may be implemented using (but is not limited to) the switch SMC1. In some embodiments, the signal level of the common-mode voltage VCM is equal to the average of the signal level of the power supply voltage VDD and the signal level of the ground voltage GND.

[0030] Switching circuit 238.1 is used to selectively couple terminal N21 of each capacitor in the switching capacitor array 234 to one of the voltage signal VIM, the power supply voltage VDD, and the ground voltage GND, according to the digital signal SD2. Switching circuit 238.1 may include (but is not limited to) a plurality of switches SP11, SP21, SP12, and SP22. Switching circuit 238.2 is used to selectively couple terminal N22 of each capacitor in the switching capacitor array 234 to the common-mode voltage VCM. Switching circuit 238.2 may be implemented using (but is not limited to) switch SMC2.

[0031] Figures 3A and 3B are schematic diagrams illustrating the operation of the digital-to-analog converter 230 shown in Figure 2 according to certain embodiments of the present disclosure. Referring first to Figure 3A, in a sampling phase PHS of a conversion cycle, each capacitor of the switched capacitor array 232 is coupled between a voltage signal VIP and a common-mode voltage VCM, and each capacitor of the switched capacitor array 234 is coupled between a voltage signal VIM and a common-mode voltage VCM. For example, each of the plurality of switches SM11, SM21, SM12, and SM22 is used to couple the voltage signal VIP to the terminal N11 of the corresponding capacitor, and switch SMC1 is used to couple the common-mode voltage VCM to the input terminal TM. Furthermore, each of the plurality of switches SP11, SP21, SP12, and SP22 is used to couple the voltage signal VIM to the terminal N21 of the corresponding capacitor, and switch SMC2 is used to couple the common-mode voltage VCM to the input terminal TP. Therefore, in the sampling phase of PHS, the signal levels of the multiple voltage signals VXM and VXP can be equal to the signal level of the common-mode voltage VCM.

[0032] In the conversion stage PHC following the sampling stage PHS, each capacitor of the switching capacitor array 232 is coupled between the power supply voltage VDD and the ground voltage GND and the input terminal TM. Furthermore, each capacitor of the switching capacitor array 234 is coupled between the power supply voltage VDD and the ground voltage GND and the input terminal TP. For example, in a conversion step ST1 of the conversion stage PHC, two capacitors in the same capacitor pair can be coupled to the power supply voltage VDD and the ground voltage GND, respectively. For the plurality of capacitor pairs CPM1 and CPM2, the plurality of capacitors CM11 and CM12 are coupled between the input terminal TM and the power supply voltage VDD, and the plurality of capacitors CM21 and CM22 are coupled between the input terminal TM and the ground voltage GND. For the multiple capacitor pairs CPP1 and CPP2, multiple capacitors CP11 and CP12 are coupled between the input terminal TP and the power supply voltage VDD, and multiple capacitors CP21 and CP22 are coupled between the input terminal TP and the ground voltage GND.

[0033] For example, each of the plurality of switches SM11 and SM12 is used to couple the power supply voltage VDD to the terminal N11 of the corresponding capacitor, each of the plurality of switches SM21 and SM22 is used to couple the ground voltage GND to the terminal N11 of the corresponding capacitor, and switch SMC1 is open. Furthermore, each of the plurality of switches SP11 and SP12 is used to couple the power supply voltage VDD to the terminal N21 of the corresponding capacitor, each of the plurality of switches SP21 and SP22 is used to couple the ground voltage GND to the terminal N21 of the corresponding capacitor, and switch SMC2 is open.

[0034] Furthermore, in conversion step ST1, comparator 110 compares voltage signal VXM with voltage signal VXP to generate a comparison result CR. It is worth noting that since the two capacitors (having the same capacitance value) in each capacitor pair are respectively coupled to the power supply voltage VDD and the ground voltage GND, the comparison result between voltage signal VXM and voltage signal VXP can be equal to or approximately equal to the comparison result between voltage signal VIM and voltage signal VIP, which can be expressed as: VXP - VXM = VIP - VIM. In other words, the digital-to-analog converter 230 can be used as a differential approximation analog-to-digital converter, which can be used to convert an input signal AIN containing a plurality of voltage signals VIP and VIM.

[0035] When the comparison result CR indicates that the signal level of voltage signal VXM is less than the signal level of voltage signal VXP, the digital-to-analog converter 230 can enter the operation state OP21 in the conversion step ST2. When the comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, the digital-to-analog converter 230 can enter the operation state OP22 in the conversion step ST2.

[0036] In operation state OP21, capacitor CM22 is coupled between the power supply voltage VDD and the input terminal TM, and capacitor CP12 is coupled between the ground voltage GND and the input terminal TP. For example, switch SM22 is used to couple the power supply voltage VDD to terminal N11 of capacitor CM22, and switch SP12 is used to couple the ground voltage GND to terminal N21 of capacitor CP12. Next, comparator 110 compares voltage signal VXM with voltage signal VXP to generate a comparison result CR. When the comparison result CR indicates that the signal level of voltage signal VXM is less than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP31 in conversion step ST3. When the comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP32 in conversion step ST3.

[0037] In operation state OP22, capacitor CM12 is coupled between ground voltage GND and input terminal TM, and capacitor CP22 is coupled between power supply voltage VDD and input terminal TP. For example, switch SM12 is used to couple ground voltage GND to terminal N11 of capacitor CM12, and switch SP22 is used to couple power supply voltage VDD to terminal N21 of capacitor CP22. Next, comparator 110 compares voltage signal VXM with voltage signal VXP to generate comparison result CR. When comparison result CR indicates that the signal level of voltage signal VXM is less than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP33 in conversion step ST3. When comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP34 in conversion step ST3.

[0038] Referring to Figure 3B along with Figure 2, in operation state OP31, capacitor CM21 is coupled between the power supply voltage VDD and the input terminal TM, and capacitor CP11 is coupled between the ground voltage GND and the input terminal TP. For example, switch SM21 is used to couple the power supply voltage VDD to terminal N11 of capacitor CM21, and switch SP11 is used to couple the ground voltage GND to terminal N21 of capacitor CP11. In operation state OP32, capacitor CM11 is coupled between the ground voltage GND and the input terminal TM, and capacitor CP21 is coupled between the power supply voltage VDD and the input terminal TP. For example, switch SM11 is used to couple the ground voltage GND to terminal N11 of capacitor CM11, and switch SP21 is used to couple the power supply voltage VDD to terminal N21 of capacitor CP21.

[0039] Similarly, in operation state OP33, capacitor CM21 is coupled between the power supply voltage VDD and the input terminal TM, and capacitor CP11 is coupled between the ground voltage GND and the input terminal TP. In operation state OP34, capacitor CM11 is coupled between the ground voltage GND and the input terminal TM, and capacitor CP21 is coupled between the power supply voltage VDD and the input terminal TP. Based on the operations shown in Figures 3A and 3B, the digital-to-analog converter 230 shown in Figure 2 can be used to implement a 3-bit successive approximation analog-to-digital converter, which uses a binary search algorithm to perform signal conversion operations.

[0040] In some embodiments, the digital-to-analog converter 230 shown in FIG2 can be used to implement a 3-bit successive approximation analog-to-digital converter, which operates in single-ended mode to convert the input signal AIN. FIG3C and FIG3D are schematic diagrams of the operation of the digital-to-analog converter 230 shown in FIG2 according to some embodiments of the present disclosure. In the embodiments shown in FIG3C and FIG3D, the input signal AIN is a single-ended signal implemented using (but not limited to) a voltage signal VIP. Except that the plurality of capacitors CP11, CP21, CP12 and CP22 are coupled to the same reference voltage in the sampling phase PHS and the conversion phase PHC, the operation shown in FIG3C and FIG3D may be similar to / the same as the operation shown in FIG3A and FIG3B.

[0041] First, please refer to Figure 3C along with Figure 2. In the sampling phase PHS, each capacitor of the switching capacitor array 232 is coupled between the voltage signal VIP and the common-mode voltage VCM, and each capacitor of the switching capacitor array 234 is coupled between the common-mode voltage VCM and the ground voltage GND. For example, each of the plurality of switches SP11, SP21, SP12 and SP22 is used to couple the ground voltage GND to the terminal N21 of the corresponding capacitor, and switch SMC2 is used to couple the common-mode voltage VCM to the input terminal TP.

[0042] In the conversion phase PHC, each capacitor of the switched capacitor array 232 is coupled between the power supply voltage VDD and the ground voltage GND and the input terminal TM, while each capacitor of the switched capacitor array 234 remains coupled between the input terminal TP and the ground voltage TP. In conversion step ST1, comparator 110 compares the voltage signal VXM and the voltage signal VXP to generate a comparison result CR. When the comparison result CR indicates that the signal level of the voltage signal VXM is less than the signal level of the voltage signal VXP, the digital-to-analog converter 230 can enter the operation state OP21 in conversion step ST2. When the comparison result CR indicates that the signal level of the voltage signal VXM is greater than the signal level of the voltage signal VXP, the digital-to-analog converter 230 can enter the operation state OP22 in conversion step ST2. It is worth noting that the comparison result of the voltage signal VXM and the voltage signal VXP can be equal to or approximately equal to the comparison result of the voltage signal VIP and the ground voltage GND. Therefore, the digital-to-analog converter 230 can be used as a single-ended successive approximation analog-to-digital converter.

[0043] In operation state OP21, switch SM22 is used to couple the power supply voltage VDD to terminal N11 of capacitor CM22, while switches SP12 and SP12 are both maintained between ground voltage GND and the corresponding capacitor. Comparator 110 compares voltage signal VXM and voltage signal VXP to generate a comparison result CR. When the comparison result CR indicates that the signal level of voltage signal VXM is less than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP31 in conversion step ST3. When the comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP32 in conversion step ST3.

[0044] In operation state OP22, switch SM12 is used to couple the ground voltage GND to terminal N11 of capacitor CM12, while switches SP12 and SP12 are both maintained between the ground voltage GND and the corresponding capacitor. Comparator 110 compares voltage signal VXM and voltage signal VXP to generate a comparison result CR. When the comparison result CR indicates that the signal level of voltage signal VXM is less than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP33 in conversion step ST3. When the comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, digital-to-analog converter 230 can enter operation state OP34 in conversion step ST3.

[0045] Referring to Figure 3D together with Figure 2, in operation states OP31 and OP33, switch SM21 is used to couple the power supply voltage VDD to terminal N11 of capacitor CM22. In operation states OP32 and OP34, switch SM11 is used to couple the ground voltage GND to terminal N11 of capacitor CM12. Since those skilled in the art should understand the operation of the digital-to-analog converter 230 in conversion step ST3 shown in Figure 3D after reading the description of the relevant paragraphs of Figures 1 to 3C, further explanation will not be repeated here. Based on the operation shown in Figures 3C and 3D, the digital-to-analog converter 230 shown in Figure 2 can be used to implement a 3-bit successive approximation analog-to-digital converter operating in single-ended mode.

[0046] The digital-to-analog converter structure and operation described above are for illustrative purposes only and are not intended to limit the scope of this disclosure. In some embodiments, the common-mode voltage VCM may be implemented using a reference signal different from the plurality of reference signals VR1 and VR2. In some embodiments, a capacitor pair corresponding to a predetermined bit in the output signal DOUT may be replaced by a single capacitor, which may be coupled between the voltage signal VIP / VIM and the common-mode voltage VCM in the sampling phase PHS, and may be coupled between the common-mode voltage VCM and the input terminal TM / TP at the beginning of the conversion phase PHC. In some embodiments, a capacitor pair may be coupled to the power supply voltage VDD and the ground voltage GND in the sampling phase PHS, instead of being coupled to the common-mode voltage VCM. Any digital-to-analog converter that can provide at least one capacitor pair (each capacitor pair containing multiple capacitors with the same capacitance value) to replace a single capacitor electrically connected to a common-mode voltage, and that multiple capacitors are coupled to multiple reference signals different from the common-mode voltage, any related modifications and variations in design that follow the spirit of this disclosure and fall within the scope of this disclosure.

[0047] FIG4 is a schematic diagram of another embodiment of the digital-to-analog converter 130 shown in FIG1 according to certain embodiments of the present disclosure. Except for the switching circuit 439, the structure of the digital-to-analog converter 430 is similar to / identical to the structure of the digital-to-analog converter 230 shown in FIG2. In this embodiment, the switching circuit 439 is used to couple the two capacitors of a capacitor pair to the power supply voltage VDD and the ground voltage GND respectively, or to couple the two capacitors to the same input terminal of the comparator 110 respectively.

[0048] Figures 5A and 5B are schematic diagrams of the operation of the digital-to-analog converter 430 shown in Figure 4 according to certain embodiments of the present disclosure. Referring first to Figure 5A, in the sampling phase PHS, one capacitor in each capacitor pair of the switched capacitor array 232 is coupled between the voltage signal VIP and the power supply voltage VDD, and the other capacitor in the same capacitor pair is coupled between the voltage signal VIP and the ground voltage GND. Furthermore, one capacitor in each capacitor pair of the switched capacitor array 234 is coupled between the voltage signal VIM and the power supply voltage VDD, and the other capacitor in the same capacitor pair is coupled between the voltage signal VIM and the ground voltage GND.

[0049] For example, the switching circuit 439 may include a plurality of switches SWA0~SWA4, SWB0~SWB4, and SWD1~SWD4. During the sampling phase PHS, a plurality of switches SM11, SM21, SM12, and SM22 are used to couple the voltage signal VIP to the terminal N11 of the corresponding capacitor. A plurality of switches SWA0, SWB0, and SWD1~SWD4 are all turned on, and a plurality of switches SWA1~SWA4 and SWB1~SWB4 are all turned off. Therefore, a plurality of capacitors CM11 and CM12 are coupled between the voltage signal VIP and the power supply voltage VDD, and a plurality of capacitors CM21 and CM22 are coupled between the voltage signal VIP and the ground voltage GND. In addition, multiple capacitors CP11 and CP12 are coupled between the voltage signal VIM and the power supply voltage VDD, and multiple capacitors CP21 and CP22 are coupled between the voltage signal VIM and the ground voltage GND.

[0050] In the conversion phase PHC, each capacitor of the switching capacitor array 232 is coupled between one of the power supply voltage VDD and the ground voltage GND and the input terminal TM. Furthermore, each capacitor of the switching capacitor array 234 is coupled between one of the power supply voltage VDD and the ground voltage GND and the input terminal TP. For example, in conversion step ST1, each of the plurality of switches SM11 and SM12 is used to couple the power supply voltage VDD to the corresponding capacitor terminal N11, and each of the plurality of switches SM21 and SM22 is used to couple the ground voltage GND to the corresponding capacitor terminal N11. Each of the plurality of switches SP11 and SP12 is used to couple the power supply voltage VDD to the corresponding capacitor terminal N21, and each of the plurality of switches SP21 and SP22 is used to couple the ground voltage GND to the corresponding capacitor terminal N21. In addition, multiple switches SWA0, SWB0 and SWD1~SWD4 are all open, and multiple switches SWA1~SWA4 and SWB1~SWB4 are all closed.

[0051] Furthermore, in conversion step ST1, comparator 110 compares voltage signal VXM with voltage signal VXP to generate a comparison result CR. It is worth noting that the comparison result between voltage signal VXM and voltage signal VXP is equal to or approximately equal to the comparison result between voltage signal VIM and voltage signal VIP, which can be expressed as: VXP - VXM = VIP - VIM. Therefore, the digital-to-analog converter 430 can be used as a differential approximation analog-to-digital converter, which can be used to convert an input signal AIN containing a plurality of voltage signals VIP and VIM. Since those skilled in the art should understand the operational details of the digital-to-analog converter 430 in the plurality of conversion steps ST1~ST3 shown in Figures 5A and 5B after reading the relevant paragraphs in Figures 1 to 3B, further explanation will not be repeated here. Furthermore, in some embodiments, based on the operations shown in Figures 3C and 3D, the digital-to-analog converter 430 shown in Figure 4 can be used to implement a progressive approximation analog-to-digital converter operating in single-ended mode without departing from the scope of this disclosure.

[0052] In some embodiments, at least one capacitor pair shown in FIG. 4, which is coupled to the power supply voltage VDD and the ground voltage GND in the sampling phase PHS, may be coupled to a common-mode voltage at the beginning of the conversion phase PHC. FIG. 6 is a schematic diagram of another embodiment of the digital-to-analog converter 130 shown in FIG. 1 according to some embodiments of the present disclosure. Except for the plurality of switch circuits 636 and 638, the structure of the digital-to-analog converter 630 is similar / identical to the structure of the digital-to-analog converter 430 shown in FIG. 4. The plurality of switch circuits 636 and 638 may be embodiments of the plurality of switch circuits 136.1 and 138.1 shown in FIG. 1, respectively.

[0053] In this embodiment, the switching circuit 636 is used to selectively couple the terminal N11 of each capacitor in the switching capacitor array 232 to one of the voltage signal VIP, the common-mode voltage VCM, the power supply voltage VDD, and the ground voltage GND according to the digital signal SD1. The switching circuit 636 can be implemented using the plurality of switches SM11, SM21, SM12, and SM22 shown in FIG2. The switching circuit 638 is used to selectively couple the terminal N21 of each capacitor in the switching capacitor array 234 to one of the voltage signal VIM, the common-mode voltage VCM, the power supply voltage VDD, and the ground voltage GND according to the digital signal SD2. The switching circuit 638 can be implemented using the plurality of switches SP11, SP21, SP12, and SP22 shown in FIG2.

[0054] FIG7 is a schematic diagram of the operation of the digital-to-analog converter 630 shown in FIG6 according to certain embodiments of the present disclosure. Referring to FIG7 together with FIG6, the operation of the digital-to-analog converter 630 in the sampling phase PHS can be similar to / the same as the operation of the digital-to-analog converter 430 shown in FIG4. In the conversion phase PHC, each capacitor of the switching capacitor array 232 can be coupled between the input terminal TM and the common-mode voltage VCM. Each capacitor of the switching capacitor array 234 can be coupled between the input terminal TP and the common-mode voltage VCM. For example, in the conversion step ST1, each of the plurality of switches SM11, SM21, SM12 and SM22 is used to couple the common-mode voltage VCM to the terminal N11 of the corresponding capacitor, and each of the plurality of switches SP11, SP21, SP12 and SP22 is used to couple the common-mode voltage VCM to the terminal N21 of the corresponding capacitor. In addition, multiple switches SWA0, SWB0 and SWD1~SWD4 are all open, and multiple switches SWA1~SWA4 and SWB1~SWB4 are all closed.

[0055] Furthermore, in conversion step ST1, comparator 110 compares voltage signal VXM with voltage signal VXP to generate a comparison result CR. When the comparison result CR indicates that the signal level of voltage signal VXM is less than the signal level of voltage signal VXP, digital-to-analog converter 630 can enter operation state OP21 in conversion step ST2. When the comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, digital-to-analog converter 630 can enter operation state OP22 in conversion step ST2. It is worth noting that the comparison result between voltage signal VXM and voltage signal VXP can be equal to or approximately equal to the comparison result between voltage signal VIM and voltage signal VIP, which can be expressed as: VXP - VXM = VIP - VIM. Therefore, the digital-to-analog converter 630 can be used as a differential approximation analog-to-digital converter, which can be used to convert an input signal AIN containing multiple voltage signals VIP and VIM.

[0056] In operation state OP21, capacitors CM12 and CM22 are both coupled between the power supply voltage VDD and the input terminal TM, and capacitors CP12 and CP22 are both coupled between the ground voltage GND and the input terminal TP. For example, each of the plurality of switches SM12 and SM22 is used to couple the power supply voltage VDD to the terminal N11 of the corresponding capacitor, and each of the plurality of switches SP12 and SP22 is used to couple the ground voltage GND to the terminal N21 of the corresponding capacitor. Next, comparator 110 can compare the voltage signal VXM with the voltage signal VXP to generate a comparison result CR. When the comparison result CR indicates that the signal level of the voltage signal VXM is less than the signal level of the voltage signal VXP, the digital-to-analog converter 630 can enter operation state OP31 in conversion step ST3. When the comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, the digital-to-analog converter 630 can enter the operation state OP32 in the conversion step ST3.

[0057] In operation state OP22, capacitors CM12 and CM22 are both coupled between ground voltage GND and input terminal TM, and capacitors CP12 and CP22 are both coupled between power supply voltage VDD and input terminal TP. For example, each of the plurality of switches SM12 and SM22 is used to couple ground voltage GND to the corresponding capacitor terminal N11, and each of the plurality of switches SP12 and SP22 is used to couple power supply voltage VDD to the corresponding capacitor terminal N21. Next, comparator 110 can compare voltage signal VXM and voltage signal VXP to generate comparison result CR. When the comparison result CR indicates that the signal level of voltage signal VXM is less than the signal level of voltage signal VXP, digital-to-analog converter 630 can enter operation state OP33 in conversion step ST3. When the comparison result CR indicates that the signal level of voltage signal VXM is greater than the signal level of voltage signal VXP, the digital-to-analog converter 630 can enter the operation state OP34 in the conversion step ST3.

[0058] Since those skilled in the art will understand after reading the descriptions of the paragraphs related to Figures 1 to 6 that the operation of the digital-to-analog converter 630 in the plurality of operating states OP31 to OP34 is similar to / the same as the operation shown in Figure 5B, further descriptions will not be repeated here. Furthermore, in some embodiments, based on the operations shown in Figures 3C and 3D, the digital-to-analog converter 630 can be used to implement a successive approximation analog-to-digital converter operating in single-ended mode without departing from the scope of this disclosure.

[0059] FIG8 is a schematic diagram of another embodiment of the digital-to-analog converter 130 shown in FIG1 according to certain embodiments of the present disclosure. For example, except that the digital-to-analog converter 830 uses an on-board sampling scheme to perform signal conversion operations, the structure of the digital-to-analog converter 830 is similar / identical to that of the digital-to-analog converter 230 shown in FIG2. The plurality of switching circuits 836 and 838 included in the digital-to-analog converter 830 can be respectively used as embodiments of the plurality of switching circuits 136.1 and 138.1 shown in FIG1.

[0060] In this embodiment, the switching circuit 836 is used to selectively couple the terminal N11 of each capacitor of the switching capacitor array 232 to one of the power supply voltage VDD and the ground voltage GND according to the digital signal SD1. The switching circuit 836 can be implemented using a plurality of switches SM11, SM21, SM12 and SM22 shown in FIG2. The switching circuit 838 is used to selectively couple the terminal N21 of each capacitor of the switching capacitor array 234 to one of the power supply voltage VDD and the ground voltage GND according to the digital signal SD2. The switching circuit 838 can be implemented using a plurality of switches SP11, SP21, SP12 and SP22 shown in FIG2. In addition, switch SMC1 is selectively coupled between voltage signal VIM and input terminal TM, and switch SMC2 is selectively coupled between voltage signal VIP and input terminal TP.

[0061] FIG9 is a schematic diagram of the operation of the digital-to-analog converter 830 shown in FIG8 according to certain embodiments of the present disclosure. Referring to FIG9 together with FIG8, in the sampling phase PHS, one capacitor in each capacitor pair of the switched capacitor array 232 is coupled between the voltage signal VIM and the power supply voltage VDD, and the other capacitor in the capacitor pair is coupled between the voltage signal VIM and the ground voltage GND. In addition, one capacitor in each capacitor pair of the switched capacitor array 234 is coupled between the voltage signal VIP and the power supply voltage VDD, and the other capacitor in the capacitor pair is coupled between the voltage signal VIP and the ground voltage GND.

[0062] For example, in the sampling phase of PHS, multiple switches SM11 and SM12 are used to couple the power supply voltage VDD to the corresponding capacitor terminal N11. Multiple switches SM21 and SM22 are used to couple the ground voltage GND to the corresponding capacitor terminal N11. Multiple switches SP11 and SP12 are used to couple the power supply voltage VDD to the corresponding capacitor terminal N21. Multiple switches SP21 and SP22 are used to couple the ground voltage GND to the corresponding capacitor terminal N21. In addition, switch SMC1 is used to couple the voltage signal VIM to the input terminal TM. Switch SMC2 is used to couple the voltage signal VIP to the input terminal TP.

[0063] In the conversion phase PHC, the two capacitors in the same capacitor pair can be coupled to the power supply voltage VDD and the ground voltage GND, respectively. For example, in conversion step ST1, both switches SMC1 and SMC2 are open. Since those skilled in the art will understand after reading the description of the relevant paragraphs of Figures 1 to 8 that the operation of the digital-to-analog converter 830 in the plurality of conversion steps ST1 to ST3 is similar / the same as the operation shown in Figures 3A and 3B, further description will not be repeated here. In addition, in some embodiments, based on the operation shown in Figures 3C and 3D, the digital-to-analog converter 830 can be used to implement a progressive approximation analog-to-digital converter operating in single-ended mode without departing from the scope of this disclosure.

[0064] FIG10 is a schematic diagram of another embodiment of the digital-to-analog converter 130 shown in FIG1 according to certain embodiments of the present disclosure. For example, except that each capacitor in the digital-to-analog converter 1030 can be coupled to one of the common-mode voltage VCM, the power supply voltage VDD, and the voltage GND, the structure of the digital-to-analog converter 1030 is similar to / the same as that of the digital-to-analog converter 830 shown in FIG8.

[0065] In this embodiment, the switching circuit 1036 is used to selectively couple the terminal N11 of each capacitor of the switching capacitor array 232 to one of the common-mode voltage VCM, the power supply voltage VDD, and the ground voltage GND according to the digital signal SD1. The switching circuit 1036 can be implemented using the plurality of switches SM11, SM21, SM12, and SM22 shown in FIG2. The switching circuit 1038 is used to selectively couple the terminal N21 of each capacitor of the switching capacitor array 234 to one of the common-mode voltage VCM, the power supply voltage VDD, and the ground voltage GND according to the digital signal SD2. The switching circuit 1038 can be implemented using the plurality of switches SP11, SP21, SP12, and SP22 shown in FIG2.

[0066] FIG11 is a schematic diagram of the operation of the digital-to-analog converter 1030 shown in FIG10 according to certain embodiments of the present disclosure. Referring to FIG11 together with FIG10, in the sampling phase PHS, both switches SMC1 and SMC2 are turned on. Each capacitor of the switched capacitor array 232 is coupled between the common-mode voltage VCM and the voltage signal VIM, and each capacitor of the switched capacitor array 234 is coupled between the common-mode voltage VCM and the voltage signal VIP. At the beginning of the conversion phase PHC, both switches SMC1 and SMC2 are turned off. Capacitors CM11 and CM12 are coupled between the input terminal TM and the power supply voltage VDD, and capacitors CM21 and CM22 are coupled between the input terminal TM and the ground voltage GND. Capacitors CP11 and CP12 are coupled between the input terminal TP and the power supply voltage VDD, and capacitors CP21 and CP22 are coupled between the input terminal TP and the ground voltage GND. Since those skilled in the art will understand, after reading the descriptions of Figures 1 to 10, that the operation of the digital-to-analog converter 1030 in the conversion stage PHC shown in Figure 11 is similar to / the same as the operation shown in Figures 3A and 3B, further descriptions will not be repeated here. Furthermore, in some embodiments, based on the operations shown in Figures 3C and 3D, the digital-to-analog converter 1030 can be used to implement a successive approximation analog-to-digital converter operating in single-ended mode without departing from the scope of this disclosure.

[0067] FIG12 is a schematic diagram of the operation of the digital-to-analog converter 1030 shown in FIG10 according to certain embodiments of the present disclosure. Referring to FIG12 together with FIG10, in the sampling phase PHS, switches SMC1 and SMC2 are both turned on. Capacitors CM11 and CM12 are both coupled between the voltage signal VIM and the power supply voltage VDD, and capacitors CM21 and CM22 are both coupled between the voltage signal VIM and the ground voltage GND. Capacitors CP11 and CP12 are both coupled between the voltage signal VIP and the power supply voltage VDD, and capacitors CP21 and CP22 are both coupled between the voltage signal VIP and the ground voltage GND. At the beginning of the conversion phase PHC, switches SMC1 and SMC2 are both turned off. Each capacitor in the switched capacitor array 232 is coupled between the common-mode voltage VCM and the input terminal TM, and each capacitor in the switched capacitor array 234 is coupled between the common-mode voltage VCM and the input terminal TP. Since those skilled in the art will understand, after reading the descriptions of the paragraphs related to Figures 1 to 10, that the operation of the digital-to-analog converter 1030 in the conversion stage PHC shown in Figure 12 is similar to / the same as the operation shown in Figures 3A and 3B, further explanation will not be repeated here.

[0068] In some embodiments, the reference signals of two capacitors respectively coupled to the same capacitor pair can be exchanged according to different conversion cycles to reduce the effects of capacitor mismatch. FIG13 is a schematic diagram of the operation of the digital-to-analog converter 230 shown in FIG2 according to some embodiments of the present disclosure at different conversion cycles. In this embodiment, the digital-to-analog converter 230 can operate in different conversion cycles CC1 and CC2, wherein conversion cycle CC1 includes the sampling phase PHS and the conversion phase PHC shown in FIG3A and FIG3B.

[0069] Referring to Figure 13 along with Figure 1, the digital-to-analog converter 230 can be used to implement the digital-to-analog converter 130 shown in Figure 1, wherein the signal conversion circuit 100 can convert the input signal AIN in conversion cycle CC1 to produce a conversion result, such as the output signal DOUT output at the end of conversion cycle CC1. Furthermore, the signal conversion circuit 100 can convert the input signal AIN in conversion cycle CC2 to produce another conversion result, such as the output signal DOUT output at the end of conversion cycle CC2. Conversion cycle CC2 includes a sampling phase PHS2 and a conversion phase PHC2.

[0070] Except for the reference signal applied to the same capacitor pair, the operations performed in the sampling phase PHS2 and the conversion phase PHC2 are similar to / the same as those performed in the sampling phase PHS and the conversion phase PHC. For example, in the embodiment shown in FIG13, in the conversion phase PHC of the conversion cycle CC1, a plurality of capacitors CM11 and CM12 are coupled between the input terminal TM and the power supply voltage VDD, and a plurality of capacitors CM21 and CM22 are coupled between the input terminal TM and the ground voltage GND. In the conversion phase PHC2 of the conversion cycle CC2, a plurality of capacitors CM11 and CM12 are coupled between the input terminal TM and the ground voltage GND, and a plurality of capacitors CM21 and CM22 are coupled between the input terminal TM and the power supply voltage VDD. Similarly, during the conversion phase PHC of conversion cycle CC1, multiple capacitors CP11 and CP12 are coupled between the input terminal TP and the power supply voltage VDD, and multiple capacitors CP21 and CP22 are coupled between the input terminal TP and the ground voltage GND. During the conversion phase PHC2 of conversion cycle CC2, multiple capacitors CP11 and CP12 are coupled between the input terminal TP and the ground voltage GND, and multiple capacitors CP21 and CP22 are coupled between the input terminal TP and the power supply voltage VDD. That is, when the digital-to-analog converter 230 operates in different conversion cycles, the reference signals coupled to two capacitors in the same capacitor pair can be exchanged / swapped.

[0071] In some embodiments, the signal conversion scheme provided by this disclosure can exchange the reference signals applied to the two capacitors in the same capacitor pair once within a predetermined number of conversion cycles. It is worth noting that the signal conversion scheme shown in FIG13 can be applied to other embodiments of the digital-to-analog converter 130 shown in FIG1, the digital-to-analog converter 230 shown in FIG2, the digital-to-analog converter 430 shown in FIG4, the digital-to-analog converter 630 shown in FIG6, the digital-to-analog converter 830 shown in FIG8, the digital-to-analog converter 1030 shown in FIG1, and the digital-to-analog converter 130 shown in FIG1, thereby reducing the impact of capacitor mismatch.

[0072] The signal conversion scheme provided by this disclosure can significantly reduce the power consumption caused by the high-power register used to store common-mode voltage. In addition, the signal conversion scheme provided by this disclosure can exchange the reference signals applied to the two capacitors in the same capacitor pair according to different conversion cycles, so as to reduce the impact of capacitor mismatch.

[0073] The term "approximately" as used in this disclosure is used to describe and indicate minor variations. When these terms are used in conjunction with an event or situation, they can cover examples of an event or situation occurring precisely and examples of an event or situation being very close to occurring. For example, when the term "approximately" is used with a given value or range, it generally means ±10%, ±5%, ±1%, or ±0.5% of that given value or range. In this disclosure, a numerical range is expressed as from one endpoint to another or between two endpoints. Unless otherwise stated, all numerical ranges described in this disclosure include the endpoints. Furthermore, when multiple values ​​or characteristics are mentioned as "approximately" the same, it can cover situations where these values ​​are all within ±10%, ±5%, ±1%, or ±0.5% of the average of these values.

[0074] The foregoing description briefly outlines the features of certain embodiments of this disclosure, enabling those skilled in the art to gain a more comprehensive understanding of the various forms of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A signal conversion circuit, comprising: a first capacitor pair, including a first capacitor and a second capacitor having the same capacitance value, wherein the first capacitor and the second capacitor are both coupled to an input signal in the first sampling stage, and are not coupled to the input signal in the first conversion stage following the first sampling stage; and a comparator having a first input terminal and a second input terminal, wherein in the first conversion stage, the first capacitor is coupled between the first input terminal and a first reference signal, and the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal; and the comparator is configured to compare the signal level of the first input terminal with the signal level of the second input terminal. The input signal is converted; wherein the signal conversion circuit is used to convert the input signal in a first conversion cycle to generate a first conversion result, and to convert the input signal in a second conversion cycle to generate a second conversion result; the first conversion cycle includes the first sampling stage and the second sampling stage, and the second conversion cycle includes a second sampling stage and a second conversion stage; wherein the first capacitor and the second capacitor are both coupled to the input signal in the second sampling stage, and are not coupled to the input signal in the second conversion stage; in the second conversion stage, the first capacitor is coupled between the first input terminal and the second reference signal, and the second capacitor is coupled between the first input terminal and the first reference signal.

2. A signal conversion circuit, comprising: a first capacitor pair, including a first capacitor and a second capacitor having the same capacitance value, wherein in a first sampling stage, the first capacitor is coupled between an input signal and a first reference signal, and the second capacitor is coupled between the input signal and a second reference signal different from the first reference signal; and a comparator having a first input terminal and a second input terminal, wherein in a first conversion stage after the first sampling stage, both the first capacitor and the second capacitor are coupled to the first input terminal but not coupled to the input signal, and the comparator is used to compare the signal level of the first input terminal with the signal level of the second input terminal to convert the input signal. An input signal; wherein the signal conversion circuit is used to convert the input signal in a first conversion cycle to generate a first conversion result, and to convert the input signal in a second conversion cycle to generate a second conversion result; the first conversion cycle includes a first sampling phase and a second sampling phase, and the second conversion cycle includes a second sampling phase and a second conversion phase; wherein the first capacitor and the second capacitor are both coupled to the input signal in the second sampling phase, and are not coupled to the input signal in the second conversion phase; in the second conversion phase, the first capacitor is coupled between the first input terminal and the second reference signal, and the second capacitor is coupled between the first input terminal and the first reference signal.

3. A signal conversion circuit, comprising: a first capacitor pair, including a first capacitor and a second capacitor having the same capacitance value, wherein the first capacitor and the second capacitor are both coupled to an input signal in the first sampling stage, and are not coupled to the input signal in the first conversion stage following the first sampling stage; and a comparator having a first input terminal and a second input terminal, wherein in the first conversion stage, the first capacitor is coupled between the first input terminal and a first reference signal, and the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal. The comparator is used to compare the signal level of the first input terminal with the signal level of the second input terminal to convert the input signal; wherein in the first sampling stage, the first terminals of the first capacitor and the second capacitor are respectively coupled to the input signal, and the second terminals of the first capacitor and the second capacitor are respectively coupled to the first reference signal and the second reference signal; in the first conversion stage, the first terminals of the first capacitor and the second capacitor are respectively coupled to the first reference signal and the second reference signal, and the second terminals of the first capacitor and the second capacitor are respectively coupled to the first input terminal.

4. The signal conversion circuit as described in claim 3, wherein when a comparison result output by one output of the comparator indicates that the signal level of the first input is less than the signal level of the second input, the second capacitor is used to couple between the first input and the first reference signal; and when the comparison result indicates that the signal level of the first input is greater than the signal level of the second input, the first capacitor is used to couple between the first input and the second reference signal.

5. A signal conversion circuit, comprising: a first capacitor pair, including a first capacitor and a second capacitor having the same capacitance value, wherein the first capacitor and the second capacitor are both coupled to an input signal in the first sampling stage, and are not coupled to the input signal in the first conversion stage following the first sampling stage; and a comparator having a first input terminal and a second input terminal, wherein in the first conversion stage, the first capacitor is coupled between the first input terminal and a first reference signal, and the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal; and the comparator is configured to convert the first capacitor into a second reference signal. The signal level of the first input terminal is compared with the signal level of the second input terminal to convert the input signal; wherein, in the first sampling stage, the first terminals of the first capacitor and the second capacitor are each coupled to a third reference signal, and the second terminals of the first capacitor and the second capacitor are each coupled to the input signal; the third reference signal is different from the first reference signal and different from the second reference signal; in the first conversion stage, the first terminals of the first capacitor and the second capacitor are respectively coupled to the first reference signal and the second reference signal, and the second terminals of the first capacitor and the second capacitor are each coupled to the first input terminal.

6. The signal conversion circuit as described in claim 5, wherein the signal level of the third reference signal is equal to the average of the signal level of the first reference signal and the signal level of the second reference signal.

7. The signal conversion circuit as claimed in claim 3, wherein the input signal is a differential signal comprising a positive component and a negative component, and the first capacitor and the second capacitor are both coupled to one of the positive component and the negative component during the first sampling stage; the signal conversion circuit further comprises: a second capacitor pair comprising a third capacitor and a fourth capacitor having the same capacitance value, the third capacitor and the fourth capacitor being both coupled to the other of the positive component and the negative component during the first sampling stage, but not coupled to the input signal during the first conversion stage, wherein during the first conversion stage, the third capacitor is coupled between the second input terminal and the first reference signal, and the fourth capacitor is coupled between the second input terminal and the second reference signal.

8. The signal conversion circuit as described in claim 3, further comprising: a second capacitor pair, including a third capacitor and a fourth capacitor, wherein the third capacitor and the fourth capacitor each have a capacitance value equal to half the capacitance value of the first capacitor, and are both coupled to the input signal during the first sampling phase; during the first conversion phase, the third capacitor is coupled between the first input terminal and the first reference signal, and the fourth capacitor is coupled between the first input terminal and the second reference signal.

9. The signal conversion circuit as claimed in claim 3, configured to convert the input signal in a first conversion cycle to generate a first conversion result, and to convert the input signal in a second conversion cycle to generate a second conversion result, wherein the first conversion cycle includes the first sampling phase and the second sampling phase, and the second conversion cycle includes a second sampling phase and a second conversion phase; the first capacitor and the second capacitor are both coupled to the input signal in the second sampling phase, and are not coupled to the input signal in the second conversion phase; in the second conversion phase, the first capacitor is coupled between the first input terminal and the second reference signal, and the second capacitor is coupled between the first input terminal and the first reference signal.

10. A signal conversion circuit, comprising: a first capacitor pair, including a first capacitor and a second capacitor having the same capacitance value, wherein in a first sampling stage, the first capacitor is coupled between an input signal and a first reference signal, and the second capacitor is coupled between the input signal and a second reference signal different from the first reference signal; and a comparator having a first input terminal and a second input terminal, wherein in a first conversion stage after the first sampling stage, both the first capacitor and the second capacitor are coupled to the first input terminal but not to the input signal, and the comparator is configured to compare the signal level of the first input terminal with the signal level of the second input terminal to convert the input signal; wherein in the first conversion stage, both the first capacitor and the second capacitor are coupled between a third reference signal and the first input terminal, the third reference signal being different from the first reference signal and the second reference signal.

11. The signal conversion circuit as claimed in claim 10, wherein when a comparison result output by one output of the comparator indicates that the signal level of the first input is less than the signal level of the second input, both the first capacitor and the second capacitor are coupled between the first input and the first reference signal; and when the comparison result indicates that the signal level of the first input is greater than the signal level of the second input, both the first capacitor and the second capacitor are coupled between the first input and the second reference signal.

12. The signal conversion circuit as claimed in claim 10, wherein in the first sampling stage, the first terminals of the first capacitor and the second capacitor are each coupled to the input signal, and the second terminals of the first capacitor and the second capacitor are each coupled to the first reference signal; and in the first conversion stage, the first terminals of the first capacitor and the second capacitor are each coupled to the third reference signal, and the second terminals of the first capacitor and the second capacitor are each coupled to the first input terminal.

13. The signal conversion circuit as described in claim 10, wherein in the first sampling stage, the first terminals of the first capacitor and the second capacitor are respectively coupled to the first reference signal and the second reference signal, and the second terminals of the first capacitor and the second capacitor are both coupled to the input signal; in the first conversion stage, the first terminals of the first capacitor and the second capacitor are both coupled to the third reference signal, and the second terminals of the first capacitor and the second capacitor are both coupled to the first input terminal.

14. The signal conversion circuit as claimed in claim 10, wherein the input signal is a differential signal comprising a positive component and a negative component, and the first capacitor and the second capacitor are both coupled to one of the positive component and the negative component during the first sampling phase; the signal conversion circuit further comprises: a second capacitor pair comprising a third capacitor and a fourth capacitor having the same capacitance value, the third capacitor and the fourth capacitor being both coupled to the other of the positive component and the negative component during the first sampling phase, but not coupled to the input signal during the first conversion phase, wherein during the first conversion phase, the third capacitor is coupled between the second input terminal and the first reference signal, and the fourth capacitor is coupled between the second input terminal and the second reference signal.

15. The signal conversion circuit as claimed in claim 10, further comprising: a second capacitor pair, including a third capacitor and a fourth capacitor, wherein the third capacitor and the fourth capacitor each have a capacitance value equal to half the capacitance value of the first capacitor, and are both coupled to the input signal during the first sampling phase; during the first conversion phase, the third capacitor is coupled between the first input terminal and the first reference signal, and the fourth capacitor is coupled between the first input terminal and the second reference signal.

16. The signal conversion circuit as claimed in claim 10, configured to convert the input signal in a first conversion cycle to produce a first conversion result, and to convert the input signal in a second conversion cycle to produce a second conversion result, wherein the first conversion cycle includes the first sampling phase and the second sampling phase, and the second conversion cycle includes a second sampling phase and a second conversion phase; the first capacitor and the second capacitor are both coupled to the input signal in the second sampling phase, and are not coupled to the input signal in the second conversion phase; in the second conversion phase, the first capacitor is coupled between the first input terminal and the second reference signal, and the second capacitor is coupled between the first input terminal and the first reference signal.

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