Graphics processing unit, data processing system and method for accelerating machine learning operations

Abstract

An embodiment of a computing device for performing machine learning operations is provided. The computing device includes instruction decoding logic for decoding a single instruction comprising multiple operands into a single decoded instruction, the multiple operands having different accuracies, and a general-purpose graphics computing unit including a first logic unit and a second logic unit for executing the single decoded instruction. Executing the single decoded instruction includes performing a first instruction operation with a first accuracies on a first set of operands among the multiple operands, and simultaneously performing a second instruction operation with a second accuracies on a second set of operands among the multiple operands.

Description

[Technical Field] The embodiments generally relate to data processing, and more specifically to data processing via a general graphics processing unit. [Previous Technology] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, and depth testing. Traditionally, graphics processors (GPUs) use fixed-function computing units (FMUs) to process graphics data; however, more recently, some GPUs have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data. To further enhance performance, graphics processing units (GPUs) typically implement processing techniques such as pipeline operations, which attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel GPUs with a Single Instruction, Multiple Thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, an array of parallel threads attempts to execute program instructions together synchronously as frequently as possible to increase processing efficiency. A general overview of the software and hardware for SIMT architecture can be found in Shane Cook, CUDA Programming, Chapter 3, pp. 37–51 (2013) and / or Nicholas Wilt, CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2–3.1.2 (June 2013). [Simplified Explanation of the Diagram] To enable a detailed understanding of the features of the invention, a more specific description of the invention can be obtained by referring to the embodiments, parts of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments and should therefore not be considered as limiting the scope of all embodiments. Figure 1 is a block diagram showing a computer system configured to implement one or more embodiments described herein; Figures 2A-2D show parallel processor components according to embodiments; Figures 3A-3B are block diagrams of graphics multiprocessors according to embodiments; Figures 4A-4F show exemplary architectures in which a plurality of GPUs are communicatively coupled to a plurality of multi-core processors; Figure 5 shows a graphics processor pipeline according to an embodiment; Figure 6 shows a machine learning software stack according to an embodiment; Figure 7 shows a highly parallel general-purpose graphics processing unit according to an embodiment; Figure 8 shows a multi-GPU computing system according to an embodiment; Figures 9A-9B show exemplary deep neural networks. Figure 10 shows an example recurrent neural network; Figure 11 shows the training and deployment of a deep neural network; Figure 12 is a block diagram showing distributed learning; Figure 13 shows an example inference system single-chip (SOC) suitable for performing inference using a trained model; Figure 14 is a block diagram of a multiprocessor unit according to one embodiment; Figure 15 shows a mixed-precision processing system according to one embodiment; Figure 16 shows an additional mixed-precision processing system according to one embodiment; Figure 17 is a flowchart of the computational logic for a mixed-precision processing system according to one embodiment; Figure 18 is a diagram of a mixed-precision processing system according to one embodiment. Figure 19 shows a machine learning system according to one embodiment; Figure 20 shows the logical operation of a machine learning system according to one embodiment; Figure 21 is a block diagram of a processing system according to an embodiment; Figure 22 is a block diagram of a processor according to an embodiment; Figure 23 is a block diagram of a graphics processor according to an embodiment; Figure 24 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments; Figure 25 is a block diagram of a graphics processor provided by an additional embodiment; Figure 26 shows the thread execution logic including an array of processing elements utilized in some embodiments; Figure 27 shows the execution logic according to some embodiments. Figure 28 is a block diagram of a graphics processor instruction format according to another embodiment; Figures 29A-29B show the graphics processor command format and command sequence according to some embodiments; Figure 30 shows an example graphics software architecture for a data processing system according to some embodiments; Figure 31 shows a block diagram of an IP core development system according to an embodiment; Figure 32 shows a block diagram of an example system-on-a-chip integrated circuit according to an embodiment; Figure 33 shows a block diagram of an additional graphics processor according to an embodiment; and Figure 34 shows a block diagram of an additional example graphics processor of the system-on-a-chip integrated circuit according to an embodiment. [Summary of the Invention] [Summary of the Invention] and [Implementation Methods] In some embodiments, the graphics processing unit (GPU) is communicatively coupled to the host / processor core to accelerate graphics processing, machine learning processing, pattern analysis processing, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated onto the same package or die as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or die). Regardless of the GPU connection method, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions. In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of this embodiment. System Overview Figure 1 is a block diagram showing a computing system 100 configured to implement one or more embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104, which communicates via interconnect paths including a memory hub 105. The memory hub 105 may be a standalone component within a chipset assembly or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, which enables the computing system 100 to receive input from one or more input devices 108. Furthermore, the I / O hub 107 enables a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, one or more display devices 110A coupled to I / O hub 107 may include local, internal or embedded display devices. In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to a memory hub 105 via a bus or other communication link 113. The communication link 113 may be any number of standard-based communication link technologies or protocols, such as (but not limited to) PCI Express; or it may be a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 112 form a compute-intensive parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a plurality of integrated core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) for enabling direct connection to one or more display devices 110B. Within the I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide a storage mechanism for computing system 100. I / O switch 116 can be used to provide an interface mechanism for connecting I / O hub 107 to other components, such as network adapter 118 and / or wireless network adapter 119 which may be integrated into the platform, and various other devices that can be added via one or more external devices 120. Network adapter 118 may be an Ethernet adapter or other wired network adapter. Wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other networking devices including one or more radios. The computing system 100 may include other components not explicitly shown (including USB or other port connections, optical storage drives, video capture devices, etc.) and may also be connected to the I / O hub 107. The communication paths that interconnect the various components in FIG1 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express) or any other bus or point-to-point communication interface and / or protocol, such as NV Link high-speed interconnect or interconnect protocols known in the art. In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and form a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while retaining the basic computing architecture, as described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other MCMs into a modular computing system. It will be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connectivity topology (including the number and configuration of bridges, the number of processors 102, and the number of parallel processors 112) can be modified as needed. For example, in some embodiments, system memory 104 is directly connected to processors 102 rather than through bridges, while other devices communicate with system memory 104 via memory hub 105 and processors 102. In other alternative topologies, parallel processors 112 are connected to I / O hub 107 or directly to one or more processors 102, rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 connected via multiple sockets, which may be coupled to two or more instances of parallel processors 112. Some specific components shown in this document are optional and may not be included in all implementations of computing system 100. For example, any number of external cards or peripherals may be supported, or some components may be removed. Furthermore, some architectures may use different terms for components similar to those shown in Figure 1. For example, memory hub 105 may be referred to as the Northbridge in some architectures, while I / O hub 107 may be referred to as the Southbridge. Figure 2A shows a parallel processor 200 according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The parallel processor 200 shown is a variation of the one or more parallel processors 112 shown in Figure 1 according to an embodiment. In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface (such as memory hub 105). The connection between memory hub 105 and I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar switch 216, wherein the host interface 206 receives commands for performing processing operations, and the memory crossbar switch 216 receives commands for performing memory operations. When host interface 206 receives a command buffer via I / O unit 204, host interface 206 can direct the work operations used to execute those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to assign commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in an active state before work is assigned to a processing cluster of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, resulting in rapid preemption and background switching of threads occurring on processing array 212. In one embodiment, host software can demonstrate that workloads are scheduled on processing array 212 via one of a plurality of graphics processing doorbells. The workload can then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller. Processing cluster array 212 may include up to "N" processing clusters (e.g., clusters 214A, 214B to 214N). Each cluster 214A-214N in processing cluster array 212 can execute a large number of parallel threads. Scheduler 210 may use various scheduling and / or work allocation algorithms to allocate work to clusters 214A-214N in processing cluster array 212, which may vary depending on the workload generated by different types of programs or computations. Scheduling may be dynamically handled by scheduler 210 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N in processing cluster array 212 may be configured to process different types of programs or to perform different types of computations. The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations. In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Furthermore, the processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as (but not limited to) vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from system memory for processing via I / O unit 204. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory. In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into approximately equal-sized tasks, preferably causing the distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen blanking operations to generate a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing. During operation, the processing cluster array 212 can receive processing jobs to be executed via a scheduler 210, which receives commands defining the processing jobs from the front end 208. For graphics processing operations, processing jobs may include indicators of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as status parameters and commands defining how the data should be processed (e.g., which program should be executed). The scheduler 210 can be configured to retrieve indicators corresponding to these jobs or to receive indicators from the front end 208. The front end 208 can be configured to ensure that the processing cluster array 212 is configured to be active before the workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated. Each of one or more instances of the parallel processing unit 202 may be coupled to the parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar switch 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition units 220A, 220B to 220N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices. In various embodiments, memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will understand that specific implementations of memory units 224A-224N may vary and may be selected from a variety of conventional designs. Render targets (such as frame buffers or texture maps) may be stored across memory units 224A-224N, allowing partition units 220A-220N to write portions of each render target in parallel to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be excluded to facilitate a unified memory design that utilizes system memory combined with local cache memory. In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory cells 224A-224N within the parallel processor memory 222. The memory crossbar switch 216 can be configured to transfer the output of each cluster 214A-214N to any partition cell 220A-220N or to another cluster 214A-214N where additional processing operations can be performed on the output. Each cluster 214A-214N can communicate with the memory interface 218 via the memory crossbar switch 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar switch 216 has a connection to a memory interface 218 for communication with I / O unit 204, and a connection to a local instance of parallel processor memory 222, which enables processing units within different processing clusters 214A-214N to communicate with system memory or other memory not local to parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use a virtual channel to separate traffic streams between clusters 214A-214N and partition units 220A-220N. While a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be hosted on a single external card, or multiple external cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating-point units relative to other instances. Systems combining one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented with a variety of configurations and form factors, including but not limited to desktop computers, notebook or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. Figure 2B is a block diagram of the partitioning unit 220 according to an embodiment. In one embodiment, the partitioning unit 220 is an example of one of the partitioning units 220A-220N of Figure 2A. As shown, the partitioning unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (grid operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read errors and emergency write-back requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be transmitted to the frame buffer for processing via the frame buffer interface 225. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as memory cells 224A-224N of Figure 2 (e.g., within the parallel processor memory 222). In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. ROP 226 then outputs the processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic using one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, incremental color compression is performed on a per-tile basis for both depth and color data. In some embodiments, ROP 226 is included within processing clusters (e.g., clusters 214A-214N of FIG. 2) rather than within segmentation unit 220. In such embodiments, read and write requests for pixel data are transmitted via memory crossbar switch 216, rather than pixel fragment data. Processed graphics data may be displayed on a display device (such as one or more display devices 110 of FIG. 1), sent for further processing by processor 102, or sent for further processing by one of the processing entities within parallel processor 200 of FIG. 2A. Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an example of one of the processing clusters 214A-214N of Figure 2A. The processing cluster 214 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In some embodiments, Single Instruction Multiple Data (SIMD) instruction delivery technology is used to support the parallel execution of a large number of threads without requiring multiple independent instruction units. In other embodiments, Single Instruction Multiple Threads (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses common instruction units configured to send instructions to a set of processing engines within each of the processing clusters. Unlike SIMD execution architectures (where all processing engines typically execute the same instructions), SIMT execution allows different threads to more easily follow distributed execution paths through predetermined thread routines. Those skilled in the art will understand that the SIMD processing architecture represents a functional subset of the SIMT processing architecture. The operation of processing cluster 214 can be controlled via pipeline manager 232, which distributes processing work to SIMT parallel processors. Pipeline manager 232 receives instructions from scheduler 210 of FIG. 2 and manages the execution of those instructions via graphics multiprocessor 234 and / or texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within processing cluster 214. One or more instances of graphics multiprocessor 234 can be included within processing cluster 214. Graphics multiprocessor 234 can process data, and data crossover switch 240 can be used to distribute processed data to one of several possible destinations, including other shader units. Pipeline manager 232 can assist in the distribution of processed data by specifying the destination of the processed data to be distributed via data crossover switch 240. Each graphics multiprocessor 234 within cluster 214 may include the same group of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be sent before previous instructions complete. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units may exist. Instructions transmitted to processing cluster 214 constitute threads. A group of threads executed across this set of parallel processing engines is called a thread group. Thread groups execute the same program for different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed in consecutive clock cycles. In one embodiment, multiple thread groups may be executed simultaneously on the graphics multiprocessor 234. In one embodiment, the graphics multiprocessor 234 includes internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and use cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 also has access to L2 caches within partitioned units (e.g., partitioned units 220A-220N of FIG. 2), which can be shared among all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 202 may be used as global memory. Embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 may share common instructions and data that can be stored in the L1 cache 308. Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG2. The MMU 245 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles, and (optionally) cache line indices. The MMU 245 may include a Translation Lookaside Buffer (TLB) or a cache or L1 cache that may reside within the graphics multiprocessor 234 or the processing cluster 214. Physical addresses are processed to allocate surface data access locality to allow for efficient interleaving of request partitions. The cache line index may be used to determine whether a request for a cache line is a hit or a miss. In graphics and computing applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or (in some embodiments) from an L1 cache within the graphics multiprocessor 234, and retrieved as needed from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs processed work to a data crossbar switch 240 to provide the processed work to another processing cluster 214 for further processing, or stores the processed work in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 216. The preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct data to the ROP unit, and may be configured together with segmentation units as described herein (e.g., segmentation units 220A-220N of FIG. 2). The preROP 242 unit can perform optimization for color blending, organize pixel color data, and perform address translation. It will be understood that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Furthermore, although only one processing cluster 214 is shown, parallel processing units as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214, using independent and distinct processing units, L1 caches, etc. Figure 2D shows a graphics multiprocessor 234 according to an embodiment. In this embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to cache memory 272 and shared memory 270 via a memory and cache interconnect 268. In one embodiment, instruction cache 252 receives a string of instructions to be executed from pipeline manager 232. These instructions are cached in instruction cache 252 and scheduled for execution by instruction unit 254. Instruction unit 254 can schedule instructions into thread groups (e.g., meridians), where each thread in the thread group is assigned to a different execution unit within GPGPU core 262. Instructions can access either a local, shared, or global address space by specifying an address within a unified address space. Address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 266. Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides operands temporarily stored in the data paths of functional units (e.g., GPGPU core 262, load / store unit 266) connected to graphics multiprocessor 324. In one embodiment, register file 258 is divided among the functional units such that each functional unit is configured with a dedicated portion of register file 258. In another embodiment, register file 258 is divided among different meridians being executed by graphics multiprocessor 324. GPGPU core 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions of graphics multiprocessor 324. According to embodiments, GPGPU core 262 may be architecturally similar or architecturally different. For example, in one embodiment, a first portion of GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard in floating-point arithmetic or cause variable-precision floating-point arithmetic. Graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic. In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction for multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated at compile time by a colorimeter compiler or automatically generated at runtime, and are compiled for Single Program Multiple Data (SPMD) or SIMT architectures. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit. The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 324 to the scratchpad file 258 and to the common memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the common memory 270 and the scratchpad file 258. The scratchpad file 258 can operate at the same frequency as the GPGPU core 262, so data transfer between the GPGPU core 262 and the scratchpad file 258 has very low latency. The common memory 270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 234. The cache memory 272 can be used as a data cache, for example, to cache texture data transferred between functional units and texture units 236. The common memory 270 can also be used as a programmable cache. In addition to the auto-cached data stored in cache memory 272, the threads running on the GPGPU core 262 can programmatically store data in shared memory. Figures 3A-3B show additional graphics multiprocessors according to an embodiment. The graphics multiprocessors 325 and 350 shown are variations of the graphics multiprocessor 234 of Figure 2C. The graphics multiprocessors 325 and 350 shown can be configured as streaming multiprocessors (SM) capable of executing a large number of threads simultaneously. Figure 3A illustrates a graphics multiprocessor 325 according to an additional embodiment. The graphics multiprocessor 325 includes multiple additional instances of the execution resource units relative to the graphics multiprocessor 234 of Figure 2D. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, temporary register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346. The components can communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more cross switches to enable communication between the components of the graphics multiprocessor 325. In one embodiment, interconnect structure 327 is a separate, high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation among components. Figure 3B illustrates a graphics multiprocessor 350 according to an additional embodiment. As shown in Figures 2D and 3A, the graphics processor includes multiple sets of execution resources 356A-356D, each set of execution resources including multiple instruction units, temporary register files, GPGPU cores, and load memory units. Execution resources 356A-356D can work in conjunction with texture units 360A-360D for texture operations, while sharing an instruction cache 354 and a shared memory 362. In one embodiment, execution resources 356A-356D can share the instruction cache 354 and the shared memory 362, as well as multiple instances of texture and / or data cache memory 358A-358B. The various components can communicate via an interconnect configuration 352 similar to the interconnect configuration 327 of Figure 3A. Those skilled in the art will understand that the architectures described in Figures 1, 2A-2D, and 3A-3B are illustrative and not limiting of the scope of this embodiment. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including (not limited to) one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units (such as parallel processing unit 202 of Figure 2), and one or more graphics processors or special purpose processing units, without departing from the scope of the embodiments described herein. In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In other embodiments, the GPU may be integrated into the same package or die as such cores and communicatively coupled to those cores via internal processor buses / interconnects (i.e., within the package or die). Regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions. Technology for GPU-to-host processor interconnect Figure 4A illustrates an exemplary architecture in which a plurality of GPUs 410-413 are communicatively coupled to a plurality of multi-core processors 405-406 via high-speed links 440-443 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, high-speed links 440-443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput. Furthermore, in one embodiment, two or more of GPUs 410-413 are interconnected via high-speed links 444-445, which may use the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, all communication between the various system components shown in FIG. 4A may be accomplished using the same protocol / link (e.g., via a common interconnect configuration). However, as stated above, the basic principles of the invention are not limited to any particular type of interconnect technology. In one embodiment, each multi-core processor 405-406 is individually communicatively coupled to processor memory 401-402 via memory interconnects 430-431, and each GPU 410-413 is individually communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. For example (and not limitingly), processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory while other portions may be non-volatile memory (e.g., using a second-order memory (2LM) hierarchy). As described below, although individual processors 405-406 and GPUs 410-413 can be physically coupled to specific memories 401-402, 420-423, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the "effective address" space) is allocated among all the individual physical memories. For example, processor memories 401-402 may each contain 64GB of system memory address space, while GPU memories 420-423 may each contain 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example). Figure 4B shows additional details regarding the interconnect between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407. The processor 407 shown includes a plurality of cores 460A-460D, each having a translation backup buffer 461A-461D and one or more caches 462A-462D. These cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the invention (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, recorder buffer, etc.). Caches 462A-462D may include first-order (L1) and second-order (L2) caches. Furthermore, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple sets of cores 460A-460D. For example, one embodiment of processor 407 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and graphics accelerator integrated module 446 are connected to system memory 441, which may include processor memory 401-402. Data and instructions stored in the various caches 462A-462D, 456 and system memory 441 are kept in sync via inter-core communication through a sync bus 464. For example, each cache may have associated cache sync logic / circuit to communicate via the sync bus 464 in response to a detected read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented on the sync bus 464 to snoop on cache accesses. Cache snooping / sync technology is well known to those skilled in the art and will not be described in detail herein so as not to obscure the basic principles of the invention. In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to a synchronization bus 464, allowing graphics acceleration module 446 to participate in cache synchronization protocols as a peer of those cores. Specifically, interface 435 provides connection to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), while interface 437 connects graphics acceleration module 446 to high-speed link 440. In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, background management, and interrupt management services for the plurality of graphics processing engines 431, 432, and N of the graphics acceleration module 446. Each of the graphics processing engines 431, 432, and N may contain its own graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, and N may contain different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and splitting engines. In other words, the graphics acceleration module may be a GPU with a plurality of graphics processing engines 431-432, and N, or the graphics processing engines 431-432, and N may be individual GPUs integrated into a common package, line card, or chip. In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as valid-to-real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation backup buffer (TLB) (not shown) for translating virtual / valid cache to physical / real addresses. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, N. In one embodiment, the data stored in cache 438 and graphics memories 433-434, N are kept in sync with core caches 462A-462D, 456 and system memory 411. As described above, this can be accomplished via proxy circuit 425, which participates in cache synchronization mechanism for cache 438 and memory 433-434, N (e.g., sending updates to cache 438 for modifications / accesses to cache lines on processor caches 462A-462D, 456, and receiving updates from cache 438). A set of registers 445 stores background data for use by threads executed by graphics processing engines 431-432, N, while background management circuitry 448 manages the thread background. For example, background management circuitry 448 can perform save and restore operations to save and restore the background of each thread during background switching (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during background switching, background management circuitry 448 can store the current register values ​​to a designated area in memory (e.g., identified by a background indicator). When returning to the background, it can then restore these register values. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from the system device. In one implementation, the virtual / valid address from the graphics processing engine 431 is translated into a real / physical address in system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 446 and / or other accelerator devices. The graphics acceleration module 446 may be dedicated to a single application executed on the processor 407 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). These resources may be subdivided into "slices" that are configured to different VMs and / or applications according to the processing needs and priorities associated with the VMs and / or applications. Therefore, the accelerator integrated circuitry functions as a bridge to the system for the graphics acceleration module 446, and provides address translation and system memory caching services. Furthermore, the accelerator integrated circuitry 436 can provide virtualization assistance to the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engine. Because the hardware resources of graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is to physically decouple the graphics processing engines 431-432, N, so that they appear as independent units to the system. As described above, in the illustrated embodiment, one or more graphics memories 433-434, M are individually coupled to each of the graphics processing engines 431-432, N. Graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. Graphics memories 433-434, M can be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, to reduce data traffic through high-speed link 440, an offset technique is used to ensure that the data stored in graphics memory 433-434, M is data that is most frequently used by graphics processing engines 431-432, N and preferably not used (at least infrequently) by cores 460A-460D. Similarly, the offset mechanism attempts to keep the data required by these cores (and preferably not graphics processing engines 431-432, N) in the caches 462A-462D, 456 of these cores and system memory 411. Figure 4C shows another embodiment in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via a high-speed link 440 through interfaces 437 and 435 (which, again, may utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform the same operations as those described with respect to Figure 4B, but potentially has higher throughput due to its proximity to the harmonic bus 462 and caches 462A-462D, 426. One embodiment supports different programming models, including a dedicated programming model (without graphics acceleration module virtualization) and a common programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446. In one embodiment of the dedicated application model, graphics processing engines 431-432, N are dedicated to a single application or program within a single operating system. A single application can inject requests from other applications into graphics engines 431-432, N, which provide virtualization within a VM / segment. In a dedicated programming model, graphics processing engines 431-432, N can be shared by multiple VMs / application partitions. These shared models require a system supermanager to virtualize graphics processing engines 431-432, N to allow access from individual operating systems. For a single-partition system without a supermanager, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to individual programs or applications. For a common programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N-series use program disposal to select program elements. In one embodiment, the program element is stored in system memory 411 and is addressable using the effective address to real address translation technique described herein. The program disposal may be an implementation-specific value provided to the host program when the graphics processing engine 431-432, N logs into its background (i.e., when calling system software to add the program element to the program element list). The lower 16 bits of the program disposal may be an offset of the program element within the program element list. Figure 4D shows an example accelerator integrated chip 490. As used herein, "chip" includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application-enabled address space 482 within system memory 411 stores program elements 483. In one embodiment, program element 483 is stored in response to a GPU call 481 from an application 480 executed on processor 407. Program element 483 contains the program state of the corresponding application 480. The job descriptor (WD) 484 contained in program element 483 may be a single job requested by the application or may contain a pointer to a queue of jobs. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482. The graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all or a subset of programs in the system. Embodiments of the invention include an infrastructure for setting program states and transmitting WD 484 to the graphics acceleration module 446 to begin operation in a virtualized environment. In one implementation, a dedicated programming model is used for implementation-specific purposes. In this model, a single program owns either a graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single program, when the graphics acceleration module 446 is assigned, the super administrator initializes the accelerator integrated circuit 436 for its owned partition, while the operating system initializes the accelerator integrated circuit 436 for its owned program. During operation, the WD retrieval unit 491 in the accelerator integration chip 490 retrieves the next WD 484, which includes instructions for the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, the data from the WD 484 can be stored in a register 445 and used by the MMU 439, interrupt management circuitry 447, and / or background management circuitry 446. For example, one embodiment of the MMU 439 includes segmentation / page walkthrough circuitry for accessing segmentation / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the valid address 493 generated by the graphics processing engines 431-432, N is translated into a real address by the MMU 439. In one embodiment, the registers 445 of the same group are copied to the respective graphics processing engines 431-432, N and / or graphics acceleration modules 446, and can be initialized by the super manager or the operating system. Each of these copied registers may be included in the accelerator integration chip 490. Example registers that can be initialized by the super manager are shown in Table 1. Example registers that can be initialized by the operating system are shown in Table 2. In one embodiment, each WD 484 is dedicated to a specific graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required for the graphics processing engine 431-432, N to perform its work, or it may be an index pointing to the memory location of a command queue that the application has set to complete the work. Figure 4E shows additional details of one embodiment of the shared model. This embodiment includes a super manager real address space 498 where a program element list 499 is stored. The super manager real address space 498 is accessible via a super manager 496 that virtualizes the graphics acceleration module engine of the operating system 495. The shared programming model allows all or a subset of programs from all or a subset of segments within the system to use the graphics acceleration module 446. The graphics acceleration module 446 is based on two programming models shared by multiple programs and segments: time-slice sharing and graphics-guided sharing. In this model, the system super manager 496 possesses the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization via the system super manager 496, the graphics acceleration module 446 must meet the following requirements: 1) Application job requests must be autonomous (i.e., the state does not need to be maintained between jobs); or the graphics acceleration module 446 must provide background saving and recovery mechanisms. 2) Application job requests must be completed within a specified time frame by the graphics acceleration module 446, including any conversion errors, or the graphics acceleration module 446 must provide the ability to pre-empt the processing of the job. 3) When operating in this guided shared programming model, the graphics acceleration module 446 must ensure fairness between programs. In one embodiment, for the common model, application 480 is required to make a system call to operating system 495 using the graphics acceleration module 446 type, working descriptor (WD), permission mask register (AMR) value, and background save / restore region index (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is explicitly formatted for the graphics acceleration module 446 and can be in the following forms: a graphics acceleration module 446 command, a valid address index pointing to a user-defined structure, a valid address index pointing to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current program. The value passed to the operating system is similar to that of an application setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implement a User Access Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the HyperManager call. The HyperManager 496 can selectively apply the current User Access Mask Overwrite Register (AMOR) value before placing the AMR in program element 483. In one embodiment, CSRP is one of registers 445 containing the valid address of a region in the application address space 482 of the graphics acceleration module 446, used to save and restore the background state. This indicator is selective if no state needs to be saved between tasks or when a task is preempted. The background save / restore region can be fixed system memory. Upon receiving the system call, operating system 495 verifies that application 480 is logged in and has been granted permission to use graphics acceleration module 446. Operating system 495 then calls super manager 496, which has the information shown in Table 3. Upon receiving a call from the super manager, the super manager 496 verifies that the operating system 495 is logged in and has been granted permission to use the graphics acceleration module 446. The super manager 496 then places the program element 483 into the program element link table for the corresponding graphics acceleration module 446 type. The program element may include the information shown in Table 4. In one embodiment, the super manager initializes a plurality of accelerator integration chip 490 registers 445. As shown in Figure 4F, one embodiment of the present invention utilizes a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 access processor memories 401-402 using the same virtual / effective memory address space and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby allocated across processor memories 401-402 and GPU memories 420-423 to allow any processor or GPU to access any physical memory using a virtual address mapped to that memory. In one embodiment, the offset / coherence management circuitry 494A-494E within one or more of the MMUs 439A-439E ensures cache coherence between the host processor (e.g., 405) and the cache of the GPUs 410-413, and implements offset techniques to indicate which types of data should be stored in physical memory. While multiple instances of the offset / coherence management circuitry 494A-494E are shown in FIG. 4F, the offset / coherence circuitry may also be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuitry 436. One embodiment allows GPU-mounted memories 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without suffering the typical performance drawbacks associated with system-wide cache coherency. The ability to access GPU-mounted memories 420-423 as system memory without the burden of heavy cache coherency provides a favorable operating environment for GPU offloading. This configuration allows the host processor 405 to software-configure operands and access computation results without the burden of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) access, all of which are inefficient compared to simple memory access. Furthermore, the ability to access GPU-mounted memories 420-423 without the burden of cache coherency can be critical for offloading computation execution time. In cases with substantial streaming write traffic to memory, for example, cache coherency overhead can significantly reduce the effective write bandwidth as seen by GPUs 410-413. Operator setting efficiency, result access efficiency, and GPU computation efficiency all contribute to determining the effectiveness of GPU offloading. In one implementation, the selection between GPU offset and host processor offset is driven by an offset tracker data structure. An offset table can be used, for example, as a page-granular structure (i.e., controlled at the memory page level), comprising 1 or 2 bits per GPU-loaded memory page. The offset table can be implemented within the stolen memory range of one or more GPU-loaded memories 420-423, with or without offset caching in GPUs 410-413 (e.g., for caching frequently / recently used items in the offset table). Alternatively, the entire offset table can be maintained within the GPU. In one implementation, the offset table entries associated with each access to the GPU-mounted memories 420-423 are accessed before the actual access to the GPU memory, resulting in the following operations: First, local requests from GPUs 410-413 whose pages are found in the GPU offset are directly passed to the corresponding GPU memories 420-423. Local requests from GPUs whose pages are found in the host offset are passed to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, a request from processor 405 whose requested page is found in the host processor offset completes a general memory read similar to the requested one. Alternatively, a request to a GPU offset page can be passed to GPUs 410-413. If the GPU is not currently using the page, the GPU can then redirect the page to the host processor offset. The page offset state can be changed by any of the following: a software-based mechanism, a hardware-assisted software-based mechanism, or (for a limited set of cases) a purely hardware-based mechanism. One mechanism for changing the offset state utilizes an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which then sends a message (or places a command descriptor in the queue) to the GPU to instruct it to change the offset state, and (for some transitions) performs a cache clearing operation on the host machine. The cache clearing operation is necessary for transitions from host processor 405 offset to GPU offset, but not for the reverse transition. In one embodiment, cache synchronization is maintained by the host processor 405 temporarily preventing GPU-offset pages from being cached. To access these pages, the processor 405 may request access from the GPU 410, depending on the implementation of which the GPU 410 may or may not immediately grant access. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that GPU-offset pages are those required by the GPU, not by the host processor 405, and vice versa. Graphics processing pipeline Figure 5 illustrates a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein, such as parallel processor 200 of Figure 2, which in one embodiment is a variant of parallel processor 112 of Figure 1. Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of parallel processing units as described herein (e.g., parallel processing unit 202 of Figure 2). For example, a shader unit (e.g., graphics multiprocessor 234 of Figure 3) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of data assembler 502, primitive assemblers 506, 514, 518, mosaic unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines within processing clusters (e.g., processing cluster 214 of FIG. 3) and corresponding partitioning units (e.g., partitioning units 220A-220N of FIG. 2). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 can be performed by parallel processing logic within a general-purpose processor (e.g., CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 can access on-chip memory (e.g., parallel processor memory 222 of FIG. 2) via a memory interface 528 (which may be an example of memory interface 218 of FIG. 2). In one embodiment, the data set decoder 502 is a processing unit that collects vertex data of surfaces and primitives. The data set decoder 502 then outputs the vertex data (including vertex attributes) to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, illuminates, and transforms vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory for processing vertex data and can be programmed to convert vertex data from object-based coordinate representation to world space coordinate space or normalized device coordinate space. The first instance of the primitive translator 506 receives vertex attributes from the vertex processing unit 50. The primitive translator 506 reads the stored vertex attributes as needed and constructs graphics processing primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches (etc.), as supported by various graphics processing application programming interfaces (APIs). The tessellation control processing unit 508 treats input vertices as control points for a geometric patch. These control points are converted from an input representation of the patch (e.g., the base of the patch) into a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate tessellation factors for the edges of the geometric patch. The tessellation factors apply to a single edge and quantify the degree of viewpoint dependence on details associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into multiple geometric primitives (such as line, triangle, or quadrilateral primitives), which are then transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the sub-segmented patch to generate surface representations and vertex attributes for each vertex associated with the geometric primitives. A second instance of the primitive translator 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics processing primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to translate graphics primitives received from the primitive translator 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and calculate parameters used to rasterize the new graphics primitives. In some embodiments, the geometry processing unit 516 can add or remove elements in the geometry stream. The geometry processing unit 516 outputs these parameters and the vertices specifying the new graphic primitives to the primitive translator 518. The primitive translator 518 receives these parameters and vertices from the geometry processing unit 516 and constructs graphic primitives for processing by the viewport scaling, culling, and trimming unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for processing the geometric data. The viewport scaling, culling, and trimming unit 520 performs trimming, culling, and viewport scaling and outputs the processed graphic primitives to the rasterizer 522. Rasterizer 522 can perform depth culling and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphics primitives to generate fragments and outputs those fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations, including but not limited to texture mapping, shading, blending, texture correction, and individual correction, to produce shaded fragments or pixels that are output to raster operation unit 526. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use in processing the fragment data. Depending on the sampling rate configured for these processing units, fragment or pixel shader programs can be configured to shade samples, pixels, tiles, or other granularities. The raster operation unit 526 is a processing unit that performs raster operations, including but not limited to stenciling, z-testing, blending, etc., and outputs pixel data as processed graphic data to be stored in graphics memory (e.g., parallel processor memory 222 as shown in FIG. 2, and / or system memory 104 as shown in FIG. 1) for display on one or more display devices 110 or for further processing by one or more processors 102 or parallel processors 112. In some embodiments, the raster operation unit 526 is configured to compress z- or color data written to memory and decompress z- or color data read from memory. Machine Learning Overview Machine learning algorithms are algorithms that learn from a set of data. Implementations of machine learning algorithms can be designed to model high-order abstract concepts within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output numerical values ​​from a given input; and morphology recognition algorithms can be used to generate text-to-speech or perform text-to-speech and / or speech recognition. One paradigm type of machine learning algorithm is the neural network. There are many types of neural networks; a simple type is the feedforward network. A feedforward network can be implemented as a non-periodic graph where nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received from the input layer into a representation used to produce the output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within the layers. Data received by nodes in the input layer of the feedforward network is propagated (i.e., "feedforward") to nodes in the output layer via a start-up function that calculates the state of nodes in each successive layer of the network based on coefficients ("weights") individually associated with the edges connecting the layers. Depending on the specific model represented by the algorithm in execution, the output from the neural network algorithm can take many forms. Before a machine learning algorithm can be used to model a specific problem, it is trained using a training dataset. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting the weights until the network model performs with minimal error across all instances of the training dataset. For example, during a supervised learning training procedure for a neural network, the output produced by the network in response to inputs representing instances in the training dataset is compared to the output of the instance's "correct" label. An error signal representing the difference between the output and the labeled output is calculated, and the weights associated with those connections are adjusted to minimize the error as the error signal is passed backward through those layers of the network. The network is considered "trained" when the error of each output produced from the instances of the training dataset is minimized. The accuracy of machine learning algorithms can be significantly affected by the quality of the dataset used to train them. Training procedures can be computationally intensive and can require a significant amount of time on traditional general-purpose processors. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed when adjusting the coefficients in the neural network naturally participate in parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to utilize the parallel processing hardware within general-purpose graphics processing units. Figure 6 is a generalized diagram of the machine learning software stack 600. The machine learning application 602 can be configured to train neural networks using training datasets or to implement machine intelligence using trained deep neural networks. The machine learning application 602 may include training and inference capabilities for neural networks and / or specialized software that can be used to train neural networks before deployment. The machine learning application 602 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation. Hardware acceleration of the machine learning application 602 can be enabled via the machine learning framework 604. The machine learning framework 604 provides a library of machine learning primitives. Machine learning primitives are basic operations commonly performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms would be required to build and optimize their main computational logic associated with their machine learning algorithms, and then further optimize that computational logic as new parallel processors are developed. Instead, the machine learning application can be configured to use the primitives provided by the machine learning framework 604 to perform the necessary computations. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 also provides primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations. The machine learning framework 604 processes input data received from the machine learning application 602 and generates appropriate inputs for the computing framework 606. The computing framework 606 extracts the main instructions provided to the GPGPU driver 608, enabling the machine learning framework 604 to utilize hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to possess internal knowledge of the GPGPU hardware 610's architecture. Furthermore, the computing framework 606 can enable hardware acceleration of the machine learning framework 604 across various types and generations of GPGPU hardware 610. GPGPU Machine Learning Acceleration Figure 7 illustrates a highly parallel general-purpose graphics processing unit 700 according to an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 can be configured to be particularly efficient for the type of computational workload associated with training deep neural networks. Furthermore, the GPGPU 700 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster to improve training speed, particularly for deep neural networks. The GPGPU 700 includes a host interface 702 for enabling connection to a host processor. In one embodiment, the host interface 702 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or communication organization. The GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to allocate threads associated with those commands to a set of compute clusters 706A-706H. These compute clusters 706A-706H share a cache memory 708. The cache memory 708 can serve as a higher-order cache for the cache memory within the compute clusters 706A-706H. The GPGPU 700 includes memories 714A-714B coupled to the compute cluster 706A-H via a set of memory controllers 712A-712B. In various embodiments, memories 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory or 3D stacked memory, including but not limited to high bandwidth memory (HBM). In one embodiment, each compute cluster 706A-706H includes a group of graphics multiprocessors, such as the graphics multiprocessor 400 of FIG. 4A. The graphics multiprocessors of the compute cluster include various types of integer and floating-point logic units capable of performing computational operations ranging from a precision suitable for machine learning computations. For example, and in one embodiment, a subset of the floating-point units in each of the compute clusters 706A-706H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations. Multiple instances of GPGPU 700 can be configured to operate as a compute cluster. The communication mechanisms used for synchronization and data exchange by the compute cluster vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to GPU link 710, which causes direct connection to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are placed in separate data processing systems and communicate via a network device (accessible via host interface 702). In one embodiment, in addition to (or as a replacement for) the host interface 702, the GPU link 710 may be configured to connect to the host processor. While the configuration shown for the GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration for the GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 700 includes fewer compute clusters 706A-706H compared to the training configuration. Furthermore, the memory technology associated with the memories 714A-714B may differ between the inference and training configurations. In one embodiment, the inference configuration of the GPGPU 700 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer inner product instructions, which are commonly used during inference operations of a deployed neural network. Figure 8 illustrates a multi-GPU computing system 800 according to an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to multiple GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI Express switch that couples the processor 802 to a PCI Express bus through which the processor 802 can communicate with the group of GPGPUs 806A-806D. Each of the multiple GPGPUs 806A-806D may be an example of the GPGPU 700 of Figure 7. The GPGPUs 806A-806D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU links may be connected to each of the GPGPUs 806A-806D via dedicated GPU links (such as GPU link 710 in Figure 7). The P2P GPU link 816 enables direct communication between the GPGPUs 806A-806D without requiring communication through the host interface bus (connected to the processor 802). Using the GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or communication with other instances of the multi-GPU computing system 800, for example, via one or more network devices. While in the illustrated embodiment, the GPGPUs 806A-806D are connected to the processor 802 via the host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-806D. Machine learning neural network implementation The computational architectures provided by the embodiments described herein can be configured to perform multiple types of parallel processing, making them particularly suitable for training and deploying neural networks for machine learning. Neural networks can be generalized as networks with graph-like relational capabilities. As is well known in the art, there are various types of neural network implementations for machine learning. As previously mentioned, one exemplary type of neural network is the feedforward network. The second type of neural network is the Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network designed to process data with a known, grid-like topology, such as image data. Therefore, CNNs are commonly used in computational vision and image recognition applications, but they can also be used in other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors driven by individual columns found in the retina), and the outputs of each set of filters are propagated to nodes in subsequent layers of the network. The computation of a CNN involves applying convolutional mathematical operations to each filter to produce the output of that filter. Convolution is a special kind of mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer could be a multidimensional array of data defining various color components of an input image. A convolutional kernel can be a multidimensional array of parameters, which are tuned by the training procedure of the neural network. Recurrent Neural Networks (RNNs) are a family of feedforward neural networks that include feedback connections between layers. RNNs model continuous data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes periods. These periods represent the influence of the current value of a variable on its value at future time points, because at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature of linguistic data. The following graphical representations illustrate exemplary feedforward, CNN, and RNN networks, and describe general procedures for individually training and deploying each of those types of networks. It will be understood that these descriptions with respect to any particular embodiment described herein are exemplary and not limiting, and that in general, the concepts shown can be commonly applied to deep neural networks and machine learning techniques. The neural networks described above can be used to perform deep learning. Deep learning is machine learning that uses deep neural networks. Deep neural networks used for deep learning are artificial neural networks consisting of multiple hidden layers, unlike shallow neural networks that only include a single hidden layer. Deeper neural networks are typically more computationally intensive for training. However, the additional hidden layers enable multi-step pattern recognition, leading to a reduction in output error compared to shallow machine learning techniques. Deep neural networks used for deep learning typically consist of a front-end network for performing feature recognition, coupled to a back-end network that represents a mathematical model that performs operations based on feature representations provided to the model (e.g., object classification, speech recognition, etc.). Deep learning enables machine learning to be performed without requiring manual feature engineering to the model. Instead, deep neural networks learn features based on statistical structure or correlations within the input data. The learned features are then fed to a mathematical model that maps the measured features to the output. The mathematical model used by the network is generally specialized for the specific task to be performed, and different models will be used to perform different tasks. Once the neural network is constructed, a learning model can be applied to it to train it to perform a specific task. This learning model describes how to adjust the weights within the model to reduce the network's output errors. Error backpropagation is a common method used to train neural networks. Input vectors are submitted to the network for processing. The network's output is compared to the desired output using a loss function, and error values ​​are calculated for each neuron in the output layer. These error values ​​are then backpropagated until each neuron has a relevant error value that roughly represents its contribution to the original output. The network can then learn from those errors using algorithms such as stochastic gradient descent to update the neural network's weights. Figures 9A and 9B show an example convolutional neural network. Figure 9A shows the layers within the CNN. As shown in Figure 9A, the example CNN used to model image processing receives input 902 describing the red, green, and blue (RGB) components of an input image. Input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The outputs from the multiple convolutional layers can be selectively processed by a set of fully connected layers 908. As previously described for feedforward networks, neurons in fully connected layers have full connections to all activations in previous layers. The outputs from fully connected layers 908 can be used to produce the output from the network. Activations within fully connected layers 908 can be computed using matrix multiplication instead of convolutions. Not all CNN implementations utilize fully connected layers 908. For example, in some implementations, convolutional layers 906 can produce the output for the CNN. The convolutional layers are sparsely connected, unlike the traditional neural network configuration seen in fully connected layers 908. Traditional neural network layers are fully connected, such that each output unit interacts with each input unit. However, as shown, the convolutional layers are sparsely connected because the output of the convolution of a column is input (replacing the individual state values ​​of the nodes in that column) to nodes in subsequent layers. The kernels associated with these convolutional layers perform convolution operations, and their outputs are passed to the next layer. This dimensionality reduction performed within the convolutional layers is a form of scaling the CNN to process large images. Figure 9B illustrates an example computation phase within a convolutional layer of a CNN. The input to convolutional layer 912 of the CNN can be processed in three stages of convolutional layer 914. These three stages may include convolutional stage 916, detector stage 918, and pooling stage 920. Convolutional layer 914 can then output data to successive convolutional layers. The final convolutional layer of the network can produce output feature map data or provide input to fully connected layers, for example, to generate classification values ​​for the input to the CNN. In convolution stage 916, several convolutions are performed in parallel to produce a set of linear activations. Convolution stage 916 may include affine transformations, which are any transformations that can be specified as a linear transformation plus a transformation. Affine transformations include rotations, transformations, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) that is connected to a specific region in the input, which can be determined as the local region associated with that neuron. The neuron computes the inner product between the weights of the neurons and the local region in the local input to which the neurons are connected. The output from convolution stage 916 defines a set of linear activations, which are processed by successive stages of convolutional layer 914. These linear primings can be handled by detector stage 918. In detector stage 918, each linear priming system is handled by a nonlinear priming function. The nonlinear priming function adds nonlinearity to the overall network without affecting individual cells of the convolutional layer. Several types of nonlinear priming functions can be used. One particular type is the Rectified Linear Unit (ReLU), which uses a priming function defined as f(x) = max(0,x) such that the priming system is thresholded at zero. Pooling stage 920 replaces the pooling function of convolutional layer 906 with a summary statistic of nearby outputs. Pooling functions can be used to introduce transformation invariance into neural networks, so that small transformations to the input do not change the pooled output. Invariance to local transformations can be useful in situations where the presence of a feature in the input data is more important than the precise location of that feature. Several types of pooling functions can be used during pooling stage 920, including max pooling, average pooling, and 12-norm pooling. Furthermore, some CNN implementations do not include a pooling stage. Instead, such implementations use an additional convolutional stage with an increased stride relative to the previous convolutional stage. The output from convolutional layer 914 can then be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or a fully connected layer 908. For example, the first convolutional layer 904 in Figure 9A can output to a second convolutional layer 906, and the second convolutional layer can output to the first layer of the fully connected layer 908. Figure 10 shows an example recurrent neural network 1000. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state. RNNs can be built in various ways using a variety of functions. The use of RNNs typically revolves around using mathematical models to predict the future based on a previous sequence of inputs. For example, RNNs can be used to perform statistical language modeling to predict future words based on a previous sequence of words. The RNN 1000 shown can be described as having an input layer 1002 that receives the input vector, a hidden layer 1004 that implements the recursive function, a feedback mechanism 1005 that causes the "memory" of the previous state, and an output layer 1006 that outputs the result. RNN 1000 operates according to time steps. The state of the RNN at a given time step is influenced by the feedback mechanism 1005 according to the previous time step. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input of the current time step. The initial input (x1) in the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by the hidden layer 1004 using state information determined during the processing of the initial input (x1). The given state can be computed as st = f(Uxt + Wst-1), where U and W are parameter matrices. The function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or the rectified function f(x) = max(0,x). However, the specific mathematical function used for the hidden layer 1004 can vary depending on the specific implementation details of the RNN 1000. In addition to the basic CNN and RNN networks described above, variations can be made to these networks. One example RNN variant is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies that may be necessary for processing longer language sequences. A variant of CNN is a convolutional deep neural network, which has a similar structure to CNNs and is trained in a similar manner to deep neural networks. A deep neural network (DBN) is a generative neural network consisting of multiple layers with random (arbitrary) variables. DBNs can be trained layer by layer using greedy unsupervised learning. The learned weights of a DBN can then be used to pre-train a neural network by determining the optimal initial set of weights for that neural network. Figure 11 illustrates the training and deployment of deep neural networks. Once a given network has been constructed for a task, the neural network is trained using training dataset 1102. Various training frameworks 1104 have been developed to accelerate the hardware of the training process. For example, the machine learning framework 604 of Figure 6 can be configured as training framework 604. Training framework 604 can be linked to untrained neural network 1106 and cause the untrained neural network to be trained using the parallel processing resources described herein to produce trained neural network 1108. To begin the training process, the initial weights can be chosen randomly or pre-trained using a deep-belief network. The training cycle is then performed in either a supervised or unsupervised manner. Supervised learning is a learning method in which training is performed as an intermediary operation, such as when the training dataset 1102 includes inputs paired with desired outputs for inputs, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes these inputs and compares the resulting outputs with a set of expected or desired outputs. Errors are then fed back through the system. The training framework 1104 can adjust the weights controlling the untrained neural network 1106. The training framework 1104 provides tools to monitor how the untrained neural network 1106 appropriately converges toward a model suitable for producing correct answers based on the known input data. The training process is repeated as the network weights are adjusted to improve the outputs produced by the neural network. The training process can continue until the neural network reaches a statistically desirable accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations. Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training dataset 1102 will include input data without any associated output data. The untrained neural network 1106 can learn clusters within the unlabeled inputs and determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1108 capable of performing operations that can be used to reduce the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, allowing the identification of data points in the input dataset that deviate from the normal pattern of the data. Variations in supervised and unsupervised training can also be utilized. Semi-supervised learning is a technique where the training data set 1102 includes a mixture of labeled and unlabeled data with the same distribution. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning causes the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge taught within the network during the initial training period. Whether supervised or unsupervised, training procedures, especially for deep neural networks, can be too computationally intensive for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to accelerate the training process. Figure 12 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of neural networks. Each distributed computing node may include one or more host processors and one or more general-purpose processing nodes, such as the highly parallel general-purpose graphics processing unit 700 in Figure 7. As shown, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204. In model parallelism 1202, different computing nodes in a distributed system can perform training computations on different parts of a single network. For example, different layers of a neural network can be trained by different processing nodes in a distributed system. Advantages of model parallelism include the ability to scale to particularly large models. Separating the computations associated with different layers of a neural network enables the training of very large neural networks (where the weights of all layers would not fit into the memory of a single computing node). In some instances, model parallelism can be particularly useful for performing unsupervised training of large neural networks. In data parallelism 1204, different nodes in a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different methods of data parallelism are possible, data parallelism training requires a technique to combine the results and synchronize the model parameters between nodes. Exemplary methods of combining data include parametric averaging and update-based data parallelism. Parametric averaging trains nodes on a subset of the training data and sets global parameters (e.g., weights, biases) as the average of the parameters from each node. Parametric averaging uses a central parameter server that stores the parameter data. Update-based data parallelism is similar to parametric averaging, except that updates to the model are transferred instead of parameters being transferred from nodes to a parameter server. Furthermore, update-based data parallelism can be performed in a distributed manner, where the updates are compressed and transferred between nodes. The combined model and data parallelism 1206 can be implemented in, for example, a distributed system where each computing node includes multiple GPUs. Each node can have a full instance of the model, where separate GPUs within each node are used to train different parts of the model. Distributed training carries an increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described in this paper can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerating remote data synchronization. Exemplary Machine Learning Applications Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual abilities (such as recognizing faces) to generating new kinds of visual abilities. For example, computer vision applications can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processors accelerate machine learning systems, enabling computer vision applications to use significantly larger training datasets than previous approaches, and causing inference systems to be deployed using low-power parallel processors. Parallel processors accelerate machine learning for autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described in this paper enable rapid training of increasingly complex neural networks used in autonomous driving solutions and facilitate the deployment of low-power inference processors suitable for integration into mobile platforms within autonomous vehicles. Parallel processors have accelerated deep neural networks, enabling machine learning schemes for Automatic Speech Recognition (ASR). ASR comprises functions that generate the most probable speech sequence given a sequence of sound waves. The accelerated machine learning using deep neural networks has led to the replacement of previously used Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) for ASR. Parallel processors can accelerate machine learning and also be used to speed up natural language processing. Automatic learning programs can utilize statistical inference algorithms to generate models that are resistant to errors or unfamiliar input. Exemplary natural language processor applications include automatic machine translation between human languages. Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate single-node multi-GPU training and multi-node multi-GPU training. Examples of parallel processors suitable for training include the highly parallel general-purpose graphics processing unit 700 in Figure 7 and the multi-GPU computing system 800 in Figure 8. Conversely, deployed machine learning platforms typically include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles. Figure 13 illustrates a paradigmatic inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model. The SOC 1300 may integrate processing components including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 may additionally include on-chip memory 1305, which enables a shared pool of on-chip data accessible by the various processing components. The processing components can be optimized for low-power operation, enabling deployment on various machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1300 can be used as part of the main control system of an autonomous vehicle. When the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction. During operation, the media processor 1302 and the vision processor 1304 can work together to accelerate computer vision operations. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare them for processing using a trained image recognition model. For example, the vision processor 1304 can accelerate the convolution operations of a CNN used to perform image recognition on high-resolution video data, while the back-end model computation is performed by the GPGPU 1306. The multi-core processor 1308 may include control logic to assist in the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also function as an application processor to execute software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executed on the multi-core processor 1308. This software may directly send computational workloads to the GPGPU 1306, or the computational workloads may be sent to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306. The GPGPU 1306 may include compute clusters, such as low-power configurations of compute clusters 706A-706H within the highly parallel general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 can support instructions explicitly optimized for performing inference computations on trained neural networks. For example, the GPGPU 1306 can support instructions for performing low-precision computations such as 8-bit and 4-bit integer vector operations. Using a hybrid reasoning approach with low and high accuracy GPGPU-accelerated computation results in the offloading of parallel portions of the application to the GPGPU, while the remainder of the code executes on the main processor (e.g., CPU). As described herein, a GPGPU contains compute units capable of performing integer and floating-point operations. Typically, these operations are dedicated to a compute unit, which is allocated to perform integer operations that would power-dam or otherwise disable the compute elements responsible for floating-point operations. Conversely, it is also possible for a compute unit to disable the integer component while performing floating-point operations. Such a configuration reduces the power consumption of each compute unit. Alternatively, some compute units can be configured to selectively perform computations in one of multiple precisions. For example, a compute unit can be configured to perform FP32 operations or dual FP16 operations. A compute unit configured to perform 32-bit integer operations can perform four simultaneous 8-bit integer operations. Selective multi-precision or multi-data-type compute units can make compute units powerful yet power-efficient, as various operations can be performed by a single compute unit while idle logic units within each compute unit are disabled to reduce power consumption. However, it is also possible to save power in the computing unit by utilizing other idle logic units within the computing unit for computation. In the embodiments described herein, variable precision and / or variable data type logic components within the computing unit can be operated simultaneously, allowing computing units not used to service the initial computation to handle one or more additional computations. For example, in one embodiment, a computing unit with floating-point and integer logic units can handle integer and floating-point operations simultaneously. In one embodiment, a computing unit configured to selectively perform 32-bit operations or dual 16-bit operations can be configured to perform 32-bit operations and dual 16-bit operations or 32-bit operations and multiple independent 16-bit operations. In one embodiment, such computation is caused by allowing multiple instructions of different types to be issued to a single computing unit. In one embodiment, mixed data type instructions are enabled to allow single-instruction multithreaded operations to accept mixed data type and / or mixed precision operands. Figure 14 is a block diagram of a multiprocessor unit 1400 according to one embodiment. The multiprocessor unit 1400 may be a variant of the graphical multiprocessor 234 of Figure 2D. The multiprocessor unit 1400 includes a fetch and decode unit 1402, a branch unit 1404, a register file 1406, a thread manager 1408, a Single Instruction Multiple Threads (SIMT unit 1410), and a voltage and frequency manager 1420. The fetch and decode unit 1402 can fetch instructions for execution by the multiprocessor unit 1400. The branch unit 1404 can calculate instruction parameter adjustments based on executed jump instructions. The register file 1406 can store general-purpose and architectural registers used by the SIMT unit 1410. The thread manager 1408 can allocate and reallocate threads among the computational units of the SIMT unit 1410. In one embodiment, the SIMT unit 1410 is configured to execute a single instruction as multiple threads, wherein each thread of the instruction is executed by an independent computational unit. In one embodiment, each of computing units 1411 to 1418 includes an integer ALU (e.g., ALUs 1411A-1418A) and a floating-point unit (e.g., FPUs 1411B-1418B). The voltage and frequency of each computing unit 1411-1418 within the SIMT unit 1410 can be dynamically managed by a voltage and frequency manager 1420, which can increase or decrease the voltage and clock frequency supplied to each computing unit when components of the computing unit are enabled and disabled. In some previously implemented configurations, each compute unit can execute a single thread of integer instructions or floating-point instructions. If any of the ALUs 1411A-1418A are responsible for executing the thread of integer instructions, then the respective FPUs 1411B-FPU 1418B cannot be used to execute the thread of floating-point instructions and may be power-damped during the operation of the corresponding ALUs 1411A-ALU 1418A. For example, when ALU 1411A can execute the thread of integer instructions, while FPU 1413B executes the thread of floating-point instructions, then FPU 1411B is power-damped when ALU 1411A is active. The embodiments described herein overcome these limitations by, for example, causing ALU 1411A to execute the thread of one instruction while ALU 1411B executes the thread of a different instruction. In addition, one embodiment provides support for mixed precision or mixed data type operands, enabling a single instruction to simultaneously execute instructions with floating-point and integer operands and / or operands with different precisions. The embodiments described herein can increase the computational throughput of a cluster of computing units by making all logical units within each computing unit available to perform computations. In such embodiments, logical units within a computing unit, designed to selectively perform computations at one of multiple precisions or multiple data types, can be configured to perform multiple simultaneous operations for each precision or data type supported by the computing unit. For a given computing unit 1411-1418, ALUs 1411A-1418A can perform integer operations, while FPUs 1411B-1418B perform floating-point operations. These operations can be performed against a single instruction or multiple instructions. In one embodiment, a new type of mixed-precision instruction is enabled, where one or more operands are of one data type or precision, and one or more different operands are of different data types or precisions. For example, an instruction can accept two or more multi-element operands containing floating-point and integer data types, and can execute a single instruction based on each data type or each precision. Figure 15 shows a mixed-precision processing system 1500 according to one embodiment. The mixed-precision processing system 1500 includes a computing unit 1509 comprising an FPU 1508A and an ALU 1508B. In the embodiment described herein, the computing unit 1509 can execute mixed-precision / mixed data type instructions. For example, and in one embodiment, the instructions can be processed to perform a single operation or multiple fused operations on multiple operands comprising multiple data elements. In one embodiment, the data elements within the operands can be mixed-precision or mixed data type elements. For example, a first input register 1501 can store a first operand comprising a floating-point element 1502A and multiple integer elements comprising integer elements 1504A and 1506A. A second input register 1503 can store a second operand comprising a floating-point element 1502B and multiple integer elements comprising integer elements 1504B and 1506B. The third input register 1505 can store a third arithmetic element containing a floating-point element 1502C and multiple integer elements including an integer element 1504C and an integer element 1506C. The components can be used as input to perform a single operation defined by a single operation code (e.g., operation code 1510). For example, operation code 1510 can specify a multiply-add operation fused from multiple components, where the FPU 1508A multiplies and adds floating-point components. The FPU 1508A can multiply floating-point components (FP components 1502A and FP components 1502B) and add the product of the multiplications to a third floating-point component (FP component 1502C). In parallel, the ALU 1508B can perform a multiply-add operation fused from two integers, where a first set of integer components (INT components 1504A and INT components 1504B) and a second set of integer components (INT components 1506A and INT components 1506B) are multiplied, and the product of each multiplication is added to a third integer component (INT components 1504C and INT components 1506C). Independent state flags 1512A-1512C can be set based on each operation. Independent state flags 1512A-1512C can be configured to indicate state outputs known in the art, including but not limited to carry, negative, zero, and overflow. In one embodiment, independent state flags 1512A-1512C are output as a state vector, where each element of the state vector is associated with each operation. Multiple results can be generated (e.g., result 1522A, result 1522B, result 1522C), where the first result 1522A is a floating-point result, while the second and third results 1522B-1522C are integer results. In one embodiment, the precision of the elements can also be mixed. For example, and in one embodiment, input registers 1501, 1503, and 1505 are 32-bit registers. FP elements 1502A-1502C can be 16-bit floating-point elements (e.g., FP16), while INT elements 1504A-1504C and INT elements 1506A-1506C can each be 8-bit integer elements (e.g., INT8). Output register 1520 can also be a 32-bit register, where result 1522A is 16-bit, while results 1522B and 1522C are each 8-bit. In various embodiments, different register sizes can be used, including 64-bit, 128-bit, 256-bit, and 512-bit registers, such that the range of input elements is between 8 bits and 64 bits. The arithmetic logic 1700 of the mixed-precision processing system 1500 is shown in Figure 17 and can be implemented via the multiprocessor unit 1400 of Figure 14. Referring also to Figure 14, the fetch and decode unit 1402 of the multiprocessor unit 1400 can fetch and decode a single instruction containing multiple operands, which reference multiple data elements with different precisions, as shown in block 1702 of Figure 17. As shown in block 1704, the thread manager 1408 can dispatch multiple threads of a single instruction to be executed within a computing unit of the GPGPU (e.g., computing unit 1509 in Figure 15). As shown in block 1706, in parallel, the computing unit can execute instruction operations on a first set of operands with a first precision via a first logic unit within the computing unit, and, as shown in block 1708, execute instruction operations on a second set of operands with a second precision via a second logic unit within the computing unit. As shown in block 1710, the logic unit can output multiple results of the operation. Operands of different precisions can be of the same data type (e.g., floating-point, fixed-point, integer) with different precisions (e.g., 8-bit, 16-bit, 32-bit, etc.), operands of the same precision but different data types (e.g., FP-16 and INT-16), or different data types with different precisions (e.g., dual INT-8 and FP16). This instruction can be particularly useful when performing processing operations on neural networks with mixed precisions or mixed data types, where the input data of the layer has a different precision or data type than the weights applied to the input data. Although the integer ALU 150B is consistently described in Figure 15, the embodiments are not particularly limited to using arithmetic logic units that contain only integers. In one embodiment, the integer ALU described herein may be a floating-point unit configured to perform integer operations. Figure 16 illustrates an additional mixed-precision processing system 1600 according to one embodiment. The shown mixed-precision processing system 1600 is configured such that floating-point workloads (e.g., FP workload 1602) and integer workloads (e.g., INT workload 1604) are executed in parallel across multiple computing units (e.g., computing units 1607 and 1609). Both computing units 1607 and 1609 include a set of floating-point units (FPU 1606A, FPU 1608A) and a set of integer arithmetic logic units (e.g., ALU 1606B, ALU 1608B). In previous implementations, for example, threads of FP workload 1602 would execute, for example, on the FPU 1606A of computing unit 1607, while threads of INT workload 1604 would execute in parallel on the ALU 1608B of computing unit 1609. The embodiment described herein causes the FPUs and ALUs of the computing units to operate in parallel. Figure 18 shows arithmetic logic 1800 for a mixed-precision processing system 1600. As shown in block 1802, in one embodiment, arithmetic logic 1800 can extract and decode integer instructions to be executed across multiple threads within the GPGPU. As shown in block 1804, logic 1800 can also extract and decode floating-point instructions to be executed across multiple threads within the GPGPU. At block 1805, arithmetic logic 1800 can cause parallel execution of integer and floating-point instructions, executing integer instructions via integer units of the first and second computation units, and, as shown in block 1806, executing floating-point instructions via floating-point units of the first and second computation units. At block 1807, logic 1800 can cause integer instructions to output integer results, and at block 1808, cause floating-point operations to output floating-point results. Dedicated inference systems for neural networks If the parallel processors or GPGPUs used to perform inference operations are specifically designed for computations performed during inference in neural networks, then performing inference operations can become more efficient in deploying machine learning systems. In one embodiment, dedicated inference logic can perform computations using compressed and / or encoded weight data in memory. Adaptive encoding can be enabled based on a profile generated for the neural network. This profile can be generated based on determining a set of commonly used weight values ​​or common patterns that appear within the weight values. Byte-based simplified encoding for common weight values ​​can be stored in memory, thereby reducing power consumption or allowing larger networks to be stored in memory. Figure 19 illustrates a machine learning system 1900 according to one embodiment. In one embodiment, the machine learning system 1900 is a dedicated inference system for neural networks that supports the encoding of weight data for the neural networks. The encoded weight data enables a scaled-down representation of weight information used in deployed neural networks. This scaled-down weight data can enable power-efficient inference or enable processing of larger neural networks for a given memory size. In one embodiment, the machine learning system 1900 begins with an untrained neural network 1902 that can be processed by a training system 1903. The training system 1903 can generate a trained neural network 1904. A weight data profiling system 1905 can be used to profile the weight data of the trained neural network 1904. The weight data profiling system 1905 can generate frequency-encoded weight data 1906 and an encoded profile 1910 for generating the frequency-encoded weight data 1906. The frequency-encoded weight data 1906 and the encoded profile 1910 can be stored in GPGPU memory 1908. The frequency-encoded weight data 1906 and the encoded profile 1910 stored in the GPGPU memory 1908 can be used to perform neural network layer computations on the GPGPU computing unit 1914. In one embodiment, the encoded profile 1910 can be read from the GPGPU memory 1908 and used to configure the GPGPU weight decoder 1912. The GPGPU weight decoder 1912 can decode the frequency-encoded weight data 1906 to provide decoded weight data 1913 to the GPGPU computing unit 1914. The input data 1911 of the neural network layer can also be read from the GPGPU memory 1908. The input data 1911 and the decoded weight data 1913 can be processed by the GPGPU computing unit 1914 to generate GPGPU computation results 1915. In one embodiment, the GPGPU computing unit 1914 may be configured to include a GPGPU weight decoder 1912, such that the encoded profile 1910 and frequency encoded weight data 1906 can be directly provided to the computing unit 1914 along with the input data 1911 to generate the GPGPU computing result 1915. The logic operation 2000 of the machine learning system 1900 is shown by the flowchart in Figure 20. In one embodiment, as shown in block 2002, the logic operation 2000 may configure the GPGPU to profile the weights of the trained neural network to generate a weight profile of the neural network's weight data. As shown in block 2004, the logic operation 2000 may then cause the GPGPU to use the weight profile to encode the weights of the neural network. As shown in block 2006, the logic operation 2000 may then cause the GPGPU to store the encoded weights and the weight profile into GPGPU memory. As shown in block 2008, when performing neural network computation, the logic operation 2000 may cause the GPGPU to read the encoded weights from the GPGPU memory during neural network processing. As shown in block 2010, in one embodiment, the logic operation 2000 may cause the GPGPU to decode the encoded weights based on the weight profile before the GPGPU performs neural network computation at block 2012. As shown in Figure 19, the encoded weights can be decoded using the GPGPU weight decoder 1912. When the GPGPU is configured to receive the encoded weights directly from the GPGPU memory, the decoding process can be skipped. In this embodiment, logic operation 2000 can be configured so that the GPGPU performs neural network computations at block 2012 without pre-decoding the weight data. Additional Exemplary Graphics Processing Systems The details of the above embodiments can be incorporated into the graphics processing system and apparatus described below. The graphics processing system and apparatus of Figures 21-34 illustrate alternative systems and graphics processing hardware that can implement any and all of the above-described technologies. Additional Exemplary Graphics Processing System Overview Figure 21 is a block diagram of a processing system 2100 according to an embodiment. In various embodiments, the system 2100 includes one or more processors 2102 and one or more graphics processors 2108, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2102 or processor cores 2107. In one embodiment, the system 2100 is a processing platform integrated within a system-on-a-chip (SoC) for use in mobile, handheld, or embedded devices. Embodiments of system 2100 may include or be incorporated into server-based gaming platforms, game consoles, including game and media consoles, mobile game consoles, handheld game consoles, or online game consoles. In some embodiments, system 2100 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Data processing system 2100 may also include, be coupled to, or be integrated into wearable devices, such as smartwatch wearable devices, smart glasses devices, augmented reality devices, or virtual reality devices. In some embodiments, data processing system 2100 is a television or set-top box device having one or more processors 2102 and a graphical interface generated by one or more graphics processors 2108. In some embodiments, one or more processors 2102 each include one or more processor cores 2107 for processing instructions that, when executed, perform operations on the system and user software. In some embodiments, each of the one or more processor cores 2107 is configured to process a specific instruction set 2109. In some embodiments, the instruction set 2109 may assist in Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). Multiple processor cores 2107 may each process different instruction sets 2109, which may include instructions to assist in the emulation of other instruction sets. Processor cores 2107 may also include other processing devices, such as digital signal processors (DSPs). In some embodiments, processor 2102 includes cache memory 2104. Depending on the architecture, processor 2102 may have a single internal cache or multiple levels of internal cache. In some embodiments, cache memory is shared among various components of processor 2102. In some embodiments, processor 2102 also uses external caches (e.g., Level 3 (L3) cache or Last-in-Time (LLC) cache) (not shown), which can be shared among processor cores 2107 using known cache coherency techniques. A register file 2106 is additionally included in processor 2102 and may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while others may be specifically designed for processor 2102. In some embodiments, processor 2102 is coupled to processor bus 2110 for transmitting communication signals (such as address, data, or control signals) between processor 2102 and other components in system 2100. In one embodiment, system 2100 uses an exemplary "hub" system architecture including memory controller hub 2116 and input / output (I / O) controller hub 2130. Memory controller hub 2116 facilitates communication between memory devices and other components of system 2100, while I / O controller hub (ICH) 2130 provides connectivity to I / O devices via local I / O buses. In one embodiment, the logic of memory controller hub 2116 is integrated within the processor. Memory device 2120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device having suitable performance for functioning as program memory. In one embodiment, memory device 2120 may operate as system memory for system 2100 to store data 2122 and instructions 2121 for use when one or more processors 2102 execute an application or program. Memory controller hub 2116 is also coupled to an optional external graphics processor 2112, which may communicate with one or more graphics processors 2108 in processor 2102 to perform graphics and media operations. In some embodiments, ICH 2130 enables peripheral devices to be connected to memory device 2120 and processor 2102 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 2146, a firmware interface 2128, a wireless transceiver 2126 (e.g., Wi-Fi, Bluetooth), a data storage device 2124 (e.g., hard drive, flash memory, etc.), and a traditional I / O controller 2140 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2142 are connected to input devices, such as a keyboard and mouse combination 2144. A network controller 2134 may also be coupled to ICH 2130. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 2110. It will be understood that the system 2100 shown is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, the I / O controller hub 2130 may be integrated into one or more processors 2102, or the memory controller hub 2116 and the I / O controller hub 2130 may be integrated into individual external graphics processors, such as external graphics processor 2112. Figure 22 is a block diagram of an embodiment of processor 2200, which has one or more processor cores 2202A-2202N, an integrated memory controller 2214, and an integrated graphics processor 2208. Those elements of Figure 22 having the same reference numerals (or names) as those in any other illustration herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 2200 may include up to (and include) additional cores 2202N represented by dashed boxes. Each of processor cores 2202A-2202N includes one or more internal cache units 2204A-2204N. In some embodiments, each processor core may also access one or more shared cache units 2206. Internal cache units 2204A-2204N and shared cache unit 2206 represent cache memory hierarchies within processor 2200. A cache memory hierarchy within each processor core may include at least one order of instruction and data cache, and one or more orders of shared intermediate-order cache, such as order 2 (L2), order 3 (L3), order 4 (L4), or other orders of cache, wherein the highest-order cache preceding external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherence between the various cache units 2206 and 2204A-2204N. In some embodiments, the processor 2200 may further include one or more bus controller units 2216 and a system agent core 2210. The one or more bus controller units 2216 manage a set of peripheral device buses, such as one or more peripheral device component interconnect buses (e.g., PCI, PCI Express). The system agent core 2210 provides management functions for each processor component. In some embodiments, the system agent core 2210 includes one or more integrated memory controllers 2214 for managing access to various external memory devices (not shown). In some embodiments, one or more processor cores 2202A-2202N include support for simultaneous multithreading. In this embodiment, system agent core 2210 includes components for coordinating and operating cores 2202A-2202N during multithreaded processing. System agent core 2210 may additionally include a power control unit (PCU) including logic and components for regulating the power states of processor cores 2202A-2202N and graphics processor 2208. In some embodiments, processor 2200 additionally includes a graphics processor 2208 for performing graphics processing operations. In some embodiments, graphics processor 2208 shares cache unit 2206 and system proxy core 2210, and is coupled to one or more integrated memory controllers 2214. In some embodiments, display controller 2211 is coupled to graphics processor 2208 to drive graphics processor outputs to one or more coupled displays. In some embodiments, display controller 2211 may be a separate module coupled to graphics processor via at least one interconnect, or may be integrated within graphics processor 2208 or system proxy core 2210. In some embodiments, the ring interconnect unit 2212 is used to couple internal components of the processor 2200. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art, may be used. In some embodiments, the graphics processor 2208 is coupled to the ring interconnect 2212 via I / O link 2213. Example I / O link 2213 represents at least one of a variety of I / O interconnects, including on-package I / O interconnects, which facilitate communication between various processor components and high-performance embedded memory modules 2218 (such as eDRAM modules). In some embodiments, each of the processor cores 2202A-2202N and the graphics processor 2208 uses the embedded memory module 2218 as a shared last-order cache. In some embodiments, processor cores 2202A-2202N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 2202A-2202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 2202A-2202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 2202A-2202N are heterogeneous in terms of microarchitecture, wherein one or more cores having relatively high power consumption are coupled to one or more power cores having lower power consumption. Furthermore, processor 2200 may be implemented on one or more chips, or as a SoC integrated circuit having, among other components, the components shown. Figure 23 is a block diagram of a graphics processing unit 2300, which may be a standalone graphics processing unit or a graphics processing unit integrated with a complex processing core. In some embodiments, the graphics processing unit communicates with registers on the graphics processing unit via a memory-mapped I / O interface and communicates with commands loaded into the processor memory. In some embodiments, the graphics processing unit 2300 includes a memory interface 2314 for accessing memory. The memory interface 2314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory. In some embodiments, the graphics processor 2300 further includes a display controller 2302 for driving display output data to the display device 2320. The display controller 2302 includes hardware for displaying and assembling one or more overlapping planes of multi-layer video or user interface elements. In some embodiments, the graphics processor 2300 includes a video encoding / decoding engine 2306 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including but not limited to the Motion Picture Experts Group (MPEG) format, such as MPEG-2; the Advanced Video Coding (AVC) format, such as H.264 / MPEG-4 AVC; and the Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1 and the Joint Group of Picture Experts (JPEG) formats, such as JPEG and Motion Picture JPEG (MJPEG). In some embodiments, the graphics processor 2300 includes a block image transfer (BLIT) engine 2304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2310. In some embodiments, the GPE 2310 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations. In some embodiments, GPE 310 includes a 3D pipeline 2312 for performing 3D operations such as rendering 3D images and scenes using processing functions acting on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2312 includes programmable and fixed-function elements that perform various tasks and / or production threads within those elements to the 3D / media subsystem 2315. While the 3D pipeline 2312 can be used to perform media operations, embodiments of GPE 2310 also include a media pipeline 2316, which is explicitly used to perform media operations such as video post-processing and image enhancement. In some embodiments, the media pipeline 2316 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, to replace or supersede the video encoding / decoding engine 2306. In some embodiments, the media pipeline 2316 additionally includes a thread production unit for producing threads for execution on the 3D / media subsystem 2315. The produced threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 2315. In some embodiments, the 3D / media subsystem 2315 includes logic for executing threads produced by the 3D pipeline 2312 and the media pipeline 2316. In one embodiment, the pipelines transmit thread execution requests to the 3D / media subsystem 2315, which includes thread scheduling logic for arbitrating and scheduling requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data. Additional Paradigm Graphics Processing Engine Figure 24 is a block diagram of a graphics processing engine 2410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2410 is a version of the GPE 2310 shown in Figure 23. Elements of Figure 24 having the same reference numerals (or names) as any other elements illustrated herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. For example, the 3D pipeline 2312 and media pipeline 2316 of Figure 23 are shown. The media pipeline 2316 is optional in some embodiments of the GPE 2410 and may not be explicitly included within the GPE 2410. For example, and in at least one embodiment, individual media and / or image processors are coupled to the GPE 2410. In some embodiments, the GPE 2410 is coupled to (or includes) a command streamer 2403 that provides command streaming to the 3D pipeline 2312 and / or the media pipeline 2316. In some embodiments, the command streamer 2403 is coupled to memory, which may be one or more of system memory, internal cache memory, and shared cache memory. In some embodiments, the command streamer 2403 receives commands from the memory and transmits those commands to the 3D pipeline 2312 and / or the media pipeline 2316. These commands are directly retrieved from a ring buffer that stores commands from the 3D pipeline 2312 and the media pipeline 2316. In one embodiment, the ring buffer may additionally include a batch command buffer that stores batches of multiple commands. Commands in the 3D pipeline 2312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 2312 and / or image data and memory objects for the media pipeline 2316. The 3D pipeline 2312 and the media pipeline 2316 process these commands and data by performing operations through logic within their respective pipelines or by scheduling one or more threads to the graphics core array 2414. In various embodiments, the 3D pipeline 2312 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing these instructions and scheduling threads to the graphics core array 2414. The graphics core array 2414 provides a unified block of execution resources. The multi-purpose execution logic (e.g., execution units) within the graphics core array 2414 includes multiple concurrent threads that support various 3D API shader languages ​​and can execute multiple shaders. In some embodiments, the graphics core array 2414 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution unit additionally includes general-purpose logic that is programmable to perform parallel general-purpose computing operations in addition to graphics processing operations. The general-purpose logic may perform processing operations in parallel or in conjunction with the general-purpose logic within processor core 1607 of FIG. 16 or cores 2202A-2202N of FIG. 22. Output data generated by threads executed on the graphics core array 2414 can be output to memory in a unified return buffer (URB) 2418. URB 2418 can store data for multiple threads. In some embodiments, URB 2418 can be used to transfer data between threads executed on the graphics core array 2414. In some embodiments, URB 2418 can additionally be used for synchronization between threads on the graphics core array and fixed-function logic within shared-function logic 2420. In some embodiments, the graphics core array 2414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units depending on the target power and performance level of the GPE 2410. In one embodiment, the execution resources are dynamically scalable such that the execution resources can be enabled or disabled as needed. The graphics core array 2414 is coupled to common function logic 2420, which includes multiple resources shared among the graphics cores in the graphics core array. The common functions within the common function logic 2420 are hardware logic units that provide specialized supplementary functions to the graphics core array 2414. In various embodiments, the common function logic 2420 includes, but is not limited to, sampler 2421, math 2422, and inter-thread communication (ITC) 2423 logic. Furthermore, some embodiments implement one or more caches 2425 within the common function logic 2420. Common functions are implemented where the requirements for a given specialized function are insufficient to be included within the graphics core array 2414. Instead, a single instance of this specialized function is implemented as a separate unit within the common function logic 2420 and shared among the execution resources within the graphics core array 2414. The exact set of functions shared among and included within the graphics core array 2414 varies between embodiments. Figure 25 is a block diagram of another embodiment of the graphics processor 2500. Elements of Figure 25 having the same reference numerals (or names) as those in any other illustration herein may be operated or functioned in any manner similar to, but not limited to, those described elsewhere herein. In some embodiments, the graphics processor 2500 includes a ring interconnect 2502, a pipeline front end 2504, a media engine 2537, and graphics cores 2580A-2580N. In some embodiments, the ring interconnect 2502 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system. In some embodiments, the graphics processor 2500 receives batches of commands via a ring interconnect 2502. Incoming commands are interpreted by a command streamer 2503 in the pipeline front-end 2504. In some embodiments, the graphics processor 2500 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2580A-2580N. For 3D geometry processing commands, the command streamer 2503 supplies commands to the geometry pipeline 2536. For at least some media processing commands, the command streamer 2503 supplies these commands to a video front-end 2534 coupled to a media engine 2537. In some embodiments, the media engine 2537 includes a video quality engine (VQE) 2530 for video and post-processing and a multi-format encoding / decoding (MFX) engine 2533 for providing hardware acceleration for media data encoding and decoding. In some embodiments, the geometry pipeline 2536 and the media engine 2537 each generate threads for thread execution resources provided by at least one graphics core 2580A. In some embodiments, the graphics processor 2500 includes scalable thread execution resource feature modular cores 2580A-2580N (sometimes referred to as core shards), each having a plurality of sub-cores 2550A-550N, 2560A-2560N (sometimes referred to as core shards). In some embodiments, the graphics processor 2500 may have any number of graphics cores 2580A to 2580N. In some embodiments, the graphics processor 2500 includes a graphics core 2580A having at least a first sub-core 2550A and a second sub-core 2560A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2550A). In some embodiments, the graphics processor 2500 includes a plurality of graphics cores 2580A-2580N, each including a set of first sub-cores 2550A-2550N and a set of second sub-cores 2560A-2560N. Each sub-core in the first group of sub-cores 2550A-2550N includes at least a first set of execution units 2552A-2552N and media / texture samplers 2554A-2554N. Each sub-core in the second group of sub-cores 2560A-2560N includes at least a second set of execution units 2562A-2562N and samplers 2564A-2564N. In some embodiments, each sub-core 2550A-2550N and 2560A-2560N shares a set of shared resources 2570A-2570N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor. Additional example execution units Figure 26 shows the thread execution logic 2600 of an array of processing elements utilized in some embodiments including GPE. Elements of Figure 26 having the same reference numerals (or names) as any other elements illustrated herein may be operated or functioned in any manner similar to, but not limited to, those described elsewhere herein. In some embodiments, the thread execution logic 2600 includes a shader processor 2602, a thread scheduler 2604, an instruction cache 2606, a scalable execution unit array including a plurality of execution units 2608A-2608N, a sampler 2610, a data cache 2612, and a data port 2614. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 2608A, 2608B, 2608C, 2608D, through 2608N-1 and 2608N) according to the computational needs of the workload. In one embodiment, the included components are interconnected via an interconnect configuration linking each of the components. In some embodiments, the thread execution logic 2600 includes connections to one or more memories, such as system memory or cache memory, via one or more instruction caches 2606, data ports 2614, samplers 2610, and execution units 2608A-2608N. In some embodiments, each execution unit (e.g., 2608A) is an independent programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2608A-2608N is scalable to include any number of individual execution units. In some embodiments, execution units 2608A-2608N are primarily used to execute shader programs. Shader processor 2602 can handle various shader programs and schedule threads associated with these shader programs via thread scheduler 2604. In one embodiment, the thread scheduler includes logic for arbitrating thread initiation requests from the graphics and media pipeline and instantiating the requested threads onto one or more execution units 2608A-2608N. For example, the geometry pipeline (e.g., 2536 of FIG. 25) can schedule vertex, tessellation, or geometry shaders to thread execution logic 2600 (FIG. 26) for processing. In some embodiments, thread scheduler 2604 can also handle runtime thread production requests from running shader programs. In some embodiments, execution units 2608A-2608N support instruction sets including native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal conversion. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the execution units 2608A-2608N is capable of multiple-threaded single-instruction multiple-data (SIMD) execution, which enables an efficient execution environment when facing high-latency memory access. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multiplexed per clock cycle to the pipeline, enabling integer, single- and double-precision floating-point operations, SIMD branching capabilities, logical operations, overriding operations, and various other operations. When waiting for data from memory or one of the shared functions, the dependency logic within execution units 2608A-2608N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources can be used to process other threads. For example, during the latency associated with vertex shader operations, the execution unit can execute programs for pixel shaders, fragment shaders, or other types of shaders, including operations for different vertex shaders. Each execution unit in the execution units 2608A-2608N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels for that instruction. An execution channel is a logic unit for executing data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2608A-2608N support integer and floating-point data types. The execution unit instruction set includes SIMD instructions. Individual data elements can be stored as compressed data types in temporary registers, and the execution unit processes each element according to its data size. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a temporary register, and the execution unit operates on that vector as four individual 64-bit compressed data elements (quad-word (QW) size elements), eight individual 32-bit compressed data elements (double-word (DW) size elements), sixteen individual 16-bit compressed data elements (word (W) size elements), or thirty-two individual 8-bit compressed data elements (byte (B) size elements). However, different vector widths and temporary register sizes are possible. One or more internal instruction caches (e.g., 2606) are included in the thread execution logic 2600 to cache the thread instructions of the execution unit. In some embodiments, one or more data caches (e.g., 2612) are included to cache thread data during thread execution. In some embodiments, a sampler 2610 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2610 includes specialized texture or media sampling functions to process the texture or media data during the sampling process before providing the sampled data to the execution unit. During execution, the graphics and media pipeline transmits thread initiation requests to thread execution logic 2600 via thread production and scheduling logic. Once the group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2602 is invoked to further compute output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of individual vertex attributes to be interpolated across the rasterized object. In some embodiments, the pixel processor logic within shader processor 2602 then executes a pixel or fragment shader program provided by an application programming interface (API). To execute the shader program, shader processor 2602 schedules threads to execution units (e.g., 2608A) via thread scheduler 2604. In some embodiments, pixel shader 2602 uses texture sampling logic in sampler 2610 to access texture data in a texture map stored in memory. Arithmetic operations on texture data and input geometry data calculate pixel color data for each geometric segment or discard one or more pixels without further processing. In some embodiments, data port 2614 provides a memory access mechanism to thread execution logic 2600 for outputting processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2614 includes or is coupled to one or more cache memories (e.g., data cache 2612) for caching data via the data port for memory access. Figure 27 is a block diagram illustrating a graphics processor instruction format 2700 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having multiple instruction formats. Solid boxes show components typically included in the execution unit instructions, while dashed lines represent components that are selectively included or only included in subsets of those instructions. In some embodiments, the instruction format 2700 shown is a macro instruction, which, once processed, is an instruction supplied to the execution unit, rather than a micro-operation derived from instruction decoding. In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 2710. A 64-bit compressed instruction format 2730 may be used for some instructions depending on the selected instructions, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are limited to 64-bit format 2730. Native instructions available for 64-bit format 2730 vary depending on the embodiment. In some embodiments, the instruction is partially compressed using a set of index values ​​in index field 2713. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compressed table output to reconstruct the native instructions of 128-bit instruction format 2710. For each format, instruction code 2712 defines the operation that the execution unit should perform. The execution unit executes instructions in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or image element. By default, the execution unit executes instructions across all data channels of the operand. In some embodiments, instruction control field 2714 enables control over certain execution options, such as channel selection (e.g., assertion) and data channel order (e.g., mixing). For instructions in 128-bit instruction format 2710, execution size field 2716 limits the number of data channels that will be executed in parallel. In some embodiments, execution size field 2716 may not be used in 64-bit compressed instruction format 2730. Some execution unit instructions have up to three operands, including two source operands (src0 2720, src1 2722) and a destination 2718. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2724), where the instruction operand 2712 determines the number of source operands. The final source operand of an instruction may be an immediate (e.g., hard-coded) value passed using the instruction. In some embodiments, the 128-bit instruction format 2710 includes an access / address mode field 2726, which indicates, for example, whether a direct register addressing mode or an indirect register addressing mode is used. When the direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction. In some embodiments, the 128-bit instruction format 2710 includes an access / address mode field 2726, which specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment of the instruction. Some embodiments support access modes, including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction can use byte-aligned addressing for both source and destination operands, while in a second mode, the instruction can use 16-byte aligned addressing for both source and destination operands. In one embodiment, the address mode portion of the access / address mode field 2726 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, bits in the instruction directly provide the register addresses of one or more operands. When indirect register addressing mode is used, the register addresses of one or more operands can be calculated based on the address register values ​​in the instruction and the address immediate field. In some embodiments, instructions are grouped according to the 2712-bit fields of the operand code to simplify operand code decoding 2740. For 8-bit operand codes, bits 4, 5, and 6 allow the execution unit to determine the type of the operand code. The precise operand code groups shown are merely examples. In some embodiments, the move and logic operand code group 2742 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2742 shares five most significant bits (MSBs), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. The flow control instruction group 2744 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2746 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction group 2748 includes component-based arithmetic instructions (e.g., addition, multiplication (mu1)) in the form of 0100xxxxb (e.g., 0x40). Parallel math group 2748 performs arithmetic operations in parallel across data channels. Vector math group 2750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic such as calculating the inner product of vector operands. Additional example graphics pipeline Figure 28 is a block diagram of another embodiment of the graphics processor 2800. Elements of Figure 28 having the same reference numerals (or names) as those in any other illustration herein may be operated or functioned in any manner similar to, but not limited to, those described elsewhere herein. In some embodiments, the graphics processor 2800 includes a graphics pipeline 2820, a media pipeline 2830, a display engine 2840, thread execution logic 2850, and a rendering output pipeline 2870. In some embodiments, the graphics processor 2800 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by registers written to one or more control registers (not shown), or by commands sent to the graphics processor 2800 (via ring interconnect 2802). In some embodiments, ring interconnect 2802 couples the graphics processor 2800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 2802 are interpreted by command streamer 2803, which supplies instructions to individual components of the graphics pipeline 2820 or media pipeline 2830. In some embodiments, command streamer 2803 directs the operation of vertex extractor 2805, which reads vertex data from memory and executes vertex processing commands provided by command streamer 2803. In some embodiments, vertex extractor 2805 provides vertex data to vertex shader 2807, which performs coordinate space transformation and illumination operations for each vertex. In some embodiments, vertex extractor 2805 and vertex shader 2807 execute vertex processing instructions, and the threads are scheduled to execution units 2852A-2852B by thread scheduler 2831. In some embodiments, execution units 2852A-2852B are arrays of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 2852A-2852B have an attached L1 cache 2851, which is dedicated to each array or shared among multiple arrays. The cache can be configured as a data cache, an instruction cache, or a single cache, which is divided into segments containing data and instructions. In some embodiments, the graphics pipeline 2820 includes tessellation components for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operation. A programmable realm shader 817 provides back-end evaluation of the tessellation output. A tessell 2813 operates in the direction of the hull shader 2811 and contains special-purpose logic for generating a set of detailed geometric objects based on a coarse geometric model provided as input to the graphics pipeline 2820. In some embodiments, if tessellation is not used, the tessellation components (e.g., hull shader 2811, tessell 2813, and realm shader 2817) may be omitted. In some embodiments, the complete geometry object may be processed by the geometry shader 2819 via one or more threads scheduled to execution units 2852A-2852B, or it may proceed directly to the chopper 2829. In some embodiments, the geometry shader operates on the entire geometry object, rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2819 receives input from the vertex shader 2807. In some embodiments, if tessellation is disabled, the geometry shader 2819 may be programmed by a geometry shader program to perform geometry tessellation. Before rasterization, the cutter 2829 processes vertex data. The cutter 2829 can be a fixed-function cutter or a programmable cutter with both cutter and geometry shader functionality. In some embodiments, the rasterizer and depth testing component 2873 in the rendering output pipeline 2870 schedules the pixel shader to convert the geometry into its pixel-by-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2850. In some embodiments, the application may omit the rasterizer and depth testing component 2873 and access the unrasterized vertex data via the streaming output unit 2823. The graphics processor 2800 has interconnect buses, interconnect structures, or other interconnect mechanisms that allow data and messages to be transferred between the processor's main components. In some embodiments, execution units 2852A-2852B and associated caches 2851, texture and media samplers 2854, and texture / sampler cache 2858 are interconnected via data port 2856 to perform memory access and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2854, caches 2851 and 2858, and execution units 2852A-2852B each have individual memory access paths. In some embodiments, the rendering output pipeline 2870 includes a rasterizer and a depth testing component 2873 that converts vertex-based objects into their corresponding pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangulation and linear rasterization. The associated rendering cache 2878 and depth cache 2879 are also available in some embodiments. The pixel manipulation component 2877 performs pixel-based operations on the data, although in some examples, pixel operations related to 2D operations (e.g., using blended bit-block image transfer) are performed by the 2D engine 2841 or replaced by the display controller 2843 at display time using an overlay display plane. In some embodiments, a shared L3 cache 2875 can be used across all graphics components, allowing data sharing without using main system memory. In some embodiments, the graphics processor media pipeline 2830 includes a media engine 2837 and a video front-end 2834. In some embodiments, the video front-end 2834 receives pipeline commands from a command streamer 2803. In some embodiments, the media pipeline 2830 includes individual command streamers. In some embodiments, the video front-end 2834 processes the media commands before transmitting them to the media engine 2837. In some embodiments, the media engine 2837 includes a thread production function for producing threads for scheduling to thread execution logic 2850 via a thread scheduler 2831. In some embodiments, the graphics processor 2800 includes a display engine 2840. In some embodiments, the display engine 2840 is located external to the processor 2800 and coupled to the graphics processor via a ring interconnect 2802 (or some other interconnect bus or organization). In some embodiments, the display engine 2840 includes a 2D engine 2841 and a display controller 2843. In some embodiments, the display engine 2840 contains special-purpose logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2843 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop) or an external display device attached via a display device connector. In some embodiments, the graphics pipeline 2820 and media pipeline 2830 may be configured to perform operations based on multiple graphics and media programming interfaces, rather than being dedicated to any single application programming interface (API). In some embodiments, the graphics processor driver software translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), the Open Computing Language (OpenCL), and / or the Vulkan graphics and computing API, all from the Khronos Group. In some embodiments, support for the Direct3D library from Microsoft Corporation may also be provided. In some embodiments, a combination of these libraries may be supported. Support for the Open Source Computer Vision Library (OpenCV) may also be provided. Future APIs with compatible 3D pipelines will also be supported if mapping from the pipeline of future APIs to the graphics processor pipeline is executable. Graphics pipeline programming Figure 29A is a block diagram of a display graphics processor command format 2900 according to some embodiments. Figure 29B is a block diagram of a display graphics processor command sequence 2910 according to an embodiment. Solid boxes in Figure 29A show components typically included in a graphics command, while dashed lines represent components that are selective or only included in a subset of the graphics command. The example graphics processor command format 2900 of Figure 29A includes data fields for identifying the target client 2902 of the command, a command opcode (operation code) 2904, and related data 2906 for the command. Suboperation codes 2905 and command sizes 2908 are also included in some commands. In some embodiments, client 2902 refers to a client unit of a graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client fields of each command to adapt the further processing of the command and sends the command data to the appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the commands. Once the command is received by the client unit, the client unit reads the operation code 2904 and (if present) the sub-operation code 2905 to determine the operation to be performed. The client unit executes the command using the information in the data field 2906. For some commands, a specific command size 2908 is expected to indicate the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command operation code. In some embodiments, commands are aligned via multiple double words. The flowchart in Figure 29B shows an exemplary graphics processor command sequence 2910. In some embodiments, the software or firmware of the data processing system of the embodiment of the graphics processor uses a version of the shown command sequence to set, execute, and terminate a set of graphics operations. The exemplary command sequence is shown and described for illustrative purposes only, as the embodiments are not limited to these particular commands or this command sequence. Furthermore, these commands may be sent as batches of commands in a command sequence, such that the graphics processor will process the sequence of commands with at least partial parallelism. In some embodiments, the graphics processor command sequence 2910 may begin with a pipeline cleanup command 2912, causing any active graphics pipeline to complete its currently suspended command. In some embodiments, the 3D pipeline 2922 and the media pipeline 2924 do not operate in parallel. Pipeline cleanup is performed to cause any suspended commands to be completed by the active graphics pipeline. In response to pipeline cleanup, the graphics processor's command parser suspends command processing until the active graphics engine completes the suspended operation and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the render cache may be cleared to memory. In some embodiments, the pipeline cleanup command 2912 may be used for pipeline synchronization or before putting the graphics processor into a low-power state. In some embodiments, pipeline selection command 2913 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline selection command 2913 is only required once within the execution context before a pipeline command is sent, unless the context will send commands to both pipelines. In some embodiments, pipeline clear command 2912 is required immediately before the pipeline switching via pipeline selection command 2913. In some embodiments, pipeline control command 2914 configures the graphics pipeline for operation and is used to program the 3D pipeline 2922 and the media pipeline 2924. In some embodiments, pipeline control command 2914 configures the pipeline state of the active pipeline. In one embodiment, pipeline control command 2914 is used for pipeline synchronization and to clear data from one or more caches within the active pipeline before processing a batch of commands. In some embodiments, the return buffer status command 2916 is used to configure a set of return buffers for individual pipelines to write data. Some pipeline operations require the configuration, selection, or setup of one or more return buffers, where these operations write intermediate data to these return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer status 2916 includes selecting the size and number of return buffers for a set of pipeline operations. The residual commands in the command sequence vary depending on the active pipeline for the operation. Based on pipeline determination 2920, the command sequence is adjusted to either 3D pipeline 2922 starting with 3D pipeline state 2930 or media pipeline 2924 starting with media pipeline state 2940. Commands used to configure 3D pipeline states 2930 include 3D state setting commands for vertex buffers, vertex element states, constant color states, depth buffer states, and other state variables, which should be configured before 3D primitive commands are processed. The values ​​of these commands are determined at least in part based on the specific 3D API being used. In some embodiments, 3D pipeline state 2930 commands can also selectively disable or omit certain pipeline elements if those elements will not be used. In some embodiments, the 3D primitive 2932 command is used to submit 3D primitives for processing by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2932 command are delivered to the vertex extraction function in the graphics pipeline. The vertex extraction function uses the 3D primitive 2932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2932 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2922 schedules shader threads to the graphics processor execution unit. In some embodiments, the 3D pipeline 2922 is triggered by executing command 2934 or an event. In some embodiments, register writes trigger command execution. In some embodiments, execution is triggered by a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to clear the command sequence through the graphics pipeline. The 3D pipeline performs geometric processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations. In some embodiments, when performing media operations, the graphics processor command sequence 2910 follows the media pipeline 2924 path. Typically, the specific use and manner of programming the media pipeline 2924 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations may be offloaded to the media pipeline. In some embodiments, the media pipeline may also be omitted, and media decoding may be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor typically performs SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives. In some embodiments, media pipeline 2924 is configured in a manner similar to that of 3D pipeline 2922. Prior to media object command 2942, a set of commands for configuring media pipeline state 2940 is scheduled or queued. In some embodiments, media pipeline state command 2940 includes data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, media pipeline state command 2940 also supports the use of one or more pointers to "indirect" state elements containing state settings. In some embodiments, media object command 2942 provides a pointer to a media object for media pipeline processing. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before sending media object command 2942. Once the pipeline states are configured and media object command 2942 is scheduled, media pipeline 2924 is triggered by executing command 2944 or an equivalent execution event (e.g., register write). Output from media pipeline 2924 can then be post-processed by operations provided by 3D pipeline 2922 or media pipeline 2924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations. Graphical software architecture Figure 30 illustrates an exemplary graphics software architecture for a data processing system 3000 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 3010, an operating system 3020, and at least one processor 3030. In some embodiments, the processor 3030 includes a graphics processor 3032 and one or more general-purpose processor cores 3034. The graphics application 3010 and the operating system 3020 each execute in the system memory 3050 of the data processing system. In some embodiments, the 3D graphics application 3010 includes one or more shader programs including shader instructions 3012. The shader language instructions may be a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 3014 in machine language suitable for execution by a general-purpose processor core 3034. The application also includes graphics objects 3016 defined by vertex data. In some embodiments, the operating system 3020 is a Microsoft® Windows® operating system, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a variant of the Linux kernel from Microsoft Corporation. The operating system 3020 may support graphics APIs 3022, such as the Direct3D API, OpenGL API, or Vulkan API. When using the Direct3D API, the operating system 3020 uses a front-end shader compiler 3024 to compile any shader instructions 3012 in HLSL into a low-level shader language. This compilation may be just-in-time (JIT) compilation or pre-compilation of the application executable shaders. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 3010. In some embodiments, shader instructions 3012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API. In some embodiments, the user-mode graphics driver 3026 includes a back-end shader compiler 3027 for translating shader instructions 3012 into a hardware-specific representation. When using the OpenGL API, shader instructions 3012 in the GLSL high-level language are passed to the user-mode graphics driver 3026 for compilation. In some embodiments, the user-mode graphics driver 3026 communicates with the kernel-mode graphics driver 3029 using operating system kernel-mode functionality 3028. In some embodiments, the kernel-mode graphics driver 3029 communicates with the graphics processor 3032 to schedule commands and instructions. IP Core Implementation One or more of the embodiments can be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, these instructions can cause the machine to manufacture logic for performing the techniques described herein. Such a representation (known as an "IP core") is a reusable unit for the logic of an integrated circuit, which can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model onto manufacturing machines that manufacture the integrated circuit. The integrated circuit can be manufactured such that the circuit performs the operations described in accordance with any of the embodiments described herein. Figure 31 is a block diagram showing an IP core development system 3100 that can be used to fabricate integrated circuits to perform operations according to an embodiment. The IP core development system 3100 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to construct complete integrated circuits (e.g., SOC integrated circuits). Design facility 3130 can generate a software simulation 3110 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 3110 can be used with a simulation model 3112 to design, test, and verify the behavior of the IP core. The simulation model 3112 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 3115 can then be generated or synthesized from the simulation model 3112. The RTL design 3115 is an abstract concept of the behavior of the integrated circuit, modeling the flow of digital signals between hardware registers, which include relevant logic executed using the modeled digital signals. In addition to the RTL design 3115, low-order designs at the logic or transistor levels can also be generated, designed, or synthesized. Therefore, specific details of the initial design and simulation can be altered. The RTL design 3115 or equivalent may be further synthesized by the design facility into a hardware model 3120, which may be a Hardware Description Language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to validate the IP core design. The IP core design may be stored using non-volatile memory 3140 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 3165. Alternatively, the IP core design may be transmitted via a wired connection 3150 or a wireless connection 3160 (e.g., via the Internet). The manufacturing facility 3165 may then manufacture integrated circuits based at least in part on the IP core design. The manufactured integrated circuits may be configured to operate according to at least one embodiment described herein. Example System Single-Chip Integrated Circuit Figures 32-34 show exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to the various embodiments described herein. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. Figure 32 is a block diagram showing an exemplary system-on-a-chip integrated circuit 3200 manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 3200 includes one or more application processors 3205 (e.g., CPUs), at least one graphics processor 3210, and may additionally include an image processor 3215 and / or a video processor 3220, any of which may be modular IP cores from the same or more different design facilities. The integrated circuit 3200 includes peripheral or bus logic, including a USB controller 3225, a UART controller 3230, an SPI / SDIO controller 3235, and an I2S / I2C controller 3240. Furthermore, the integrated circuit may include a display device 3245 coupled to one or more high-resolution multimedia interface (HDMI) controllers 3250 and a mobile industry processor interface (MIPI) display interface 3255. Storage may be provided by a flash memory subsystem 3260 including flash memory and a flash memory controller. The memory interface can be provided via the memory controller 3265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 3270. Figure 33 is a block diagram of an example graphics processor 3310, which is a system-on-a-chip integrated circuit that can be manufactured using one or more IP cores according to an embodiment. The graphics processor 3310 may be a variant of the graphics processor 3210 of Figure 32. The graphics processor 3310 includes a vertex processor 3305 and one or more fragment processors 3315A-3315N (e.g., 3315A, 3315B, 3315C, 3315D to 3315N-1 and 3315N). The graphics processor 3310 may execute different shader programs via individual logic, such that the vertex processor 3305 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 3315A-3315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3305 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. Fragment processors 3315A-3315N use primitive and vertex data generated by vertex processor 3305 to produce a frame buffer displayed on a display device. In one embodiment, fragment processors 3315A-3315N are optimized to execute fragment shader programs as provided for the OpenGL API, which can be used to perform similar operations as pixel shader programs provided for the Direct 3D API. The graphics processor 3310 additionally includes one or more memory management units (MMUs) 3320A-3320B, caches 3325A-3325B, and circuit interconnects 3330A-3330B. The one or more MMUs 3320A-3320B provide virtual-to-physical address mapping for the integrated circuit 3310, including for the vertex processor 3305 and / or fragment processors 3315A-3315N, which, in addition to vertex or image / texture data stored in the one or more caches 3325A-3325B, can also reference vertex or image / texture data stored in memory. In one embodiment, one or more MMUs 3325A-3325B may be combined with other MMUs within the system, including one or more MMUs associated with one or more application processors 3205, image processor 3215, and / or video processor 3220 in FIG. 32, such that each processor 3205-3220 can be added to a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3330A-3330B enable the graphics processor 3310 to interface with other IP cores within the SoC via internal buses of the SoC or via direct connections. Figure 34 is a block diagram of an additional example graphics processor 3410 of a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. Graphics processor 3410 may be a variant of graphics processor 3210 of Figure 32. Graphics processor 3410 includes one or more MMUs 3320A-3320B, caches 3325A-3325B, and circuit interconnects 3330A-3330B of integrated circuit 3300 of Figure 33. The graphics processor 3410 includes one or more shader cores 3415A-3415N (e.g., 3415A, 3415B, 3415C, 3415D, 3415E, 3415F to 3415N-1 and 3415N) that provide a unified shader core architecture, wherein a single core or core type can execute all types of programmable shader code (including shader program code) to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. In addition, the graphics processor 3410 includes an inter-core job manager 3405, which functions as a thread scheduler to schedule threads to one or more shader cores 3415A-3415N and a brick-filling unit 3418 to accelerate brick-filling operations for brick-based rendering, wherein rendering operations for a scene are subdivided into image space, for example, to take advantage of local spatial coherence within a scene or to optimize the use of internal caches. The following terms and / or examples relate to specific embodiments or examples thereof. Details in the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some included features and some excluded features to suit a variety of different applications. Examples may include subjects such as methods, means for performing actions of the method, at least one machine-readable medium containing instructions that, when executed by a machine, cause the machine to perform the actions of the method, or devices or systems according to the embodiments and examples described herein. Various components may be means for performing the described operations or functions. One embodiment provides a computing device for performing machine learning operations. The computing device includes instruction decoding logic for decoding a single instruction comprising multiple operands into a single decoded instruction, the multiple operands having different accuracies, and a general-purpose graphics computing unit including a first logic unit and a second logic unit. The general-purpose graphics computing unit is used to execute the single decoded instruction, wherein executing the single decoded instruction includes performing a first instruction operation with a first accuracies on a first group of operands among the multiple operands, and simultaneously performing a second instruction operation with a second accuracies on a second group of operands among the multiple operands. One embodiment provides a method for performing machine learning operations. The method includes extracting and decoding a single instruction comprising multiple operands, the multiple operands referring to multiple data elements with different accuracies, performing a first instruction operation on a first group of the multiple data elements via a first logic unit within a computing unit, the first group of the multiple data elements having a first accuracies, performing a second instruction operation on a second group of the multiple data elements via a second logic unit within the computing unit in parallel with the execution of the first instruction operand via the first logic unit, the second group of the multiple data elements having a second accuracies, and outputting the result of the first instruction operation and the second instruction operation. One embodiment provides a data processing system including a non-transitory machine-readable medium for storing instructions executable by one or more processors in the data processing system, and a general-purpose graphics processing unit including instruction decoding logic for decoding a single instruction comprising multiple operands into a single decoded instruction, the multiple operands having different accuracies, and a computing unit including a first logic unit and a second logic unit for executing the single decoded instruction, wherein executing the single decoded instruction includes performing a first instruction operation with a first accuracies for a first set of operands among the multiple operands, and simultaneously performing a second instruction operation with a second accuracies for a second set of operands among the multiple operands. The embodiments described herein relate to specific hardware configurations, such as application-specific integrated circuits (ASICs) configured to perform some computation or have predetermined functions. Such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connectivity. The coupling of the collection of processors and other components is typically via one or more buses and bridges (also known as bus controllers). Storage devices carrying network traffic and signals represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on the collection of one or more processors of the electronic device. Of course, one or more parts of the embodiments may be implemented using different combinations of software, firmware, and / or hardware. Throughout the detailed description, numerous specific details have been set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these embodiments may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in detail to avoid obscuring the inventive subject matter of the embodiments. Therefore, the scope and spirit of the invention should be determined in accordance with the following claims.

Claims

1. A graphics processing unit (GPU) for accelerating machine learning computations, the GPU comprising: a separate graphics processing circuit including multiple general-purpose graphics computing units, the separate graphics processing circuit including: An instruction cache is used to store a first instruction and a second instruction, wherein the first instruction and the second instruction are single instructions. The first instruction includes four operands, including two 16-bit floating-point source operands and one 32-bit floating-point source operand. The first instruction is used to cause the GPU to perform multidimensional mixed-precision floating-point operations in response to the first instruction. The second instruction includes at least one integer operand. The second instruction is used to cause the GPU to perform integer operations in response to the second instruction, and the integer operations correspond to address calculations; and a plurality of general-purpose graphics computing units. The unit has a single instruction multiple thread (SIMT) architecture, wherein each of the plurality of general-purpose graphics computing units includes a first functional unit and a second functional unit. The first functional unit is used to execute a plurality of threads of the first instruction, and the second functional unit is a computing unit configured to execute a plurality of threads of the second instruction during the plurality of threads of the first instruction executed by the first functional unit. At least one general-purpose graphics computing unit is used to dynamically configure the precision of the first functional unit to perform the multidimensional mixed precision floating-point operation of the first instruction.

2. The GPU of claim 1, wherein the multidimensional mixed-precision floating-point operation is a two-dimensional matrix multiplication operation, and the multidimensional mixed-precision floating-point operation is associated with inner product operation.

3. The GPU of claim 2, wherein the at least one integer operand is an indicator of memory location.

4. The GPU of claim 3, wherein performing the multidimensional mixed-precision floating-point operation includes performing a multiplication operation on the two 16-bit floating-point source operands and performing an addition operation on the product of the multiplication operation and the 32-bit floating-point source operand.

5. The GPU of claim 1 further includes a scheduler for scheduling at least one thread of the first instruction and at least one thread of the second instruction to the at least one general-purpose graphics computing unit, wherein the at least one general-purpose graphics computing unit is configured to dynamically cause the second functional unit to execute the at least one thread of the second instruction from an idle state based on the computing requirements of the workload associated with the first instruction or the second instruction.

6. The GPU of claim 5, wherein the scheduler is used to independently schedule multiple threads of each of the first instruction and the second instruction.

7. The GPU of claim 6, wherein the first instruction and the second instruction have independent thread states.

8. A data processing system, comprising: an external card coupled to a system interface of the data processing system, the external card comprising: An independent graphics processing unit (GPU) for accelerating machine learning computation includes an instruction cache for storing a first instruction and a second instruction, wherein the first instruction and the second instruction are single instructions. The first instruction includes four operands, including two 16-bit floating-point source operands and one 32-bit floating-point source operand. The first instruction causes the GPU to perform multidimensional mixed-precision floating-point operations in response to the first instruction. The second instruction includes at least one integer operand. The second instruction causes the GPU to perform integer operations in response to the second instruction, and the integer operations correspond to address calculations. The GPU also includes... The system comprises a plurality of general-purpose graphics computing units, each having a single instruction multiple thread (SIMT) architecture. Each general-purpose graphics computing unit includes a first functional unit and a second functional unit. The first functional unit is used to execute a plurality of threads of the first instruction, and the second functional unit is a computing unit configured to execute a plurality of threads of the second instruction simultaneously with the plurality of threads of the first instruction executed by the first functional unit. At least one general-purpose graphics computing unit is used to dynamically configure the precision of the first functional unit to perform the multidimensional mixed precision floating-point operation of the thread of the first instruction. And memory, which is communicatively coupled to the graphics processing unit.

9. The data processing system of claim 8, wherein the multidimensional mixed-precision floating-point operation is a two-dimensional matrix multiplication operation, the first instruction is a single instruction, the GPU is used to respond to the single instruction to perform the multidimensional mixed-precision floating-point operation, and the multidimensional mixed-precision floating-point operation is associated with inner product operation.

10. The data processing system of claim 9, wherein the at least one integer operand is an index of memory location.

11. The data processing system of claim 10, wherein performing the multidimensional mixed precision floating-point operation includes performing a multiplication operation on the two 16-bit floating-point source operands and performing an addition operation on the product of the multiplication operation and the 32-bit floating-point source operand.

12. The data processing system of claim 8, wherein the GPU further includes a scheduler for scheduling at least one thread of the first instruction and at least one thread of the second instruction to the at least one general-purpose graphics computing unit, wherein the at least one general-purpose graphics computing unit is configured to dynamically cause the second functional unit to execute the at least one thread of the second instruction from an idle state based on the computing requirements of the workload associated with the first instruction or the second instruction.

13. The data processing system of claim 12, wherein the scheduler is used to independently schedule multiple threads of each of the first instruction and the second instruction.

14. The data processing system of claim 13, wherein the first instruction and the second instruction have independent thread states.

15. A method for accelerating machine learning computation, the method comprising: decoding a first instruction and a second instruction on a graphics processing unit (GPU), the GPU including independent graphics processing circuitry having a single instruction multiple thread (SIMT) architecture and a plurality of SIMT multiprocessors, wherein the first instruction and the second instruction are a single instruction, the first instruction including four operands, including two 16-bit floating-point source operands and a 32-bit floating-point source operand, and the second instruction including at least one integer operand; and simultaneously executing the first instruction on a first multiprocessor of the plurality of SIMT multiprocessors of the GPU. The thread executing the first instruction and the thread executing the second instruction, wherein the thread executing the first instruction includes performing multidimensional mixed-precision floating-point operations, wherein the thread executing the first instruction includes dynamically configuring the precision of the first functional unit to perform the multidimensional mixed-precision floating-point operations, wherein the thread executing the second instruction includes performing integer operations on the second functional unit, the integer operations corresponding to address calculations, and wherein performing the multidimensional mixed-precision floating-point operations includes performing multiplication operations on the two 16-bit floating-point source operands and performing addition operations on the product of the multiplication operations and the 32-bit floating-point source operands.

16. The method of claim 15, wherein the multidimensional mixed-precision floating-point operation is a two-dimensional matrix multiplication operation, the first instruction is a single instruction, the GPU is used to respond to the single instruction to perform the multidimensional mixed-precision floating-point operation, and the multidimensional mixed-precision floating-point operation is associated with inner product operation.

17. The method of claim 16, wherein the at least one integer operand is an index of memory location.

18. The method of claim 17, wherein the integer operand is a 32-bit operand.

19. The method of claim 15 further includes scheduling at least one thread of the first instruction and at least one thread of the second instruction via a scheduler within the GPU; and dynamically causing the second functional unit to execute the at least one thread of the second instruction from an idle state based on the computational requirements of the workload associated with the first instruction or the second instruction.

20. The method of claim 19 further comprises independently scheduling multiple threads of each of the first instruction and the second instruction, wherein each of the threads of the first instruction and the second instruction has an independent thread state.

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