Method of protecting low-k layers

Abstract

A process is provided in which a low-k layer is protected from etching damage by selectively forming a protective layer on the low-k layer. In one embodiment, the low-k layer may be a low-k dielectric layer used in the BEOL processing step. In one embodiment, the selectively formed protective layer may be formed by a selective deposition process that selectively forms a film on the low-k dielectric but not on the conductor layer. The selectively formed protective layer may then be used to protect the low-k layer from plasma etching, which is used to recess the conductor. In this way, the conductor (e.g., a metal) can be recessed in the low-k dielectric layer by plasma etching.

Description

[Technical Field] This invention relates to substrate processing. In particular, it provides a method for suppressing damage to the processed layer. [Cross-reference to related applications] This application claims priority to U.S. Provisional Patent Application No. 62 / 685,372, filed June 15, 2018, entitled "Method of Protecting Low K Layers," and U.S. Provisional Patent Application No. 62 / 696,697, filed July 11, 2018, entitled "Method of Protecting Low K Layers," the disclosures of which are hereby expressly incorporated herein by reference. [Previous Technology] As the critical dimensions of features formed on substrates continue to shrink, the use of low-k materials (materials with a dielectric constant lower than that of silicon dioxide) in substrate processing has become increasingly important. Low-k materials can be used to form low-k layers, which are applied at various points in the substrate processing flow, including front-end online (FEOL) and back-end online (BEOL) processing steps. For example, it has been found that the lower dielectric constant of low-k dielectric layers improves electrical properties (e.g., capacitance), thereby improving device performance when BEOL wires are embedded in the dielectric layer. The shrinking critical size also increases the requirements for the alignment and coverage of various patterned film layers on the substrate. To address these requirements for BEOL conductors and interposer windows, a fully self-aligned interposer window (FSAV) process has been proposed to connect upper and lower conductor layers (typically metal layers) through an interposer window. Many techniques have been used to form FSAVs. In many embodiments, the FSAV can be formed by creating recesses in the lower conductor layer. The formation of conductor recesses is typically accomplished using wet etching or dry plasma etching. Dry plasma etching is preferred due to its cost-effectiveness. However, it has been found that when FSAV processing is used in conjunction with low-k dielectrics, the operation of using plasma etching to provide conductor recesses may damage the low-k dielectric layer. For example, plasma etching may damage the low-k dielectric material by increasing the dielectric constant at the surface of the low-k dielectric layer, thereby hindering the benefits of using the low-k material. Figures 1A-1C illustrate the effects of using plasma etching to form metal recesses in a low-k dielectric layer. As shown in Figure 1, a structure 100 is provided on a substrate 105. A low-k layer 115 (e.g., a low-k dielectric layer) and an underlying layer 110 are provided. A conductor layer 120 may be formed as illustrated. A barrier or pad layer 125 may be provided below the conductor layer 120 and between the conductor layer 120 and the low-k layer 115. Next, as shown in FIG1B, structure 100 can be exposed to plasma 130 to provide recesses in conductor layer 120 as part of the FSAV process. The plasma etching of the recesses may result in damage to the low-k layer 135 at the surface of the low-k dielectric layer, as shown in FIG1C. The dielectric constant of the damaged low-k layer 135 may be increased due to the damage caused by the recess plasma etching. The damaged low-k layer 135 may therefore have a higher dielectric constant than the undamaged portion of the low-k layer 115. Regions with higher dielectric constants may offset some of the benefits of using low-k materials, such as affecting electrical device characteristics. Therefore, the following processing flow is desired: a processing flow in which the low-k layer is not damaged by the conductor recess etching process. [Summary of the Invention] In one embodiment, a process is provided in which a low-k layer is protected from etching damage by selectively forming a protective layer on the low-k layer. In one embodiment, the low-k layer may be a low-k dielectric layer used in the BEOL processing step. In one embodiment, the selectively formed protective layer may be formed by a selective deposition process that selectively forms a film on the low-k dielectric but not on the conductor layer. The selectively formed protective layer may then be used to protect the low-k layer from plasma etching, which is used to recess the conductor. In this way, the conductor (e.g., a metal) can be recessed in the low-k dielectric layer by plasma etching. In another embodiment, a substrate processing method is disclosed. The method includes providing a patterned structure for the substrate, the patterned structure including a conductor layer and a low-k layer. The method further includes forming a self-aligned monolayer on an exposed surface of the conductor layer and selectively depositing a protective layer, the selective deposition step selectively forming a protective layer on the low-k layer. The method further includes performing a conductor recess dry etching to selectively remove the self-aligned monolayer and a portion of the conductor layer, wherein the protective layer suppresses damage to the low-k layer during the conductor recess dry etching. In another embodiment, a method for forming a self-aligned dielectric window is disclosed. The method includes providing a patterned structure for a substrate, the patterned structure including a conductor layer and a low-k dielectric layer, the conductor layer being embedded within the low-k dielectric layer and the conductor layer being a lower conductor layer, the self-aligned dielectric window being located on the conductor layer. The method also includes performing selective formation of a protective layer, the selective formation step selectively forming the protective layer on the low-k dielectric layer but not on the conductor layer. The method further includes performing a conductor recess dry etching to selectively remove a portion of the conductor layer, wherein the protective layer suppresses damage to the low-k dielectric layer during the conductor recess dry etching. In another embodiment, a method for forming a recess in a metal layer is disclosed. The method includes providing a patterned structure for a substrate, the patterned structure including a metal layer and a low-k dielectric layer, the metal layer being embedded in the low-k dielectric layer, the metal layer having a plurality of exposed metal surfaces and the low-k dielectric layer having a plurality of exposed low-k dielectric surfaces. The method also includes performing selective formation of a protective layer, the selective formation step selectively forming the protective layer on the plurality of exposed low-k dielectric surfaces. The method further includes performing a metal recess dry etching to remove a portion of the metal layer, thereby forming a recess in the metal layer, wherein the protective layer suppresses damage to the low-k dielectric layer during the metal recess dry etching. [Simplified Explanation of the Diagram] A more complete understanding of the invention and its advantages can be obtained by taking into account the accompanying drawings, in which similar reference numerals denote similar features. However, it should be noted that the drawings show only exemplary embodiments of the disclosed concepts and are therefore not intended to limit the scope; other equivalent embodiments are permissible based on the disclosed concepts. Figures 1A-1C show prior art treatments used to depress the conductor layer, in which the low-k dielectric layer is damaged. Figures 2A-2C show exemplary treatments used to create a concave conductor layer without damaging the low-k layer. Figures 3A-3F show another exemplary treatment used to recess the conductor layer without damaging the low-k layer. Figure 4 shows an illustrative formation of the etch stop layer after the treatment in Figure 3F. Figures 5A-5B show another illustrative formation of the etch stop layer after the treatment shown in Figure 3F. Figures 6A-6G show exemplary additional processing following the processing steps in Figure 5B to form a self-aligned mesolayer window. Figure 7-9 shows an exemplary method using the techniques disclosed herein.

Implementation Method

Claims

1. A substrate processing method, the method comprising: providing a patterned structure for a substrate, the patterned structure including a conductor layer and a low-k layer; forming a self-aligned monolayer on an exposed surface of the conductor layer; performing selective deposition of a protective layer, the selective deposition step selectively forming a protective layer on the low-k layer; and performing a conductor recess dry etching to selectively remove the self-aligned monolayer and a portion of the conductor layer, wherein the protective layer suppresses damage to the low-k layer during the conductor recess dry etching.

2. The substrate processing method of claim 1 further includes: providing a barrier or pad layer between the conductor layer and the low-k layer, wherein the conductor recess dry etching selectively etches the conductor layer to the barrier or pad layer, so that the barrier or pad layer suppresses damage to the sidewall of the low-k layer during the dry etching of the conductor recess.

3. The substrate processing method of claim 1 further includes: providing a barrier or pad layer between the conductor layer and the low-k layer; and performing a barrier or pad layer removal process after dry etching of the conductor recess to remove the exposed portion of the barrier or pad layer.

4. The substrate processing method of claim 3 further includes: forming an etch stop layer on the substrate after performing dry etching of the conductor recess, wherein the protective layer is located on the substrate during the step of forming the etch stop layer.

5. The substrate processing method of claim 3 further includes: forming an etch stop layer on the substrate after performing dry etching of the conductor recess, wherein the protective layer is removed from the substrate before the step of forming the etch stop layer.

6. The substrate processing method of claim 1 further includes: forming an etch stop layer on the substrate after performing dry etching of the conductor recess, wherein the protective layer is located on the substrate during the step of forming the etch stop layer.

7. The substrate processing method of claim 1 further includes: forming an etch stop layer on the substrate after performing dry etching of the conductor recess, wherein the protective layer is removed from the substrate before the step of forming the etch stop layer.

8. The substrate processing method of claim 1, wherein the suppression of damage to the low-k layer suppresses the increase in the dielectric constant of the low-k layer.

9. A method for forming a self-aligned dielectric window, the method comprising: providing a patterned structure for a substrate, the patterned structure including a conductor layer and a low-k dielectric layer, the conductor layer being embedded in the low-k dielectric layer and the conductor layer being a lower conductor layer, the self-aligned dielectric window being disposed on the conductor layer; performing selective formation of a protective layer, the selective formation step selectively forming the protective layer on the low-k dielectric layer and not forming the protective layer on the conductor layer; and performing a conductor recess dry etching to selectively remove a portion of the conductor layer, wherein the protective layer suppresses damage to the low-k dielectric layer during the conductor recess dry etching.

10. The method for forming a self-aligned mesolayer window as claimed in claim 9 further comprises: forming a self-aligned monolayer on the exposed surface of the conductor layer prior to the selective forming step of the protective layer.

11. The method for forming a self-aligned interlayer window as claimed in claim 9 further includes: forming an etch stop layer on the substrate after performing dry etching of the conductor recess, wherein the protective layer is located on the substrate during the step of forming the etch stop layer.

12. The method for forming a self-aligned interlayer window as claimed in claim 9 further includes: forming an etch stop layer on the substrate after performing dry etching of the conductor recess, wherein the protective layer is removed from the substrate prior to the step of forming the etch stop layer.

13. The method for forming a self-aligned interlayer window as claimed in claim 9 further comprises: leaving the protective layer on the substrate during one or more additional self-aligned interlayer window processing steps after dry etching of the conductor recess.

14. The method for forming a self-aligned interlayer window as claimed in claim 9 further includes: removing the protective layer after dry etching of the conductor recess.

15. The method for forming a self-aligned dielectric window as claimed in claim 9, wherein the suppression of damage to the low-k dielectric layer suppresses the increase in the dielectric constant of the low-k dielectric layer.

16. A method for forming a recess in a metal layer, the method comprising: providing a patterned structure for a substrate, the patterned structure including a metal layer and a low-k dielectric layer, the metal layer being embedded in the low-k dielectric layer, the metal layer having a plurality of exposed metal surfaces and the low-k dielectric layer having a plurality of exposed low-k dielectric surfaces; performing selective formation of a protective layer, the selective formation step selectively forming the protective layer on the plurality of exposed low-k dielectric surfaces; and performing a metal recess dry etching to remove a portion of the metal layer, thereby forming a recess in the metal layer, wherein the protective layer suppresses damage to the low-k dielectric layer during the metal recess dry etching.

17. The method for forming a recess in a metal layer, as claimed in claim 16, wherein the metal layer comprises ruthenium, and the dry etching of the metal recess comprises an oxygen-containing plasma.

18. The method for forming a recess in a metal layer as claimed in claim 16 further comprises: forming a self-aligned monolayer on the plurality of exposed metal surfaces prior to the selective forming step of the protective layer.

19. The method for forming a recess in a metal layer as claimed in claim 16 further includes: removing the protective layer after performing dry etching of the metal recess.

20. The method for forming a recess in a metal layer as claimed in claim 16 further comprises: leaving the protective layer on the substrate during one or more additional processing steps performed after the recess is formed.

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