Architecture for a hardware based explainable neural network

Abstract

Interpretable neural networks can be designed to be easily and efficiently implemented in hardware, resulting in significant speed and space improvements. One exemplary embodiment extends possible hardware implementations of XNNs, making them suitable for low-power applications, smartphones, mobile computing devices, autonomous machines, server accelerators, Internet of Things (IoT) and edge computing applications, and many other applications. Leveraging the ability of XNNs to transform from one form to another while preserving their logical equivalence produces efficient, secure hardware implementations that are optimized for the desired application domain and whose behavior is predictable.

Description

[Technical Field]

[0001] An exemplary embodiment presents a hardware implementation of an interpretable neural network or artificial intelligence. [Previous Technology]

[0002] Neural networks have proven adept at complex tasks, particularly in situations requiring the automatic discovery of complex relationships between a set of inputs and outputs. The application of backpropagation-based methods (such as deep learning) has driven a resurgence of useful AI algorithms that outperform humans. Despite their success, neural networks suffer from a lack of transparency due to their inherent black-box architecture, leading to a lack of trust, hidden biases, and over-reliance on training data.

[0003] Neural network architectures have been implemented to solve various problems with better model performance, but very limited research has been conducted on interpretable and explainable architectures, thus eliminating the need for post-hoc methods for interpretability applications. This lack of interpretability limits the adoption of new AI applications in decision-critical applications such as autonomous driving and healthcare.

[0004] A lack of understanding of the inner workings of neural networks has limited some of their potential applications. An analyst or engineer may find it difficult to interpret the relationship between the inputs and corresponding outputs of a black-box neural network. Because a neural network can have multiple layers and neurons, it may be impossible to identify which functions occur through the neural network to produce the output.

[0005] There is a great deal of research on how an artificial neural network (ANN) can be implemented directly and efficiently in hardware; however, there is a need in this field for an interpretable and decipherable hardware implementation. [Summary of the Invention]

[0006] According to at least one exemplary embodiment, a method, system, and apparatus for implementing an interpretable neural network or artificial intelligence may be shown and described.

[0007] Neural networks have proven adept at complex tasks, particularly in situations requiring the automatic discovery of complex relationships between a set of inputs and outputs. Despite their success, neural networks suffer from a lack of transparency due to their inherent black-box architecture, leading to a lack of trust, hidden biases, and over-reliance on training data. Interpretable neural networks (XNNs) represent a new type of artificial neural network (ANN) that is inherently interpretable and explainable.

[0008] XNN is also designed to be easily and efficiently implemented in both software and hardware, resulting in significant speed and space improvements. An exemplary embodiment extends possible hardware embodiments of XNN, making it suitable for low-power applications, smartphones, mobile computing devices, autonomous navigation devices, server accelerators, Internet of Things (IoT), TinyML and edge computing applications, and many other applications.

[0009] The ability of XNN to transform from one form to another while preserving their logical equivalence can be used to generate efficient hardware implementations optimized for the application domain.

[0010] In a first embodiment, the present invention provides a computer implementation method for adapting an interpretable neural network (XNN) to perform operations on one or more hardware types, the method further comprising: receiving the XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of the one or more hardware types; transforming the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted into a logically equivalent architecture during the transformation; using the transformed XNN to perform operations on inputs received by the at least one hardware type; and outputting the operations based on satisfying one or more evaluation guarantee criteria.

[0011] In a second embodiment, the present invention provides an apparatus for deploying an interpretable neural network (XNN), the apparatus comprising: one or more processors, or the like including a graphics processor, the one or more processors: receiving the XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of the one or more hardware types; transforming the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted into a logically equivalent architecture during the transformation; using the transformed XNN operation received by the at least one hardware type as input; and outputting the operation based on satisfying one or more evaluation guarantee criteria.

[0012] In a third embodiment, the present invention provides a non-transitory computer-readable medium comprising instructions that, when executed, cause hardware to at least: receive an XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of one or more hardware types; transform the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted to a logically equivalent architecture during the transformation; operate using the transformed XNN on an input received by the at least one hardware type; and output the operation based on satisfying one or more evaluation guarantee criteria.

[0013] Alternative embodiments and implementations of the hardware circuitry can also be extended to provide logically equivalent white-box machine learning models with functionality similar to interpretable neural networks (XNNs), such as interpretable artificial intelligence (XAI) models, interpretable neural networks (INNs), interpretable transducer transformers (XTTs), interpretable spike networks (XSNs), interpretable memory networks (XMNs), and the like, as well as reinforcement learning applications therein that are compatible with interpretable reinforcement learning (XRL). The methods described herein can be considered for interchangeable application to XNNs, XAI models, XTTs, XSNs, XMNs, and XRLs. Interpretable neural networks (INNs) can provide some form of interpretation and thus form a superset of XNNs and XTTs. The methods described herein can also be considered for application to INNs.

Implementation Method

[0014] The features of the invention are disclosed in the following description and related drawings concerning specific embodiments thereof. Alternative embodiments may be designed without departing from the spirit or scope of the invention. In addition, well-known elements of exemplary embodiments of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention. Furthermore, to facilitate an understanding of the description, several terms used herein are discussed below.

[0015] As used herein, the term "illustrative" means "serving as an example, example, or illustration." The embodiments described herein are not limiting but merely illustrative. It should be understood that the described embodiments are not necessarily to be construed as preferred or superior to other embodiments. Furthermore, the terms "embodiment of the invention," "embodiment," or "the invention" do not require that all embodiments of the invention encompass the discussed features, advantages, or modes of operation.

[0016] Furthermore, the various embodiments described herein are described in accordance with sequences of actions to be performed by, for example, elements of a computing device. Those skilled in the art will recognize that the various sequences of actions described herein can be executed by specific circuitry (e.g., application-specific integrated circuits (ASICs)) and / or by program instructions executed by at least one processor. Additionally, the sequences of actions described herein can be fully embodied in any form of computer-readable storage medium, such that execution of the sequences of actions enables at least one processor to perform the functionality described herein. Furthermore, the sequences of actions described herein can be embodied in a combination of hardware and software. Therefore, various embodiments of the present invention can be embodied in several different forms, all of which have been considered within the scope of the claimed subject matter. Furthermore, for each embodiment described herein, any corresponding form of this embodiment can be described herein as, for example, a "computer" configured to perform the described actions.

[0017] Explainable Neural Networks (XNNs) are a novel type of white-box neural network that offers new possibilities for various AI systems and is inherently interpretable and explainable. A key concept behind an XNN is that its internal network structure is fully interpretable without sacrificing model performance (i.e., accuracy and feedforward execution speed). Interpretability is built into the architecture itself, yet it functions like a standard neural network. This eliminates the need for additional techniques or processing to interpret the results of a neural network. XNNs compute both the answer and its interpretation, as well as the plausibility of the interpretation, in a single feedforward step, without requiring any simulation, iteration, perturbation, etc.

[0018] Referring now to illustrative Figure 1, Figure 1 illustrates a schematic diagram of one exemplary high-order XNN architecture. An input layer 100 may be input (possibly simultaneously) to both a conditional network 110 and a prediction network 120. The conditional network 110 may include a conditional layer 112, a summarizing layer 114, and a switch output layer (which outputs conditional values) 116. The prediction network 120 may include a feature generation and transformation layer 122, a fitting layer 124, and a prediction output layer (value output) 126. These layers may be analyzed by a selection and ranking layer 128, which may multiply the switch output by the value output to produce a ranking or score output 130. The XNN may simultaneously compute the explanation and the answer using the conditional network and the prediction network. The selection and ranking layer 128 ensures that the answer and explanation are correctly matched, appropriately ranked, and scored before being sent to the output 130.

[0019] The processing of the conditional network 110 and the prediction network 120 is considered to be in any order. Depending on the specific application of the XNN, it may be considered that some components of the conditional network 110 (such as components 112, 114, and 116) may be selected or replaced with a common implementation. Depending on the specific application of the XNN, it may be considered that some components of the prediction network 120 (such as components 122, 124, and 126) may be selected or replaced with a common implementation.

[0020] Further consideration may be made that, in some cases, the selection and ranking layers 128 and the output 130 can be combined into a single integrated component. For optimization purposes, the XNN can also be implemented using both the conditional network 110 and the prediction network 120, as well as all such components combined into a single network. This merging of the conditional and prediction networks can also be combined with a combined selection and ranking layer 128 and the output 130. This optimization will still result in a logically equivalent XNN that is faster for feedforward processing, but may be affected when training via backpropagation and gradient descent techniques is involved.

[0021] Therefore, XNN can be implemented such that there is a combination of input layer 100 and conditional network 110 and prediction network 120, including conditional layer 112, summarization layer 114, switching output layer 116, feature generation and transformation layer 122, fitting layer 124, prediction layer 126 and ranking layer 128, resulting in output 130. This combination can be applied to all embodiments and implementations of XNN, including both software and hardware implementations. XNN's versatility in this respect is unique and unparalleled among other neural network implementations because the white-box nature of XNN allows for flexibility and extreme merging without affecting the logical behavior of XNN, but this affects various attributes of a practical implementation, such as size / space usage, performance, resource usage, trainability and total processing power.

[0022] The XNN may include a feature generation and transformation layer 122 containing one of the polynomial transformation neurons and a concatenation or fitting layer 124, thereby combining all polynomial features into one layer.

[0023] An exemplary embodiment of a prediction network 120 using a linear model may utilize a polynomial equation represented by or mathematically equivalent to the following exemplary polynomial equation:

[0024] The feature generation and transformation layer 122 can generate a set of variables related to the output. The fitting layer 124 can generate a set of coefficients that weight the variables obtained in the feature generation and transformation layer 122. Finally, the coefficients can be analyzed, and a value can be generated in the value output layer 126.

[0025] Feature generation and transformation layer 122 is used to implement any advanced transformations, such as nonlinear transformations, that can be applied to the input features and related data. In an exemplary embodiment applying a polynomial transformation, polynomial transformation neurons can be used, which can model polynomial equations using a system of specially interconnected weights and neurons, which enable a white-box approach to the polynomial transformation. Fitting layer 124 can be used to implement any model fitting and prediction method, including (but not limited to) linear and nonlinear fitting methods, Fourier series, Bezier curves, recursive relations, causal operators, etc. Value output layer 126 combines value answers together and ensures that they are equally combinable into a matching pair consisting of an answer and its corresponding interpretation.

[0026] If the XNN focusing step determined by the conditional network 110 has selected more than one partition, multiple such pairs can be generated. The XNN can be implemented to work in full parallel, thereby generating reasonable answer and explanation pairs, which are then filtered and selected by the output of the conditional network 110 in a subsequent stage. Therefore, both parallel and sequential implementations of the XNN are possible because the implementation can be fine-tuned according to a specific application domain and also conforms to the implementation constraints of the system used to implement the XNN.

[0027] Higher-order polynomials can be successfully used to model complex data; however, in a high-dimensional space, they remain uninterpretable and computationally intensive. An XNN can alternatively split the fit of the entire model into multiple smaller fits. This can be accomplished through the concept of "partitions." A partition models a specific region within the entire model. Partitions can be overlapping or non-overlapping, depending on their configuration. In the case of overlapping partitions, a priority function can be used to determine which partition to activate. The procedure for identifying partitions is part of the XNN initialization procedure. When implemented in hardware, partitions can be implemented using some form of rewritable addressable memory or similar type of memory, or hard-coded into circuitry that can significantly increase performance, usually with some form of trade-off between flexibility and performance, depending on the specific hardware implementation chosen.

[0028] When polynomial features can be used to fit the data, the resulting model can be intuitive. In a standard neural network, modeling nonlinearity simply involves adding multiple layers together using a start-up function. This is feasible, but the resulting model is a black box and may not be interpretable in an intuitive way.

[0029] Alternatively, if the data can be modeled using something simpler, such as a polynomial fit, the polynomial transformation can be embedded within the neural network itself and linear / logistic regression can be simply applied after the transformation. The resulting configuration is treated as a white box. The architecture of XNN allows for the seamless incorporation of other logically equivalent methods into its design, such as the use of Fourier series transforms and other methods, such as chain models and stochastic procedural modeling, which can be considered for incorporation into the prediction network 120. It can be further considered that the XNN transformation function can be a transformation pipeline that includes (but is not limited to) polynomial expansion, rotation, dimensionality and dimensionless scaling, Fourier transform, Walsh function, state-space and phase-space transformation, Haar and non-Haar wavelets, generalized L2 function, fractal-based transformation, Hadamard transform, type I and type II fuzzy logic, knowledge graph network, classification coding, differential analysis, and data normalization / standardization. Upon further consideration, the transformation function may utilize at least one of the following: (i) a sub-neural network; (ii) a gradient descent-based method, such as backpropagation; or (iii) a subset of an interpretable neural network. The transformation function pipeline may further include analysis of transformations of data sequences ordered according to the values ​​of one or more variables, including time-ordered data sequences.

[0030] The terms interpretability and interpretability can have different meanings. Interpretability can be a characteristic that may need to be defined by an interpreter. An interpreter can be an agent that interprets system outputs or human products using one of the following combinations: (i) its own knowledge and beliefs; (ii) goal-action plans; (iii) context; and (iv) the world environment. An illustrative interpreter can be a knowledgeable person.

[0031] One alternative to a knowledgeable human interpreter could be a system suitable for automation, such as an expert system in a narrow domain, which may be able to interpret outputs or human products for a limited range of applications. For example, a medical expert system or some logical equivalent (such as an end-to-end machine learning system) may be able to output an effective interpretation of medical results in a specific set of medical application areas.

[0032] It can be considered that in the future, non-human interpreters may emerge, which can partially or completely replace the role of a human interpreter, and / or extend interpretation capabilities to a wider range of application areas.

[0033] There may be two different types of interpretability: (i) model interpretability, which measures the interpretability of any form of automated or mechanical model and its sub-components, structures and behaviors; and (ii) output interpretability, which measures the interpretability of the output from any form of automated or mechanical model.

[0034] Therefore, interpretability may not be a simple binary property, but can be evaluated on a sliding scale ranging from fully interpretable to uninterpretable. Model interpretability may be the interpretability of the underlying implementation, implementation and / or program that produces the output, while output interpretability may be the interpretability of the output itself or any artificial product being examined.

[0035] A machine learning system or suitable alternative embodiments may include several model components. A model component is model-interpretable if its internal behavior and functionality can be fully understood and correctly predicted by an interpreter (for a subset of possible inputs). In one embodiment, the behavior and functionality of a model component can be implemented and represented in various ways, such as a state transition diagram, a flowchart or program description, a behavioral model, or some other suitable method. A model component is output-interpretable if its output can be understood and correctly interpreted by an interpreter (for a subset of possible inputs).

[0036] An exemplary machine learning system or suitable alternative embodiment may be (i) globally interpretable, provided that it is fully model interpretable (i.e., all its components are model interpretable); or (ii) modularly interpretable, provided that it is partially model interpretable (i.e., only some of its components are model interpretable). Furthermore, if all outputs of the machine learning system or suitable alternative embodiment are output interpretable, then it may be partially interpretable.

[0037] A gray box (which is a mixture of characteristics of a black box and a white box) may have the characteristics of a white box when it comes to output, but may have the characteristics of a black box when it comes to its internal behavior or function.

[0038] A white-box system can be a system with fully interpretable model and interpretable output, achieving both local and global interpretability. Therefore, a fully white-box system can be fully interpretable and fully interpretable in terms of both internal function and output.

[0039] A black box can be an output that is interpretable but not a model that is interpretable, and can achieve limited local interpretability, thereby making it the least interpretable, having little or no interpretability, and having minimal understanding of its internal functions. A deep learning neural network can be a system whose output is interpretable but whose model is not interpretable.

[0040] A gray box can be a system that is partially interpretable in terms of model and interpretable in terms of output, and can be partially interpretable in terms of internal functionality and interpretable in terms of output. Therefore, an exemplary gray box can lie between a white box and a black box on a scale from most interpretable (white box) to least interpretable (black box). A gray box system can have a certain degree of modular interpretability because some of its components are interpretable in terms of model.

[0041] It should be understood that some neural network architectures output interpretable results, but these results are not entirely model interpretable. Therefore, such neural network architectures are considered black boxes, or gray boxes if some internal components are considered model interpretable. XNN offers advantages over such neural network architectures, for example, by providing a system with both interpretable outputs and a fully model interpretable system (white box). Unlike XNN, these neural network architectures do not use partitioning to structure the model into well-defined and interpretable local models. In addition, since they are only output interpretable, it is impossible to encode the network into machine- and human-readable rules. Therefore, they may only provide local interpretations and may not provide global interpretability directly from the model structure. Other types of neural network architectures may have similar disadvantages. Since they do not have the concept of partitioning, modeling the functions of different components may require a complex nonlinear transformation, the result of which may be a completely black box component, so the model may only be output interpretable rather than model interpretable. For a fully interpretable understanding of the model, the transformations within different components should also be interpretable. XNN can employ a wide-network approach through different partitions, thus making transformations simpler and easier to understand, rather than as complex and unbelievably opaque as deep networks. Furthermore, XNN can also support the use of internal components within a deep network structure, thus offering superior composability compared to any existing neural network architecture.

[0042] While this technique can use a linear equation of some form to model an interpretable function using a neural network, XNN differs in several ways: First, XNN uses the concept of hierarchical features (or hierarchical concepts) through the concepts of partitions and rules. In XNN, a function f(x) can be viewed as a local function that models the importance of features within a specific partition. The combination of all functions produces a globally interpretable model. Furthermore, XNN can utilize an external procedure to identify suitable partitions during its initialization, but also supports further training using backpropagation and related techniques. Current techniques rely solely on backpropagation to learn a function, which can limit the degree of interpretability.

[0043] Because XNNs can be encoded as rules and their partition structures can be initialized using an external program, human knowledge can be embedded within the neural network. Therefore, XNNs can blend human knowledge with machine-generated knowledge. By using gradient descent methods, such as backpropagation, regular knowledge can be refined to produce a global model that can also function locally. Current techniques cannot achieve this because a typical neural network is simply used to fit a single large function.

[0044] The weights and structure of an XNN can be encoded by a sequence of one of the following rules: IF-THEN rule, Disjunctive Normal Form (DNF) rule, or Conjunctive Normal Form (CNF) rule. Currently, the resulting model consists of a single equation incorporating all features (or concepts).

[0045] XNN supports rotation and scale invariance as well as nonlinear functions, and also supports summarization of multiple partitions across multiple dimensions. Current techniques use a combination of linear functions and cannot represent nonlinear data in the same way that XNN, with its high-order interpretability, can.

[0046] XNN provides a higher level of flexibility by allowing partitions to be customized according to the desired level of simplicity or complexity. Currently, if the resulting model is interpretable but still too complex to understand, new partitions cannot be generated to simplify local interpretability while maintaining the global interpretability of XNN.

[0047] An XNN (which is a true white-box system) is not subject to any reconstruction loss or classification loss. An XNN can generate an accurate classification as part of its interpretation without a reconstruction step and in a lossless manner. The XNN retains all the information required for classification and can also easily identify all the startup paths and methods used without any additional computational cost.

[0048] Hierarchical clustering techniques or other logically equivalent methods can be used to identify suitable partitions, such as an XAI model induction method, which can input a set of training data into a black box system and use a partitioning function to analyze the corresponding output.

[0049] In one exemplary embodiment where a first-order clustering method can be used for partitioning, a variety of suitable methods can be used in a practical implementation, including (but not limited to) agglomerative clustering, splitting clustering, relocation partitioning, probabilistic clustering, k-medoid method, k-means method, fuzzy clustering, density-based clustering, grid-based method, gradient descent-based method, evolutionary method, region splitting, region growing, subspace clustering, projection method, cooperative clustering method, and slow clustering method.

[0050] The input to the partitioning method can be input features that are directly used for low-dimensional data (i.e., tables) or pre-processed data (e.g., from a spiral network). Features that have undergone a spiral transformation can typically represent a higher-order abstraction, such as an edge, a stroke, or a pattern.

[0051] Partitions can be initially generated as part of the XNN by an external procedure (such as the model induction method described previously). However, once generated, the XNN can further refine the partitions (if necessary) using gradient descent. XNN partitions can be locked by setting their values ​​to immutable static values ​​or dynamically moved for each backpropagation training iteration using standard backpropagation and related techniques.

[0052] Prior to hardware deployment, hierarchical clustering can always be converted into logically equivalent planar clustering. Furthermore, the hierarchical structure can be pre-computed and converted into a suitable hardware implementation, or, in the case of more advanced hardware (such as FPGAs), can be implemented locally on the board. The parts of a hierarchy can be implemented as part of the same hardware circuitry or as a set of components corresponding to a subset of the hierarchy. In this way, high parallelism can be natively achieved in hardware (especially in high-performance applications).

[0053] Furthermore, the white-box nature of XNNs allows for additional ways to modify partitions and values ​​using techniques such as genetic algorithms and Monte Carlo simulations, or through causal logic and simulation techniques. These additional ways are typically attributed to their black-box nature, making them unsuitable for standard neural network implementations, thus giving XNNs a significant advantage. XNN partitions can be hierarchical rather than just planar. (However, planar partitions can be encompassed by a hierarchical structure definition. Thus, planar partitions can be supported as a subset of hierarchical partitions, where only a single level exists.) The use of a single level allows for more fully modeling and more expressive interpretations of the expected properties, providing a better explanation.

[0054] Compared to a typical black-box ANN, deep learning network, and similar models, the white-box nature of XNN offers significant advantages when implemented in hardware. Because the parts of an XNN are understood and interpretable, logical equivalence between different circuit types can be proven, for example, transforming and optimizing circuits for space efficiency or overall processing speed. Such transformations cannot be achieved using a black-box model. Furthermore, white-box XNN allows for the implementation of action triggers in hardware, enabling rapid, real-time signaling without pausing or stopping the network in any way. Triggers can be defined based on specific conditions occurring within the network and can be configured or hard-coded in a circuit. Upon triggering, a signal is raised, which then activates another part of the circuit to perform an action; hence, it is called an action trigger. In an exemplary hardware implementation with a sensor, the signal can be used to communicate with a sensor or some form of interface device. Signals can also be used to provide reentrant or non-reentrant functionality in hardware, and can also provide a means of efficient communication with a parent system and / or embedded systems. When using action triggers, distributed XNN systems can be implemented in hardware, using an implementation that supports some form of multithreading or parallelism, or directly using custom circuitry. The white-box nature of XNNs allows such circuitry to be optimized both in terms of its functionality and in terms of the physical layout of the resulting circuitry. In one exemplary embodiment, a hardware XNN chip can be embedded within a larger system, such as an autonomous vehicle, and can use dedicated hardware to perform fast, low-power processing and send any anomalies, discrepancies, characteristics, and / or other signals back to the vehicle for immediate evaluation, action, and interpretation.

[0055] In an exemplary INN implementation in hardware, since the INN can be partially composed of a black-box model integrated with a white-box model, the white-box advantages of the hardware implementation can be largely applied to the white-box portion of the INN. All hardware white-box optimization techniques applicable to XNN can also be applied to the white-box portion of the INN, while the black-box portion of the INN can be implemented in hardware in a manner similar to that of a standard ANN.

[0056] It can be considered that, depending on the results of the inductive method used to generate the XNN, an XNN can be a type of white-box wide neural network (WNN). WNN complements the mainstream black-box deep neural networks (DNN) and offers significant advantages over DNN. Independent analysis of WNN in (Zagoruyko and Komadikis, 2017) shows that WNN can significantly outperform logically equivalent but much more structurally complex DNNs by several orders of magnitude in performance, and WNN training can also be several times faster than DNN. XNN can provide both of these additional advantages simultaneously, and our preliminary experimental results from XNN implementations strongly indicate that these advantages apply to most XNNs and that hardware implementations of XNN can leverage these advantages to achieve the same effect with fewer resources.

[0057] XNN can be fully implemented directly in hardware as digital electronic circuits, analog circuits or digital-analog hybrids, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) computer hardware, neuromorphic circuits, quantum computing hardware, firmware and / or combinations thereof.

[0058] These various forms or features may include implementations that can be executed and / or interpreted on a hardware system typically comprising at least one programmable processor (which may be dedicated or general purpose), the at least one programmable processor being coupled to typically receive and transmit data and instructions from at least one storage system, at least one input device and at least one output device. Other alternative embodiments may exist in which the need for a processor is eliminated by implementing the XNN directly as a hardware circuit, the need for memory is eliminated by having hard-coded values ​​(at the expense of training flexibility without sacrificing typical operational functionality), the need for input is eliminated when processing sensorless systems, and the need for output devices is eliminated when processing memory-based implementations that do not directly generate outputs.

[0059] The hardware system may include client and server components. A client and server are generally geographically distant from each other and typically interact via a communication network. This remoteness can be geographical or network-based. For example, a server may be located in a geographically remote location from the client interface. The client and server components may be other hardware systems or a combination of software and hardware systems. For example, the server storing the XNN may be remote and requires one or more network-connected systems to receive the XNN for deployment. Some types of XNNs (such as distributed XNNs) are optimized for this client-server architecture or a more flexible distributed architecture that includes serverless systems and fully or partially distributed systems. Additionally, any of the above systems may be locally connected via a network connection system such as Bluetooth or a local Ethernet link.

[0060] Any software that the hardware system may require to function (such as hardware systems containing programmable processors) will need to implement some form, programmable representation, or machine instruction of such programmable processors as XNN. This software may be implemented in a high-level programming language, an object-oriented programming language, a functional programming language, a logic programming language, and / or a combination / machine language.

[0061] The hardware system implementation of XNN may utilize a machine-readable medium, such as a software product, device, and / or other instrument, for providing machine instructions and / or data to a programmable processor, an unprogrammable processor, or some encoding mechanism, including a machine-readable medium that receives machine instructions as a machine-readable signal. The machine-readable signal may be any signal used to provide machine instructions and / or data to a hardware system and may be transmitted or relayed through some network or other transmission system. The machine-readable medium may store such machine instructions non-transitory, such as using a hard disk drive or solid-state memory or any equivalent storage medium. Alternatively, the machine-readable medium may store such machine instructions transiently, such as using a cache memory, a random access memory associated with one or more physical processor cores, a time synchronization pulse, an encoded waveform, or any equivalent transient storage medium.

[0062] XNN can also be expanded and enriched by adding items such as taxonomic information, links to internal and external taxonomy, and bias detectors, and can also be seamlessly integrated with knowledge bases and rule systems, all of which are impossible with existing methods (which are all black-box methods). XNN can also form part of a causal logical induction system that can extract higher-order concepts and link them to a causal model, something that is completely impossible with a standard black-box neural network. XNN can link causal effects not only at the output layer, but also at its internal layers, thus giving the XNN architecture unique capabilities. These unique capabilities allow AI systems using XNN to achieve knowledge, understanding, and advanced reasoning capabilities beyond the scope of deep learning-based systems and machine learning techniques, which do not fully support the full range of first-order logical rules and assertions.

[0063] XNN outputs are typically provided as an interpretation in a general, human- and machine-readable format, as well as in the form of any additional information specific to the application being implemented. According to at least one exemplary embodiment, a method for encoding and transmitting knowledge, data, and rules (such as for an interpretable AI (XAI) system) can be shown and described. Data can be in a machine- and human-readable format suitable for transmission and processing via online and offline computing devices, edge and Internet of Things (IoT) devices, and through telecommunications networks. This method can result in a large number of rules and assertions that can have a localized trigger. Answers and interpretations can be processed and generated simultaneously. Interpretations can encompass both a direct model interpretation of the answer and an explanation / reasoning for how the interpretation itself was generated. Rules can be applied to domain-specific applications, such as transmitting and encoding rules, knowledge, and data for a medical diagnostic imaging scanner system to generate a diagnosis and an image and its interpretation. The resulting diagnosis can be further used by other AI systems in an automated pipeline while maintaining human readability and interpretability.

[0064] The representation format can be constructed from a system of disjunctive normal form (DNF) rules or other logical alternatives (such as conjunctive normal form (CNF) rules, first-order logic assertions, and the like). The representation format can also be directly implemented as a hardware circuit, which can be implemented using (i.) flexible architectures such as FPGAs; or (ii.) more static architectures such as ASICs or analog / digital electronics; or (iii.) neuromorphic architectures suitable for hardware implementations of connection mechanism models (such as XNNs); or (iv.) quantum computing hardware. When using flexible architectures that can be dynamically configured, representation transmission can be implemented entirely in hardware. Quantization and other compression techniques can be applied to XNNs for faster and more efficient execution.

[0065] A localization trigger can be defined by a localization method that determines which partition to activate. A partition is a region of data that may be disjoint or overlapping. Different partitions may be implemented on separate components or in the same component. It can be considered that if a partition is implemented on a separate component, the system only needs to activate that unit, and other components containing other partitions may not need to be activated or powered. A rule may be a linear or nonlinear equation consisting of coefficients having their own dimensions, and the result may represent both the answer to the problem and the explanatory coefficients, which can be used to generate a domain-specific explanation that is both machine- and human-readable. An exemplary embodiment applies a human-readable element to encoded knowledge, data, and rules that are otherwise too complex for ordinary people to reproduce or understand without any automation.

[0066] The explanation can be personalized, allowing control over the details and degree of personalization presented to the user. The explanation can also be further customized using a user model known to the system and can depend on a combination of factors such as the user's level of expertise, familiarity with the model's domain, current goals, plans and actions, current stage of work, the user and world model, and other relevant information that can be utilized in the personalization of the explanation. The explanation can be presented in various forms. For example, a human-understandable explanation can be presented audibly using a speaker. In another exemplary embodiment, the explanation can be visually presented by displaying it on a user's screen or device. The display can take any form, such as human-understandable text, machine-readable text, a heatmap, an image, or any other considered form.

[0067] Various methods for identifying rules may be implemented, such as using an XAI model inductive method, an interpretable neural network (XNN), an interpretable transducer transformer (XTT), or any other logically equivalent method that may exist or is yet to be invented.

[0068] Various devices can be used to provide user interaction, including (but not limited to) display devices, haptic feedback devices (such as visual, auditory, or haptic feedback), haptic devices, and any other output devices suitable for the application. User input can be received in any form, including (but not limited to) acoustic, voice, or haptic input, touch-sensitive devices, voice recognition devices, optical scanners, imaging devices, multi-dimensional scanners, LIDAR / RADAR, time-of-flight measurement devices, and other devices that can provide input to the hardware implementation.

[0069] XNN ensures that best practices are fully supported in interpreting encoding, transmission, and ultimately converting into a higher-order domain-specific interpretation that is human-readable or machine-readable. Various hierarchical partitioning techniques exist for XNN initialization, including hierarchical partitioning, slow clustering, agglomerated clustering, splitting clustering, relocation partitioning, probabilistic clustering, k-medoid method, k-means method, fuzzy clustering, density-based clustering, grid-based methods, gradient descent-based methods, evolutionary methods, region splitting, region growing, subspace clustering, projection methods, cooperative clustering methods, slow clustering methods, etc. The number of partitions typically depends on the overall complexity of the original predictor model or the underlying dataset; the more complex the dataset, the more partitions we usually generate. Multiple partitions can be connected using a "switch." The switch determines which partitions to activate using a binary value. The resulting switch is then multiplied by the linear output.

[0070] XNN can be designed to work with various nonlinear transformations, including (but not limited to) polynomial expansions, Fourier transforms, continuous data bucketing, causal operators, etc. Conditional features can also be applied. XNN can also intelligently merge and summarize partitions at multiple levels of detail, while also satisfying some scale and rotation invariance as much as possible. Having a possible matching of adjacent partitions in a multidimensional space (which more efficiently summarizes one or more partitions) will yield a more relevant summary that is likely to be better suited for interpretation.

[0071] Scale invariance can be considered by adjusting appropriate coefficients of the scale across multiple dimensions. Rotation invariance can be considered by having appropriate rotation coefficients that adjust the rotation across multiple dimensions. This is a powerful feature of XNNs, enabling nonlinear data to be interpreted in a way that is superior to simply using a linear approach. For example, if there are multiple partitions in an XNN model representing the boundary of a rotated ellipse, these partitions can be merged into a single representation of a rotated ellipse, thus providing an accurate but highly summarized representation of a potentially complex boundary that would be difficult to describe using linear fitting. The resulting summary interpretation is also more accurate than that achievable using linear fitting and follows the widely accepted principle that a shorter interpretation is better than a longer one, provided it is available.

[0072] Depending on the desired configuration, an exemplary embodiment may be embodied in various systems, apparatuses, methods, and / or objects. The embodiments described herein do not represent all possible embodiments and are merely examples consistent with the nature of the invention. Although several variations have been described in detail above, other modifications or additions are possible. Specifically, in addition to the described features and / or variations, further features and / or variations may be provided; for example, embodiments may relate to various combinations and sub-combinations of the disclosed features and / or combinations and sub-combinations of several further features.

[0073] Referring to Figure 1, Figure 1 illustrates a schematic diagram of an exemplary high-order XNN architecture. An input layer 100 may pass an input (possibly simultaneously) to both a conditional network 110 and a prediction network 120. The conditional network 110 may include a conditional layer 112, a summarizing layer 114, and a switch output layer (which outputs conditional values) 116. The prediction network 120 may include a feature generation and transformation layer 122, a fitting layer 124, and a prediction / value output layer 126. These layers may be analyzed by a selection and ranking layer 128, which may multiply the switch output by the value output to produce a ranking or score output 130. The XNN may simultaneously compute the explanation and the answer using the conditional network and the prediction network. The selection and ranking layer 128 ensures that the answer and explanation are correctly matched, appropriately ranked, and scored before being sent to the output 130.

[0074] The processing of conditional network 110 and prediction network 120 is considered to be in any order. Depending on the specific application of the XNN, it may be considered that some components of conditional network 110 (such as components 112, 114 and 116) may be selected or replaced with a common implementation. Depending on the specific application of the XNN, it may be considered that some components of prediction network 120 (such as components 122, 124 and 126) may be selected or replaced with a common implementation.

[0075] Further consideration may be made that, in some cases, the selection and ranking layers 128 and the output 130 can be combined into a single integrated component. For optimization purposes, the XNN can also be implemented using both the conditional network 110 and the prediction network 120, as well as all such components combined into a single network. This merging of the conditional and prediction networks can also be combined with a combined selection and ranking layer 128 and the output 130. This optimization will still result in a logically equivalent XNN that is faster for feedforward processing, but may be affected when training via backpropagation and gradient descent techniques is involved.

[0076] Therefore, XNN can be implemented such that there is a combination of input layer 100 and conditional network 110 and prediction network 120, including conditional layer 112, summarization layer 114, switching output layer 116, feature generation and transformation layer 122, fitting layer 124, prediction layer 126 and ranking layer 128, resulting in output 130. This combination can be applied to all embodiments and implementations of XNN, including both hardware and software implementations. XNN's variability in this respect is unique and unparalleled among other neural network implementations because the white-box nature of XNN allows for flexibility and extreme merging without affecting the logical behavior of XNN, but this affects various attributes of a practical implementation, such as size / space usage, performance, resource usage, trainability and total processing power.

[0077] The interpretability of an XNN circuit in the hardware allows for smarter circuit and hardware designs than a black-box model. Black-box models can waste significant hardware resources and circuitry. Because sub-parts of a black-box model's circuitry are not interpretable, optimization is typically impossible. Therefore, hardware circuitry can be optimized for an XNN in ways that a black-box ANN cannot achieve. For example, in an exemplary XNN circuit with repetitive or redundant parts, these parts can be implemented as a single circuit, which is then used along multiple execution paths. Since the precise function of the circuitry is known and understood in an XNN, this logic circuit merging and optimization decision can be made safely knowing that the overall behavior of the implemented XNN will be the same as that of the unoptimized original XNN. This kind of optimization is typically not possible with a black-box ANN, which would need to be implemented as a whole, even at the cost of a significant percentage of hardware resources, circuitry, and power wasted due to redundancy in the black box.

[0078] Another major benefit of XNNs and INNs implemented in a hardware environment is that interpretation can be used to trigger intelligent actions, which is impossible with black-box methods. This is useful in autonomous AI applications where every action, outcome, and failure occurring in the system may require full interpretability. Black-box neural networks deployed on edge hardware may require additional post-hoc comparison techniques to generate an interpretation. These methods may utilize some form of perturbation and / or offline analysis. Therefore, black-box methods may be completely unsuitable for real-time applications. In contrast to black-box implementations, hardware XNNs / INNs advantageously generate a prediction and an interpretation in a single feedforward pass, without relying on software or external interaction, but rather on an end-to-end hardware deployment.

[0079] One exemplary embodiment may implement an XNN in hardware. Implementations of the present subject may include (but are not limited to) methods consistent with the descriptions provided herein and articles comprising a tangible machine-readable medium operable to cause one or more machines (e.g., computers, FPGAs, hardware chips, etc.) to perform one or more of the described features. Similarly, hardware systems that may include one or more processors and one or more memories coupled to one or more processors are also described. Similarly, hardware systems having a direct implementation of an XNN in circuitry are also described, thus eliminating the need for processors and selected memory for storing weights.

[0080] If the XNN implementation does not need to be trainable, a static (hard-coded) implementation of the weights in the hardware is also possible, thereby removing the need for a processor and / or a memory in the conventional sense. A memory that may include a non-transitory computer-readable or machine-readable storage medium may contain, encode, store, or similarly process one or more programs that cause one or more processors to perform one or more operations described herein. Computer implementations consistent with one or more embodiments of the present subject may be implemented by one or more data processors residing in a single computing system or multiple computing systems. These multiple computing systems may be interconnected and may exchange data and / or commands or other instructions or the like via one or more connections, including (but not limited to) a connection through a network (e.g., the Internet, a wireless wide area network, a local area network, a wide area network, a wired network, or the like), or a direct connection between one or more of the multiple computing systems.

[0081] In addition to one of the known implementations of XNN on general-purpose computing hardware, hardware-only or primary hardware XNN can be implemented using various hardware implementation methods, including (but not limited to): flexible computing architectures, such as FPGA; ASIC; analog electronics; analog-digital electronics; conventional discrete electronic components, transistors, etc.; spintronics; and neuromorphic chips.

[0082] Other possible hardware implementations and embodiments of XNNs may be considered, including currently available hardware such as surface-mount chip architectures, optical computing architectures, memristors, and quantum computing components. The principles summarized herein are fully applicable to hardware XNN implementations on such architectures.

[0083] One exemplary embodiment may implement a hybrid solution involving a combination of technologies with one of the known general-purpose processing hardware, such as a standard CPU, a graphics processing unit (GPU), and a tensor processing unit (TPU). It can be considered that the choice of a particular hardware implementation may be guided by the specific application to which the hardware XNN will be deployed.

[0084] Certain parts of the XNN (such as the switching network) can be designed to be implemented efficiently directly in hardware, thus achieving a significant improvement in speed and performance. When implemented in hardware, an exemplary embodiment can be represented using different numerical precisions because the coefficients and interpretations can generally be implemented without loss of accuracy. Furthermore, when implemented in hardware, an exemplary embodiment can achieve significant power and cost savings without adversely affecting performance.

[0085] The XNN is designed to be robust relative to quantization errors that can be introduced in hardware implementations, which are due to limitations in the processing power of the hardware itself (e.g., when there are fewer available bits than the original logical XNN equivalent, precision loss is forced), low-fidelity errors that can be introduced in analog-to-digital conversion and / or sampling of sensory or other inputs, floating-point implementations, or any other source that reduces the high-fidelity representation of various XNN weights to a low-fidelity representation in the hardware. The separation of the conditional network 110 and the prediction network 120 shown in the exemplary embodiments illustrated in Figures 1, 4, 5, and 6 can significantly reduce the overall error and other related precision losses attributable to quantization.

[0086] For certain applications, such as classification, the accuracy of the results can remain completely unaffected, allowing for much faster and / or cheaper implementations using lower-specification floating-point representations in the hardware (e.g., using 16-bit, 8-bit, or even 4-bit floating-point representations). The white-box nature of XNNs uniquely allows quantization methods to be applied together with reweighting methods that utilize information about the components within the XNN. Experimental data from early quantized XNN implementations have indicated superior speedups with minimal loss of accuracy while preserving interpretability.

[0087] Flexible computing architectures such as FPGAs allow for on-the-fly or specially programmed reconfiguration of hardware, providing advantages similar to giving a software implementation on a general-purpose computing architecture the full performance and power benefits of a custom hardware circuit.

[0088] Flexible computing architectures or reconfigurable computing can be used to implement XNNs and all XNN variants in a relatively straightforward manner. XNNs can be initially generated using a hardware-appropriate description language (such as VHDL, an IEEE 1164-compatible description, or a similar language description), and then output directly from the description to flexible computing hardware. Flexible computing architectures offer the advantage of allowing subsequent changes to XNNs to be made and reimplemented multiple times. Flexible computing architectures also provide significantly higher performance per watt than a general-purpose computing architecture, thus allowing a typical embodiment to process significantly larger amounts of data with less power. Flexible computing architectures also allow XNNs to be easily trained using gradient descent methods (such as backpropagation).

[0089] The flexible computing architecture also allows advanced XNN methods (such as dynamic architecture adaptation using genetic algorithms (GA) and Monte Carlo simulation methods (MCSM) or related techniques and alternatives) to be fully implemented in hardware. An exemplary embodiment may implement a network adaptation algorithm on a portion of the flexible computing architecture or using a separate interconnected flexible computing architecture, and then dynamically reprogram the original XNN.

[0090] Additional unused connections, neurons, and layers can be added and activated and dynamically changed as a result of the XNN adaptation algorithm.

[0091] The flexible computing architecture can also be used to implement different XNN variants simultaneously on the same hardware or on a system with interconnected FPGAs, for example, having a hardware XNN optimized for training and a sparse XNN optimized for processing power. This will allow FPGA-based systems to generate, train, and optimize hardware XNNs during their operation without multiple restarts, while achieving high performance during runtime nominal operation.

[0092] XNNs can also be implemented in hardware using fixed-resource models, which allows them to run ideally on real-time operating systems (RTOS) and robot operating systems (ROS). Dedicated XNN acceleration hardware or XNN processing units (XPUs) can be used in practical implementations to accelerate part or all of an XNN. In one exemplary embodiment, an XPU can be used to accelerate the prediction network or conditional network, or both, of an XNN. Further consideration is that inductive procedure acceleration hardware or inductive processing units (IPUs) can be used in practical implementations to accelerate inductive procedures for converting black-box AI predictor models into white-box interpretable models, including direct conversion to an XNN. In one exemplary embodiment, an IPU can be used to accelerate hierarchical partitioning discovery, merging and splitting, and faster generation of appropriate rules, linear and nonlinear model fitting, and other appropriate parts or all of the inductive procedure. Further consideration is that an interpretable processing unit (EPU) can be used to accelerate the generation and output processing steps involved in generating an interpretation in a generic interpretation format. In one exemplary embodiment, an EPU can be used to accelerate the generation of a hierarchical structured interpretation output, to more quickly link to an ontology structure, and to more quickly link to a reverse indexing mechanism for tables, text, and image data.

[0093] In a dense XNN, the coefficients can be zero, resulting in more nodes and connections. Since zero-valued coefficients are still connections, the result is a dense network, meaning the number of possible links has been maximized. On the other hand, in a sparse XNN, zero-valued coefficients can be eliminated, leading to a more compact network. Therefore, a dense set of equations used as the basis of a sparse XNN (where zero-valued coefficients are eliminated and the set of equations has all non-zero elements) can produce a sparse network, such as the exemplary embodiment in Figure 5, because the number of possible links is less than its possible number. Conversely, using a sparse set of equations where most elements are zero can produce a dense network where connections between all units are maintained, as shown in the exemplary dense XNN architecture illustrated in Figure 6.

[0094] Referring now to exemplary Figure 5, Figure 5 illustrates an exemplary sparse XNN architecture. A sparse XNN may include a conditional network 110 and a prediction network 120, which may include transformed features 500, derived rules 306, and a value output layer 308.

[0095] A prediction network 120 in a sparse XNN can apply a dot product between input 500 and weights 304. The result is equivalent to solving a linear function, such as: This is equivalent to an illustrative dot product:

[0096] This dot product can be represented by the prediction / value network 120. In a neural network, the intercept of a linear equation can be represented using a separate bias vector. Both dense and sparse XNNs support rule refinement through incremental learning using gradient descent methods (such as backpropagation). Although a sparse network architecture may be more complex, it is ideal for low memory footprint, low-power hardware and edge handling, zero-value coefficient pruning rules, or prevention of overfitting of zero-value coefficients. Furthermore, sparse XNNs can employ efficient processing techniques and are ideal for both large and small datasets.

[0097] The exemplary XNN architecture in Figure 5 is logically equivalent to the following set of equations:

[0098] In an exemplary dense XNN, each neuron in a layer is fully connected to all neurons in the previous layer. Referring now to exemplary Figure 6, Figure 6 illustrates an exemplary dense XNN architecture. A dense XNN may contain the same components as a sparse XNN, such as a prediction network 120 and a conditional network 110. However, the prediction network 120 in a dense XNN differs from the prediction network 120 in a sparse XNN in that nodes in one layer are fully connected to nodes in another layer, even if the connection is via zero-valued weights or coefficients as represented by a set of rules. For example, the rule output values ​​in rule 306 obtained by transforming the nodes in feature layer 500 to connect to the next layer.

[0099] The difference between a sparse XNN and a dense XNN can be seen in the way the dot product is calculated. For example, in a dense XNN, although the illustrative diagram shows two separate steps 306 and 308 for visual purposes, they can actually be performed as a single step. In these illustrative steps 306 / 308, matrix multiplication is performed between the weight / coefficient matrix and the vector / matrix of the input / transformed value 500. The intercept of the equation can also be represented as a separate bias vector. An illustrative matrix multiplication of the coefficient matrix and the transformed value can be:

[0100] Alternatively, in a sparse XNN, the dot product can be split into multiple dot products and combined into a single layer. Each rule is computed individually using a separate dot product. For example:

[0101] Finally, the prediction network of the sparse XNN concatenates the output vectors into a vector 308 [R0,R1,R2,R3], so that matrix multiplication can be applied to the switch output in step 700.

[0102] Like a sparse XNN, a dense XNN can still support rule refinement through incremental learning using gradient descent methods (such as backpropagation). However, the network architecture of a dense XNN is easier to construct compared to a sparse XNN. Dense XNNs are ideal for high-power hardware, rules with non-zero coefficients, and for implementing or analyzing high-dimensional data. Dense XNNs are efficient for GPU processing and ideal for both small and large datasets. Sparse XNNs can be used to constrain training using regularization, while dense XNNs can be used for service prediction and interpretation.

[0103] The example dense XNN shown in Figure 6 is logically equivalent to the following set of equations:

[0104] After zeroing out unused features, a dense network is logically equivalent to a sparse network. Therefore, to transform a sparse XNN into a dense XNN, additional features can be added, which are multiplied by the coefficient weights of 0. Alternatively, to transform from a dense XNN to a sparse XNN, features with coefficient weights of 0 are removed from the equation.

[0105] For example, the dense XNN in Figure 6 is logically equivalent to the following system of equations:

[0106] It can be simplified to:

[0107] Logical equivalence applies to feedforward propagation. Once a network is converted into a dense XNN and trained on it, the zero-value weights (i.e., coefficients) can be updated via backpropagation.

[0108] Referring now to illustrative Figure 2, Figure 2 illustrates a comparison of a dense XNN and a sparse XNN implementing the same model. The use of one or the other depends on the use case. For example, a sparse XNN can be used during training to restrict certain coefficients from becoming non-zero, which allows for the maintenance of a simpler model that has already been regularized or compressed. Once training or refinement is applied, the sparse XNN can be converted into a dense XNN, which is fully connected to have a simpler network for serving prediction and interpretation, resulting in faster execution time. Sparse network construction and execution can be slightly more complex but use less memory, making them suitable for applications where memory and space are major concerns. These space, time, and performance tradeoffs can initially be used to select the best type of XNN for a specific application. It is recommended to conduct additional testing on different variants on a case-by-case basis to determine the optimal architecture, as XNN variants can be optimized for ease of training, loading time, memory and space utilization, execution speed, etc.

[0109] An exemplary embodiment may be implemented as an ASIC or similar static circuit by directly converting a general XNN into a circuit or by first applying a transformation of the desired XNN (such as a dense or sparse transformation) to the XNN and then converting the transformed XNN into a circuit.

[0110] The general procedure for converting a neural network into a known ASIC circuit is well known, because XNNs follow standard ANN implementation schemes. No additional dedicated circuitry is required to implement XNNs as ASICs and related circuitry. Possible practical implementations involve generating a VHDL or similar language description for the XNN and then converting it into an ASIC circuit.

[0111] An ASIC-implemented XNN can utilize unique XNN triggering capabilities that can be used for real-time or near-real-time control of other hardware or software systems. An exemplary embodiment can implement a suitable control bus or channel and the appropriate handling of control and triggering signals within the resulting system.

[0112] ASICs and related static implementations can potentially offer significant speed and performance advantages to hardware XNNs. Due to the fixed nature of these implementations, certain techniques applicable to XNNs (such as dynamic network adaptation and optimization) cannot be fully utilized in them. A certain form of flexibility can be achieved by making sufficient dynamic or external memory available, which allows for additional redundancy and capacity within the hardware XNN to allow for a degree of network adaptation, and may also allow for a degree of training if weights are implemented dynamically rather than statically hard-coded within the circuit.

[0113] When it comes to instructions derived from human knowledge injection (HKI) that are guaranteed to always be static and immutable, which are practically impossible to change for the AI ​​system, the static nature of an ASIC implementation has a clear advantage. This can be an advantage for systems that need to be secure in their operation or as part of a simpler, stand-alone, fail-safe system that monitors a more complex system to ensure compliance with safety, ethical, trustworthiness parameters, and other important considerations that may need to be imposed and hard-coded within the AI ​​system, without sacrificing the overall adaptability and learning of that system.

[0114] For example, one of the hardware XNNs may be an ASIC deployed in a security and ethical watchdog chip or kill switch system, which can quickly process the current state of an autonomous system and can quickly initiate an emergency failsafe state if it detects or predicts potential harm to humans.

[0115] Analog electronics or a hybrid of analog and digital electronics can be used to implement hardware XNN in a manner similar to an ASIC implementation. Analog electronics can implement hardware such as a sensor input, resulting in novel sensors that combine intelligent processing and interpretation in a single package without a central processing unit or similar circuitry.

[0116] One exemplary distributed approach to hardware XNN deployment can lead to significant advantages in an edge computing or IoT deployment environment. For example, in robotics and industrial applications, this implementation can achieve even greater power savings and higher efficiency than ASICs or other implementations.

[0117] One exemplary embodiment may be a fully analog implementation of an XNN. The analog approach can replace the activation function in the neuron, and neuron activation can be represented as analog voltages, spikes, or similar techniques. One exemplary embodiment may use a combination of analog and digital electronics to transform analog real-world input into a format suitable for further digital processing. The flexibility of XNNs makes them ideal for certain applications, such as fast, low-power digital signal processing of analog sensor data. One exemplary embodiment may extract meaning from the signal and pass relevant portions of the data, along with a digital interpretation, to more complex processing in the pipeline.

[0118] A typical embodiment can implement a known discrete component. Such implementations can be useful for smaller XNNs. The advantages and disadvantages of this implementation are similar for ASICs and related implementations. For example, cost and robustness considerations can make this type of implementation attractive when high-power systems are involved or when a simple XNN is required for basic control or safety monitoring.

[0119] The sparse XNN transform is well-suited for this exemplary implementation and can be used to rapidly prototype and test different designs on actual hardware before proceeding to more expensive ASIC or FPGA implementations. One potential use of this type of implementation is to quickly test the underlying hardware characteristics of circuits that may not be easily simulated in software.

[0120] Another exemplary embodiment may implement a spintronic device. Spintronic devices interweave memory and computing components, resulting in a potentially more efficient hardware implementation because many transfers of memory values, weights, etc. (if present) are not required during operation.

[0121] If the spintronic XNN implementation is reprogrammable, it may have characteristics similar to an FPGA implementation. Non-reprogrammable spintronic devices may have characteristics similar to ASICs.

[0122] By converting all the different layers and neurons in an XNN into a single spintronic circuit, XNNs can be implemented efficiently using spintronic devices. Spintronic implementations of predictive XNNs and related predictive variants are particularly efficient in practice due to the combined availability of memory and processing within a single spintronic circuit. Faster data access and the elimination or reduction of computationally expensive data transfer requests via data buses significantly improve the performance of XNNs and all their variants. In the case of predictive XNN variants, the amount of input data as a stream or series rather than just a single snapshot can be much larger, thus multiplying and amplifying the performance gain.

[0123] Neuromorphic chips also intertwine memory and processing in a manner similar to spintronic devices. Since XNNs can be implemented directly in hardware, they can be efficiently implemented on neuromorphic chips. Hardware XNNs running on neuromorphic chips can be highly efficient while retaining all the advantages and flexibility of a general-purpose computing architecture. Practical implementations of hardware XNNs on neuromorphic chips do not require significant changes to an XNN deployed on a standard CPU / GPU combination.

[0124] Further, one XNN implementation on a neuromorphic chip could employ spike neurons instead of the more common activation function-based neurons. Spike neurons in an XNN implementation could significantly increase power efficiency and processing power, thereby making some practical applications that would otherwise be infeasible using non-spiky neurons feasible.

[0125] Compared to black-box ANNs and other black-box systems, a major advantage of using white-box XNNs is their interpretability, which provides implementations for intelligent transformation methods that optimize the XNN architecture for a specific deployment while preserving the logical structure and functionality of the underlying model. When it comes to XNNs, there are different implementation options, including the ability to optimize for trainability, speed, and performance, which is particularly important in a primary or hardware-only implementation. Sparse, dense, and micro-XNN variants also have significant implications for hardware implementations of XNNs.

[0126] Although a sparse network architecture may be more complex, it is ideal for low memory footprint, low power hardware, edge processing, zero-value coefficient pruning rules, and prevention of overfitting of zero-value coefficients. Furthermore, sparse XNNs can utilize efficient CPU processing techniques and are ideal for both large and small datasets. In an exemplary embodiment for medical imaging, an XNN can be used to classify and interpret an X-ray image or an MRI scan.

[0127] Dense and sparse XNNs can be applied to different stages of the model lifecycle. In one exemplary embodiment, an XAI model can be converted into an XNN after initial model generalization. It may then be necessary to convert the XAI model into a sparse XNN to refine the model in a global manner. Figure 5 illustrates a typical sparse XNN architecture that can be implemented directly in hardware. Figure 6 illustrates a typical dense XNN architecture that can be implemented directly in hardware.

[0128] Sparse XNNs enable XNNs to utilize regularization and compression already incorporated into the XAI model. Once the model is sufficiently trained, the sparse XNN model is converted into a dense XNN model for deployment in a production environment where it can be useful, thereby requiring a simpler architecture to allow for faster classification and interpretation by the server. It should also be noted that in this embodiment, sparse and dense XNNs can provide different levels of accuracy. In this exemplary embodiment, hardware resources may be sacrificed as needed to increase model performance (accuracy). These trade-offs can be applied on a case-by-case basis. In one exemplary embodiment, a dense XNN may be implemented as part of a large-scale MRI scanner, while a sparse XNN may be implemented as part of a smaller, portable device.

[0129] Micro XNNs employ a technique similar to a sparse network but are divided into multiple micro-networks. These micro-networks are XNN equivalents of modules in traditional software engineering, allowing neural networks to be structured according to best practice modular design. Micro XNNs can operate in feedforward propagation and may not support rule refinement via gradient descent methods (such as backpropagation). Therefore, micro XNNs may be best suited for deployment in production-type environments or conversion to fixed hardware circuits, such as ASICs, neuromorphic chips, or analog / digital circuits. Micro XNNs can be used for server prediction and interpretation. One or more micro XNNs can be implemented in low memory footprint, low-power hardware, and edge processing. A micro XNN can handle high-dimensional data and handle fast anomaly prediction and interpretation. Backpropagation and related techniques can still be used in conjunction with micro XNNs. This is achieved by using a simple transformation step from micro XNN to one of other XNN variants (such as sparse XNN or dense XNN), running the backpropagation procedure, and then converting back to the micro XNN format without any loss of information.

[0130] Further to an exemplary medical imaging embodiment, an alternative deployment on a low-power handheld device may be required. In this exemplary use case, a miniature XNN may be suitable because it may require fewer hardware resources to process classification and interpretation.

[0131] The choice of XNN transformation used in hardware XNN implementation schemes depends on the application domain and hardware, resources, performance and other engineering constraints.

[0132] Referring now to illustrative Figure 2, Figure 2 illustrates a comparison of one dense XNN 210 and one sparse XNN 220 implementing the same rule-based model. The use of one or the other depends on the use case. For example, during training, a sparse XNN 220 can be used to restrict certain coefficients from becoming non-zero, which allows for the maintenance of a simpler model that has already been regularized or compressed. Once training or refinement is applied, the sparse XNN 220 can be converted into a dense XNN 210, which is fully connected to have a simpler network for serving prediction and interpretation, resulting in faster execution time. Sparse network construction and execution can be slightly more complex but use less memory, making them suitable for applications where memory and space are major concerns. These space and time and performance tradeoffs can initially be used to select the best type of XNN for a particular application. It is recommended to conduct additional tests on different variants on a case-by-case basis to determine the optimal architecture, because XNN variants can be optimized for ease of training, loading time, memory and space utilization, execution speed, etc.

[0133] In an exemplary embodiment for medical imaging, an XNN can be used to classify and interpret an X-ray image or an MRI scan. Dense and sparse XNNs can be applied at different stages of the model lifecycle. Converting an XAI model to an XNN after initial model generalization may be suitable for this particular use case. It may then be necessary to convert the XAI model to a sparse XNN to refine the model in a global manner. Sparse XNNs can utilize regularization and compression already incorporated into the XAI model. Once the model is sufficiently trained, it may be useful, depending on the application, to convert the sparse XNN model to a dense XNN model (e.g., in a production environment), where a simpler architecture is needed to serve fast classification and interpretation (e.g., a dense XNN may be best suited for an implementation with GPU hardware, as mentioned above). It should also be noted that in this embodiment, a sparse XNN and a dense XNN can provide different levels of accuracy. In this scenario, hardware resources may be sacrificed as needed to increase model performance (accuracy). These trade-offs can be applied on a case-by-case basis. In one exemplary embodiment, a dense XNN may be implemented as part of a large-scale MRI scanner, while a sparse XNN may be implemented as part of a smaller portable device.

[0134] Miniature XNNs are best suited for deployment in production-type environments or for conversion into fixed hardware circuits, such as ASICs, neuromorphic chips, or analog / digital circuits. Miniature XNNs can be used for servo prediction and interpretation. One or more miniature XNNs can be implemented in low memory footprint, low-power hardware, and edge processing. A miniature XNN can handle high-dimensional data and fast anomaly prediction and interpretation. Backpropagation and related techniques can still be used in conjunction with miniature XNNs. This is achieved by using a simple transformation step from a miniature XNN to one of other XNN variants (such as sparse XNNs or dense XNNs), running a backpropagation procedure, and then converting back to the miniature XNN format without any loss of information.

[0135] Further to an exemplary medical imaging embodiment, an alternative deployment can be provided on a low-power handheld device. In this exemplary use case, a miniature XNN may be suitable because it may require fewer low-hardware resources to process classification and interpretation.

[0136] Referring now to the exemplary embodiment in FIG3, FIG3 illustrates four exemplary value micronetworks 300. An XNN network can combine one or more micronetworks, wherein the feedforward pass is decomposed into smaller parts. Taking the prediction network illustrated in FIG3 as an example, once a prediction network is evaluated, the results of the switch output layers S0 to S3 can determine which value network to execute. Separate micronetworks can be used for the value network.

[0137] For example, if S0 is triggered, it is used for the value network triggering of rule R0; if S1 is triggered, it is used for the value network triggering of rule R1; if S2 is triggered, it is used for the value network triggering of rule R2; and if S3 is triggered, it is used for the value network triggering of rule R3.

[0138] Referring to the exemplary embodiment in Figure 4, Figure 4 illustrates a flowchart of an exemplary combination of micro-XNN architectures for forming a micro neural network. The conditional network 110 can be its own micro-XNN and can interface with separate value network micro-XNNs 300. This allows best practices in software engineering to be reflected in the XNN design. Due to the white-box nature of XNNs, this precise and functional modularization is only possible in XNNs. Each micro-network 300 can be implemented on separate hardware. For example, the hardware can be a low-power chip. The conditional network 110 can also be implemented on separate hardware. The main difference between an XNN and a set of micro-XNNs is that the subnetworks in the set of micro neural networks are constructed such that they can operate independently by a complete data flow transformation (such as a polynomial) with input-to-output prediction. The data flow path followed by the micro neural network (starting from a specific input and ending with an appropriate output prediction) describes the initiation path of that specific input and output combination. The initiation path for multiple input and output combinations can always be decomposed into a set of initiation paths, with each single input and output combination having its own initiation path. For a deterministic micro-neural network, each input and output combination always has a unique initiation path. For a non-deterministic micro-neural network, such as an XNN with overlapping partitions, each input and output combination may have one or more initiation paths, requiring some form of ranking, probability, or other prioritization of the initiation path branches.

[0139] In one exemplary embodiment, the switch output layer 116 is also initialized by the same external procedure defining the XNN and is typically implemented as the same procedure for initializing the aggregation layer 114, but it can be considered that such procedures may be independent (if necessary). All values ​​in the connection weights between neurons can be updated using standard neural network training techniques. XNN provides a further novel approach to updating the connections themselves using machine learning methods (such as genetic algorithms, Monte Carlo simulations, particle swarm optimization (PSO), multi-objective optimization (MOO), simulated annealing, reinforcement learning, etc.) or via causal logic models.

[0140] XNN can be hardware implemented and realized on various types of hardware architectures. Figure 8 illustrates an exemplary embodiment using a hardware architecture that does not require immediate external input or other forms of sensory input (also known as a sensorless hardware architecture). Figure 9 illustrates an exemplary embodiment using a hardware architecture that provides immediate environmental input or other forms of sensory input (also known as a sensor-based or sensor-equipped hardware architecture). It should be noted that in both Figures 8 and 9, the feedback controller 870 is shown as part of either the main hardware system 802 or the output system 803, because it can be interpreted and implemented differently using either an internal feedback system or an external feedback system (such as an electromechanical controller), or potentially both types (in which case the feedback controller 870 can potentially be implemented as multiple controllers) for interpretation and implementation. An exemplary XNN implementation can be implemented as illustrated in Figures 8 or 9.

[0141] Figure 8 illustrates an exemplary sensorless hardware system 802 and an optional output module 803. The sensorless hardware implementation 802 may include a component 810 in the form of internal circuitry, a clock, a data table, etc., which controls the program and provides internal parameters to the XNN input layer 100. The XNN implementation 830 includes three main parts: a conditional network 110, a prediction network 120, and a ranking layer 128. The XNN 830 outputs an answer and explanation, as illustrated by the XNN output component 130. The XNN output 130 may be connected to any combination of output methods 803, as appropriate. Output method 803 may include any combination of the following: hardware supporting non-real-time output, such as memory-based output, packet network transmission, etc., as illustrated in components 850 and 851; hardware supporting real-time or near-real-time output and / or control signals, such as displays, actuators, repeaters, hardwired dedicated networks, and fly-by-wire systems, as illustrated in components 860 and 861; and hardware supporting feedback 870, which may be considered as an output form, such as components 850 or 860. Feedback 870 may further take the form of closed loop, open loop, feedforward feedback, etc. Feedback may be connected to XNN input layer 100 to complete the feedback loop.

[0142] The exemplary embodiment in Figure 9 may illustrate a selection of a non-sensor input 800, a selection of a sensor input 801, a primary sensor-based or sensor-equipped hardware system 804, and a selection of an output method 803. It should be noted that for sensor-based hardware, at least one of component 800 or 801 needs to be implemented (otherwise, the implementation would fall into the sensorless category as depicted in Figure 8). Non-sensor data 800 may originate from external storage, network communication, repeaters, or external bus data, etc. Sensor data 801 may typically originate from local sensors, which may typically be hardwired to a local bus, converter, or repeater, or transmit sensor data to some other method in the sensor-equipped hardware system 804. The sensor-based hardware implementation 804 then includes a component 810, in the form of internal circuitry, a clock, a datasheet, etc., which assists in the control program and provides internal parameters to the XNN input layer 100. For implementations with sensor hardware, component 810 may be optional because the implementation can uniquely rely on input data from components 800 and / or 801. XNN implementation 830 includes three main parts: a conditional network 110, a prediction network 120, and a ranking layer 128. XNN 830 outputs an answer and explanation, as illustrated by XNN output component 130. XNN output 130 may be connected to any combination of output methods 803, as appropriate. Output methods 803 may include one of the following combinations: hardware supporting non-real-time output, such as memory-based output, packet network transmission, etc., as illustrated in components 850 and 851; hardware supporting real-time or near-real-time output and / or control signals, such as displays, actuators, repeaters, hardwired dedicated networks, and fly-by-wire flight control systems, as illustrated in components 860 and 861; and hardware supporting feedback 870, which may be considered as an output form, such as in components 850 or 860. Feedback 870 can be further implemented in the form of closed loop, open loop, feedforward feedback, etc. Feedback can be connected to the XNN input layer 100 to complete the feedback loop. In sensor-based hardware, the feedback loop can be completed by connecting component 870 back to 810 (or even 800, depending on the implementation) instead of directly connecting it to the XNN input layer 100.

[0143] Figures 8 and 9 illustrate illustrative embodiments and do not cover all possible embodiments. All combinations of different types of hardware architectures and features can also be considered, including (but not limited to) combinations of some or all of sensorless hardware 802 and sensor-equipped hardware 804 and components 800, 801, 803, 850, 851, 860, 861, and 870, as well as any other practical embodiment options. The XNN embodiment 830 itself may have components 100, 110, 120, and 130 combined or incorporated in any combination in a practical hardware embodiment. Other further combinations of hardware components are considered possible, for example, by implementing components 810 and 100 using the same hardware components.

[0144] In the case of sensorless hardware, it is considered that one possible embodiment of an XNN system with one output option can actually be achieved using a combination of mechanical methods, existing mechanical devices for tasks or applications, and / or by using elapsed time to determine the appropriate state space or other input information required for the correct operation of this sensorless system in the case of using an internal clock. For example, the embodiment illustrated in Figure 8 may have an internal timer and a table that is scheduled to move according to a time offset as component 810.

[0145] "An Exploration of Sensorless Manipulation" (Erdmann and Mason, 1988) presents an exploration of how such sensorless implementations (or a combination of sensored and sensorless systems) can be used to achieve practical solutions for various applications requiring hardware and / or control systems. For example, the theoretical industrial pallet manipulation example of orienting objects in a sensorless manner, as given by Erdmann and Mason, can be implemented in practice by training an XNN to perform the desired manipulation and embedding it into a controller system, ultimately using a modern neural network. In Erdmann and Mason's example, an XNN solution can be built using a sensorless implementation (such as the sensorless implementation illustrated in Figure 8), where the real-time output 860 controls the actuator 861 without any need for components 850, 851, or 870.

[0146] XNN can also automatically provide an additional advantage that was previously impossible. In addition to performing manipulations, the system can explain why specific angles and durations of each manipulation are performed. Furthermore, the system can interface with some form of visualization system or other form of operational awareness system that allows the operator to understand the behavior of the system. XNN also provides the advantages of predictability and interpretability. The simulation of the entire XNN behavioral state can ensure a guarantee of a safe and reliable operating mode or a better understanding of at least some form of the risks involved, which can be crucial in setting up examples such as object and pallet manipulation, where an error could cause an object to fall outside its intended position and potentially injure bystanders. The identification and interpretation of such errors and potential unsafe conditions can then be corrected in the XNN or additional measures can be taken to mitigate or eliminate this risk.

[0147] Hardware-based XNN implementations also allow modern AI systems to achieve a higher Evaluation Assurance Level (EAL) within the ISO / IEC 15408 standard and in the context of the Common Standard Identification Configuration (CCRA). Due to the black-box nature of modern deep learning AI, most systems based on such black-box methods cannot achieve an EAL rating higher than EAL1 and may be almost unacceptable for EAL2. XNN's white-box and fully understandable and predictable behavior allows for direct certification at EAL1 to EAL4 levels. XNN combined with white-box behavioral models also allows for higher and more difficult-to-achieve certification at EAL5 to EAL7 levels, which are the highest levels of verification and testing achievable within globally accepted practical quality assurance frameworks. Therefore, XNN-based AI system implementations allow users to obtain a higher level of confidence in one of the key safety features of a reliable implementation system by meeting specific assurance requirements. Typically, the functional characteristics of each certified product or system are established in a safety target document tailored for EAL assessment. Therefore, a system's compliance with a specific security application depends on how well the features listed in the appropriate security objectives meet the actual security requirements of the application. For example, white-box systems like XNNs can use semi-formal and formal methods for analysis and prediction, which is beyond the scope of black-box systems. This inherent EAL-related benefit of XNNs allows XNN-based hardware AI devices to achieve successful EAL assessments that would otherwise be impossible. EAL-related benefits also apply to other similar contexts, such as US FIPS 140-2, UK CESG Auxiliary Product Scheme (CAPS), ISO / IEC 27001 standards, and other applicable national and international standards and treaties.

[0148] In one exemplary embodiment, XNN-based hardware incorporating event-driven sensors and / or supporting some form of AI filter or operation at a hardware sensor level can leverage the white-box nature of XNNs to improve the quality and performance of the implemented system. For example, an XNN can be used to process event-driven multidimensional data streams in an incremental manner (which in these embodiments may be segmented by time and / or events), thereby supporting feedforward processing and simultaneous updating of both based on XNN-interpreted inverse indexing capabilities, without having to process an entire input data frame. In a further example, an XNN can be used to directly utilize pre-processed or partially processed input data and correctly perform a combination of fusion, routing, transformation, dimensionality reduction, and / or flattening operations, thereby leveraging the white-box nature of XNNs to do so correctly and efficiently.

[0149] Upon further consideration, a hardware XNN implementation can also be used to implement the termination output caused by the HKI procedure. In some cases, such as security boundaries, ethical applications, and security applications, incorporating such human-provided rules and information can prove beneficial. A security processor, secure cryptographic processor, hardware security module, trusted platform module, or suitable hardware device can be used in this implementation. An exemplary application would be in a factory or warehouse utilizing autonomous robots that adapt to changing environments, where humans have access to such robots. Security parameters loaded into the robot's behavioral model and linked to the interpretable system controlling the robot can be encoded in a secure hardware environment to provide a tamper-proof element, since tampering in this application could lead to potentially unsafe situations for humans interacting with such robots.

[0150] One exemplary embodiment implements the HKI method and technology within a neuromorphic hardware architecture. Interpretable models such as XNNs become understandable by presenting a white-box model, which can then be presented to humans in the form of rules and / or workflows. This surface representation can be edited and then seamlessly reverted back to the neural connectivity mechanism format required by the neuromorphic hardware. This exemplary embodiment provides a practical solution for editing, adding, and deleting relevant information, and thus altering the behavior of neuromorphic devices in a controlled, reliable, and reproducible manner.

[0151] One exemplary embodiment may use a quantum processing system to implement an XNN. It is considered that implementing an interpretable model on a quantum processing system would have rules similar to those of a classical interpretable model, with the addition of quantum-specific extensions. For example, this extension may allow the correct interpretation of the specification of quantum annealing effects and the like. In another instance, an extension may allow the correct interpretation of multiple qubit states, qubit ground states, mixed states, subsidiary bits, and other related quantum effects attributable to entangled states and / or decoherence. In yet another instance, an extension may allow the introduction of quantum logic-specific operators and / or hardware logic gates within an XNN, such as quantum CNOT, CSWAP, XX, YY, ZZ gates, Pauli gates, Hadamard gates, Toffoli gates, and other related quantum logic operations that can be combined in series or parallel.

[0152] One exemplary embodiment uses the HKI method and technology within an interpretation and interpretation generation system (EIGS) to enable seamless bidirectional collaboration within an EIGS-based system.

[0153] In one exemplary embodiment, XNN can also be used as the basis for a practical data privacy-preserving AI system implementation. Data privacy can be intentionally or unintentionally violated by AI systems in several scenarios: (i.) personal data from the training dataset is eventually incorporated into the AI ​​model; (ii.) personal data can be re-extracted or regenerated by repeatedly analyzing model answers; (iii.) personal data of certain uniquely identifiable groups can eventually have a higher identification risk; (iv.) model inversion and membership inference techniques, which can associate model data with unique keys or signatures; (v.) other information sources (such as public data sources) can be combined with private information to regenerate or otherwise identify private information. The main data privacy protection solutions for AI can be classified into four categories: (i.) differential privacy; (ii.) secure multi-party computation; (iii.) federated learning; and (iv.) homomorphic encryption. XNN implements practical implementations under all four categories.

[0154] In privacy protection solutions (i.) differential privacy, noise or other suitable obfuscation methods are introduced into the training data to generate a controlled amount of privacy through a noise factor or ratio in the AI ​​model. XNN, with its selective deletion and editing capabilities, can selectively add this noise according to a data privacy model. The data owner has the added advantage of controlling the level of noise added to the model, making it a superior solution that can be achieved through a black box. An audit trail function of an XNN can also be used to detect an anti-obfuscation attack and deliberately generate noisy information to defend against this attack to prevent the identification of privacy information by repeatedly querying the same data column. More specifically, the audit trail may contain or correspond to an identifier of a uniquely designated audit trail. The audit trail with an associated unique code may be stored internally or externally or may be stored in a storable manner. For example, the audit trail may be stored in a recording system or a BLT / blockchain type system.

[0155] In the privacy protection solution (ii.), Secure Multi-Party Computation (SMPC) is used to obtain a correct answer while hiding some information about the data, but simultaneously computes the answer using data from many sources. XNN can extend the SMPC protocol to cover interpretation generation beyond the answer output. Common protocols used for SMPC implementations (such as the SPDZ protocol) typically allow operations such as combinations of addition and multiplication between two secret shared numbers. XNNs utilizing a polynomial basis of the fitting layer and having a hierarchical partitioning function that can be described by a sequence of addition and multiplication are ideal for SMPC implementations. In addition, due to the white-box nature of XNNs, XNNs can be formally analyzed and tested for security and trust building purposes without revealing any secrets. A secure enclave can also be used to decrypt data in a protected space within the hardware processor, thereby limiting the possibility of other parts of the system accessing this data in plaintext. An end-to-end hardware implementation of an XNN with a secure enclave will be quite resilient to most forms of data attacks.

[0156] In privacy-preserving solutions (iii.) such as federated learning, an AI model is jointly trained across various distributed devices that only maintain local data samples. These local data samples are not shared with other devices, thus limiting but not completely eliminating the privacy risks involved. XNN is ideally suited for a distributed or federated implementation and can be implemented directly, for example, in IoT or edge computing applications where communication options are limited or constrained by network topology, such as in a mesh network.

[0157] In privacy-preserving solutions (iv.) such as homomorphic encryption or homomorphic operations, protocols such as CKKS or other protocols such as BGV, BFV, or FHEW are used to allow operations on encrypted data without decryption and, where appropriate, the use of an encrypted AI model. Homomorphic encryption is widely applicable to applications where data privacy is paramount and the use of this privacy data is often complex due to regulations, the importance of the data, and security concerns. Homomorphic encryption is also important for applications where the AI ​​model itself and its learning information may need to remain encrypted and protected by the data user or owner. Most homomorphic encryption schemes are based on ring algebra structures, which allow addition-like and multiplication-like operations to be performed while acknowledging neutral elements in the two operations, such as natural integers. Homomorphic operations typically use an integer polynomial expression to encrypt information and can perform operations on the encrypted polynomial. In one exemplary embodiment, data may be homomorphically encrypted, and depending on the specific application, the XNN model itself may also be homomorphically encrypted. In an exemplary embodiment using homomorphically encrypted data and a homomorphically encrypted XNN, a private key and a public key are generated using CKKS. The public key is used for encryption and can be shared, while the private key is used for decryption and must be kept secret, for example, in a secure hardware-defined address space or similar implementation solution. CKKS and many other homomorphic encryption schemes are based on the principle of the fault-tolerant learning (LWE) problem, in which noisy pairs of data tuples are distinguished from truly random data tuples, where the noise is typically provided via the public key. The fault-tolerant learning on rings (RLWE) problem is a variant of LWE on algebraic rings. RLWE requires much smaller keys and sufficiently fast computation to allow for practical implementation. Problems often arise when multiplying encrypted data, which is a common operation in the prediction network 120 and conditional network 110 of an encrypted XNN. Essentially, the size of the encrypted data increases with each multiplication step, making simple RLWE schemes impractical in practice. One practical solution to this problem is to use a relinearization technique and a publicly available evaluation key, applied immediately after each multiplication of the encrypted data. A further problem is that after relinearization, the noise level increases with the number of multiplications required. A technique known as rescaling is used to manage the total noise allowed in each multiplication step or layer within a neural network. For a practical implementation, the number of multiplications to be performed needs to be known in advance, as this will affect the degree of the polynomial used for encryption. XNNs, as wide neural networks (WNNs) rather than deep neural networks (DNNs), have an inherent advantage in this homomorphic encryption application. Therefore, the number of multiplications required in an XNN is significantly lower than in a typical neural network. Furthermore, precise prior knowledge of the exact function and importance of each neuron and connection in an XNN allows for selective homomorphic encryption of the XNN weights on the model.In one exemplary embodiment where only homomorphic encryption is applied to the data, further optimization is possible in practice, thereby giving white-box XNNs an inherent advantage for such applications. XNNs can also be easily integrated with homomorphic operation libraries, including (but not limited to) HEAAN, SEAL, HElib, and PALISADE libraries. The choice and type of functions within XNNs also allow for more efficient implementation for such privacy-preserving applications, for example, by further minimizing the number of multiplications that must be performed by utilizing reasonably low-order linear polynomial transformations where possible. XNNs also have the additional advantage of being able to construct an encrypted interpretation based on the encrypted answer, which can then be securely decoded in the recipient's secure environment. The application of homomorphic operations and hardware-based secure XNN implementations presents a practical way to utilize highly secure AI models in environments and applications involving highly sensitive data and / or models without establishing numerous trusts (if any) among the involved parties.

[0158] The following are several exemplary embodiments of hardware XNN, which can be regarded as different variations of XNN implemented in hardware.

[0159] The CNN-XNN allows for seamless integration of cyclotron layers with XNNs to process multidimensional data, including images, 3D data, and other signal processing suitable for cyclotron feature recognition, transformation, and extraction. Exemplary hardware implementations and applications of CNN-XNNs may include computer vision systems, autonomous vehicles and devices, robots, manufacturing devices, and industrial automation systems. Figure 7 illustrates a high-level architecture of CNN-XNN. In the exemplary embodiment in Figure 7, a general XNN architecture 106 (illustrated in Figure 1) receives input from one or more cyclotron layers 104. The raw input is given to an input layer 102, which then passes the data to a cyclotron layer 104, where the input is cyclotronized. The result of the cyclotron layer may be a list of features recognized from the input. The remainder of the general XNN architecture may operate identically to that described in Figure 1.

[0160] The capsule XNN (CAP-XNN) protects hierarchical information captured by a CNN-XNN during the spin step. An exemplary hardware implementation and application of CAP-XNN is similar to that of CNN-XNN.

[0161] Text XNN (T-XNN) is a variant of XNN that can handle text processing and text data, including syntactic and semantic information. T-XNN can incorporate technologies such as word2vec and end-to-end processing for text feature engineering. Exemplary hardware implementations and applications of T-XNN may include dedicated database query accelerator hardware, information retrieval devices, dedicated text indexing and processing hardware, smartphones, and any hardware that needs to process text.

[0162] Speech XNN (S-XNN) is an extension of XNN for speech recognition and generation, which adds an interpretation to speech recognition by inserting an XNN or alternatively using an inductive model as part of the speech recognition solution. Exemplary hardware implementations and applications of S-XNN may include computer audio systems, smart microphones and audio recording / capture systems, and applications requiring speech-to-text or voice-based control systems, such as in aviation or other applications, where a human operator has high-level multitasking needs or needs to operate without removing their hands from vehicle or machine controls.

[0163] Dialogue and Conversation XNN (QA-XNN) and XNN combine to automate conversation, dialogue, and question-and-answer (Q&A) systems. Given a specific question, there is an explanation that can account for the neural network's output answer and why that answer was specified. Exemplary hardware implementations and applications of QA-XNN may include edge-deployed chatbots and robots, interactive devices, and accelerator hardware that accelerates QA and interaction tasks between humans and machines.

[0164] Predictive and recursive XNNs (PR-XNNs) add a time or sequence element to the input and output. These XNNs can match an input sequence and identify its trends, while simultaneously outputting and predicting possible outputs and interpretations of each possible output. These XNNs can utilize recursion in the interpretation and modularize the interpretation by referencing itself. Specific types of predictive architectures will lead to, for example, different variants of PR-XNNs, and Long Short-Term Memory (LSTM) PR-XNNs or Gated Recursive Unit (GRU) PR-XNNs. Exemplary hardware implementations and applications of PR-XNNs may include digital signal processing (DSP) systems, advanced mechanical control systems using interpretation as part of feedback and error control loops, and general control engineering. Hardware PR-XNN can be deployed in a variety of advanced machines and systems that require real-time or near-real-time prediction of edge or difficult environments, such as space, underwater or underground systems, or systems that must operate with little or no communication with the outside world or face significant delays in transmission, such as marine systems or space exploration systems, such as AI robots that can be deployed on the Moon, Mars, asteroids and other celestial bodies.

[0165] PR-XNN adds contextual location information to the conditional and prediction networks of an XNN. Depending on the specific application and implementation, this contextual location information may also form part of the output if needed. Contextual location information can also be added to matching answer and explanation pairs, as it may be necessary to accurately distinguish the PR-XNN output as part of a sequence of outputs rather than a single output.

[0166] It is considered that PR-XNNs typically have some form of recurrence relation in the prediction network, and to a lesser extent, may also require recurrence relations in the conditional network. Recurrence relations are learned from the original predictor model during the PR-XNN initialization step. For example, if the original predictor model is an LSTM network, the recurrence relation can reflect the LSTM behavior as part of the underlying explanation given by the PR-XNN.

[0167] Consideration may be made to a practical implementation that would completely replace the original model. Therefore, in an exemplary case, the LSTM model could be implemented as part of the prediction network of a PR-XNN; or alternatively, the original predictor could be placed before or after the input layer of an XNN. When the original predictor is placed before the input layer of an XNN, the resulting PR-XNN will treat the output of the original predictor as a sequence of input features, just as any other black-box predictor model is generalized to a white-box XNN. When the original predictor model is placed after the input layer of an XNN, the resulting PR-XNN will have additional data that ensures any explanatory coefficients are passed through the predictor model. For example, if an LSTM is placed between the input layer and the conditional and prediction network of an XNN, or if an LSTM is incorporated as part of the prediction network of an XNN, the LSTM model needs to be passed through the explanatory coefficients to ensure that the resulting PR-XNN remains a white-box model. This approach innovatively allows a PR-XNN to remain a white box, even if one of its predicted elements is effectively a black box or a gray box containing both white box and black box elements.

[0168] PR-XNN can also incorporate an LSTM or similar model after its output layer, allowing the LSTM to learn to predict the explanation itself. It can be considered that similar models, such as RNNs, transformers, Bayesian networks, Markov models, and other suitable models, can be used instead of an LSTM. This combination of LSTM or other similar models with PR-XNN can lead to efficient new systems that not only generate an explanation from a single data item and / or an ordered or unordered sequence of data items, but also predict possible explanations. This capability of PR-XNN makes it particularly suitable for industrial applications that require anticipating the consequences before actually executing planned actions.

[0169] For example, in industrial robot manufacturing applications involving a robotic arm, the predictive interpretation of a set of movement commands can be used to determine whether such movement commands will result in an unsafe condition for any human operator, living object, or inanimate equipment in the vicinity of the robotic arm. Therefore, PR-XNN can create a new set of capabilities in industrial, commercial, and non-commercial applications that allow safety to be part of the control loop of automated machinery, devices, and systems.

[0170] Another example of the practical implementation and advantages of a PR-XNN is the anticipation of the behavior and subsequent consequences of an autonomous vehicle, including (but not limited to) autonomous air, land, sea, underwater, and indoor and outdoor vehicles. Using a PR-XNN (e.g., an autonomous driverless car), it can determine that one of its anticipated future interpretations contains a reference to the potential collision of a child or adult by the driverless car. When the safety control system in the driverless car detects this anticipated reference, it can take an appropriate safety-related action, such as switching the car to a safer driving mode, slowing down, or activating a higher-resolution sensor to better address the potential future event before it actually occurs. PR-XNN allows practical systems to operate automated machinery safely based on the anticipation and prediction of consequences. The ability to ensure the safe operation of machinery and robots (especially machinery and robots that interact with humans) is a major unresolved issue that PR-XNN can largely address.

[0171] Video XNN (V-XNN) is a combination of CNN-XNN and PR-XNN, using a sequence of images (frames) to predict, anticipate, and interpret what might happen in future frames. Video XNN is not limited to 2D video. A 3D data stream processed by CNN-XNN will enable the XNN to process and interpret 3D data. Exemplary hardware implementations and applications of V-XNN may include stereo vision systems, LiDAR, RADAR, SONAR, and any other application that needs to know its environment and anticipate and interpret its past, present, and future states.

[0172] An exemplary application of V-XNN will be in medical devices that perform continuous scanning of a patient, such as during the operation of an X-ray fluoroscopy device involving continuous scanning of a patient with X-rays during a surgeon's procedure. In this situation, V-XNN can provide the surgeon with near-real-time feedback on any diagnosis and its interpretation, which is particularly important in time-sensitive situations (such as a surgical procedure). Another exemplary application of V-XNN is during troubleshooting of industrial machinery, where continuous scanning is performed and anomalies need to be detected. Subsequent intervention and troubleshooting steps will force the system to adapt its answers and interpretations to the new situation, where the resulting interpretation makes V-XNN a more suitable solution than other solutions that do not provide an interpretation.

[0173] It can be considered that V-XNN can be combined with other XNN variants (such as a QA-XNN) to implement interactive solutions that require situational awareness of interventions and actions affecting the physical world, enabling the system to adapt to changing circumstances while maintaining its ability to explain itself. Combining this system with PR-XNN also, to some extent, endows it with the ability to anticipate the future, thus giving it further useful capabilities beyond the scope of current black-box neural network-based systems.

[0174] Interpretable Generative Adversarial Networks (XGANs) extend the architectural concept of XNNs to Generative Adversarial Networks (GANs). Exemplary hardware implementations and applications of XGANs can include rapid image generation systems, advanced manufacturing and customization systems, and rapid object generation and customization systems. For example, a CNC manufacturing system with XGAN capabilities can allow a factory to produce customized construction materials for a specific order with unique patterns or customized for a particular style, without the need for costly human design for each manufacturing batch.

[0175] Explainable reinforcement learning using XNNs can utilize XNNs as part of a reinforcement learning (RL) training method, incorporating explanations into the action planning and world model components of an RL system. The explanations themselves are used as part of a cost and reward function, leading to explainable reinforcement learning (XRL). Exemplary hardware implementations and applications of XRL can include advanced autonomous robots and autonomous devices that intelligently adapt to their environments while maintaining the ability to explain their actions. Hardware XRL can also lead to advanced safety solutions that ensure the safe operation of autonomous systems that can interact with humans in potentially hazardous spaces, such as in a manufacturing scenario where a robot is handling equipment that could potentially harm a human, provided that the robot unintentionally moves close to a human or performs an operation predicted to cause harm, such as cutting through a pillar supporting a platform while someone is still on the platform. This XRL system will be able to accurately detect and predict future situations that could lead to harm to a human and therefore stop or modify its operational steps to avoid and prevent such harm in the first place. If a solution cannot be implemented automatically, the XRL system will be able to explain to the human operator why they took certain evasive actions.

[0176] Interpretable autoencoders (XAEs) and autodecoders (XADs) extend the XNN architecture concept to autoencoders and autodecoders, thereby enabling the generation, processing, and incorporation of interpretation in encoding and / or decoding processes. Exemplary hardware implementations and applications of XAEs and XADs may include telecommunications and networking devices as well as network security devices that may need to process large amounts of data, which requires hardware implementations.

[0177] Causal XNN (C-XNN) extends XNN to integrate with causal logic models, thereby giving causal power to explanations. Indicative hardware implementations and applications of C-XNN may include onboard controllers, which can make rapid decisions in situations where they are completely offline and require rapid consideration of a large number of alternatives to select the best next action.

[0178] All the above variations of hardware XNN remain compatible with the general XNN architecture, meaning that they can be combined and matched in various ways as part of a larger and more complex XNN deployment involving both software and hardware, as well as a combination of hybrid XNNs. For example, a hardware C-XNN can be combined with a hardware CNN-XNN or a hardware V-XNN to provide a causal in-situ explanation of an autonomous vehicle, while a data center-based C-XNN can then be used to provide higher-order and more complex explanations than those that can be generated at the edge.

[0179] Some XNN variants, such as PR-XNN, are also able to output an ordered sequence of triggers and / or suggested actions, making them highly suitable for target / plan / action systems, robotic systems, RL systems, etc., especially when implemented only in hardware for deployment in edge and offline contexts.

[0180] XNNs can also be used alone or in combination with other XNNs and XNN variants to utilize the resulting answer and its (some) interpretations as a suggested action or a trigger for one of a set of actions in an overall goal / plan / action system. Hardware XNN action triggers using a variety of possible components (including but not limited to electrical, optical, mechanical repeaters, switches, bus systems, control networks, network devices, and hardwired transmitters) can be used in a variety of industrial and home applications. This feature of hardware XNNs makes it practical and easy to integrate them into larger deployments and hardware or hybrid software-hardware systems. In such deployments, XNNs can provide significant control inputs or add specific desired behaviors to the entire system.

[0181] In one embodiment of the present invention, there is a computer implementation method for adapting an interpretable neural network (XNN) to perform operations on one or more hardware types. The method further includes: receiving the XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of the one or more hardware types; transforming the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted into a logically equivalent architecture during the transformation; using the transformed XNN to perform operations on inputs received by the at least one hardware type; and outputting the operations based on satisfying one or more evaluation guarantee criteria.

[0182] In another embodiment of the present invention, there is an apparatus for deploying an interpretable neural network (XNN), the apparatus comprising: one or more processors, or the like including a graphics processor, the one or more processors: receiving the XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of the one or more hardware types; transforming the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted into a logically equivalent architecture during the transformation; using the transformed XNN operation to receive input from the at least one hardware type; and outputting the operation based on satisfying one or more evaluation guarantee criteria.

[0183] In another embodiment of the invention, there is a non-transitory computer-readable medium comprising instructions that, when executed, cause hardware to at least: receive an XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of one or more hardware types; transform the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted into a logically equivalent architecture during the transformation; operate using the transformed XNN on input received by the at least one hardware type; and output the operation based on satisfying one or more evaluation guarantee criteria.

[0184] In another embodiment of the present invention is a system for a hardware-implemented, interpretable, and explainable artificial neural network, the system comprising: an input layer configured to receive an input and identify one or more input features; a conditional network comprising: a conditional layer configured to model the input features based on one or more partitions, wherein each of the one or more partitions includes a rule; a summarizing layer configured to summarize one or more rules into one or more summarized partitions; and a switch output layer configured to selectively aggregate the summarized partitions from the summarizing layer and the one or more partitions from the conditional layer; and a prediction network comprising a feature generation and transformation network, the feature generation and transformation network comprising a feature generation and transformation network configured to convert one or more rules into a predictive value. The input features are applied to one or more transform neurons; a fitting layer configured to combine features generated by the features and transformed by the transform network to identify one or more coefficients associated with at least one of the following: one or more features and one or more partitions; a value output layer configured to analyze the one or more coefficients and configured to output a value associated with at least one of the one or more features or the one or more partitions; and an output layer configured to generate an output that can be interpreted and explained by a machine program or a human; wherein at least one layer is implemented in a hardware circuit; wherein each of the one or more partitions forms at least one local model and one of the local models is combined to form a global model; and wherein one or more execution paths through the partitions can be identified by an external program.

[0185] As an option, the received XNN includes: an input layer configured to receive inputs to the interpretable neural network; a conditional network configured to receive the inputs from the input layer, wherein the conditional network is adapted to divide the inputs into a plurality of partitions based on a set of rules; the conditional network further includes at least one of: a conditional layer configured to receive the input partitions from the input layer, wherein each of the plurality of partitions corresponds to at least one rule of the set of rules; a summarizing layer configured to combine the outputs of the plurality of partitions and present them as conditional values; and a switch output layer configured to output the conditional values ​​as a result of summarizing from the plurality of partitions; a prediction network configured to receive the inputs from the input layer, wherein the prediction network is adapted to fit at least one model associated with the plurality of partitions, such that one combination of the at least one model forms a generation associated with the plurality of partitions. The predictive network further includes at least one of the following: a feature generation and transformation layer configured to apply one or more transformations to the inputs received from the input layer, wherein the feature generation and transformation layer generates a set of variables based on the inputs; a fitting layer configured to locally model the inputs based on the set of variables generated from the feature generation and transformation layer, wherein the fitting layer estimates coefficients corresponding to each variable or a combination thereof associated with the inputs; a value output layer that outputs a set of predicted outputs based on the coefficients estimated from the fitting layer; a ranking layer configured to receive a combined output from the conditional network and the predictive network, wherein the combined output is computed by multiplying a conditional value from the switch output layer with the set of predicted outputs from the value output layer to ensure that the predictions and interpretations match correctly; and an output layer configured to receive the combined outputs for providing the predictions and interpretations.

[0186] As an option, the logically equivalent architecture provides a white-box machine learning model with functionality similar to the transformed XNN. As an option, the logically equivalent architecture includes: an interpretable artificial intelligence (XAI) model, an interpretable neural network (INN), an interpretable transducer transformer (XTT), an interpretable spike network (XSN), an interpretable memory network (XMN), and reinforcement learning (RL) applications, wherein these are compatible with interpretable reinforcement learning (XRL), and wherein the transformed XNN is interchangeably applied with XAI models, XTT, XSN, XMN, and XRL. As an option, the transformed XNN is configured to form an interpretable neural network (INN) that is a superset of the transformed XNN and the interpretable transducer transformer. Entity constraints are associated with limitations of a hardware type, including attributes associated with the size / space usage, performance, resource usage, trainability, processing power, and physical location of the hardware type. As an option, the logically equivalent architecture exhibits a planar structure exhibiting the logically equivalent behavior of an untransformed XNN, wherein the planar structure includes planar grouping that parallelizes the hierarchical grouping of the untransformed XNN. As an option, the transformed XNN is configured as a wide neural network of a hardware type. As an option, an algebraic operation is pre-determined to pass through the wide neural network. As an option, the one or more hardware types are associated with circuit types, including: digital electronic circuits, analog circuits or digital-analog hybrids, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) computer hardware, neuromorphic circuits, quantum computing hardware, firmware, quantum computing units, and / or combinations thereof. As an option, the transformed XNN is adapted to an ASIC circuit by being converted to a hardware description language used with the ASIC circuit. As an option, the one or more hardware types include at least one processor configured to implement the received XNN, wherein the at least one processor includes a central processing unit, a graphics processing unit, a singleton processing unit, or a combination of two or more different processing units; or the received XNN is encoded onto a hardware type without a known processor using one or more numerical precision representations / the received XNN is encoded using a hardware type without a known processor. As an option, the at least one hardware type is associated with or is part of a security and ethics monitoring chip or a cut-off switch system. As an option, the at least one hardware type is associated with or is part of a real-time operating system and / or a robotic operating system, and is one or more acceleration hardware components, wherein the acceleration hardware includes at least one of: an interpretable processing unit, an inductive processing unit, and an acceleration unit. As an option, the one or more evaluation assurance criteria include evaluation assurance levels related to common standard identification configurations.As an option, the transformed XNN is configured to protect data privacy associated with an input of a hardware type. As an option, the method further includes: using differential data privacy, secure multi-party computation, joint learning, and homomorphic encryption to protect the integrity of data traversing the transformed XNN to ensure data privacy associated with the output computation. As an option, selectively deleting, modifying, and / or adding noise to the data traversing the transformed XNN based on a data privacy model. As an option, the method further includes: providing an audit trail associated with the output computation, wherein the audit trail corresponds to an identifier that can be stored via a system; detecting a deobfuscation attack and generating noise in response to the deobfuscation attack; and / or preventing the identification of data traversing the transformed XNN associated with the audit trail by applying the generated noise to the data. As an option, the method further includes: applying one or more security protocols based on a hardware type to traversing the data of the transformed XNN, wherein the one or more security-based protocols are configured to encrypt and / or decrypt the data, thereby preventing potential attacks on the data. As an option, the method further includes: encrypting the data traversing the transformed XNN in a homography manner when the data is processed by the transformed XNN to prevent subsequent decryption. As an option, the method further includes: encrypting the transformed XNN based on a hardware type; and applying relinearization and / or rescaling to the encrypted XNN. As an option, the method further includes: the output computation includes interpretation and prediction based on hardware type encryption. As an option, the transformed XNN is configured to process multidimensional data, wherein the multidimensional data includes tabular data, text data, video data, audio data, 3D data, volumetric data, discrete data, continuous data, question-and-answer format data, and time or sequence data. As an option, the transformed XNN is configured to protect hierarchical information. As an option, the transformed XNN includes one or more nodes and associated connections with zero-value coefficients adaptively adjusted between a dense network and a sparse network, wherein the dense network and the sparse network include micronetworks representing the dense network or the sparse network. As an option, the transformed XNN is a sparse network implementation on a portable device or a fixed device. As an option, the transformed XNN includes one or more micronetworks associated with partitions of the XNN, wherein the one or more micronetworks are configured based on a hardware type. As an option, the transformed XNN includes one or more nodes and connections with zero-value coefficients adaptively adjusted between a dense network and a sparse network. As an option, the output computation is used to predict the behavior and consequences of autonomous machinery.As an option, the transformed XNN is a type of reductive neural network, adversarial neural network, wide neural network, network applying reinforcement learning, autoencoder network, autodecoder network, causal network, interpretable network, transducer network, spike network, memory network, distributed network, or a combination thereof. Alternatively, the transformed XNN is configured to adapt to a hardware type where a wide neural network cannot be efficiently used for computation. As an option, the at least one hardware type is an electrical hardware, an acceleration hardware, an optical computing hardware, a mechanical repeater, a switch, a bus system, a control network, a low-power chip, a surface-mount chip, a network device, a hardwired transmitter, a memristor, and a quantum computing component, or one or more circuits, wherein the one or more circuits include digital electronic circuits, analog circuits or digital-analog hybrid circuits, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), neuromorphic circuits, quantum computing hardware, and firmware. As an option, the at least one hardware type is geographically located away from the XNN and adapted to one or more network connectivity systems to receive the XNN for deployment. As an option, the at least one hardware type is locally connected via a network connectivity system, including: a Bluetooth system, a local Ethernet network. As an option, the method further includes: embedding an action trigger on the at least one hardware type, such that the output operation is used as the action trigger for real-time processing without pausing the transformed XNN. As an option, the output operation is used as a signal to initiate an action trigger in a hardware type. As an option, the transformed XNN is configured to execute or co-execute on a sensor-equipped hardware type or a sensorless hardware type. As an option, the transformed XNN is configured to perform optimization and prediction using linear and nonlinear optimization methods, including: Fourier series, Multidimensional Betz curves, recursive relations, and causal operators. As an option, the transformed XNN is partitioned into overlapping and / or non-overlapping partitions based on a hardware type, wherein a hierarchical clustering method is used to partition the transformed XNN, such hierarchical clustering methods include: agglomerative clustering, splitting clustering, relocation partitioning, probabilistic clustering, k-medoid method, k-means method, fuzzy clustering, density-based clustering, grid-based method, gradient descent-based method, evolutionary method, region splitting, region growing, subspace clustering, projection method, cooperative clustering method, and slow clustering method.As an option, the transformed XNN is externally partitioned and optimized during or before the transformation, wherein the transformed XNN is optimized using local and global optimization methods, including gradient-based methods, simulation-based methods, and causal logical induction methods. As an option, the method further includes enriching the transformed XNN with taxonomic information, information about links to internal and external taxonomics, and bias detector information, wherein the enriched information is related to a hardware type embedded in the transformed XNN. As an option, the transformed XNN forms part of a causal local system, wherein the transformed XNN is configured to extract higher-order data and the correlations between that data for output to a causal model. As an option, the transformed XNN is externally partitioned and optimized during the transformation. As an option, the transformed XNN is partitioned into overlapping and / or non-overlapping partitions based on a hardware type. As an option, the transformed XNN supports disjunctive and conjunctive paradigm encoding, wherein the supported encoding is suitable for implementation on static, flexible, neuromorphic, and quantum computing architectures. As an option, the transformed XNN supports rotation and scale invariance, nonlinear functions, and summarization of multiple partitions across multiple dimensions. As an option, the transformed XNN is configured to reduce the error rate associated with an implementation for a particular hardware type. As an option, the XNN is transformed to adapt to a hardware type by at least one of the following: Fourier transform, integer transform, real transform, complex transform, quaternion transform, octonion transform, Walsh function, state-space transform, phase-space transform, Haar and non-Haar wavelets, generalized L2 function, fractal-based transform, Hadamard transform, fuzzy logic, knowledge graph networks, classification encoding, discriminant analysis, normalization, standardization, multidimensional Bezier curves, recursive relations, and causal operators. As an option, the XNN is transformed using a fixed resource model associated with one or more systems, including a real-time operating system and a robotic operating system. As an option, the output computation is in a general interpretation format, human-readable text, machine-readable text, a heatmap, a graphical representation, or an audio format, which may be human-readable, machine-readable, or both. As an option, the output computation further includes application-specific information implemented on a particular hardware type. As an option, the output computation is personalized to control the level of detail based on one or more user models, wherein the one or more user models are configured based on a user's user expertise, familiarity with the model domain, the user's current goals, plans, and actions.As an option, the method further includes: providing user input from one or more sources in a suitable format to the at least one type of hardware, wherein the one or more sources include a haptic feedback device, a tactile device, a touch-sensitive device, a voice recognition device, an optical scanner, an imaging device, a multidimensional scanner, a LiDAR / RADAR system, and a time-of-flight measurement device. As an option, the switch output layer is configured to identify and select partitioned inputs for use as conditional value outputs. As an option, the fitting layer estimates coefficients corresponding to variables in the generated set or combinations of variables associated with the inputs and at least one partition of the plurality of partitions. As an option, the prediction network further includes: at least one transformation layer configured to transform the inputs before and / or after the inputs are received by the fitting layer. As an option, the conditional network further includes: at least one transformation layer configured to transform the inputs before and after the inputs are received by the conditional layer. As an option, the at least one transformation layer includes transformations adapted to be applied simultaneously linearly, nonlinearly, or both to one or more of the inputs. As an option, the one or more transformations include a transformation function pipeline. As an option, when neurons associated with one or more partitions in the conditional network are activated, the ranking layer selects from the plurality of partitions for subsequent activation. As an option, the conditional network and the prediction network are simultaneously configured to receive the inputs from the input layer simultaneously. As an option, at least one of the plurality of partitions overlaps with a second partition of one of the plurality of partitions, and the interpretable neural network further includes a feedforward step traversing multiple paths, and calculating a probability or ranking score for each of the multiple paths.

[0187] As an additional option, at least one of the conditional network and the prediction network is implemented as a wide neural network. As an additional option, each of the conditional network and the prediction network is implemented on one or more separate hardware circuits. As an additional option, one or more of the input layer, the conditional layer, the aggregation layer, the switching output layer, the feature generation and transformation network, the fitting layer, the value output layer, and the output layer are each implemented separately on separate devices that communicate with each other. As an additional option, one or more rules or one or more coefficients of the fitting layer are identified by a human user, wherein the identified rules or coefficients are directly hard-coded into the hardware circuit and cannot be changed by the neural network. As an additional option, the hardware system is one or more of digital electronic circuits, analog circuits, a digital-analog hybrid, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), neuromorphic circuits, optical circuits, optical-electronic hybrids, and quantum computing hardware. As an additional option, the system further includes a processor configured to receive an input and to generate an output, wherein the input is from one or more sensors, and wherein the output is human- or machine-readable. As an additional option, one or more of the rules and one or more of the coefficients are implemented directly in the hardware, wherein the directly implemented rules and coefficients cannot be changed by software. As an additional option, a plurality of identical redundant functions are identified, wherein the identical redundant functions are implemented on a single circuit, and wherein the neural network is configured to activate the single circuit when the identical redundant functions are executed. As an additional option, a plurality of zero-value coefficients are identified, wherein the identified zero-value coefficients are not implemented on the hardware circuit. As an additional option, the output further includes an explanation and a reason. As an additional option, the output layer further generates an output signal, wherein the output signal includes a set of instructions for performing an action. As an additional option, the hardware circuitry is one or more of a neuromorphic chip, a spintronic device, a memristor, a spike neuron, or quantum computing hardware. As an additional option, each partition is interpretable and decipherable, such that each local model formed by the partitions is interpretable and decipherable, and the global model formed by the combination of local models is interpretable and decipherable, wherein an interpretation is formed using the output in a single feedforward step.As an additional option, the feature generation and transformation layer is configured to apply at least one of a linear transformation and a nonlinear transformation, wherein such transformation functions include one or more of the following: polynomial expansion, rotation, dimension scaling, dimensionless scaling, Fourier transform, integer / real / complex / quaternion / octon transformation, Walsh function, state-space transformation, phase-space transformation, Haar and non-Haar wavelets, generalized L2 function, fractal-based transformation, Hadamard transform, type 1 fuzzy logic, type 2 fuzzy logic, modality transformation, probability transformation, quantum / qubit transformation, knowledge graph network, classification coding, difference analysis, normalization, standardization, scaling, multidimensional Betz curve, recursive relation, causal operator, gradient descent-based transformation, and a subset of interpretable neural network. As an additional option, the transformation layer is further configured to perform multiple transformations in a transformation pipeline, wherein the transformation pipeline is configured to perform transformations that analyze one or more time-ordered data sequences based on the values ​​of one or more variables. As an additional option, the system is further configured to form partitions based on the input by comparing features from the input with a set of localization values ​​and conditions, wherein an internal and / or external program is used to identify the localization values ​​and conditions. As an additional option, the hardware circuitry is configured to operate without a processor or sensor. As an additional option, the hardware circuitry is generated by describing the rules of the neural network using a Very High Speed ​​Integrated Circuit Programming Language (VHSIC) hardware description language (VHDL) and converting the VHDL description into an Application Specific Integrated Circuit (ASIC). As an additional option, the hardware circuitry further includes one or more hard-coded security rules, wherein these hard-coded security rules cannot be changed by software and wherein these hard-coded security rules are configured to perform an action based on a detected future hazard. As an additional option, the action includes shutting down the system. As an additional option, the neural network is configured to achieve an Evaluation Assurance Level (EAL) of EAL5 or higher. As an additional option, at least one of the layers is implemented as a miniature neural network. As an additional option, a cryptographic layer is further included, wherein the cryptographic layer is configured to encrypt at least one of the inputs, the partitions, the rules, and the output according to a homomorphic encryption protocol. As an additional option, the cryptographic layer is configured to relinearize the encrypted data. As an additional option, the encrypted data is rescaled based on a predetermined maximum allowable amount of total noise. As an additional option, the output layer is configured to produce an encrypted output and an encrypted decryption, wherein the encrypted output and the encrypted decryption are configured to be decrypted in a secure environment for a receiver.

[0188] As will be understood by those skilled in the art, the selected features described in this application can be appropriately combined and can be combined with any form or embodiment of the present invention.

[0189] The foregoing description and accompanying drawings illustrate the principles, preferred embodiments, and modes of operation of the present invention. However, the present invention should not be construed as limited to the specific embodiments discussed above. Those skilled in the art will recognize additional variations of the embodiments discussed above (e.g., features associated with certain configurations of the present invention may alternatively be associated with any other configuration of the present invention as needed).

[0190] Therefore, the embodiments described above should be considered illustrative rather than restrictive. It should be understood that variations can be made to these embodiments by those skilled in the art without departing from the scope of the invention as defined by the following claims. The advantages of the embodiments of the invention will become apparent from the following detailed description of exemplary embodiments of the invention, which should be considered in conjunction with the accompanying drawings, wherein like element symbols indicate like elements, wherein: [Simplified Explanation of the Diagram]

[0192] Figure 1 is an illustrative embodiment of a schematic diagram of a general XNN architecture.

[0193] Figure 2 is an illustrative example of a schematic diagram of a relatively dense and sparse XNN.

[0194] Figure 3 is an illustrative schematic diagram of one of the miniature XNN prediction networks.

[0195] Figure 4 shows an example of a combined version of one of the micro XNN subnetworks.

[0196] Figure 5 shows an exemplary embodiment of one of the sparse XNN architectures.

[0197] Figure 6 shows an exemplary embodiment of one of the dense XNN architectures.

[0198] Figure 7 shows one of the higher-order architectures of CNN-XNN architecture.

[0199] Figure 8 shows an exemplary embodiment of an XNN using a sensorless hardware implementation with various output options.

[0200] Figure 9 shows an exemplary embodiment of an XNN using one of the sensor hardware with various output options.

Claims

1. A computer implementation method for adapting an interpretable neural network (XNN) to perform operations on one or more hardware types, the method further comprising: Receive the XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of the one or more hardware types; transform the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted into a logically equivalent architecture during the transformation; use the transformed XNN operation to receive input from the at least one hardware type; and output the operation based on satisfying one or more evaluation guarantee criteria.

2. The method of request item 1, wherein the received XNN includes: An input layer, configured to receive inputs to the interpretable neural network; A conditional network configured to receive inputs from an input layer, wherein the conditional network is adapted to divide the inputs into a plurality of partitions based on a set of rules; the conditional network further includes at least one of the following: a conditional layer configured to receive the input partitions from the input layer, wherein each of the plurality of partitions corresponds to at least one rule of the set of rules; a summarizing layer configured to combine the outputs of the plurality of partitions and present them as conditional values; and a switch output layer configured to output the conditional values ​​as a result of summarizing from the plurality of partitions; a prediction network configured to receive the inputs from the input layer, wherein the prediction network is adapted to fit at least one model associated with the plurality of partitions, such that one of the at least one models is combined to form a representative global model associated with the plurality of partitions; the prediction network further includes at least one of the following The system comprises: a feature generation and transformation layer configured to apply one or more transformations to the inputs received from the input layer, wherein the feature generation and transformation layer generates a set of variables based on the inputs; a fitting layer configured to locally model the inputs based on the set of variables generated from the feature generation and transformation layer, wherein the fitting layer estimates coefficients corresponding to each variable or a combination thereof associated with the inputs; a value output layer that outputs a set of predicted outputs based on the coefficients estimated from the fitting layer; a ranking layer configured to receive a combined output from the conditional network and the prediction network, wherein the combined output is computed by multiplying a conditional value from the switch output layer with the set of predicted outputs from the value output layer to ensure that the predictions and interpretations match correctly; and an output layer configured to receive the combined outputs to provide the predictions and interpretations.

3. The method of request item 1, wherein the logically equivalent architecture provides a white-box machine learning model with functionality similar to the transformed XNN.

4. As in request item 1, the logically equivalent architecture includes: Explainable artificial intelligence (XAI) models, explainable neural networks (INN), explainable transducer transformers (XTT), explainable spike networks (XSN), explainable memory networks (XMN), and reinforcement learning (RL) applications, wherein they are compatible with explainable reinforcement learning (XRL), and wherein the transformed XNN is interchangeable with XAI models, XTT, XSN, XMN, and XRL.

5. The method of claim 1, wherein the transformed XNN is configured to form a interpretable neural network (INN) of a superset of the transformed XNN and the interpretable transducer transformer.

6. The method of claim 1, wherein the entity constraints are associated with a hardware type limitation, the entity constraints including attributes associated with the size / space usage, performance, resource usage, trainability, processing power and entity location of the hardware type.

7. The method of claim 1, wherein the logically equivalent architecture is a planar structure exhibiting the logically equivalent behavior of an untransformed XNN, wherein the planar structure includes planar clustering that parallelizes the hierarchical clustering of the untransformed XNN.

8. The method of claim 1, wherein the transformed XNN is configured as a wide neural network of one hardware type.

9. The method of request item 8, wherein an algebraic operation is pre-determined to pass through the wide neural network once.

10. The method of claim 1, wherein the one or more hardware types are associated with a circuit type, including: Digital electronic circuits, analog circuits or digital-analog hybrids, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), computer hardware, neuromorphic circuits, quantum computing hardware, firmware, quantum computing units, and / or combinations thereof.

11. The method of claim 1, wherein the transformed XNN is adapted to the ASIC circuit by being converted to a hardware description language used with the ASIC circuit.

12. The method of claim 1, wherein the one or more hardware types include at least one processor configured to implement the received XNN, wherein the at least one processor includes a central processing unit, a graphics processing unit, a singleton processing unit, or a combination of two or more different processing units; or the received XNN is encoded onto a hardware type that does not have a known processor using one or more numerical precision representations.

13. The method of claim 1, wherein the at least one hardware type is associated with or is part of a security and ethics monitoring chip or disconnect switch system.

14. The method of claim 1, wherein the at least one hardware type is associated with or is part of a real-time operating system and / or a robotic operating system, and is one or more acceleration hardware, wherein the acceleration hardware includes at least one of: an interpretable processing unit, an inductive processing unit, and an acceleration unit.

15. The method of claim 1, wherein the one or more evaluation assurance criteria include an evaluation assurance level related to the common standard identification configuration.

16. The method of claim 1, wherein the transformed XNN is configured to protect the privacy of data associated with an input of a hardware type.

17. The method of claim 1, further comprising: Differential data privacy, secure multi-party computation, joint learning, and homomorphic encryption are used to protect the integrity of the data traversing the transformed XNN to ensure data privacy associated with the output computation.

18. The method of claim 17, wherein data traversing the transformed XNN is selectively deleted, modified, and / or noise is added based on a data privacy model.

19. The method of claim 1, further comprising: Provide an audit trail associated with the output operation, wherein the audit trail corresponds to an identification code that can be stored via a system; detect a deobfuscation attack and generate noise in response to the deobfuscation attack; and / or prevent the audit trail from identifying the data traversing the transformed XNN by applying the generated noise to the data traversing the transformed XNN.

20. The method of claim 1, further comprising: One or more security protocols are applied to traversing the transformed XNN data based on a hardware type, wherein the one or more security-based protocols are configured to encrypt and / or decrypt the data, thereby preventing potential attacks on the data.

21. The method of claim 1, further comprising: When the transformed XNN processes the data traversing the transformed XNN, the data traversing the transformed XNN is encrypted using a singleton method to prevent subsequent decryption.

22. The method of claim 1, further comprising: The transformed XNN is encrypted based on a hardware type. And apply relinearization and / or rescaling to the encrypted XNN.

23. The method of request item 1, wherein the output operation includes interpretation and prediction based on a hardware type encryption.

24. The method of claim 1, wherein the transformed XNN is configured to process multidimensional data, wherein the multidimensional data includes tabular data, text data, video data, audio data, 3D data, volumetric data, discrete data, continuous data, question-and-answer format data, and time or sequence data.

25. The method of request 1, wherein the transformed XNN is configured to protect hierarchical information.

26. The method of claim 1, wherein the transformed XNN includes one or more nodes and associated connections with zero-value coefficients adaptively adjusted between a dense network and a sparse network, wherein the dense network and the sparse network include micronetworks representing the dense network or the sparse network.

27. The method of claim 1, wherein the transformed XNN is a sparse network implementation on a portable device or a fixed device.

28. The method of claim 1, wherein the transformed XNN includes one or more micronetworks associated with a partition of the XNN, wherein the one or more micronetworks are configured based on a hardware type.

29. The method of claim 1, wherein the transformed XNN includes one or more nodes and connections to zero-value coefficients adaptively adjusted between a dense network and a sparse network.

30. The method of request 1, wherein the output computation is used to predict the behavior and consequences of autonomous machinery.

31. The method of claim 1, wherein the transformed XNN is a type of reduction and recursive neural network, adversarial neural network, wide neural network, network applying reinforcement learning, autoencoder network, autodecoder network, causal network, interpretable network, transducer network, spike network, memory network, distributed network, or a combination thereof.

32. The method of claim 1, wherein the transformed XNN is configured to adapt to a hardware type of deep neural network, wherein the hardware type cannot efficiently use a wide neural network for computation.

33. The method of claim 1, wherein the at least one hardware type is an electrical hardware, an accelerator hardware, an optical computing hardware, a mechanical repeater, a switch, a bus system, a control network, a low-power chip, a surface-mount chip, a network device, a hardwired transmitter, a memristor, and a quantum computing component or one or more circuits, wherein the one or more circuits include digital electronic circuits, analog circuits or digital-analog hybrids, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) computer hardware, neuromorphic circuits, quantum computing hardware, spintronic circuits, and firmware.

34. The method of claim 1, wherein the at least one hardware type is geographically located away from the XNN and is adapted to one or more network connectivity systems to receive the XNN for deployment.

35. The method of claim 1, wherein the at least one hardware type is locally linked via a network connectivity system, the network connectivity system comprising: A Bluetooth system and a regional Ethernet network.

36. The method of claim 1, further comprising: An action trigger is embedded in the at least one hardware type, such that the output operation is used as the action trigger for immediate processing without pausing the transformed XNN.

37. The method of request item 1, wherein the output operation is used as a signal to initiate an action trigger in a hardware type.

38. The method of claim 1, wherein the transformed XNN is configured to be executed or performed together with a sensor-equipped hardware type or a sensorless hardware type.

39. The method of claim 1, wherein the transformed XNN is configured to be optimized and predicted using linear and nonlinear optimization methods, the linear and nonlinear optimization methods including: Fourier series, multidimensional Betz curves, recursive relations, causal operators.

40. The method of claim 1, wherein the transformed XNN is partitioned into overlapping and / or non-overlapping partitions based on a hardware type, wherein a hierarchical clustering method is used to partition the transformed XNN, the hierarchical clustering method comprising: Agglomerative clustering, splitting clustering, relocation partitioning, probabilistic clustering, k-medoid method, k-means method, fuzzy clustering, density-based clustering, grid-based method, gradient descent-based method, evolutionary method, region splitting, region growing, subspace clustering, projection method, cooperative clustering method, and slow clustering method.

41. The method of claim 1, wherein the transformed XNN is externally partitioned and optimized during or before the transformation, wherein the transformed XNN is optimized using local and global optimization methods, wherein such local and global optimization methods include gradient-based methods, simulation-based methods, and causal logic induction methods.

42. The method of claim 1, further comprising: The transformed XNN is enriched with taxonomic information, information about links to internal and external taxonomy, and bias detector information, wherein the enriched information is related to a hardware type embedded in the transformed XNN.

43. The method of claim 1, wherein the transformed XNN forms part of a causal local system, wherein the transformed XNN is configured to extract higher-order data and the correlations between the data for output to a causal model.

44. The method of request 1, wherein the transformed XNN is externally partitioned and optimized during the transformation.

45. The method of request item 1, wherein the transformed XNN partition is divided into overlapping and / or non-overlapping partitions based on a hardware type.

46. ​​The method of claim 1, wherein the transformed XNN supports encoding of disjunctive and conjunctive paradigms, wherein the supported encoding is suitable for implementation on static, flexible, neuromorphic and quantum computing architectures.

47. The method of claim 1, wherein the transformed XNN supports rotation and scale invariance, nonlinear functions, and summarization of multiple partitions in multiple dimensions.

48. The method of claim 1, wherein the transformed XNN is configured to reduce the error rate associated with an implementation of a hardware type.

49. The method of claim 1, wherein the XNN is transformed to adapt to a hardware type by at least one of the following: a Fourier transform, integer transform, real transform, complex transform, quaternion transform, octonion transform, Walsh function, state-space transform, phase-space transform, Haar and non-Haar wavelets, generalized L2 function, fractal-based transform, Hadamard transform, fuzzy logic, knowledge graph network, classification coding, difference analysis, normalization, standardization, multidimensional Betz curve, recursive relation and causal operator.

50. The method of claim 1, wherein the XNN is transformed by using a fixed resource model relating to one or more systems, wherein the one or more systems include a real-time operation system and a robotic operation system.

51. The method of claim 1, wherein the output operation is a general interpretation format, human-readable text, machine-readable text, a heatmap, a graphical representation, an audio format, which is human-readable, machine-readable, or both.

52. The method of claim 1, wherein the output operation further includes information specific to the application implemented on a hardware type.

53. The method of Request 1, wherein the output computation is personalized for controlling the level of detail based on one or more user models, wherein the one or more user models are configured based on a user's user expertise, familiarity with the model domain, the user's current goals, plans and actions.

54. The method of claim 1, further comprising: User input is provided to the hardware of at least one type from one or more sources in a suitable format, wherein the one or more sources include a haptic feedback device, a tactile device, a touch-sensitive device, a voice recognition device, an optical scanner, an imaging device, a multi-dimensional scanner, a LiDAR / RADAR system, and a time-of-flight measurement device.

55. The method of claim 2, wherein the switch output layer is configured to identify and select partitioned inputs for use as condition value outputs.

56. The method of claim 2, wherein the fitting layer estimates coefficients corresponding to each variable in the generated group or a combination of the group of variables associated with the inputs and at least one partition of the plurality of partitions.

57. The method of claim 2, wherein the prediction network further comprises: At least one transformation layer is configured to transform the inputs before and / or after the fitting layer receives them.

58. The method of request item 2, wherein the conditional network further includes: At least one transformation layer is configured to transform the inputs before they are received by the conditional layer and after they are received by the conditional network.

59. The method of claim 2, wherein the at least one transformation layer includes transformations adapted to be applied simultaneously linearly, nonlinearly, or both to one or more of the inputs.

60. The method of request item 2, wherein the one or more transformations include a transformation function pipeline.

61. The method of claim 2, wherein when a neuron associated with one or more partitions in the conditional network is activated, the ranking layer selects from the plurality of partitions for subsequent activation.

62. The method of claim 2, wherein the conditional network and the predictive network are simultaneously configured to receive the inputs from the input layer simultaneously.

63. The method of claim 2, wherein at least one of the plurality of partitions overlaps with a second partition of one of the plurality of partitions, and the interpretable neural network further includes a feedforward step of traversing one of the interpretable neural networks across a plurality of paths, and calculating a probability or ranking score for each of the plurality of paths.

64. An apparatus for deploying an interpretable neural network (XNN), comprising: One or more processors, or the like, including a graphics processor, wherein the one or more processors: receive the XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of one or more hardware types; transform the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted into a logically equivalent architecture during the transformation; use the transformed XNN operation to receive input from the at least one hardware type; and output the operation based on satisfying one or more evaluation guarantee criteria.

65. A non-transitory computer-readable medium comprising instructions that, when executed, cause hardware to at least: receive an XNN and a set of parameters for the XNN, wherein the set of parameters is associated with entity constraints of one or more hardware types; transform the XNN based on the set of parameters suitable for deployment on at least one hardware type, wherein the XNN is converted to a logically equivalent architecture during the transformation; operate on the transformed XNN using input received by the at least one hardware type; and output the operation based on satisfying one or more evaluation guarantee criteria.

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