Stacked RF circuit topology

Abstract

This invention discloses an integrated circuit device package comprising: a substrate; a first die including active electronic components attached to the substrate; and package leads configured to conduct electrical signals between the first die and an external device. At least one integrated interconnect structure is disposed on the first die and opposite the substrate. The at least one integrated interconnect structure extends from the first die to a neighboring die attached to the substrate and / or to at least one of the package leads, and provides electrical connection between them. This invention also discusses related devices and power amplifier circuits.

Description

[Technical Field]

[0001] This invention relates to integrated circuit devices, and more particularly to the structure of integrated circuit device packages. [Previous Technology]

[0002] RF power amplifiers are used in a variety of applications, such as base stations for wireless communication systems. The signals amplified by an RF power amplifier typically contain a modulated carrier signal with a frequency ranging from megahertz (MHz) to gigahertz (GHz). The baseband signal of the modulated carrier is typically at a relatively low frequency, and depending on the application, can be as high as 300 MHz or higher. Many RF power amplifier designs utilize semiconductor switching devices as amplification devices. Examples of such switching devices include power transistor devices such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), DMOS (Double-Diffused Metal-Oxide-Semiconductor) transistors, HEMT (High Electron Mobility Transistor), MESFET (Metal-Oxide-Semiconductor Field-Effect Transistor), LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) transistors, etc.

[0003] RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented using silicon or wide-bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV) such as silicon carbide ("SiC") and group III nitride materials. As used herein, the term "group III nitride" refers to a semiconducting compound formed between nitrogen and an element from group III of the periodic table (typically aluminum (Al), gallium (Ga), and / or indium (In)). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have an empirical formula in which one mole of nitrogen is bonded to a total of one mole of group III elements.

[0004] Silicon-based RF amplifiers are typically implemented using LDMOS transistors and can be manufactured relatively inexpensively, exhibiting high linearity. Group III nitride-based RF amplifiers are typically implemented using HEMTs, primarily in applications requiring high power and / or high frequency operation, where LDMOS transistor amplifiers may have inherent performance limitations.

[0005] An RF transistor amplifier may include one or more amplification stages, wherein each stage is typically implemented as a transistor amplifier. To increase output power and current handling capability, an RF transistor amplifier is typically implemented as a "unit cell" configuration, wherein a large number of individual "unit cell" transistors are electrically connected in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include a plurality of dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0006] RF amplifiers typically include matching circuitry, such as impedance matching circuitry designed to improve impedance matching between the active transistor chip (e.g., including MOSFETs, HEMTs, LDMOS, etc.) and the transmission lines connected to it for the RF signal used at the basic operating frequency, and harmonic termination circuitry designed to at least partially terminate harmonic products (such as second- and third-order harmonic products) that may be generated during device operation. The termination of harmonic products also affects the generation of intermodulation distortion products.

[0007] (Several) RF amplifier transistors, impedance matching, and harmonic termination circuitry may be enclosed in a device package. A die or wafer may refer to a small piece of semiconducting material or other substrate on which electronic circuitry elements are fabricated. An integrated circuit package may refer to encapsulating one or more dies in a support housing or package that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuitry. Input and output impedance matching circuitry in an integrated circuit device package typically includes an LC network that provides at least a portion of an impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. Electrical leads may extend from the package to electrically connect the RF amplifier to external circuitry elements (such as input and output RF transmission lines and bias voltage sources).

[0008] Many functional blocks, such as impedance matching circuits, harmonic filters, couplers, baluns, and power combiners / distributors, can be implemented using integrated passive devices (IPDs). IPDs contain passive electrical components and are generally manufactured using standard wafer fabrication techniques (such as thin-film and photolithography). IPDs can be designed as flip-chip mounted or wire-bondable components. The substrate used for IPDs is typically a thin-film substrate (such as silicon, alumina, or glass), which allows for easy fabrication and packaging with active transistor chips.

[0009] Some conventional methods for assembling RF power devices may involve assembling a transistor die and some matching network components (e.g., pre-matched capacitors, such as MOS capacitors) in a ceramic or overmolded package on a CPC (copper, copper-molybdenum, copper laminate) or copper flange. The transistor die, capacitors, and input / output leads may be interconnected with wires (such as gold and / or aluminum wires). This assembly process may be slow and sequential (e.g., bonding one package at a time) and the assembly cost may be high (e.g., due to the cost of gold wires and expensive wire bonding machines). [Summary of the Invention]

[0010] According to some embodiments of the present invention, an integrated circuit device package includes: a substrate; a first die including active electronic components attached to the substrate; and at least one integrated interconnect structure on the first die and opposite to the substrate. The at least one integrated interconnect structure extends from the first die to a neighboring die attached to the substrate and / or toward at least one package lead, and provides electrical connection between them.

[0011] In some embodiments, the electrical connection may not have a wire connection.

[0012] In some embodiments, the first die may include a first bonding pad on a surface of the first die opposite to the substrate, the first bonding pad being electrically connected to one or more of the active electronic components. The at least one integrated interconnect structure may include a contact pad on the first bonding pad.

[0013] In some embodiments, the at least one integrated interconnect structure may be a conductive wiring pattern on a layer.

[0014] In some embodiments, the at least one integrated interconnect structure may include or provide at least a portion of an impedance matching network for a circuit defined by the active electronic components of the first die.

[0015] In some embodiments, the at least one integrated interconnect structure may be a passive device that includes one or more passive electronic components.

[0016] In some embodiments, the contact pad of the integrated interconnect structure may be a second bonding pad on one of the surfaces of the passive device facing the first die, the second bonding pad being electrically connected to the one or more passive electronic components. The second bonding pad is connected to the first bonding pad via a conductive bump between the second bonding pad and the first bonding pad.

[0017] In some embodiments, the active electronic components of the first die may define a first radio frequency (RF) amplifier circuit. The adjacent die may be a second active die containing active electronic components defining a second RF amplifier circuit. The first and second power amplifier circuits may be connected by the passive device to form a multi-stage amplifier configuration.

[0018] In some embodiments, the passive device may be an integrated passive device (IPD) that includes at least one inductor.

[0019] In some embodiments, the IPD may not have active electronic components.

[0020] In some embodiments, the IPD may include an insulating material between its conductive elements to define at least one capacitor integrated therein.

[0021] In some embodiments, the adjacent die may be a capacitor die comprising one or more capacitors and at least one capacitor bonding pad on one of the surfaces of the adjacent die opposite to the substrate. The contact pad of the at least one integrated interconnect structure may be a first contact pad, and the at least one integrated interconnect structure may further include at least one second contact pad on the at least one capacitor bonding pad.

[0022] In some embodiments, the at least one package lead may be a gate lead and the first bonding pad may be a gate pad. The adjacent die may be between the first die and the gate lead, and the impedance matching network may be one of the input impedance matching networks for the circuit.

[0023] In some embodiments, the at least one package lead may be a drain lead and the first bonding pad may be a drain pad. The adjacent die may be between the first die and the drain lead, and the impedance matching network may be one of the output impedance matching networks for the circuit.

[0024] In some embodiments, the active electronic components may be power transistor devices. The first grain may comprise group III nitrides and / or silicon carbide.

[0025] According to some embodiments of the present invention, a radio frequency (RF) power amplifier device package includes: a substrate; a first die comprising a plurality of transistor cells, the first die being attached to the substrate at a source pad on a bottom surface thereon and a gate or drain pad on a top surface thereon opposite to the substrate; package leads configured to conduct electrical signals between the gate or drain pad of the first die and an external device; and an integrated interconnect structure on the first die and opposite to the substrate. The integrated interconnect structure includes a first contact pad on the gate or drain pad and at least one second contact pad on a neighboring die attached to the substrate and / or coupled to one of the package leads.

[0026] In some embodiments, the integrated interconnect structure may provide electrical connections from the gate or drain pad of the first die to the adjacent die and / or to the package leads. These electrical connections may not have a single-wire connection.

[0027] In some embodiments, the integrated interconnect structure may be a conductive wiring pattern on a layer, or include one or more passive electronic components.

[0028] In some embodiments, the integrated interconnect structure may include or provide at least a portion of an impedance matching network for a circuit defined by the isoelectric transistor of the first die.

[0029] In some embodiments, the first contact pad of the integrated interconnect structure may be a bonding pad on one of the top surfaces of the passive device facing the first die, the bonding pad being electrically connected to the one or more passive electronic components. The bonding pad may be connected to the gate or drain pad via a conductive bump between the bonding pad and the gate or drain pad.

[0030] In some embodiments, the adjacent die may be contained in at least one bonding pad on one of its surfaces opposite the substrate. The at least one second contact pad of the integrated interconnect structure may be on the at least one bonding pad. The adjacent die may be a capacitor die containing one or more capacitors, or a second die containing a plurality of transistor units defining a stage of an RF amplifier circuit.

[0031] When reviewing the following figures and [implementations], those skilled in the art will understand other apparatuses, devices, and / or methods according to some embodiments. In addition to any and all combinations of the above embodiments, all such additional embodiments are also intended to be included within this description, within the scope of the invention, and protected by the claims of the appended invention.

Implementation Method

[0032] Claim of priority

[0033] This application claims priority to U.S. Provisional Application No. 63 / 004,760, filed with the U.S. Patent and Trademark Office on April 3, 2020, the disclosure of which is incorporated herein by reference.

[0034] Some embodiments of the present invention may arise from difficulties in assembling and optimizing the parameters of various components contained in an integrated circuit device package. For example, the performance of some passive electronic components (e.g., inductors or capacitors) contained in a die or IPD (generally referred to herein as a passive device or passive RF device) may be affected by proximity to a ground plane. Specifically, as the distance between the winding of an inductor coil and a ground connection flange (or other grounding structure) decreases, the quality factor Q of the inductor coil may decrease. However, since a die is typically a planar structure having only one surface providing conductive contact elements (also referred to herein as contact pads, bonding pads, or pads) for electrical connection (typically via bonding wires) to an external die or device, increasing the distance between the passive component and the ground plane may increase the connection length to one or more active electronic components (e.g., transistors, such as power transistor devices containing transistor units) contained in an active transistor die (also referred to herein as a transistor die or active die). Increased connection length can reduce or eliminate the effectiveness of impedance matching networks provided by passive components, especially at higher frequencies. Output pre-matching networks using a shunt-L topology can be challenging (e.g., for GaN die products) because long shunt-L junctions can introduce more inductance than required, degrading impedance matching quality by approximately 50 fF / W to 70 fF / W (e.g., partly due to the lower drain-to-source capacitance (Cds) / W in GaN), which can also lead to higher losses and reduced performance. Coupling between input (e.g., gate) and output (e.g., drain) junctions can also cause gain losses and instability.

[0035] In contrast to some conventional RF power devices that can use wire-bonded loops to implement input and output pre-matching, embodiments of the present invention provide packaged RF power products for high-power applications, wherein the connections between components (e.g., between circuit-level components, such as between bonding pads of one or more active transistor dies, and / or between bonding pads of active transistor dies and the gate and / or drain leads of the package) are implemented by one or more structures comprising conductive components on a layer or substrate, such as semiconductor wafers or dies that do not use wire bonding (e.g., one or more passive devices), generally referred to herein as integrated interconnect structures.

[0036] An integrated interconnect structure or device (or "integrated interconnect") can generally refer to a structure containing integrated circuitry (such as resistors (including transmission lines), vias, inductors, and / or capacitors) on a layer or substrate, for example, a dielectric substrate structure having integrated traces, vias, and / or circuitry that can replace bonding wires to reduce and / or avoid associated parasitic inductance and manufacturing problems. In some embodiments described herein, the integrated interconnect may be implemented as a passive device (including an IPD having a thin-film substrate such as silicon, alumina, or glass) and / or a conductive wiring structure (including conductive lines on a redistribution layer (RDL) laminate or other substrate). As mentioned above, the IPD includes inductors and / or other passive electrical components and can be manufactured using standard semiconductor processing techniques (such as thin-film and / or photolithography). The IPD may be a flip-chip mounted or wire-bonded component and may include a thin-film substrate such as silicon, alumina, or glass. An RDL structure refers to a substrate or laminate having conductive layer patterns and / or conductive vias. RDL structures can be manufactured using semiconductor processing techniques by depositing conductive and insulating layers and / or patterns on a substrate material, and by forming vias and copper wiring patterns within the structure for transmitting signals through the RDL structure.

[0037] As described herein, integrated interconnects can be used to provide connections to the inputs, outputs, and / or stages of transistors and to provide circuitry useful and / or necessary for the operation of (a number of) transistors. For example, an integrated interconnect can provide an impedance configured to reduce impedance mismatch between active transistors and / or with an external device connected to the package leads. In certain instances, an integrated interconnect (such as an IPD) can be used to implement input and / or output pre-matching network circuitry for an active transistor, resulting in minimal or no wire bonding. In some embodiments, a flip-chip IPD including respective contacts facing one or more transistors can be used, for example, to interconnect multiple transistors in a multistage amplifier implementation. That is, in some embodiments, an integrated interconnect can provide both an interconnect function and an impedance matching / harmonic termination function, thereby reducing or eliminating the use of wire bonding in the package. In some embodiments, an IPD as described herein may not have an active component.

[0038] In some embodiments, an IPD (also referred to herein as a pre-matched IPD) for the impedance matching network of the active die is provided directly or stacked on top of the gate and / or drain pads of the transistor die and / or capacitor die, thereby reducing or minimizing interconnect-related losses. The increased height or distance between the passive component and an attachment surface (such as the ground connection flange of a device package die pad or the flange of the package) (as provided by a stacked configuration, e.g., on top of a 100 µm thick active transistor die) reduces capacitive coupling to ground, thus reducing or minimizing the negative impact on the quality factor Q of the passive component (and in some cases increasing it) (minimizing losses) and resulting in better RF performance. Furthermore, thin, low-profile conductive traces in the integrated interconnect (e.g., pre-matched IPD) can have lower coupling to output lines or traces.

[0039] Additional passive components (e.g., for a particular application) may be included in the passive device and / or on the attachment surface of the package directly beneath the passive device. For example, in some embodiments, capacitors for pre-matching and / or harmonic termination (e.g., MOS capacitors) may be placed between the input pre-matching IPD and the attachment surface. Similarly, for improved video bandwidth (VBM), high-density output capacitors may be placed between the output pre-matching IPD and the attachment surface, providing a larger area for accommodating one of the high-density VBM capacitors. In some embodiments, the passive device may include capacitors integrated therein, such as MIM (metal-insulator-metal) capacitors.

[0040] Therefore, embodiments of the present invention can use a stacked chip topology to greatly reduce coupling problems between gate and drain junctions (which can lead to gain loss and instability). In some embodiments, gate and / or drain junctions can be eliminated or reduced, and low-profile conductive traces in integrated interconnects (e.g., input and / or output IPDs) can provide minimal coupling between them and / or lower coupling to output lines or traces. Furthermore, by implementing shunt-L and series-connected inductors in a high-Q flip-chip IPD, the desired inductance can be achieved in a smaller area and with manageable losses.

[0041] Embodiments of the present invention can be used in RF power products for 5G and base station applications, as well as in radar and / or monolithic microwave integrated circuit ("MMIC") type applications. For example, a group III nitride-based RF amplifier can be implemented as an MMIC device, wherein one or more transistor chips and their associated impedance matching and harmonic termination circuits are implemented together in a single integrated circuit chip.

[0042] FIG1A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention. As shown in FIG1A, some embodiments of the present invention provide an RF power device package 100a, which includes an active die 105 and integrated interconnects (shown as passive devices 110i, 110o; collectively referred to as 110) mounted on a package substrate 101a. In the example of FIG1A, the substrate 101a is a redistribution layer (RDL) laminate structure. The RDL 101a may include a conductive layer manufactured using semiconductor processing technology. However, it will be understood that the substrate 101a is not limited thereto; for example, the substrate 101a may be a printed circuit board (e.g., a multilayer printed circuit board with metal traces), a ceramic substrate including conductive vias and / or conductive pads, or any other suitable mounting surface for the active die 105. The bottom surface or bottom side of RDL 101a includes package leads (specifically, gate 102g, drain 102d, and source 102s leads, collectively referred to as package leads 102) that conduct electrical signals between components on an attachment surface 101s of RDL 101a and an external device (not shown), such as an external circuit board. The attachment surface 101s may include one or more conductive die pads, which in some embodiments may provide an electrical ground for the components of package 100. RDL 101a includes vias and multilayer copper wiring for transmitting signals from leads 102 to passive electronic components (such as capacitor chips containing one or more MOS capacitors 104 or high-density capacitors 106) and active electronic components (such as transistors) of active transistor die 105. For example, active die 105 may include, for example, a power transistor device defining an RF power amplifier. In some embodiments, the active die 105 may include discrete multilevel MMIC and / or multipath (e.g., Doherty) transistor devices.

[0043] The active transistor die described herein may be implemented using silicon or wide-bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. In a particular embodiment, the active die may be a unit cell transistor based on group III nitrides (such as gallium nitride (GaN)) and / or based on silicon carbide (SiC), contained in parallel connections in an upper portion of a semiconductor layer structure. The term “semiconductor layer structure” may refer to a structure comprising one or more semiconductor layers (such as a semiconductor substrate and / or a semiconductor epitaxial layer). In the illustrated embodiment, the active transistor die includes a gate pad and / or drain pad on an upper surface and a source pad on a lower surface adjacent to the attachment surface of the semiconductor layer structure. However, it will be understood that this die configuration is illustrated herein only by way of example, and the embodiments and / or topologies described herein may be used with die configurations other than those explicitly illustrated.

[0044] Because RF amplifiers are typically used in high-power and / or high-frequency applications, high heat can be generated within the transistor(s) during operation. If the transistor(s) become too hot, the performance of the RF amplifier (e.g., output power, efficiency, linearity, gain, etc.) can be degraded and / or the transistor(s) can be damaged. Therefore, RF amplifiers are typically mounted in packages that can be optimized or otherwise configured for thermal removal. In the example of FIG1A, source leads 102s include or are attached to a conductive structure 103 (shown as an embedded conductive block or via) that provides thermal conductivity (e.g., a heat sink). Specifically, a section of RDL 101a below the transistor 105 can be filled (e.g., more than about 85% filled, fully filled, or almost fully filled) by a high-density conductive array 103 of copper vias of the transistors for transferring heat away from the transistors 105. For example, in an embedded packaging process, an embedded copper block or coin can also be used to fill the conductive structure 103. The transistor die 105 and capacitor chips 104, 106 are attached to the attachment surface 101s of RDL 101a using die attachment materials 107 and techniques (such as eutectic materials, precoat (e.g., AuSn precoat), pre-form, sintering (e.g., Ag sintering)).

[0045] Referring again to FIG1A, one or more connections between the active transistor die 105 (specifically, contacts or bonding pads 105p on a top side or surface of the transistor die 105) and the package lead 102 are implemented by respective integrated interconnects (in this example, passive devices implemented by IPDs 110i and 110o), and there are no wire connections between them. The connection provided by the passive device 110 is opposite to (but not within) the attachment surface 101s or substrate 101a to which the bottom side or surface of the active die 105 is attached. More specifically, bonding pads 105p on a surface of the transistor die 105 opposite to the substrate 101 are connected to bonding pads 110p on a surface of the IPD 110 facing the transistor die 105, and the bonding pads 110p of the IPD are connected to the package lead 102. As mentioned above, (a number of) passive devices 110 may be included in passive electronic components on a semiconductor or other substrate, such as resistors / transmission lines, inductors and / or capacitors.

[0046] In Figure 1A, the components of the passive device 110 are configured to provide an impedance matching network for the input 110i and output 110o of a circuit (e.g., an RF amplifier circuit) defined by the transistors of the active chip 105, and are shown as a high-Q IPD, but the passive device as described herein is not limited thereto. The input impedance matching circuit matches the impedance of the fundamental component of the RF signal input to the RF power device package 100a to the impedance at the input of the active chip 105, the output impedance matching circuit matches the impedance of the fundamental component of the RF signal output from the RF power device package 100a to the impedance of the circuit connected to the output of the active chip 105, and the input and / or output harmonic termination circuits are configured to short-circuit to ground harmonics that may exist at the input and / or output of the fundamental RF signal of the active chip 105.

[0047] In the example of FIG1A, the high-Q IPD 110 for input and output pre-matching networks is a flip-chip device comprising respective bonding pads 110p on one surface of the IPD 110. Therefore, the IPD 110 is "flip-chipped" onto the top of the transistor die 105 and capacitor wafers 104, 106, such that the bonding pads 110p on the surface of the IPD 110 are aligned with the bonding pads 105p and 104p, 106p on the surfaces of the transistor die 105 and capacitor wafers 104, 106 facing the IPD 110. The IPD 110 may include conductive bumps 111 (e.g., conductive epoxy patterns or solder bumps, pre-attached to the IPD 110 in some embodiments) for connecting the bonding pads 110p to the bonding pads 105p and 104p, 106p. The top surfaces of capacitor chips 104, 106 and transistor chips 105 can be aligned to the same height by grinding the wafer (for chips or capacitor wafers) and / or by using preforms 107 of different thicknesses to align the heights of components 104, 105, and 106. Therefore, package 100a includes a stacked structure in which components 104, 105, and 106 are attached to attachment surfaces 101s between substrate 101a and component 110 (which provide electrical connections to ground). Component 110 provides electrical connections between components 104, 105, and 106 and leads 102 opposite to substrate 10a, without individual bonding lines extending between components 104, 105, and 106 and leads 102.

[0048] The copper shim 112 attached to RDL 101a can be used to route signals from IPD 110 to RDL 101a and to the gate and drain leads 102g and 102d of package 100a. In some embodiments, an additional IPD including a via (e.g., a through silicon via (TSV)) can replace the copper shim 112 to connect IPD 110 to the gate and drain leads 102g and 102d.

[0049] An encapsulation material (illustrated as a plastic overmold (OMP) 113) encapsulates or otherwise protects the dies 105, 110 while providing access to leads 102 for connection to circuitry or devices (generally referred to herein as external devices) outside the package 100a. The overmold 113 may substantially surround the dies 105, 110 and may be formed of a plastic or plastic polymer compound, thereby providing protection against external environmental influences. Advantages of overmold packaging include reduced overall height or thickness of the package, and design flexibility in the configuration of leads 102 and / or the spacing between leads 102. In some embodiments, the overmold package as described herein may have a height or OMP thickness of about 400 micrometers (µm) to about 700 µm. In other embodiments, the grains 105, 110 may be contained in an open-cavity package (e.g., a thermally enhanced package (TEPAC or T3PAC)) comprising a ceramic material, the open-cavity package defining a cavity surrounding the grains 105, 110 and having a height or thickness of about 1400 micrometers (µm) to about 1700 µm.

[0050] FIG1B is a cross-sectional view illustrating another example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention. As shown in FIG1B, an RF power device package 100b includes active and passive devices 105, 110 assembled on a substrate 101b. Package 100b includes the components and connections shown in the embodiment shown in FIG1A, but substrate 101b provides attachment surfaces 101s, source leads 102s, and a conductive structure 103 (e.g., a copper block) for transferring heat away from the thermal conductivity (e.g., a heat sink) of the transistor die 105. Furthermore, compared to FIG1A, the bonding pad 110p of the passive device 110 is connected to the package lead 102 by an integrated interconnect (shown as a conductive wiring structure 114, e.g., including a copper wiring layer in an RDL) instead of a copper filler 112 (or an IPD with TSV). Alternatively, in some embodiments, the bonding pads 110p of the passive device 110 may be directly connected to the package leads 102 (e.g., via respective solder bumps 111), without any conductive wiring structure 114 between them. Compared to the laminate-based embodiment of FIG. 1A, the embodiment of FIG. 1B can be described as leadframe-based.

[0051] FIG1C is a cross-sectional view illustrating another example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention. As shown in FIG1C, an RF power device package 100c is similar to the embodiment of FIG1A, but instead of copper filler 112 (or IPD with TSV), package 100c includes a second RDL layer 101c attached to the top of a first RDL layer 101a and opposite to the gate lead 102g and / or opposite to the drain lead 102d. The height or thickness of the second RDL layer 101c is selected or configured to provide a contact surface that is aligned or coplanar with the bump pads 105p, 104p of the transistor die 105 and MOS capacitor chip 104 on the input side, and similarly aligned or coplanar with the bump pads 105p, 106p of the transistor die 105 and VBW capacitor chip 106 on the output side. Therefore, the input 110i and output 110o flip-chip IPDs can be placed on a substantially coplanar surface provided by the second RDL layer 101c to interconnect the gate and drain pads 105p of the transistor die 105 with the gate lead 102g and drain lead 102d (and / or with the MOS capacitor 104 and VBW capacitor 106). An additional second RDL layer 101c and / or other intermediate substrates (although not shown) can also be disposed between the attachment surface 101s and (a number of) passive devices 110 to provide the desired gap or alignment between the contact pads of components of different heights or thicknesses.

[0052] Figure 1D is an equivalent circuit diagram of one of the embodiments in Figures 1A, 1B, and 1C. The input pre-matching network is implemented by a high-Q IPD 110i and an input capacitor 104 to provide an LC matching circuit (e.g., a low-pass LC) for the fundamental frequency f0, and a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for the optimal termination harmonic frequency (e.g., 2f0). The output pre-matching network is implemented by an output capacitor 106 and a high-Q IPD 110o to provide a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for pre-matching the fundamental frequency f0. The series transmission line 110r in each of the input 110i and output 110o IPDs can be selected to provide appropriate impedance transformation from the transistor die 105 to the gate 102g or drain 102d lead. A series transmission line (e.g., provided by conductive structure 110r) can be considered as an extension of the board transmission line matching network, and the electrical width can be selected or configured to achieve the desired characteristic impedance for impedance matching.

[0053] Figures 2A and 2B are cross-sectional views illustrating examples of integrated circuit device packages including stacked topologies according to some embodiments of the present invention. As shown in Figures 2A and 2B, RF power device packages 200a and 200b each include an active die 105 and an integrated interconnect (illustrated as an IPD or other passive device 110i) mounted on a package substrate 201. Packages 200a and 200b include the components and connections shown in the embodiment shown in Figure 1B, wherein the substrate 201 is configured to provide an attachment surface 201s for the transistor of the transistor die 105, source leads 102s, and a conductive structure 103 (e.g., a copper block) for thermal conductivity (e.g., a heat sink). In the embodiments of Figures 2A and 2B, the passive device 110 is used only on the input side of packages 200a and 200b. For example, in embodiments with a smaller die perimeter (e.g., less than about 16 mm of total gate width) and / or lower frequency operation (e.g., less than about 2.4 GHz), the output impedance of transistor 105 can be high enough to match up to 50 ohms to an RF circuit board, eliminating the need for an in-package output pre-matching network. Since only an input pre-matching network is required in these embodiments, the input of transistor 105 is electrically connected to the gate lead 102g via the IPD 110i defining the pre-matching network and the MOS capacitor 104.

[0054] More specifically, the bonding pads 105p and 104p on the top surfaces of the transistor die 105 and the MOS capacitor chip 104 are connected to the bonding pad 110p on one of the facing surfaces of the IPD 110i via their respective solder bumps 111, without any wire bonding between them. The bonding pad 110p of the IPD 110i is connected to the gate lead 102g via a conductive wiring structure 114 (e.g., a copper wiring layer in an RDL). Alternatively, the bonding pad 110p of the passive device 110i may be directly connected to the gate lead 102g, without any conductive wiring structure 114 between them. The output of the transistor die 105 is directly connected to the drain lead 102d via a conductive wiring structure (shown as a copper wiring layer in one of the RDL 214 in FIG. 2A or as a wire bonding 14 in FIG. 2B).

[0055] Figure 2C is an equivalent circuit diagram of one embodiment of Figures 2A and 2B. Similar to the input side of the embodiments of Figures 1A and 1B, the input pre-matching network is implemented by a high-Q IPD 110i and an input capacitor 104 to provide an LC matching circuit (e.g., a low-pass LC) for the fundamental frequency f0, and a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for optimal termination of one or more harmonic frequencies (e.g., 2f0). The series transmission line 110r in the input IPD 110i can be selected to provide appropriate impedance transformation from the transistor die 105 to the gate lead 102g. The electrical width of the transmission line 110r can also be configured to achieve the desired characteristic impedance for impedance matching.

[0056] FIG3A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention. As shown in FIG3A, the RF power device package 300 includes an active die 105 and an integrated interconnect (illustrated as an IPD or other passive device 110o) mounted on a package substrate 301. As in the embodiment of FIG1B, the substrate 301 is provided with attachment surfaces 301s, source leads 102s, and a conductive structure 103 (e.g., a copper block) for transferring heat away from the thermal conductivity (e.g., a heat sink) of the transistor 105. In the embodiment of FIG3A, the passive device 110o providing electrical connections to the active die 105 and the capacitor chip 106 is only provided on the output side of the package 300. More specifically, the bonding pads 105p and 106p of the transistor die 105 and the high-density capacitor chip 106 are connected to the bonding pad 110p of the IPD 110o via their respective solder bumps 111, without any wire bonding between them. The bonding pad 110p of the IPD 110o is connected to the drain lead 102d via a conductive wiring structure 114 (e.g., a copper wiring layer in an RDL). Alternatively, the bonding pad 110p of the passive device 110o may be directly connected to the drain lead 102d, without any conductive wiring structure 114 between them.

[0057] Referring again to FIG. 3A, the connection between the gate lead 102g, the capacitor chip 104, and the input of the transistor chip 105 is implemented by an integrated interconnect in the form of a conductive wiring structure 314, which is illustrated as an RDL including a copper (or other conductive) wiring layer and a contact pad, for example, illustrated as a conductive via or a pillar 314v. More specifically, in the example of FIG. 3A, the inductors for the input pre-matching network and harmonic termination are directly implemented in the copper traces and vias of the RDL 314, and the input IPD 110i is omitted. The inductors for impedance matching can be achieved in the conductive wiring structure 314, for example, using narrow strips of copper wiring or coil tracing, and can be connected to the bonding pads 105p and 104p of the transistor chip 105 and the input capacitor chip 104 using the conductive via 314v. For example, in some embodiments, modern embedded packaging assembly techniques can be used to deposit narrow copper traces (e.g., about 10 micrometers wide) and vias to collectively provide the required or desired inductance for the RDL 314. However, compared to an IPD 110, the tolerances for the trace width and / or the spacing between traces and / or vias of the RDL 314 are less controllable.

[0058] Figure 3B is an equivalent circuit diagram of one embodiment of Figure 3A. Similar to the output side of the embodiments of Figures 1A and 1B, the output pre-matching network is implemented by an output capacitor 106 and a high-Q IPD 110o to provide a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for pre-matching the fundamental frequency f0. The series transmission line 110r in the output IPD 110o can be selected to provide appropriate impedance transformation from the transistor die 105 to the drain lead 102d. The input pre-matching network is implemented by a conductive wiring structure 314 and an input capacitor 104 to provide an LC matching circuit (e.g., a low-pass LC) for the fundamental frequency f0, and a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for optimally terminating one or more harmonic frequencies (e.g., 2f0). Similarly, a series transmission line 310r may be optionally implemented in the conductive wiring structure 314 to provide appropriate impedance transformation from the transistor die 105 to the gate lead 102g.

[0059] FIG4 is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention. As shown in FIG4A, the RF power device package 400 includes an active die 105 mounted on a substrate 301 and an integrated interconnect (shown as an IPD or other passive device 110oc). As in the embodiment of FIG3A, the substrate 301 is provided with an attachment surface 301s, source leads 102s, and a thermally conductive structure 103 (e.g., a copper block). The connection between the gate lead 102g, the capacitor chip 104, and the input of the transistor die 105 is implemented by a conductive wiring structure 314, wherein inductors for input pre-matching networks and harmonic termination are directly implemented in the conductive traces and vias of the wiring structure 314. The passive device 110oc, which provides electrical connection to the active die 105, is only provided on the output side of the package 400.

[0060] In Figure 4A, the output capacitor chip 106 (e.g., a high-density capacitor, which may be used for video bandwidth) is not positioned below the output IPD 110oc; in fact, the output capacitor is integrated into the flip-chip output IPD 110oc, for example, as a metal-insulator-metal (MIM) capacitor C. In some embodiments, the MIM capacitor C may be formed by providing an insulating material between one of the conductive elements of the IPD 110oc and one or more of the bonding pads 110p. At least one conductive via or pillar 410v is used to connect one end of the integrated capacitor to, for example, a package ground provided by the conductive structure 103. In some embodiments, the conductive vias 410v may be implemented via copper vias in an RDL. Integrating the capacitor into the passive device 110oc shown in Figure 4A can be used in any of the embodiments described herein and can produce a higher Q (lower loss) output pre-matching because the flip-chip IPD process is typically performed on a high-resistivity silicon substrate, which has lower losses than a MOS capacitor that can be placed under the flip-chip IPD. High-density video bandwidth (VBW) capacitors can still be connected to the output pre-matching IPD 110oc from one of the different locations in package 400.

[0061] Figure 4B is an equivalent circuit diagram of one embodiment of Figure 4A. The output pre-matching network is implemented by a high-Q IPD 110oc and an integrated output capacitor (e.g., implemented by a MIM capacitor C) to provide a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for pre-matching the fundamental frequency f0. The integrated output capacitor C provided by IPD 110oc is connected to package ground via a conductive via 410v (which itself provides a resistor and inductor). The series transmission line 110r in the output IPD 110oc can be selected to provide appropriate impedance transformation from transistor die 105 to drain lead 102d. The input pre-matching network is implemented by conductive wiring structure 314 and input capacitor 104 to provide an LC matching circuit (e.g., a low-pass LC) for the fundamental frequency f0 and a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls). Similarly, a series transmission line 310r can be selected to provide appropriate impedance transformation from transistor die 105 to gate lead 102g.

[0062] FIG5A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention. As shown in FIG5A, the RF power device package 500 includes an active die 105 and an integrated interconnect (illustrated as an IPD or other passive device 110oc) mounted on a package substrate 501. The package substrate 501 is configured to provide attachment surfaces 501s, source leads 102s, and a thermally conductive structure 103 (e.g., a copper block), as in some other embodiments described herein. Similarly, the connection between the gate lead 102g, the capacitor chip 104, and the input of the transistor die 105 is implemented via a conductive wiring structure 314, wherein inductors for input pre-matching networks and harmonic termination are directly implemented in the conductive traces and vias of the wiring structure 314. Furthermore, similar to the embodiment of FIG4A, the passive device providing electrical connection to the active die 105 is only provided on the output side of the package 500, and is implemented by a flip-chip IPD 110oc containing an output capacitor integrated therein, wherein at least one conductive via 410v (e.g., a copper via in the RDL) connects the integrated capacitor to the package ground.

[0063] In the embodiment of FIG5A, in this example, by positioning the package drain lead 102d adjacent to the source / hot lead 102s and between the source / hot lead 102s and the ground node G for the output capacitor, the series connection from the drain pad 105p of the transistor die 105 to the package drain lead 102d is shortened (compared to the embodiment of FIG4A). Therefore, the embodiment of FIG5A can be advantageous because the inductance between the drain pad 105p of the transistor die 105 and the package drain lead 102d can be reduced to a very low value, which can be helpful and / or critical for performance in higher frequency operation (e.g., above 3 GHz operating frequency).

[0064] Figure 5B is an equivalent circuit diagram of one embodiment of Figure 5A, and the input pre-matching network provided by the conductive wiring structure 314 and the input capacitor 104 is similar to the equivalent circuit of Figure 4B. The output pre-matching network is implemented by a flip-chip IPD 110oc, which provides a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) in which the output capacitor C is integrated and connected to the ground lead G via a conductive via 410V.

[0065] As shown in Figures 5A and 5B, since the drain lead 102d is separated from the package 500 between the conductive structure 103 and the output ground lead G, the embodiments described herein provide a package coverage area 500f and PCB circuit designs 515i, 515o to support this topology. Figure 5C is a plan view of the package coverage area 500f of the embodiment of Figure 5A. As shown in Figure 5C, the ground connection to the output capacitor C integrated in the output IPD 110oc is implemented by a plurality of (shown as three) smaller ground leads G opposite to the source / hot lead 102s, with a drain lead 102d between the ground lead G and the source / hot lead 102s. (Several) output ground leads G can be aligned with the corresponding ground vias 515v in an external circuit board 515 (such as an RF circuit board shown in Figure 5D) and the external circuit board 515.

[0066] Specifically, FIG5D is a top plan view of a transparent package 500, showing the bottom side of the package coverage area 500f of FIG5C, and further showing the connection of an input matching circuit board 515i and an output matching circuit board 515o to an external circuit board 515. In some embodiments, the input and output matching circuit boards 515i, 515o may include additional active and / or passive electrical components. The ground lead G may be large enough (e.g., relative to the surface area of ​​the coverage area 500f) to be manufactured, but small enough not to substantially degrade the performance of the output matching circuit board 515o.

[0067] Figures 6A and 6B are cross-sectional views illustrating examples of integrated circuit device packages including stacked topologies according to some embodiments of the present invention. As shown in Figures 6A and 6B, RF power device packages 600a and 600b include active dies 605i, 605o and an integrated interconnect (illustrated as an IPD or other passive device 610) mounted on a substrate 101. As shown in Figure 1B, the substrate 101 is implemented to provide attachment surfaces 101s, source leads 102s and a conductive structure 103 (e.g., a copper block) for transferring heat away from the thermal conductivity (e.g., a heat sink) of the transistor dies 605i, 605o, and the connection provided by the passive device 610 is opposite to (but not within) the attachment surfaces 101s or the substrate 101.

[0068] In the embodiments of Figures 6A and 6B, active dies 605i and 605o define a multi-stage packaged RF power amplifier device (shown by way of example as two stages). For example, active die 605i may be a smaller transistor die for implementing one of the driver stages, and active die 605o may be a larger transistor die 605o for implementing the output of the amplifier or the final stage (e.g., approximately 7 to 10 times larger peripherally than the driver stage transistor die 605i). Transistor dies 605i and 605o are attached to attachment surfaces 101s of a substrate 101 / conductive structure 103 providing source / hot leads 102s, wherein interstage capacitor chips 604 are located between dies 605i and 605o on attachment surfaces 101s. An interstage passive device 610 is attached to the two transistor dies 605i and 605o and provides electrical connection between them.

[0069] Specifically, as shown in Figures 6A and 6B, an IPD 610 is flip-chip mounted on top of transistor chips 605i, 605o and interstage matching capacitor chip 604, such that the bonding pads 610p of the IPD 610 are aligned with the bonding pads 605p and 604p of the transistor chips 605i, 605o and capacitor chip 604. Specifically, the bonding pads 610p of the IPD 610 can contact one or more bonding pads 605p of the driver stage transistor chip 605i that provides a driver drain lead 605d, and one or more bonding pads 605p of the output stage transistor chip 605o that provides an output gate lead 605g. IPD 610 may include conductive bumps 111 (e.g., in some embodiments, conductive epoxy patterns or solder bumps pre-attached to IPD 610) for connecting bonding pads 610p to bonding pads 605p and 604p without wire bonding between them. The top surfaces of capacitor chip 604 and transistor chips 605i and 605o can be aligned to the same height using IPD 610 by grinding the wafer (for a die or capacitor chip) and / or by using preforms 107 of different thicknesses to align the heights of elements 604, 605i, and 605o.

[0070] In the multistage amplifiers of Figures 6A and 6B, IPD 610 includes a passive component that defines an interstage matching network configured to provide impedance matching between the output of driver stage transistor 605i and the input of output stage transistor 605o, i.e., matching the load of driver transistor 605i to the input of final transistor 605o. Although illustrated with reference to two stages 605i and 605o, it will be understood that multiple input or output transistors may exist on attachment surface 101s, with the output of one stage connected to the input of the next stage via its respective IPD 610. The connection from the package leads 102g and 102d to the gate and drain contact pads 605p of the dies 605i and 605o can be implemented by their respective conductive wiring structures (shown as the copper wiring layer and conductive via 614v in RDL 614 in FIG. 6A, and / or as a one-wire connection 14 in FIG. 6B) and / or by input / output impedance matching circuitry and / or harmonic termination circuitry (e.g., using integrated interconnects 110i / 110o), as described herein.

[0071] Figure 6C is an equivalent circuit diagram of one embodiment of Figures 6A and 6B. As shown in Figure 6C, the interstage matching network is implemented by capacitor 604 and passive device 610 to provide a shunt-L pre-matching network Ls at the output of driver stage transistor 605i and the input of last stage transistor 605o, and a series LCL network connecting the driver and last stage transistors 605i and 605o. This topology can provide a wideband response for a multi-stage RF power amplifier product. It will be understood that the interstage impedance matching network between transistors 605i and 605o shown in Figure 6C is only an example, and the interstage passive device 610 providing electrical connection between two or more active chips according to embodiments of the present invention may include or implement other network topologies.

[0072] FIG7A is a cross-sectional view illustrating one example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention. As shown in FIG7A, an RF power device package 700 includes active dies 605i, 605o and an integrated interconnect (illustrated as an IPD or other passive device 610c) mounted on a substrate 101. As in FIG6A, the substrate 101 is implemented to provide attachment surfaces 101s, source leads 102s and a conductive structure 103 (e.g., a copper block) for transferring heat away from the thermal conductivity (e.g., a heat sink) of the transistors 605i, 605o, and the active dies 605i, 605o define a multi-stage packaged RF power amplifier device. The primary passive device 610c is attached (shown as flip-chip mounted) to its bonding pad 610p and the bonding pad 605p of the two transistor chips 605i, 605o and provides electrical connection between them.

[0073] In Figure 7A, the interstage matching capacitor 604 is not positioned below the interstage IPD 610c; in fact, the capacitor is integrated into the IPD 610c, for example, as a MIM capacitor. One or more conductive vias 610v connect the ends of the integrated capacitor to, for example, a package ground provided by conductive structure 103. In some embodiments, the conductive vias 610v may be implemented via copper vias in an RDL. Thus, the IPD 610c includes the matching capacitor integrated therein to provide an interstage matching network configured to provide impedance matching between two or more amplifier stages implemented by transistor chips 605i and 605o.

[0074] Figure 7B is an equivalent circuit diagram of one embodiment of Figure 7A. As shown in Figure 7B, similar to the embodiment of Figure 6C, the interstage matching network is implemented by a passive device 610c to provide a shunt-L pre-matching network Ls having a MIM or other integrated capacitor C at the output of the driver stage transistor 605i and the input of the last stage transistor 605o, and a series LCL network connecting the driver and the last stage transistors 605i and 605o.

[0075] Figures 8A and 9A are cross-sectional views illustrating examples of sub-components of integrated circuit device packages including stacked topologies according to some embodiments of the present invention. As shown in Figures 8A and 9A, RF power device packages 800 and 900 each include an active die 105 and an integrated interconnect (illustrated as an IPD or other passive device 110i, 110c) mounted on a package substrate 201. Packages 800 and 900 include the components and connections shown in the embodiments illustrated in Figures 2A and 2B, wherein the substrate 201 is implemented to provide an attachment surface 201s, source leads 102s, and a conductive structure 103 (e.g., a copper block) providing thermal conductivity and (in some embodiments) a ground connection. Passive devices 110i and 110c are located only on the input side of packages 800 and 900 to provide electrical connection between a conductive pad 105p of the active die 105 and a gate lead 102g of the package via solder bumps 111, without wire bonding between them. Passive devices 110i and 110c (shown as a flip-chip IPD) implement an input pre-matching network for a transistor circuit implemented by the active die 105, as in the embodiments of Figures 2A and 2B.

[0076] In FIG8A, a capacitor chip 104 (e.g., a MOS capacitor) for the input matching network is disposed on the attachment surface 201s adjacent to the transistor die 105 and below the IPD 110i. The bonding pads 105p and 104p of the transistor die 105 and the capacitor chip 104 are connected to the bonding pad 110p of the IPD 110i by their respective solder bumps 111, without any wire bonding between them.

[0077] In Figure 9A, the input capacitor is integrated into the flip-chip input IPD 110c, for example as a metal-insulator-metal (MIM) capacitor, and one or more conductive vias 110v (e.g., copper vias in an RDL) are used to connect the integrated capacitor to, for example, a package ground provided by conductive structure 103. Specifically, one end of an integrated MIM capacitor (cap) can be connected to an electrically grounded copper block 103 via a copper via 110v or post built into the laminate around the die. The inductance required for pre-matching or harmonic termination at the input side of the transistor die 105 can be partially or entirely incorporated into the copper via / post to provide a high-Q, low-loss inductance.

[0078] In Figures 8A and 9A, the bonding pads 110p of IPDs 110i and 110c are directly connected to the gate lead 102g, with no conductive wiring structure between them. Similarly, the output of transistor 105 can be directly connected to the drain lead 102d. By connecting the drain and gate leads 102d and 102g to the package leads using wire bonding or copper wiring in an RDL, packages 800 and 900 can be used as sub-components in a packaged RF power product. The drain lead 102d can also be connected to an additional output pre-matching network (e.g., by conductive wiring structures (such as copper wiring or wire bonding in an RDL shown in Figures 2A and 2B) or by IPDs shown in Figures 1A and 1B) before being connected to the package output leads.

[0079] Figures 8B and 9B are equivalent circuit diagrams illustrating the embodiments of Figures 8A and 9A, respectively. Similar to the embodiment of Figure 2C, one of the inductors L and Ls is configured in IPDs 110i and 110c to provide an impedance pre-matching network for the transistor configuration of the active die 105. Specifically, IPDs 110i and 110c and the input capacitor (implemented by the external capacitor chip 104 in Figure 8B (e.g., a MOS capacitor); and the integrated capacitor C in Figure 9B (e.g., a MIM capacitor)) provide an LC matching circuit (e.g., a low-pass LC) for the fundamental frequency f0, and a shunt-L inductor Ls matching circuit (e.g., a high-pass Ls) for optimally terminating one or more harmonic frequencies (e.g., 2f0). In Figure 9B, the capacitors that may be needed for pre-matching and harmonic termination are integrated into IPD 110c.

[0080] Figures 10A and 10B are plan and perspective views, respectively, illustrating examples of high-Q IPDs 110, 610 providing impedance matching and integrated interconnects according to some embodiments of the present invention. In the examples of Figures 10A and 10B, a coil inductor Ls is used to implement the precise value of the shunt-L inductance required for proper pre-matching of the transistor. The shape, width, and overall design of the coil inductor Ls can be optimized to reduce losses. One end of the coil inductor Ls terminates on a bump or contact pad 110pl, which may be pre-attached with a conductive bump (e.g., 111) for attachment to a capacitor (e.g., 104) for pre-matching or a high-density capacitor (e.g., 106) for improving video bandwidth. The width of the series connection strip L used to implement the series inductor can be configured to provide the desired impedance transformation from the transistor die to the drain lead. Series connection strips L may extend between bumps or contact pads 110p and can be considered as an extension of the board transmission line matching network, and the width of each series connection strip L can be configured to provide a desired characteristic impedance. More generally, any passive device described herein may include or be implemented using series connection strips L coupled between contact pads 110p to provide electrical connections between contact pads 105p of one or more active dies 105, and / or between a contact pad 105p of an active die 105 and a package lead 102 (other than impedance transformation between them). Similarly, any passive device described herein may include or be implemented using coil inductors Ls configured to be connected to capacitors (e.g., connected to a capacitor integrated therein or an external capacitor via contact pads 110pl).

[0081] Figures 11 and 12 are cross-sectional views illustrating examples of thermally enhanced integrated circuit device packages including a stacked topology according to further embodiments of the present invention. For clarity, the feature dimensions in Figures 11 and 12 are enlarged. As shown in Figures 11 and 12, RF power device packages 1100, 1200 include components 104, 105, 106, 110 and connections similar to packages 100a, 100b and 100c of Figures 1A, 1B and 1C, but mounted on a conductive substrate or flange 1101, 1201 and protected by a cover member 1113, 1213 of the thermally enhanced package instead of a plastic overmolded member 113. Specifically, Figure 11 illustrates a first embodiment of a thermally enhanced package according to an embodiment of the present invention (referred to as a TEPAC package 1100), and Figure 12 illustrates a second embodiment (referred to as a T3PAC package 1200).

[0082] The TEPAC package 1100 of Figure 11 may be a ceramic-based package comprising a substrate 1101 and an upper housing, the upper housing comprising a cover member 1113 and a sidewall member 1104. The cover member 1113 and / or the sidewall 1104 may comprise a ceramic material (e.g., alumina) and may define an open cavity surrounding components 104, 105, 106, 110 on the conductive substrate or flange 1101. The conductive substrate or flange 1101 provides both an attachment surface 1101s for components 104, 105, 106, 110 and thermal conductivity (e.g., a heat sink) for dissipating or otherwise transferring heat generated by these components to the outside of the package 1100.

[0083] The T3PAC package 1200 of Figure 12 can also be a ceramic-based package comprising a substrate 1201 and an upper housing having a cover member 1213 and a sidewall member 1204. Similarly, the cover member 1213 and the sidewall 1204 define an open cavity surrounding components 104, 105, 106, 110 on the conductive substrate or flange 1201, which similarly provides both an attachment surface 1201s and thermal conductivity (e.g., a heat sink) for dissipating heat or otherwise transferring it to the outside of the package 1200. In the package 1200, the cover member 1213 can be a ceramic material (e.g., alumina), while the sidewall member 1204 is illustrated as a printed circuit board (PCB).

[0084] In Figures 11 and 12, flanges 1101 and 1201 may be a conductive material, such as a copper layer / laminate or an alloy or other metal-based composite material. In some embodiments, flange 1101 may comprise a copper-molybdenum (CuMo) layer, CPC (Cu / MoCu / Cu) or other copper alloys, such as copper-tungsten (CuW), and / or other laminated / multilayer structures. In the example of Figure 11, flange 1101 is illustrated as a sidewall 1104 and / or cover member 1113 attached to a CPC-based structure. In the example of Figure 12, flange 1201 is illustrated as a sidewall 1204 and / or cover member 1213 attached, for example, to a copper-molybdenum (RCM60)-based structure via a conductive adhesive 1208.

[0085] In Figures 11 and 12, the active die 105, the passive device (e.g., capacitor chips 104 and 106), and the integrated interconnect (collectively referred to as 110) are attached to the attachment surfaces 1101s and 1201s of the flanges 1101 and 1201 via their respective conductive die attachment material layers 107. The flanges 1101 and 1201 also provide source leads 102s for the packages 1100 and 1200. The gate lead 102g and the drain lead 102d are provided by their respective conductive wiring structures 1114 and 1214, which are attached to the flanges 1101 and 1201 and supported by their respective sidewall components 1104 and 1204.

[0086] The thickness of the sidewall components 1104, 1204 can result in a height difference between the components 104, 105, 106, 110 and the package leads 102g, 102d relative to the attachment surfaces 1101s, 1201s. For example, the combined height of the active die 105 and its integrated interconnects 110i, 110o relative to the attachment surface 1101s can be about 100 µm, while the gate and drain leads 102g and 102d can be separated from the attachment surface 1101s by a distance of about 635 µm. Therefore, in the examples of Figures 11 and 12, the respective wire connections 14 are used to connect the package leads 102g, 102d to the contact pads 104p, 106p of the passive RF components 104, 106 on the attachment surfaces 1101s, 1201s. Therefore, an RF signal input to lead 102g can be transmitted through wire junction 14 to input matching circuits 110i, 104 and to a gate terminal 105p of RF transistor amplifier chip 105, and the amplified output RF signal can be transmitted from the drain terminal 105p of RF transistor amplifier chip 105 to output matching circuits 110o, 106, and from there to junction 14 for output through lead 102d. However, it will be understood that in other embodiments, wire junction 14 may be omitted and different electrical connections may be used.

[0087] A further advantage of the integrated circuit device package incorporating a stacked topology according to embodiments of the present invention is that the stacked interconnect structure allows for a thinner or lower-height package compared to some conventional designs. In overlay molding package embodiments (e.g., as shown in Figures 1 to 9), the routing of package leads at the bottom of the package also allows for package flexibility. For example, variations in the height and / or spacing of the package leads can be accommodated by modifying the layout of traces on the circuit board / PCB based on a modified package coverage area. Thermally enhanced package embodiments (e.g., as shown in Figures 11 to 12) offer similar advantages, but may require variations in package dimensions (e.g., flange height and / or package lead spacing) relative to standardized dimensions.

[0088] Therefore, in embodiments of the present invention, electrical connections between components (e.g., between circuit-level components, such as between contact pads of one or more active transistors, and / or between contact pads of active transistors and the gate and / or drain leads of the package) are implemented by physically extending one or more integrated interconnect structures (e.g., conductive wiring structures and / or passive devices, such as IPDs) between components, rather than by wire bonding. That is, the integrated interconnect provides both an interconnect and an impedance matching / harmonic termination function, thereby reducing or eliminating the use of wire bonding in the package.

[0089] As described herein, some embodiments of the present invention utilize a high-Q IPD "flipped" on top of the transistor and capacitor. The additional height of the packaged IPD above the ground plane (e.g., provided by a conductive structure that may also define the attachment surface of the active die) results in higher Q and lower loss pre-matching. The majority of the space beneath the flipped IPD can be used for capacitors, such as high-density capacitors typically used on outputs. Larger capacitance values ​​can be used in the available space, thus improving the video bandwidth of the device. To connect RF signals from the IPD back to the RDL and gate / drain leads, a copper filler or IPD with TSV can be used. The tops of the MOS capacitor and transistor die can be aligned to the same height by grinding the wafer (die or capacitor) to a similar height, or by using preforms of different thicknesses to align the height. The IPD can be configured for both pre-matching the fundamental frequency and optimally terminating one or more harmonic frequencies.

[0090] In this document, a transistor die (e.g., 105) is illustrated in cross-section with reference to an example in which a gate and drain pad (e.g., 105p) are on a top / upper surface of a semiconductor layer structure and a source pad is on a bottom / lower surface. In some embodiments, a top-side metallization structure of the transistor die may include a plurality of gate, drain, and / or source "fingers" that can be connected by one or more respective buses.

[0091] Figure 13 is a cross-sectional view taken along line A-A' of Figure 1A through a portion of the top metallized structure of the die 105. As shown in Figure 13, the transistor die 105 includes a semiconductor layer structure 130, which has a plurality of unit cell transistors 116 disposed in the upper part of the semiconductor layer structure 130. Gate fingers 152, drain fingers 154, and source fingers 156 (and connecting buses) define the gate, drain, and source connection electrodes of the die 105, respectively. The gate fingers 152 may be formed of a material (such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN) capable of forming a Schottky contact with a group III nitride-based semiconductor material. The drain fingers 154 and / or source fingers 156 may comprise a metal (such as TiAlN) capable of forming an ohmic contact with a group III nitride-based material. Gate fingers 152 may be electrically connected to each other via a gate bus 146, and drain fingers 154 may be electrically connected to each other via a drain bus 148. For better illustration, one or more dielectric layers that help isolate the gate, drain, and source connection structures from each other are not shown.

[0092] Figure 13 also shows one of the unit cell transistors 116. As shown, the unit cell transistor 116 includes a gate finger 152, a drain finger 154, and a source finger 156, as well as a lower layer of the semiconductor layer structure 130. Since the gate finger 152 is electrically connected to a common gate bus 146, the drain finger 154 is electrically connected to a common drain bus 148, and the source finger 156 is electrically connected together via a conductive electrode via 166 and a source pad, it can be seen that all the unit cell transistors 116 are electrically connected together in parallel.

[0093] Embodiments of the present invention can be built on a substrate or laminate (e.g., a re-laid layer (RDL) laminate) and assembled in batches using modern enhanced wafer-level packaging technology. Multiple components can be built at once, thereby reducing assembly time, cost, and yield issues. Additionally, wire bonding processes can be reduced or eliminated, saving time and cost. For example, using a high-density copper-filled array or embedded copper block to effectively remove heat (because typical hollow or partially filled vias are insufficient for high-power RF applications), heat generated by transistor chips can be effectively removed and conducted to a heat sink outside the package. Embodiments of the present invention can be used, for example, in various Cellular Infrastructure (CIFR) RF power products (including but not limited to 5 W, 10 W, 20 W, 40 W, 60 W, 80 W, and different frequency bands) for 5G and base station applications. Embodiments of the present invention can also be applied to radar and single-crystal microwave integrated circuit (MMIC) type applications.

[0094] Various embodiments have been described herein with reference to the accompanying drawings, which illustrate exemplary embodiments. However, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. In fact, these embodiments are provided so that the invention is thorough and complete and fully conveys the inventive concept to those skilled in the art. Various modifications to the exemplary embodiments and general principles and features described herein will be readily apparent. In the drawings, the sizes and relative sizes of layers and regions are not shown to scale and may be enlarged in some examples for clarity.

[0095] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, such elements should not be limited by such terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the invention, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0096] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" as used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0097] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and related art, and shall not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0098] It will be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element," "attached to another element," or "extending to another element," it may be directly on the other element or an intermediate element may be present. In contrast, when an element is referred to as "directly on another element," "directly attached to another element," or "directly extending to another element," no intermediate element is present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected to or coupled to that other element or an intermediate element may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate element is present.

[0099] Relative terms such as “below” or “above” or “up” or “down” or “horizontal” or “lateral” or “vertical” may be used herein to describe the relationship between one element, layer or region and another element, layer or region as illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, these terms are also intended to cover different orientations of the device.

[0100] Embodiments of the invention are described herein with reference to cross-sectional drawings, which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be enlarged for clarity. Furthermore, variations in the shapes depicted should be anticipated due to factors such as manufacturing techniques and / or limitations. Therefore, embodiments of the invention should not be construed as limited to specific shapes of the regions depicted herein, but should include shape deviations, for example, due to manufacturing processes. In the illustrated embodiments, elements depicted by dashed lines may be optional.

[0101] In various places, the same numbers refer to the same components. Therefore, even if the same or similar numbers are not mentioned or described in the corresponding diagrams, they can be described in other diagrams. Furthermore, components not represented by component symbols can be described in other diagrams.

[0102] Typical embodiments of the present invention have been disclosed in the drawings and description, and although specific terms are used, such specific terms are used only in a general and descriptive sense and not for limiting purposes. The scope of the present invention is set forth in the following patent application scope. [Simplified Explanation of the Diagram]

[0103] Figures 1A, 1B and 1C are cross-sectional views illustrating examples of integrated circuit device packages including stacked topologies according to some embodiments of the present invention.

[0104] Figure 1D is an equivalent circuit diagram of one of the embodiments of Figures 1A, 1B and 1C.

[0105] Figures 2A and 2B are cross-sectional views illustrating examples of integrated circuit device packages including stacked topologies according to some embodiments of the present invention.

[0106] Figure 2C is an equivalent circuit diagram of one of the embodiments of Figures 2A and 2B.

[0107] FIG3A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention.

[0108] Figure 3B is an equivalent circuit diagram of one embodiment of Figure 3A.

[0109] FIG4A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention.

[0110] Figure 4B is an equivalent circuit diagram of one embodiment of Figure 4A.

[0111] FIG5A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention.

[0112] Figure 5B is an equivalent circuit diagram of one embodiment of Figure 5A.

[0113] FIG5C is a bottom plan view illustrating one of the encapsulation coverage areas of FIG5A according to some embodiments of the present invention.

[0114] FIG5D is a top plan view illustrating one of the packaging coverage areas of FIG5C according to some embodiments of the present invention.

[0115] Figures 6A and 6B are cross-sectional views illustrating examples of integrated circuit device packages including stacked topologies according to some embodiments of the present invention.

[0116] Figure 6C is an equivalent circuit diagram of one of the embodiments of Figures 6A and 6B.

[0117] FIG7A is a cross-sectional view illustrating an example of an integrated circuit device package including a stacked topology according to some embodiments of the present invention.

[0118] Figure 7B is an equivalent circuit diagram of one embodiment of Figure 7A.

[0119] Figures 8A and 9A are cross-sectional views illustrating examples of sub-components of an integrated circuit device package including a stacked topology according to some embodiments of the present invention.

[0120] Figures 8B and 9B are equivalent circuit diagrams of the embodiments of Figures 8A and 9A, respectively.

[0121] Figures 10A and 10B are plan views and perspective views respectively illustrating examples of high Q IPD according to some embodiments of the present invention.

[0122] Figures 11 and 12 are cross-sectional views illustrating examples of thermally enhanced integrated circuit device packages including stacked topologies according to further embodiments of the present invention.

[0123] Figure 13 is a cross-sectional view taken through a portion of the top-side metallized structure of Figure 1A.

Claims

1. An integrated circuit device package comprising: One substrate; A first die, which includes active electronic components attached to the substrate; and at least one integrated interconnect structure on the first die and opposite to the substrate, the at least one integrated interconnect structure extending from the first die to at least one package lead or to one or more passive components, and providing electrical connection between them.

2. An integrated circuit device package as claimed in claim 1, wherein the electrical connection does not have a wire connection.

3. As in claim 1, an integrated circuit device package, wherein: The first die includes a first bonding pad on one surface of the first die opposite to the substrate, the first bonding pad being electrically connected to one or more of the active electronic components; and the at least one integrated interconnect structure includes a contact pad on the first bonding pad.

4. The integrated circuit device package of claim 3, wherein the at least one integrated interconnect structure includes a conductive wiring pattern on a relay layer.

5. An integrated circuit device package as claimed in claim 3, wherein the at least one integrated interconnect structure includes at least a portion of an impedance matching network for a circuit defined by the active electronic components of the first die.

6. The integrated circuit device package of claim 5, wherein the at least one integrated interconnect structure includes a passive device comprising one or more passive electronic components.

7. The integrated circuit device package of claim 6, wherein the contact pad is a second bonding pad on one of the surfaces of the passive device facing the first die, the second bonding pad being electrically connected to the one or more passive electronic components, wherein the second bonding pad is connected to the first bonding pad by a conductive bump between the second bonding pad and the first bonding pad.

8. An integrated circuit device package comprising: One substrate; A first die includes active electronic components attached to the substrate; and at least one integrated interconnect structure on the first die and opposite to the substrate, the at least one integrated interconnect structure extending from the first die to a neighboring die attached to the substrate and / or toward at least one package lead, and providing electrical connection between them; wherein the active electronic components of the first die define a first radio frequency (RF) amplifier circuit, wherein the neighboring die includes active electronic components defining a second RF amplifier circuit, and wherein the first and second power amplifier circuits are connected by the passive device to form a multi-stage amplifier configuration.

9. An integrated circuit device package as claimed in claim 6, wherein the passive device includes an integrated passive device (IPD) containing at least one inductor and without active electronic components.

10. An integrated circuit device package as claimed in claim 9, wherein the IPD includes an insulating material between its conductive elements to define at least one capacitor integrated therein.

11. An integrated circuit device package comprising: One substrate; A first die includes an active electronic component attached to the substrate; and at least one integrated interconnect structure on the first die and opposite to the substrate, the at least one integrated interconnect structure extending from the first die to a neighboring die attached to the substrate and / or toward at least one package lead, and providing electrical connection between them, wherein: the neighboring die includes one or more capacitors and at least one capacitor bonding pad on a surface of the neighboring die opposite to the substrate; the contact pad of the at least one integrated interconnect structure is a first contact pad; and the at least one integrated interconnect structure further includes at least one second contact pad on the at least one capacitor bonding pad.

12. An integrated circuit device package as claimed in claim 11, wherein the at least one package lead includes a gate lead and the first bonding pad is a gate pad, wherein the adjacent die is between the first die and the gate lead, and wherein the at least one integrated interconnect structure includes at least a portion of an input impedance matching network for one of the circuits defined by the active electronic components of the first die.

13. An integrated circuit device package as claimed in claim 11, wherein the at least one package lead includes a drain lead and the first bonding pad is a drain pad, wherein the adjacent die is between the first die and the drain lead, and wherein the at least one integrated interconnect structure includes at least a portion of an output impedance matching network for one of a circuits defined by the active electronic components of the first die.

14. An integrated circuit device package as claimed in claim 1, wherein the active electronic components include power transistor devices, and wherein the first die includes group III nitride and / or silicon carbide.

15. A radio frequency (RF) power amplifier device package comprising: One substrate; A first die comprising a plurality of transistor cells, attached to the substrate at a source pad on a bottom surface thereon and including a gate or drain pad on a top surface thereon opposite the substrate; package leads configured to conduct electrical signals between the gate or drain pad of the first die and an external device; and an integrated interconnect structure on the first die and opposite the substrate, the integrated interconnect structure including a first contact pad on the gate or drain pad and at least one second contact pad on a neighboring die attached to the substrate and / or coupled to one of the package leads.

16. The RF power amplifier device package of claim 15, wherein the integrated interconnect structure provides an electrical connection from the gate or drain pad of the first die to the adjacent die and / or to one of the package leads, wherein the electrical connection does not have a wire connection.

17. The RF power amplifier device package of claim 15, wherein the integrated interconnect structure includes a conductive wiring pattern on a redistribution layer, or is a passive device containing one or more passive electronic components.

18. The RF power amplifier device package of claim 17, wherein the integrated interconnect structure includes at least a portion of an impedance matching network for a circuit defined by the isoelectric transistor of the first die.

19. The RF power amplifier device package of claim 18, wherein the first contact pad is a bonding pad on one of the top surfaces of the passive device facing the first die, the bonding pad being electrically connected to the one or more passive electronic components, wherein the bonding pad is connected to the gate or drain pad by a conductive bump between the bonding pad and the gate or drain pad.

20. The RF power amplifier device package of claim 17, wherein the adjacent die includes at least one bonding pad on one of its surfaces opposite the substrate, and the at least one second contact pad is on the at least one bonding pad, wherein: The adjacent die includes one or more capacitors; or the adjacent die includes a plurality of transistor units defining a stage of an RF amplifier circuit.

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