Method of forming the semiconductor device

Abstract

This document discloses a method for forming a semiconductor device. According to this disclosure, the method includes: etching a semiconductor substrate to form trenches and semiconductor strips, wherein the sidewalls of the semiconductor strips are exposed in the trenches; depositing a silicon-containing layer extending into the trenches, wherein the silicon-containing layer extends on the sidewalls of the semiconductor strips; filling the trenches with a dielectric material, wherein the dielectric material is located on the sidewalls of the silicon-containing layer; oxidizing the silicon-containing layer to form a first liner, wherein the first liner includes oxidized silicon, and wherein the first liner and the dielectric material form multiple portions of an isolation region; and etching an isolation region, wherein a portion of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to a method for forming a semiconductor device having Fin Field-Effect Transistors (FinFETs). [Previous Technology]

[0002] Transistors are fundamental building blocks in integrated circuits. Along the development path of integrated circuits, finned field-effect transistors (FinFETs) have been formed to replace planar transistors. The formation of a FinFET involves forming an isolation region extending into the semiconductor substrate and etching the isolation region to form semiconductor fins. A dummy gate is formed on the semiconductor fins, followed by the formation of source / drain regions. The dummy gate stack is then removed to form trenches between gate spacers. An alternative gate is then formed in the trenches. [Summary of the Invention]

[0003] Embodiments of the present invention provide a method for forming a semiconductor device, comprising: etching a semiconductor substrate to form a trench and a semiconductor strip, wherein the sidewalls of the semiconductor strip are exposed in the trench; depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewalls of the semiconductor strip; filling the trench with a dielectric material, wherein the dielectric material is located on the sidewalls of the silicon-containing layer; oxidizing the silicon-containing layer to form a first liner, wherein the first liner includes oxidized silicon, and wherein the first liner and the dielectric material form multiple parts of an isolation region; and etching an isolation region, wherein a portion of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin.

[0004] Embodiments of the present invention provide a method for forming a semiconductor device, comprising: etching a semiconductor substrate to form a semiconductor strip and a trench, wherein the semiconductor strip is located on one side of the trench and has a first longitudinal direction parallel to a second longitudinal direction of the trench, wherein the semiconductor strip includes silicon and germanium, and exposes the sidewalls of the semiconductor strip; depositing a first liner extending into the trench and contacting the sidewalls of the semiconductor strip, wherein the first liner includes silicon oxide; depositing a second liner on the first liner, wherein the second liner includes silicon, the second liner extending from the top surface of the semiconductor substrate to the bottom of the trench; depositing a dielectric material to fill the trench, wherein a portion of the second liner is located below the dielectric material; curing the dielectric material to form an oxide layer; and converting the second liner into a third liner.

[0005] Embodiments of the present invention provide a method for forming a semiconductor device, comprising: depositing a silicon-containing substrate in a trench of a semiconductor substrate; oxidizing the silicon-containing substrate to form a first oxidized silicon substrate, such that the volume ratio of the first oxidized silicon substrate to the volume of the silicon-containing substrate is greater than 0 and not greater than 2.25; depositing a dielectric material in the trench, wherein the first oxidized silicon substrate includes a first portion below the dielectric material, and the dielectric material and the first oxidized silicon substrate form a plurality of isolation regions; etching the isolation regions, wherein protruding semiconductor fins are formed in a portion of the semiconductor substrate between the etched isolation regions; forming a gate dielectric extending above the isolation regions; and forming a gate electrode above the gate dielectric.

Implementation Method

[0006] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0008] According to some embodiments, this disclosure provides an isolation region, an isolation region-based fin field-effect transistor (FinFET), and a method for forming the same. Various stages of forming the isolation region and the fin field-effect transistor (FinFET) are illustrated according to some embodiments. Some variations are within the scope of discussion. In various views and exemplary embodiments, the same element symbols are used to denote the same elements. According to some embodiments of this disclosure, a silicon liner is formed, and then it is oxidized to a silicon oxide liner during an annealing process. When the silicon liner is oxidized to a silicon oxide liner, the volume increases. Due to the aforementioned oxidation, beneficial strain is generated in the channel of the final fin field-effect transistor (FinFET). Therefore, protection of the SiGe channel, additional tensile strain, and reduction of charge trapping can be achieved by introducing a shallow trench isolation (STI) oxide liner.

[0009] Figures 1-4, 5A, 5B, 6-15, 16A, and 16B, according to some embodiments of this disclosure, illustrate perspective views and cross-sectional views of various stages in the formation of the isolation region (or STI region) and the FinFET. The corresponding processes are also schematically reflected in process flow 200, as shown in Figure 17.

[0010] Figure 1 illustrates a perspective view of the initial structure. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be formed of silicon, silicon-germanium, carbon-doped silicon, or a multilayer thereof. According to some embodiments of this disclosure, the illustrated area is a p-type device region in which a p-type transistor, such as a p-type fin field-effect transistor (FinFET), will be formed. The substrate 20 may include a substrate (partial) 20-1 and an epitaxial semiconductor layer 20-2 above the substrate 20-1. The substrate 20-1 may be a bulk substrate or a semiconductor-on-insulator (SIO) substrate. According to some embodiments, the silicon substrate 20-1 may be germanium-free, or may include silicon-germanium with a germanium percentage lower than the germanium percentage in the epitaxial semiconductor layer 20-2 (e.g., lower than about 10%). The epitaxial semiconductor layer 20-2 may be epitaxially grown on top of the substrate 20-1 (which may be a silicon substrate) to form the substrate 20. As shown in Figure 17, in process flow 200, process 202 illustrates the corresponding process. According to some embodiments of this disclosure, the epitaxial semiconductor layer 20-2 is formed of silicon germanium (SiGe) or germanium (which does not contain silicon). The percentage of germanium atoms in the epitaxial semiconductor layer 20-2 is higher than the percentage of germanium atoms in the substrate portion 20-1. According to some embodiments of this disclosure, the atomic percentage in the epitaxial semiconductor layer 20-2 is in the range of about 30% to 100%. The epitaxial semiconductor layer 20-2 may also be formed of SiP, SiC, SiPC, SiGeB, or III-V compound semiconductors, such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like.

[0011] According to an alternative embodiment of this disclosure, an n-type device is provided on the same wafer, wherein an n-type transistor, such as an n-type fin field-effect transistor (FinFET), will be formed. The substrate in the n-type device region may include a silicon substrate (e.g., the same as 20-1), and the epitaxial layer 20-2 may not be formed on the silicon substrate.

[0012] A hard mask layer 22 is formed on the semiconductor substrate 20. As shown in Figure 17, in process flow 200, process 204 illustrates the corresponding process. According to some embodiments, the hard mask layer 22 includes a hard mask (sub) layer 22A and a hard mask (sub) layer 22B above the hard mask layer 22A. The hard mask layer 22A may be a thin film formed of silicon oxide and is sometimes referred to as a pad oxide layer. According to some embodiments of this disclosure, the pad oxide layer 22A is formed by a deposition process, which may include chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. According to an alternative embodiment, the pad oxide layer 22A is formed by a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 22A serves as an adhesive layer between the semiconductor substrate 20 and the hard mask layer 22B. The hard mask layer 22A can also serve as an etch stop layer for etching the hard mask layer 22B. According to some embodiments disclosed herein, for example, the hard mask layer 22B is formed of silicon nitride. The formation methods described above may include low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The hard mask layer 22B serves as a hard mask during subsequent lithography processes.

[0013] According to an alternative embodiment, the hard mask layer 22 is formed of a homogeneous material in contact with the substrate 20. For example, the homogeneous material may include silicon nitride or similar materials such as SiCN, SiOC, etc. According to another alternative embodiment, the hard mask layer 22 includes a silicon layer 22C, a pad oxide layer 22A above the silicon layer 22C, and a hard mask layer 22B above the pad oxide layer 22A. The silicon layer 22C can be formed by deposition, for example using chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The silicon layer 22C may be a crystalline silicon layer.

[0014] Referring to Figure 2, the patterned hard mask layer 22 is etched, for example, by using a patterned photoresist (not shown) as an etch mask to expose the underlying semiconductor substrate 20. The exposed semiconductor substrate 20 is then etched using the patterned hard mask layer 22 as an etch mask to form trenches 26. As shown in Figure 17, in process flow 200, process 206 illustrates the corresponding process. The portions of the semiconductor substrate 20 between adjacent trenches 26 are hereinafter referred to as semiconductor strips 30. Some portions of the trenches 26 may have stripes parallel to each other (when viewed from the top view of the wafer 10), and the trenches 26 may be located close to each other. According to some embodiments of this disclosure, the aspect ratio (depth to width ratio) of the trenches 26 is greater than about 7 and may be greater than about 10. Although one semiconductor strip 30 is shown, multiple semiconductor strips 30 may be formed parallel to each other, with the trenches 26 separating the multiple semiconductor strips 30 from each other. According to some embodiments in which an epitaxial semiconductor layer 20-2 is formed, the bottom of the trench 26 is below the interface 23 between the substrate portion 20-1 and the epitaxial semiconductor layer 20-2.

[0015] Referring to Figure 3A, an oxide layer 32 is formed according to some embodiments of the present disclosure. As shown in Figure 17, process 208 illustrates the corresponding process in process flow 200. Throughout the description, the oxide layer 32 is also referred to as a silicon oxide substrate. According to some embodiments, the oxide layer 32 is formed by conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. Therefore, the oxide layer 32 has horizontal and vertical portions, the thickness T1 of the horizontal portion and the thickness T1' of the vertical portion being equal to or substantially equal to each other. For example, the absolute value of the ratio (T1'-T1) / T1 may be less than about 0.2% or less than about 0.1%. When using atomic layer deposition (ALD), the precursor, such as dichlorosilane (DCS, SiH₂Cl₂), silane (SiH₄), ethylene silane (Si₂H₆), hexamethyl ethylene silane (HMDS), etc., can be pulsed first, then purged. Subsequently, another process gas, such as O₂, O₃, etc., is pulsed and purged to deposit an atomic layer of silicon oxide. The two types of gases are alternately pulsed and purged to increase the thickness of the oxide layer to the desired value. The oxide layer 32 is thick enough to act as an effective barrier protecting the semiconductor strip 30 from oxidation, making the oxidation of the subsequently deposited silicon layer 34 easier to control. On the other hand, the oxide layer 32 cannot be too thick. Otherwise, the strain generated by the oxidation of the subsequently deposited silicon layer 34 cannot be effectively applied to the semiconductor strip 30. According to some embodiments, the thicknesses T1 and T1' of the oxide layer 32 are in the range of about 5 Å and about 15 Å. The atomic layer deposition (ALD) process can be a thermal atomic layer deposition (ALD) process, for example, performed at a temperature in the range of about 250°C to 450°C. When using chemical vapor deposition (CVD), precursors such as silane, ethylene silane, HMDS, DCS, O2, O3, etc., can be used. According to some embodiments of this disclosure, a silicon oxide layer is used as a barrier instead of a silicon nitride layer. Silicon nitride layers have a high density of traps (DIT) and are prone to trapping charge, resulting in higher leakage current, and are therefore not used; instead, a silicon oxide layer with a lower density of traps (DIT) and a higher bandgap is used.

[0016] Referring further to Figure 3A, according to some embodiments of this disclosure, a silicon layer 34 is deposited on an oxide layer 32. Throughout the description, the silicon layer 34 may be alternatively referred to as a silicon substrate. As shown in Figure 17, in process flow 200, process 210 illustrates the corresponding process. The above deposition can be performed by conformal deposition processes, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). When using atomic layer deposition (ALD), precursors, such as DCS, silane, ethylene silane, HMDS, etc., can be pulsed and purged, followed by pulsed and purged another process gas, such as H2. The two types of gases are pulsed and purged alternately to increase the thickness of the silicon layer to the desired value. Atomic layer deposition (ALD) processes can be thermal ALD processes, for example, performed at temperatures ranging from approximately 350°C to 500°C. When using chemical vapor deposition (CVD), precursors such as silane, ethylene silane, HMDS, DCS, H₂, etc., can be used.

[0017] Silicon layer 34 may contain no or substantially no other elements, such as germanium, carbon, etc. For example, the atomic percentage of silicon in silicon layer 34 may be higher than about 95% or higher than about 99%. Silicon layer 34 can be formed as an amorphous silicon layer or a polycrystalline silicon layer, for example, by adjusting the temperature and growth rate during the deposition process.

[0018] Silicon layer 34 has horizontal and vertical portions, the thickness T2 of the horizontal portion and the thickness T2' of the vertical portion being equal to or substantially equal to each other. For example, the absolute value of the ratio (T2'-T2) / T2 can be less than about 0.2% or less than about 0.1%. The thicknesses T2 and T2' of silicon layer 34 can be greater than about 0.5 nm to generate sufficient strain during subsequent oxidation of silicon layer 34. On the other hand, the thicknesses T2 and T2' cannot be too high to avoid introducing excessive strain. According to some embodiments, the thickness of silicon layer 34 can be in the range of about 0.5 nm to about 2 nm. It is understood that the optimal thicknesses T2 and T2' are related to the spacing of adjacent semiconductor strips 30, which will be discussed in subsequent paragraphs. Throughout the description, oxide layer 32 and silicon layer 34 are collectively referred to as substrate 33.

[0019] When using the embodiment in Figure 3A, where the oxide layer 32 is deposited before the silicon layer 34, the silicon hard mask layer 22A can be omitted or separated from the epitaxial semiconductor material 20-2. For example, the hard mask layer 22 can be formed of a homogeneous material, such as silicon nitride, or it can have a structure including a silicon layer 22C (as shown in Figure 1) contacting the epitaxial semiconductor material 20-2, a pad oxide layer 22A above the silicon layer 22C, and a hard mask layer 22B located above the pad oxide layer 22A. If the pad oxide layer is in direct contact with the material of the epitaxial semiconductor material 20-2 (e.g., SiGe), severe oxidation may occur at the interface between the pad oxide layer and the epitaxial semiconductor material 20-2, especially at the interface connecting the silicon oxide layer 32.

[0020] Figure 3B illustrates the deposition of the substrate according to an alternative embodiment. In these embodiments, instead of depositing the oxide layer 32 before depositing the silicon layer 34, the silicon layer 34 is deposited directly on the hard mask layer 22, the semiconductor substrate 20, and the semiconductor strip 30. Therefore, the silicon layer 34 substantially contacts the sidewalls of the semiconductor strip 30 and the exposed top surface of the semiconductor substrate 20.

[0021] The silicon layer 34 can be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), etc., thus forming a compliant layer. Therefore, the horizontal thickness T2 (Fig. 3A) of the horizontal portion and the thickness T2' of the vertical portion are equal to or approximately equal to each other, for example, the absolute value of the ratio (T2'-T2) / T2 is less than about 0.2% or less than about 0.1%. The thicknesses T2 and T2' of the silicon layer 34 can be greater than about 0.5 nm and can be in the range between about 0.5 nm and about 2 nm, and the desired strain can be applied by subsequent oxidation of the silicon layer 34.

[0022] Next, dielectric material 40 is deposited to fill the remaining portion of trench 26, resulting in the structure shown in Figure 4. As shown in Figure 17, in process flow 200, process 212 illustrates the corresponding process. The method for forming dielectric material 40 can be selected from flowable chemical vapor deposition (FCVD), spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0023] According to some embodiments using flow-through chemical vapor deposition (FCVD), silicon- and nitrogen-containing precursors (e.g., trisilylamine (TSA), disilylamine (DSA), etc.) are used, thus the dielectric material 40 is deposited in a flow-through manner. According to an alternative embodiment of this disclosure, a precursor based on alkylamino silane is used to form the flow-through dielectric layer 40. During this deposition process, a plasma is activated to activate the aforementioned gaseous precursor to form a flow-through oxide. The dielectric material 40 is deposited until its top surface is above the top surface of the hard mask layer 22.

[0024] Referring to Figure 5A, after depositing the dielectric material 40, an annealing (curing) process 45 is performed to transform the flowing dielectric material 40 into a solid dielectric material and a silicon oxide layer 34. As shown in Figure 17, in process flow 200, process 214 illustrates the corresponding process. The cured dielectric material is also referred to as dielectric material 40. According to some embodiments of this disclosure, the annealing process is performed in an oxygen-containing environment. The annealing temperature can be higher than about 200°C, for example, in the temperature range between about 550°C and about 700°C. The duration of the annealing process can be in the range of about 1 hour to about 3 hours. During the annealing process, an oxygen-containing process gas is introduced into the process chamber where the wafer 10 is placed. The oxygen-containing process gas may include oxygen (O2), ozone (O3), or a combination thereof. Water vapor (H2O), which also provides oxygen, may also be used. The annealing process can be performed in an oven at a pressure of one atmosphere. According to other embodiments, the annealing process is performed in a vacuum chamber, and oxygen-containing gas is introduced. For example, the flow rate of the oxygen-containing process gas can be in the range of about 100 sccm to about 1,000 sccm. After passing through the oxygen-containing process gas, the dielectric material 40 is cured and solidified. The resulting dielectric material 40 can be an oxide, such as silicon oxide.

[0025] An annealing process is performed at selected temperatures and times (for example, as previously described), transforming and oxidizing silicon layer 34 into silicon oxide layer (liner) 38, as shown in Figure 5A. Therefore, silicon oxide layer 38 includes a horizontal portion directly beneath and in solid contact with dielectric material 40, and a sidewall portion on the sidewalls of dielectric material 40. According to some embodiments where silicon oxide layer 32 is formed (as shown in Figure 5A), silicon oxide layer 38 is located between and in contact with silicon oxide layer 32 and dielectric material 40. Silicon oxide layers 32 and 38 are collectively referred to below as silicon oxide liner 41. According to alternative embodiments where silicon oxide layer 32 is not formed (as shown in Figure 5C), silicon oxide layer 38 is in contact with semiconductor substrate 20 and semiconductor strip 30.

[0026] It should be understood that, depending on the materials and composition (elements and their percentages), silicon oxide layer 38 may or may not be distinguishable from silicon oxide layer 32 and dielectric material 40. For example, in addition to silicon and oxygen, dielectric material 40 may or may not include other elements, such as carbon, hydrogen, nitrogen, etc. Furthermore, the densities of silicon oxide layers 32 and 38 may be lower than, equal to, or higher than the density of dielectric material 40. The distinction between silicon oxide layers 32 and 38 and dielectric material 40 can be determined by identifying the elements and the corresponding atomic percentages of the elements in these layers / materials, for example, by using an X-ray photoelectron spectrometer (XPS).

[0027] According to some embodiments, when the silicon layer 34 is thick, but the annealing temperature is not high enough, and / or the annealing duration is not long enough to oxidize all of the silicon layer 34, the bottom of the silicon layer 34 may remain unoxidized. The unoxidized portion is referred to as portion 34A, as shown in Figure 5B. According to some embodiments shown in Figure 5B, since the top of the silicon layer 34 receives oxygen earlier than the lower portion, the top near the top surface of the wafer 10 may be oxidized, while the lower portion is not oxidized, such that the unoxidized portion 34A has the profile shown in Figure 5B. The unoxidized silicon portion 34A may be oxidized during the formation of the corresponding semiconductor wafer by subsequent thermal budget (after which all unoxidized silicon portions 34A are oxidized to silicon oxide layer 38), or may be left in the final structure, for example in a FinFET 96, as shown in Figures 15, 16A, and 16B.

[0028] A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, can be performed to planarize the top surface of the dielectric material 40. In the planarization process, the hard mask 22 can serve as a stop layer. The dielectric material 40 and dielectric layers 32, 38 remaining after the planarization process are collectively referred to as the isolation region 42, also known as the shallow trench isolation (STI) region 42. Line 43 illustrates the top surface of the corresponding isolation region 42 after the planarization process.

[0029] According to some embodiments, the oxidation of silicon layer 34 is performed prior to the planarization process, so the oxidation of silicon layer 34 and the complete curing of dielectric material 40 are carried out in the same annealing process. According to alternative embodiments, the curing of dielectric material 40 is performed prior to the planarization process. In this case, dielectric material 40 can be partially cured to a degree to which a chemical mechanical polishing (CMP) process can be performed. The chemical mechanical polishing (CMP) process can remove the top of dielectric material 40, making it easier to completely convert the remaining dielectric material 40, for example, into silicon oxide, and making it easier to oxidize silicon layer 34 into silicon oxide layer 38, while using a smaller thermal budget. According to these embodiments, during partial curing, silicon layer 34 can remain unoxidized, or some portions (for example, the bottom 34A as shown in Figure 5B) can be partially oxidized. The annealing process following the chemical mechanical polishing (CMP) process can completely cure the dielectric material 40 and completely oxidize the silicon layer 34 to form the silicon oxide layer 38.

[0030] According to some embodiments of forming dielectric material 40 from non-flowable material, annealing processes can be performed before or after planarization processes using, for example, chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), etc.

[0031] According to some embodiments, the strain of the channel of the corresponding FinFET 96 is improved by the deposition and oxidation of the silicon layer 34. When silicon is oxidized to form silicon oxide, the volume of silicon oxide is 2.25 times the volume of silicon. Therefore, the expanded volume causes compression in the Y direction toward the semiconductor strip 30 (as shown in Figure 5A). Since the volume of the semiconductor strip 30 is fixed, when compressed, the semiconductor strip 30 generates tensile stress in the Y direction. This improves the performance of the resulting FinFET 96 (as shown in Figure 15). Experimental results on silicon wafers show that, using embodiments of the present invention, the tensile stress can be increased by 0.3%. It is understood that in order to generate strain, an oxidation process is required after the deposition of the dielectric material 40. Otherwise, the expansion is toward free space and does not generate strain or generates very small strain. Furthermore, the resulting strain is related to the thickness of the silicon layer 34 and the spacing P1 between adjacent semiconductor strips 30 (as shown in Figure 16B), and the thicker the silicon layer 34 and / or the smaller the spacing P1, the greater the resulting strain. For example, when the thickness of the silicon layer 32 is in the range of about 0.5 nm to about 1.5 nm, a spacing P1 of less than about 25 nm or less than about 20 nm can lead to a significant improvement in strain.

[0032] Next, as shown in Figure 6, the isolation region 42 is etched in the etching process. As shown in Figure 17, process 216 illustrates the corresponding process in process flow 200. The portion of the semiconductor strip 30 above the top surface of the remaining isolation region 42 is referred to as a protruding (semiconductor) fin 44. In some embodiments of this disclosure, the top surface of the isolation region 42 is above the interface 23 between the epitaxial layer 20-2 (if formed) and the underlying substrate portion 20-1. The etching of the dielectric region can be performed using a dry etching process. For example, HF 3 and NH 3 can be used as etching gases. According to alternative embodiments of this disclosure, the etching of the dielectric region can be performed using a wet etching process. For example, the etching chemicals may include a diluted HF solution.

[0033] In the above embodiments, semiconductor fins can be formed by any suitable method. For example, one or more lithography processes can be used to pattern semiconductor fins, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0034] Referring to Figure 7, a dummy gate stack 46 is formed that intersects with the protruding fins 44. As shown in Figure 17, in process flow 200, process 218 illustrates the corresponding process. The dummy gate stack 46 may include a dummy gate dielectric 48 and a dummy gate electrode 50 above the dummy gate dielectric 48. The dummy gate dielectric 48 may be formed of silicon oxide or other dielectric materials. The dummy gate electrode 50 may be formed using, for example, polycrystalline silicon or amorphous silicon, or other materials. Each dummy gate stack 46 may also include one (or more) hard masking layers 52 above the dummy gate electrode 50. The hard masking layer 52 may be formed of silicon nitride, silicon oxide, silicon carbide, or multiple layers thereof. The dummy gate stack 46 may intersect with one or more protruding fins 44 and / or shallow trench isolation (STI) regions 42. The dummy gate stack 46 also has a longitudinal direction perpendicular to the length direction of the protruding fin 44. The formation of the dummy gate stack 46 includes depositing a dummy gate dielectric layer, depositing a gate electrode layer above the dummy gate dielectric layer, depositing a hard mask layer, and patterning the stack layers to form the dummy gate stack 46.

[0035] Next, referring to Figure 8, a gate spacer 54 is formed on the sidewall of the dummy gate stack 46. As shown in Figure 17, in process flow 200, process 220 illustrates the corresponding process. The formation of the gate spacer 54 may include depositing a blanket dielectric layer and performing an isotropic etching process to remove the horizontal portion of the dielectric layer, leaving the gate spacer 54 located on the sidewall of the dummy gate stack 46. According to some embodiments of this disclosure, the gate spacer 54 is formed of an oxygen-containing dielectric material (oxide), such as SiO2, SiOC, SiOCN, etc. According to some embodiments of this disclosure, the gate spacer 54 may also include a non-oxide dielectric material, such as silicon nitride.

[0036] Subsequently, an etching process (hereinafter referred to as fin etching) is performed to etch the portion of the protruding fins 44 not covered by the dummy gate stack 46 and the gate spacer 54, resulting in the structure shown in Figure 9. As shown in Figure 17, in process flow 200, process 222 illustrates the corresponding process. The etched protruding fins 44 can be protected from etching by performing an isotropic etching process, thus the portion of the protruding fins 44 located directly below the dummy gate stack 46 and the gate spacer 54 is protected from etching. According to some embodiments, the top surface of the etched semiconductor strip 30 may be lower than the top surface 42A of the shallow trench isolation (STI) region 42. The groove 60 is thus formed between the shallow trench isolation (STI) regions 42. The groove 60 is located on the opposite side of the dummy gate stack 46.

[0037] Next, an epitaxial region (source / drain region) 62 is formed by selectively growing semiconductor material in the groove 60 to obtain the structure shown in Figure 10. As shown in Figure 17, in process flow 200, process 224 illustrates the corresponding process. According to some embodiments of this disclosure, the epitaxial region 62 includes silicon germanium, silicon, or silicon carbide. Depending on whether the formed fin field-effect transistor (FinFET) is a p-type fin field-effect transistor (FinFET) or an n-type fin field-effect transistor (FinFET), p-type or n-type impurities can be in-situ doped during epitaxy. For example, when the formed fin field-effect transistor (FinFET) is a p-type fin field-effect transistor (FinFET), silicon germanium boron (SiGeB), GeB, etc., can be grown. Conversely, when the formed FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbide phosphide (SiCP), etc., can be grown. According to an alternative embodiment disclosed herein, the epitaxial region 62 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiples thereof. After the epitaxial region 62 completely fills the trench 60, the epitaxial region 62 begins to extend horizontally and can form facets.

[0038] After the epitaxial step, epitaxial regions 62 can be further implanted with p-type or n-type impurities to form source and drain regions, also represented by element symbol 62. According to an alternative embodiment of this disclosure, when epitaxial regions 62 are in-situ doped with p-type or n-type impurities during epitaxy, the above implantation process is skipped.

[0039] According to alternative embodiments of this disclosure, instead of etching the protruding fins 44 and regrowing the source / drain regions 62, a covered source / drain region is formed. According to these embodiments, the protruding fins 44 are not etched, as shown in Figure 9, and an epitaxial region (not shown) is grown on the protruding fins 44. The growth material of the epitaxial region can be similar to the material 62 of the epitaxial semiconductor, as shown in Figure 11, depending on whether the formed fin field-effect transistor (FinFET) is a p-type or an n-type fin field-effect transistor (FinFET). Therefore, the source / drain region 62 includes the protruding fins 44 and the epitaxial region. A placement process may (or may not) be performed to place n-type or p-type impurities.

[0040] Figure 11 illustrates a perspective view of the structure after the formation of the contact etch stop layer (CESL) 66 and the interlayer dielectric (ILD) 68. As shown in Figure 17, in process flow 200, process 226 illustrates the corresponding process. The contact etch stop layer (CESL) 66 can be formed from silicon nitride, silicon carbide, etc. For example, the contact etch stop layer (CESL) 66 can be formed by conformal deposition processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The interlayer dielectric (ILD) 68 can include the formation of a dielectric material using, for example, flow-through chemical vapor deposition (FCVD), spin coating, chemical vapor deposition (CVD), or other deposition methods. The interlayer dielectric (ILD) 68 can also be formed from an oxygen-containing dielectric material, such as silica-based materials, including silica, phosphosillicate glass (PSG), borosillicate glass (BSG), and boron-doped phosphosillicate glass (BPSG). A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, is performed to make the top surfaces of the interlayer dielectric (ILD) 68, the dummy gate stack 46, and the gate spacer 54 flush with each other. An annealing process can be used when forming the interlayer dielectric (ILD) 68.

[0041] Next, in one or more etching processes, a dummy gate stack 46 comprising a hard mask layer 52, a dummy gate electrode 50, and a dummy gate dielectric 48 is etched, resulting in the formation of trenches 70 between opposite portions of the gate spacers 54, as shown in Figure 12. The etching process can be performed using, for example, a dry etching process. The etching gas is selected based on the material to be etched. For example, when the hard mask 36 comprises silicon nitride, the etching gas can include fluorine-containing process gases, such as CF4 / O2 / N2, NF3 / O2, SF6, etc. The dummy gate electrode 50 can be etched using a mixture of C2F6, CF4, SO2, HBr, Cl2, and O2, or a mixture of HBr, Cl2, O2, and CF2, etc. The dummy gate dielectric 48 can be etched using a mixture of NF3 and NH3, or a mixture of HF and NH3. If a silicon layer 22C is formed on the sidewall of the dummy gate stack 46 (as shown in Figure 1), the silicon layer is also removed.

[0042] Next, referring to Figure 13, an alternative gate stack 72 is formed, which includes a gate dielectric 74 and a gate electrode 76. As shown in Figure 17, in process flow 200, process 228 illustrates the corresponding process. Forming the gate stack 72 includes forming / depositing multiple layers, followed by a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process. The gate dielectric 74 extends into the trench 70 (as shown in Figure 13). According to some embodiments of this disclosure, the gate dielectric 74 includes interface layers (ILs) 78 (as shown in Figures 16A and 16B) as their lower portion. The interface layers (ILs) 78 are formed on the surface exposed by the protruding fins 44. The interface layers (ILs) 78 may include an oxide layer, such as a silicon oxide layer, which is formed by thermal oxidation of the protruding fins 44, a chemical oxidation process, or a deposition process. The gate dielectric 74 may also include a high-k dielectric layer 80 above the interface layer (IL) 78 (as shown in Figures 16A and 16B). The high-k dielectric layer 80 may include a high-k dielectric material, such as HfO₂, ZrO₂, HfZrOx, HfSiOx, HfSiON, ZrSiOx, HfZrSiOx, Al₂O₃, HfAlOx, HfAlN, ZrAlOx, La₂O₃, TiO₂, Yb₂O₃, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9 and may be higher than about 7.0. The high-k dielectric layer 80 is formed as a compliant layer and extends on the sidewalls of the protruding fin 44 and the gate spacer 54. According to some embodiments of this disclosure, a high-k dielectric layer 80 is formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0043] As shown in Figure 13, a gate electrode 76 is formed on top of the gate dielectric 74, filling the remaining portion of the trench left after removing the dummy gate stack. The sub-layers in the gate electrode 76 are not shown separately in Figure 14, but in fact, they can be distinguished from each other due to their different compositions. Deposition of at least the lower sub-layers can be performed using compliant deposition methods, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), such that the thickness of the vertical portion of the sub-layer in the gate electrode 76 is approximately equal to the thickness of the horizontal portion.

[0044] The sublayers in the gate electrode 76 may include, but are not limited to, titanium silicon nitride (TSN) layers, tantalum nitride (TaN) layers, titanium nitride (TiN) layers, titanium and aluminum-containing layers (e.g., TiAl or TiAlC), additional TiN and / or TaN layers, and filler metals. Some of these layers define the work function of the corresponding FinFET. Furthermore, the metal layers of the p-type FinFET and the n-type FinFET may be different from each other, such that the work function of the metal layers is suitable for either the p-type or n-type FinFET. The filler metal may include aluminum, copper, cobalt, etc.

[0045] Next, as shown in Figure 14, a hard mask 82 is formed. As shown in Figure 17, in process flow 200, process 230 illustrates the corresponding process. According to some embodiments of this disclosure, the formation of the hard mask 82 includes etching through an alternative gate stack 72 to form a groove, filling the groove with dielectric material, and performing a planarization process to remove excess dielectric material. The remaining portion of the dielectric material constitutes the hard mask 82. According to some embodiments of this disclosure, the hard mask 82 is formed of silicon nitride, silicon oxynitride, silicon oxy-carbide, silicon oxy-carbo-nitride, etc.

[0046] Figure 15 illustrates subsequent steps in forming the contact plug 86, including forming contact openings by etching into the interlayer dielectric (ILD) 68 and the contact etch stop layer (CESL) 66 to expose the source / drain region 62. A silicate region 84 and the source / drain contact plug 86 are then formed in the contact openings. As shown in Figure 17, in process flow 200, process 232 illustrates the corresponding process. The top edges of the silicon oxide layers 32 and 38 may contact the silicate region 84 or the source / drain contact plug 86, depending on the extension of the silicate region 84. Alternatively, the top edges of the silicon oxide layers 32 and 38 may contact the source / drain region 62.

[0047] In subsequent processes, as shown in Figures 16A and 16B, an etch stop layer 88 is formed, followed by the formation of an interlayer dielectric (ILD) 90. Figure 16A illustrates a cross-sectional view taken from the same plane as line AA in Figure 15. According to some embodiments of this disclosure, the etch stop layer 88 is formed of SiN, SiCN, SiC, SiOCN, or another dielectric material. Formation methods may include PECVD, ALD, CVD, etc. The material of the interlayer dielectric (ILD) 90 may be selected from the same candidate materials (and methods) used to form the interlayer dielectric (ILD) 68, and the interlayer dielectrics (ILDs) 68 and 90 may be formed of the same or different dielectric materials. According to some embodiments of this disclosure, the interlayer dielectric (ILD) 90 is formed using PECVD, FCVD, ALD, spin coating, etc., and may include silicon oxide (SiO2).

[0048] The interlayer dielectric (ILD) 90 and the etch stop layer 88 are etched to form an opening. The etching can be performed using, for example, reactive ion etching (RIE). Gate contact plugs 92 and source / drain contact plugs 94 are formed in the opening to be electrically connected to the gate electrode 76 and the source / drain contact plug 86, respectively. Thus, a finned field-effect transistor (FinFET) 96 is formed.

[0049] Figure 16B illustrates a cross-sectional view of a fin field-effect transistor (FinFET) 96 obtained from another plane, which is the same plane containing line BB in Figure 16A. Figure 16B illustrates silicon oxide layers 32 and 38 and other related components. According to an alternative embodiment, as shown in Figure 5B, the bottom of silicon layer 34 may be present between silicon oxide layers 32 and 38.

[0050] The embodiments disclosed herein have several advantageous features. In the formation of the isolation region, by depositing a silicon liner followed by an oxide liner to form an oxide liner, beneficial strain can be increased to improve the performance of the formed transistor.

[0051] According to some embodiments of the present disclosure, a method of forming a semiconductor device includes: etching a semiconductor substrate to form trenches and semiconductor strips, wherein the sidewalls of the semiconductor strips are exposed in the trenches; depositing a silicon-containing layer extending into the trenches, wherein the silicon-containing layer extends on the sidewalls of the semiconductor strips; filling the trenches with a dielectric material, wherein the dielectric material is located on the sidewalls of the silicon-containing layer; oxidizing the silicon-containing layer to form a first liner, wherein the first liner includes oxidized silicon, and wherein the first liner and the dielectric material form multiple parts of an isolation region; and etching an isolation region, wherein a portion of the semiconductor strip protrudes above the top surface of the isolation region to form semiconductor fins. In one embodiment, the method of forming a semiconductor device further includes: depositing a silicon oxide layer in contact with the sidewalls of the semiconductor strips before depositing the silicon-containing layer. In one embodiment, the silicon oxide layer is in contact with the silicon-containing layer. In one embodiment, the silicon-containing layer is oxidized after depositing the dielectric material. In one embodiment, the dielectric material is deposited as a flowable material, and the flowable material is solidified by oxidizing the silicon-containing layer. In one embodiment, the silicon-containing layer is completely oxidized to silicon oxide. In one embodiment, the thickness of the silicon-containing layer is greater than about 0.5 nm. In one embodiment, the silicon-containing layer is deposited using atomic layer deposition.

[0052] According to some embodiments of the present disclosure, a method of forming a semiconductor device includes: etching a semiconductor substrate to form a semiconductor strip and a trench, wherein the semiconductor strip is located on one side of the trench and has a first longitudinal direction parallel to a second longitudinal direction of the trench, wherein the semiconductor strip comprises silicon and germanium, and exposes the sidewalls of the semiconductor strip; depositing a first liner extending into the trench and contacting the sidewalls of the semiconductor strip, wherein the first liner comprises silicon oxide; depositing a second liner on the first liner, wherein the second liner comprises silicon, the second liner extending from a top surface of the semiconductor substrate to a bottom of the trench; depositing a dielectric material to fill the trench, wherein a portion of the second liner is located below the dielectric material; curing the dielectric material to form an oxide layer; and converting the second liner into a third liner. In one embodiment, the thickness of the first liner is in the range of about 5 Å to about 15 Å. In one embodiment, the second liner has a thickness greater than about 0.5 nm. In one embodiment, the second liner comprises amorphous silicon or polycrystalline silicon. In one embodiment, the curing of the dielectric material and the conversion of the second substrate are performed by performing the same annealing process. In one embodiment, the method of forming a semiconductor device further includes: etching the first substrate, the second substrate, and the oxide layer; and forming a gate stack extending over the etched first substrate, the second substrate, and the oxide layer. In one embodiment, the second substrate is completely converted into silicon oxide.

[0053] According to some embodiments of the present disclosure, a method for forming a semiconductor device includes: depositing a silicon-containing substrate in a trench of a semiconductor substrate; oxidizing the silicon-containing substrate to form a first oxidized silicon substrate, such that the volume ratio of the first oxidized silicon substrate to the volume of the silicon-containing substrate is greater than 0 and not greater than 2.25; depositing a dielectric material in the trench, wherein the first oxidized silicon substrate includes a first portion below the dielectric material, and the dielectric material and the first oxidized silicon substrate form a plurality of isolation regions; etching the isolation regions, wherein protruding semiconductor fins are formed in a portion of the semiconductor substrate between the etched isolation regions; forming a gate dielectric extending over the isolation regions; and forming a gate electrode over the gate dielectric. In one embodiment, the silicon-containing substrate includes crystalline silicon. In one embodiment, the method of forming a semiconductor device further includes depositing a silicon oxide layer extending into a trench prior to depositing a silicon-containing substrate, wherein the silicon-containing substrate comprises amorphous silicon. In one embodiment, the silicon-containing substrate is oxidized using a process gas selected from the group consisting of oxygen (O2), water vapor, and combinations thereof. In one embodiment, the silicon-containing substrate is oxidized after depositing a dielectric material.

[0054] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0055] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the cells can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention. Figures 1-3A, 3B, 4, 5A, 5B, 5C, 6-15, 16A and 16B, according to some embodiments of the present disclosure, illustrate cross-sectional and perspective views of various stages in forming the isolation region and the FinFET. Figure 17, according to some embodiments of the present disclosure, illustrates a process flow diagram for forming the FinFET.

Claims

1. A method for forming a semiconductor device, comprising: A semiconductor substrate is etched to form a trench and a semiconductor strip, wherein one sidewall of the semiconductor strip is exposed in the trench; A silicon-containing layer is deposited extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip; the trench is filled with a dielectric material, wherein the dielectric material is located on one sidewall of the silicon-containing layer; a planarization process is performed to make a first top surface of the dielectric material flush; after the planarization process, the silicon-containing layer is oxidized to form a first substrate, wherein the first substrate includes oxidized silicon, and wherein the first substrate and the dielectric material form multiple parts of an isolation region; And the isolation region is etched, wherein a portion of the semiconductor strip protrudes above a second top surface of the isolation region to form a semiconductor fin, wherein the silicon-containing layer comprises crystalline silicon.

2. The method of forming the semiconductor device as claimed in claim 1 further includes: Before depositing the silicon-containing layer, a silicon monoxide layer is deposited in contact with the sidewall of the semiconductor strip.

3. The method for forming a semiconductor device as claimed in claim 1, wherein the silicon oxide layer is in contact with the silicon-containing layer.

4. The method for forming a semiconductor device as claimed in claim 1, wherein the silicon-containing layer is oxidized after the dielectric material is deposited.

5. A method for forming a semiconductor device as claimed in claim 1, wherein the dielectric material is deposited as a flowable material, and the flowable material is cured by oxidizing the silicon-containing layer.

6. A method for forming a semiconductor device as claimed in any of claims 1-5, wherein the silicon-containing layer is completely oxidized to silicon oxide.

7. A method for forming a semiconductor device, comprising: The process involves etching a semiconductor substrate to form a semiconductor strip and a trench, wherein the semiconductor strip is located on one side of the trench and has a first longitudinal direction parallel to a second longitudinal direction of the trench, wherein the semiconductor strip includes an upper portion and a lower portion, the upper portion including silicon germanium and the lower portion including silicon, and having a lower percentage of germanium atoms than the upper portion; depositing a first liner extending into the trench and contacting the sidewalls of the upper and lower portions of the semiconductor strip, wherein the first liner includes silicon oxide; depositing a second liner on the first liner, wherein the second liner includes silicon and extends from a top surface of the semiconductor substrate to a bottom surface of the trench; depositing a dielectric material to fill the trench, wherein a portion of the second liner is located below the dielectric material; curing the dielectric material to form an oxide layer; and converting the second liner into a third liner.

8. A method for forming a semiconductor device as claimed in claim 7, wherein the second substrate comprises amorphous silicon or polycrystalline silicon.

9. The method of forming a semiconductor device as claimed in claim 7, wherein curing the dielectric material and converting the second substrate are performed by performing the same annealing process.

10. The method of forming a semiconductor device as described in claim 7 further includes: The first liner, the second liner, and the oxide layer are etched. And form a gate stack extending over the etched first liner, the second liner and the oxide layer.

11. A method for forming a semiconductor device, comprising: In a trench of a semiconductor substrate, a silicon-containing substrate is deposited; the silicon-containing substrate is oxidized to form a first oxidized silicon substrate, such that the volume ratio of the first oxidized silicon substrate to the volume of the silicon-containing substrate is greater than 0 and not greater than 2.25; a dielectric material is deposited in the trench, wherein the first oxidized silicon substrate includes a first portion below the dielectric material, and the dielectric material and the first oxidized silicon substrate form a plurality of isolation regions; the isolation regions are etched, wherein a protruding semiconductor fin is formed on a portion of the semiconductor substrate between the etched isolation regions; a gate dielectric is formed extending above the isolation regions; and a gate electrode is formed above the gate dielectric.

12. A method for forming a semiconductor device as claimed in claim 11, wherein the silicon-containing substrate comprises crystalline silicon.

13. The method of forming a semiconductor device as claimed in claim 11 further includes: Prior to depositing the silicon-containing liner, a silicon monoxide layer is deposited extending into the trench, wherein the silicon-containing liner comprises amorphous silicon.

14. The method of forming a semiconductor device as claimed in claim 11, wherein the silicon-containing substrate is oxidized using a process gas selected from the group consisting of oxygen (O2), water vapor, and combinations thereof.

15. A method for forming a semiconductor device as claimed in claim 11, wherein the silicon-containing substrate is oxidized after the dielectric material is deposited.

Images