Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

Abstract

A multi-chip package structure includes: a first semiconductor integrated circuit (IC) chip; a second semiconductor integrated circuit (IC) chip located above and bonded to the first semiconductor integrated circuit (IC) chip; a plurality of first metal pillars located above and coupled to the first semiconductor integrated circuit (IC) chip, wherein the first metal pillars are located in a space extending outward from the sidewall of the second semiconductor integrated circuit (IC) chip; and a first polymer layer located above the first semiconductor integrated circuit (IC) chip and in the space, wherein the first metal pillars are located in the first polymer layer, and wherein the upper surface of the first polymer layer, the upper surface of the second semiconductor integrated circuit (IC) chip, and the upper surface of each of the first metal pillars are coplanar.

Description

[Technical Field]

[0001] This application claims U.S. Provisional Application No. 62 / 768,978, filed on November 18, 2018, entitled "Logic Driver According to Standard Commercial Programmable Logic / Memory Semiconductor IC Wafer-Level Package". This application also claims U.S. Provisional Application No. 62 / 882,941, filed on August 5, 2019, entitled "Vertical Interconnect Line Elevator Constructed Based on Silicon Perforated Plug". This application also claims U.S. Provisional Application No. 62 / 891,386, filed on August 25, 2019, entitled "Vertical Interconnect Line Elevator Constructed Based on Silicon Perforated Plug".

[0002] This invention relates to a logic operation chip package, a logic operation driver package, a logic operation chip device, a logic operation chip module, a logic operation driver, a logic operation hard disk, a logic operation driver hard disk, a logic operation driver solid-state hard disk, a field-programmable gate array (FPGA) logic operation hard disk, or a field-programmable gate array logic arithmetic unit (hereinafter referred to as logic operation driver, that is, the logic operation chip package, logic operation driver package, logic operation chip device, logic operation chip module, logic operation hard disk, logic operation driver hard disk, logic operation driver solid-state hard disk, field-programmable gate array (FPGA) logic operation hard disk, or field-programmable gate array logic arithmetic unit mentioned in the following description, all referred to as logic operation driver). The logic operation driver of this invention includes multiple FPGA integrated circuit (IC) chips for field programming purposes and one (or more) non-volatile IC chips, more specifically, using multiple commercial standard FPGA ICs. Standard commercial logic operation drivers comprised of chip / HBM package structures (CSPs) (each including an FPGA IC chip and one (or more) HBM IC chips) include non-volatile random access memory cells and can be used in various applications when field-programmed. [Previous Technology]

[0003] FPGA semiconductor IC chips have been used to develop innovative applications or small-batch applications or business needs. When an application or business need expands to a certain quantity or time, semiconductor IC suppliers usually treat this application as an Application Specific IC (ASIC) chip or a Customer-Owned Tooling (COT) IC chip. For a specific application and compared to an ASIC chip or a COT chip, FPGA chips are designed as ASIC chips or COT chips due to the following factors: (1) larger semiconductor chip size, lower manufacturing yield and higher manufacturing cost; (2) higher power consumption; (3) lower performance. As semiconductor technology progresses according to Moore's Law to the next process generation (e.g., to less than 30 nanometers (nm) or 20 nanometers (nm)), the non-recurring engineering (NRE) costs for designing an ASIC or COT chip become extremely high, as shown in Figure 27. These costs can exceed US$5 million, or even surpass US$10 million, US$20 million, US$50 million, or US$100 million. For example, the cost of a single photomask used in an ASIC or COT chip with a 16nm technology generation or manufacturing technology exceeds US$2 million, US$5 million, or US$10 million. Such high NRE costs reduce or even halt the application of advanced IC technologies or next-generation process technologies in innovation or applications. Therefore, there is a need to develop new methods or technologies that enable continuous innovation and reduce barriers (manufacturing costs), and that allow innovation on semiconductor IC chips to be achieved using advanced and useful semiconductor technology nodes (or generations). [Summary of the Invention]

[0004] This invention discloses a commercial standard logic operation driver located in a multi-chip package, comprising a plurality of standard commercial field-programmable gate array / high-bandwidth memory chip-scale packages (FPGA / HBM CSP) and one (or more) non-volatile IC chips used in various applications requiring logic, computation and / or processing functions, wherein the FPGA / HBM CSPs include a standard commercial FPGA IC chip and an HBM chip or a package having a plurality of HBM chips stacked together, and the non-volatile memory IC chip used in this commercial standard logic operation driver is similar to a commercial standard solid-state storage disk (or drive), a data storage disk, a data storage floppy disk, a Universal Serial Bus (USB) flash memory disk (or drive), a USB drive, a USB memory stick, a flash memory disk or a USB memory. Standard commercial FPGA / HBM CSP systems are similar to those that use standard commercial data storage memory IC chips, such as standard commercial DRAM chips or standard commercial NAND flash chips. The difference is that the latter have data storage functions, while the former have logic operation functions and / or calculation functions for processing.

[0005] This invention further discloses a method for reducing NRE costs, which implements (i) innovations and / or applications via standard commercial logic drivers, including multiple standard commercial FPGAs / HBM CSPs. A person with an innovative idea or application needs to purchase this commercial standard logic driver and a development or writing software source code or program that can be written to (or loaded into) this commercial standard logic driver to implement his / her innovative idea or application, wherein the innovative idea or application includes (i) innovative algorithms and / or computational structures, processing methods, learning and / or inference, and / or (ii) innovative and / or specific applications. Compared to implementation via developing logic ASICs or COT IC chips, the NRE cost using standard commercial logic drivers can be reduced by 2, 5, 10, 30, 50, or more than 100 times. For advanced semiconductor technology nodes or higher generations (e.g., technologies greater than (or less than) 20 nm), the NRE cost for designing ASIC or COT chips increases significantly, exceeding $5 million, and even exceeding $10 million, $20 million, $50 million, or $100 million. At the 16nm technology node or generation, the cost of setting up a photomask for an ASIC or COT wafer can exceed $2 million, $5 million, or $10 million. Using the logic driver described in this invention to implement the same or similar innovations and / or applications can reduce NRE costs to less than $10 million, or even less than $5 million, $3 million, $2 million, or $1 million. The logic driver of this invention can inspire innovation and lower the barriers to innovation in IC chips designed and manufactured using advanced IC technology nodes or generations (e.g., technologies higher than (or transistor gate widths less than 20nm or 10nm or more advanced technology nodes or generations).

[0006] In another aspect, the present invention may again provide an "open innovation platform" that enables creators to easily and cost-effectively implement or realize their ideas or inventions on semiconductor wafers using IC technology generations advanced to 20nm, such as those advanced to 20nm, 16nm, 10nm, 7nm, 5nm, or 3nm, via the logic drivers of the present invention. The nm technology generation, where the idea or invention includes (i) innovative algorithms or architectures for computing, processing, learning and / or reasoning, and / or (ii) innovative and / or specific applications, in the 1990s, creators or inventors could realize their ideas or inventions by designing IC chips and using the technology of the 1µm, 0.8µm, 0.5µm, 0.35µm, 0.18µm or 0.13µm technology generations in semiconductor manufacturing foundries at a cost of hundreds of thousands of dollars. Semiconductor manufacturing foundries are fabless companies that own their own semiconductor manufacturing plants and provide manufacturing services to customers who are fabless companies, including (i) IC chip design companies that design and own IC chips, (ii) system companies that design and own systems, and (iii) IC chip designers who design and own IC chips.This semiconductor manufacturing plant was then considered a "public innovation platform." However, as technology generations migrated and advanced to more advanced generations than 20nm—for example, those more advanced than 20nm, 16nm, 10nm, 7nm, 5nm, or 3nm—only a few large system integrators or IC design companies (not public innovators or inventors) could afford the development costs required by semiconductor IC manufacturing foundries. The cost of developing and implementing these advanced generations was approximately over $10 million. Today's semiconductor IC foundries are no longer "public innovation platforms," ​​but rather "club innovation platforms" for club innovators or inventors. The logic driver proposed in this invention (including standard commercial field-programmable gate array (FPGA) integrated circuit chips (standard commercial FPGAs)) IC chips can provide a "public innovation platform" for public creators, allowing them to return to the semiconductor IC industry of the 1990s. Creators can execute or implement their creations or inventions by using standard commercial logic drives and writing software programs at a cost of less than $500,000 or $300,000. The software programs are common programming languages ​​such as C, Java, C++, C#, Scala, Swift, Matlab, Assembly Language, Pascal, Python, Visual Basic, PL / SQL, or JavaScript. Creators can use their own standard logic drives or they can rent standard commercial logic drives via the internet in data centers or the cloud to develop or implement their creations or inventions.

[0007] Another aspect of the present invention provides an innovative platform of the inventors, which includes (a) a plurality of logic drivers in a data center or cloud, wherein the logic drivers include a plurality of standard commercial FPGA IC chips (located in FPGA / HBM CSP packages) manufactured using a semiconductor IC process technology node prior to the 20nm technology node. (b) Devices of an innovator and multiple users communicating with the Internet or the Internet in a data center or cloud, wherein the innovator can program multiple logic drivers via the Internet or the Internet using common programming languages ​​in a data center or cloud to develop and write software programs to realize his innovation (invention) (including algorithms, architectures and / or applications), wherein common programming languages ​​include programming languages ​​such as C, Java, C++, C#, Scala, Swift, Matlab, Assembly Language, Pascal, Python, Visual Basic, PL / SQL or JavaScript, etc., (c) after programming these logic drivers, the innovator or multiple users can use the programmed logic drivers via the Internet or the Internet in their innovations (including algorithms, architectures and / or applications), wherein these innovations include: (i) computational, operational, learning and / or reasoning innovations in algorithms or architectures, and / or (ii) innovations and / or specific applications.

[0008] This invention further discloses a business model that transforms an existing logic ASIC or COT chip business model into a commercial logic IC chip business model using standard commercial logic drivers, such as current commercial DRAM or commercial NAND flash memory IC chip business models. This logic driver offers better or equal performance, power consumption, engineering, and manufacturing costs than existing conventional ASIC or COT IC chips for the same innovation (algorithm, architecture, and / or application) or application aimed at accelerating workload processing. Companies that design, manufacture, and / or produce existing logic ASIC and COT IC chips (including fabless IC design and product companies, IC foundries or contract manufacturers (possibly without products), and / or vertically integrated IC design, manufacturing, and product companies) can become companies similar to those designing, manufacturing, and / or producing DRAM or commercial flash memory IC chips, or companies similar to those designing, manufacturing, and / or producing existing flash memory modules, flash USB sticks or drives, or flash solid-state drives or disk drives. Existing logic ASIC or COT IC chip design and / or manufacturing companies (including fabless IC design and product companies, IC foundries or contract manufacturers (who may not have products), and vertically integrated IC design, manufacturing, and product companies) can become companies with the following business models: (1) designing, manufacturing, and / or selling standard commodity FPGA IC chips; and / or (2) designing, manufacturing, and / or selling standard commodity logic drivers. Users, customers, or software developers can purchase this standard commercial logic driver and write software code to program the logic driver, for example, for functions such as Artificial Intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IoT), Virtual Reality (VR), Augmented Reality (AR), automotive electronics, automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC), or central processing unit (CP), or any combination thereof, to program the logic driver to perform functions such as graphics chips, DSP chips, Ethernet chips, wireless (e.g., 802.11ac) chips, or AI chips.The logic driver can be selectively programmed to perform functions such as artificial intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IoT), virtual reality (VR), augmented reality (AR), automotive electronics, automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC), or central processing unit (CP). This logic driver is a field-programmable accelerator that can be used in user terminals, data centers, or the cloud, or in field-programmed applications for training / inference in AI functions.

[0009] This invention further discloses a business model that transforms the hardware business model of existing hard logic ASIC chips or COT chips into a software business model by using standard commercial logic drivers. For the same innovation (algorithm, structure and / or application), the logic driver can be better or the same as existing conventional ASIC chips or conventional COT IC chips in terms of performance, power consumption, engineering and manufacturing costs. Standard commercial logic drivers can be used as an alternative method for designing ASIC or COT IC chips. Existing ASIC or COT IC design companies or suppliers can become software developers or suppliers, and they may adapt to the following business models: (1) become software companies that develop software for their inventions or applications and operate primarily as software sellers and renters, allowing their customers or users to install the software into the commercial standard logic drives owned by the customers or users; and / or (2) hardware companies that still operate as hardware sellers without designing or manufacturing ASIC or COT IC chips. In model (2), customers or users can install self-developed software into the standard commercial logic drives they sell (or purchase) and then resell it to their customers or users. In modes (1) and (2), customers / users or developers / companies can write software source code into standard commodity logic drivers (i.e., load the software source code into a standardized commodity logic driver), architecture, and / or applications for their desired algorithms, such as programs for functions or combinations thereof, such as artificial intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IoT), virtual reality (VR), augmented reality (AR), automotive electronics, automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC), or central processing unit (CP). The logic driver can be programmed to perform functions such as graphics chips, DSP chips, Ethernet chips, wireless (e.g., 802.11ac) chips, or AI chips. Logic drivers can be optionally programmed to perform functions such as artificial intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IoT), virtual reality (VR), augmented reality (AR), automotive electronics, automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC), or central processing unit (CP).

[0010] This invention further discloses a method for transforming an existing system design, system manufacturing, and / or system product industry into a commercial system / product industry using standard commercial logic units, such as the current commercial DRAM industry or flash memory industry. Existing systems, computers, processors, smartphones, or electronic instruments or devices can become a standard commercial hardware company, with memory drives and logic drives as the main hardware. The memory drive can be a hard disk, a flash drive (USB flash drive), and / or a solid-state drive. The logic drive disclosed in this invention can have a sufficient number of input / output (I / O) ports to support the I / O portion of programming for all or most applications. For example, it may perform one or a combination of the following functions: Artificial Intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IoT), industrial computers, virtual reality (VR), augmented reality (AR), automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC) or central processing unit (CP) and other functions. The logic operation driver may include: (1) software, algorithm, architecture and / or application developers can download the algorithm, architecture and / or application software or programming code, and connect or couple it to the I / Os of the logic driver via I / O ports or connectors to program or configure the logic driver; (2) I / Os that operate, execute or are used by the user, who connects or couples to the I / Os of the logic operation driver via one or more external I / Os or connectors to execute or operate instructions, such as generating a Microsoft Word file, a presentation file or a spreadsheet. External I / Os or connectors of external components may be connected to or coupled to corresponding logic operation driver I / Os, including one or more (2, 3, 4 or more) USB connectors, one or more IEEE Single Layer Package Volatile Memory Driver 4 connectors, one or more Ethernet connectors, one or more audio connectors or serial ports, such as RS-232 connectors or COM (communication) connectors, wireless transceiver I / Os and / or Bluetooth transceiver I / Os. External I / Os connected to or coupled to corresponding logic operation driver I / Os may include Serial Advanced Technology Attachment (SATA) connectors or Peripheral Components Interconnect express (PCIe) connectors for communication, connection or coupling to memory drives.These I / Os for communication, connection, or coupling can be disposed, located, assembled, or connected on (or to) a substrate, a flexible board, or a rigid board, such as a printed circuit board (PCB), a silicon substrate with interconnection circuitry, a metal substrate with interconnection circuitry, a glass substrate with interconnection circuitry, a ceramic substrate with interconnection circuitry, or a flexible substrate with interconnection circuitry. The logic operation driver is mounted on the substrate, flexible board, or rigid board via tin bumps, copper pillars, or copper bumps using a flip-chip packaging process or a chip-on-film (COF) packaging process used in liquid crystal display driver packaging technology. Existing systems, computers, processors, smartphones, or electronic instruments or devices may become: (1) companies that sell standard commercial hardware, which, for the purposes of this invention, are still hardware companies, and the hardware includes memory drivers and logic operation drivers; (2) companies that develop systems, algorithms, architectures, and / or application software for users and install them on users' own standard commercial hardware, which, for the purposes of this invention, are software companies; (3) companies that install systems, algorithms, architectures, and / or application software or programs developed by third parties on standard commercial hardware and sell software download hardware, which, for the purposes of this invention, are hardware companies.

[0011] Another aspect of the present invention provides a standard commercial FPGA IC chip for use in a standard commercial FPGA / HBM CSP package, which is used in a standard commercial logic driver in a multi-chip package type. The standard commercial FPGA IC chip is designed, implemented, and manufactured using advanced semiconductor technology nodes (or generations), such as technology nodes more advanced than or equal to 30nm, 20nm, or 10nm; wherein chip size and manufacturing yield are improved and optimized, and production of the semiconductor technology node or next-generation product is achieved at the lowest manufacturing cost. The area of ​​the standard commercial FPGA IC chip can be between 400 mm² and 9 mm², 225 mm² and 9 mm², 144 mm² and 16 mm², 100 mm² and 16 mm², 75 mm² and 16 mm², or between 50 mm² and 16 mm². Transistors used in advanced semiconductor technology nodes or next-generation technologies can be FinFETs, Silicon-On-Insulators (FINFET SOI), Gate-All-Around-Field-Effect Transistors (GAAFET), Thin-Film Fully Depleted Silicon-On-Insulators (FDSOI) MOSFETs, Partially Depleted Silicon-On-Insulators (PDSOI) MOSFETs, Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), or conventional MOSFETs. This standard commercial FPGA IC chip may only communicate with other chips within the logic operation driver. The input / output circuitry of this standard commercial FPGA IC chip may only need to communicate with input / output drivers (I / O drivers) or input / output receivers (I / O receivers) and electrostatic discharge (ESD) devices. The drive capability, load, output capacitance, or input capacitance of this input / output driver, input / output receiver, or input / output circuitry is between 0.05 pF and 2 pF, or between 0.05 pF and 1 pF, or less than 2 pF or 1 pF.ESD devices are typically between 0.01pF and 2pF, or between 0.01pF and 1pF, or smaller than 2pF, 1pF, or 0.1pF. For example, a bidirectional (or tridirectional) I / O pad or circuit may include an ESD circuit, a receiver, and a driver, having input or output capacitance between 0.05pF and 2pF, or between 0.05pF and 1pF, or smaller than 2pF or 1pF. This small I / O circuit enables high performance and low power consumption for FPGA IC chips. All or most of the control and / or input / output circuitry or units are external to or not included in a standard commercial FPGA IC chip (e.g., off-logic-drive I / O circuitry, meaning large input / output circuitry used to communicate with circuitry or components of an external logic driver), but may be included in another dedicated control chip, a dedicated input / output chip, or a dedicated control and input / output chip within the same logic driver. The minimum (or no) area of ​​the standard commercial FPGA IC chip used for setting up control or input / output circuitry, such as less than 15%, 10%, 5%, 2%, 1%, 0.5%, or 0.1% of the area (excluding the chip's sealing ring and die cut areas, i.e., only including the area within the sealing ring boundary), or the standard commercial FPGA... The minimum (or none) transistor system in an IC chip is used to set up control or input / output circuits. For example, the number of transistors is less than 15%, 10%, 5%, 2%, 1%, 0.5%, or 0.1% used to set up control or input / output circuits, or all or most of the area of ​​a standard commercial FPGA IC chip is used for (i) logic blocks or units including logic gate matrices, arithmetic units or operation units, and / or look-up tables (LUTs) and multiplexers (multiplexers); and / or (ii) programmable interconnects (programmable interconnect lines). For example, in a standard commercial FPGA IC chip, more than 85%, more than 90%, more than 95%, more than 98%, more than 99%, more than 99.5%, or more than 99.9% of the area (excluding the chip's sealing ring and the chip's diced area, i.e., only including the area within the sealing ring boundary) is used to set up logic blocks and programmable interconnects, or all or most of the transistor system in a standard commercial FPGA IC chip is used to set up logic blocks, repeater arrays, and / or programmable interconnects, for example, the number of transistors is more than 85%, more than 90%, more than 95%, more than 98%, more than 99%, more than 99.5%, or more than 99.9% used to set up logic blocks and / or programmable interconnects.The area of ​​this standard commercial FPGA IC chip (as described above) is measured without a seal ring and chip dicing area; that is, the area only includes the region within the seal ring boundary. The standard repeating matrix in the FPGA chip further improves the manufacturing yield. Because the FPGA IC chip uses a standard, universal design, through-polymer metal vas (TPV) locations (hereinafter abbreviated as TPV) can be designed at fixed standard locations on the FPGA IC chip as a standard, universal design.

[0012] Another aspect of the present invention provides a standard commercial FPGA IC chip used in an FPGA / HBM CSP package, wherein the FPGA / HBM CSP is a standard commercial logic driver used in a multi-chip package, the standard commercial FPGA IC chip including complex logic blocks, the logic blocks or units including: (i) logic gate matrices including Boolean operators, such as NAND, NOR, AND and / or OR circuits; (ii) computation units including, for example, adders, multipliers, shift registers, floating point circuits and / or division circuits; (iii) look-up tables (LUTs) and multiplexers. The Boolean arithmetic unit, logic gate function, operation, or program can be executed using programmable lines or traces (programmable metal interconnects or traces) on the FPGA IC chip, while some Boolean arithmetic units, logic gate functions, operations, or programs can be executed using fixed lines or traces (metal interconnects or traces) on the FPGA IC chip. For example, adders and / or multipliers can be designed and implemented using fixed lines or traces (metal interconnects or traces) on the FPGA IC chip, and logic circuits connecting adders and / or multipliers. In addition, Boolean arithmetic units, logic gate functions, calculations, operations, or programs can be executed using, for example, lookup tables (LUTs) and / or multiplexers, where the LUT stores or remembers the logic gate operations or calculations, calculation results, decision-making processes, operations / actions, events, or activities. The lookup table can be used to perform logical functions based on truth tables. For example, the LUT in the SRAM cell can store or remember data or results. In a 5T or 6T SRAM cell, one of the two latch nodes of the four latch transistors can be connected or coupled to a multiplexer. The data stored in the 5T or 6T SRAM cell can be used on the LUTs. When a set of data, requirements or conditions are input, the multiplexer selects the corresponding data (or result value) from the data stored or remembered in the LUTs according to the set of data, requirements or conditions.For example, a 4-input NAND gate can be used as an operator having LUTs and a multiplexer, as described below: A 4-input NAND gate with 4 inputs and 16 (possibly) corresponding outputs, the circuitry required to perform the same function of a 4-input NAND operation using LUTs and a multiplexer includes: (i) a LUT for storing and memorizing the 16 (possibly) corresponding inputs (result values); (ii) a multiplexer designed and used to select the correct (corresponding) output based on a specific 4-input control or instruction data set (e.g., 1, 0, 0, 1); that is, the 16 input data (the data stored in the memory) and the control or instruction data for the multiplexer. Typically, a LUT and a multiplexer perform the same NAND function as the operator, which includes n inputs. The LUT can store or memorize 2n corresponding data or structures, and the multiplexer selects the correct (corresponding) output from the memorized 2n corresponding data or results based on a specific n-input control or instruction data set. The corresponding data or results are memorized or stored in 5T or 6T SRAM cells, which are 2n memory cells.

[0013] The complex programmable interconnects in a standard commercial FPGA IC chip include a complex number of cross-point switches located in the middle of the complex programmable interconnects. For example, n metal lines are connected to the input of the complex cross-point switches, and m metal lines are connected to the output of the complex cross-point switches, wherein the cross-point switches are located between the n metal lines and the m metal lines. These crosspoint switches are designed so that each n-metal line can be programmably connected to any m-metal line. Each crosspoint switch may include, for example, an on / off circuit comprising a pair of n-type transistors and a p-type transistor. One n-metal line can be connected to the source terminals of the pair of n-type transistors and p-type transistors in the on / off circuit, while one m-metal line is connected to the drain terminals of the pair of n-type transistors and p-type transistors in the on / off circuit. The on or off state (on or off) of the crosspoint switch is controlled by data (0 or 1) stored or latched in an SRAM cell. Because standard commercial FPGA IC chips include conventional and repeating gate matrices or blocks, LUTs and multiplexers or programmable interconnects, just like commercial standard DRAM chips and NAND flash IC chips, they have very high yields for processes with chip areas such as greater than 50 mm 2 or 80 mm 2, for example, greater than 70%, 80%, 90% or 95%.

[0014] Additionally, each crosspoint switch includes, for example, a switching buffer, which includes a first-stage inverter / buffer, a control N-MOS transistor, and a control P-MOS transistor. One n-wire is connected to the common (already connected) gate terminal of the input stage inverter in the pass / no-pass circuit, and one m-wire is connected to the common (already connected) drain terminal of the output stage inverter in the pass / no-pass circuit. This output stage is formed by stacking the control P-MOS and the control N-MOS, with the control P-MOS at the top (located between Vcc and the source of the P-MOS of the output stage inverter) and the control N-MOS at the bottom (located between Vss and the source of the N-MOS of the output stage inverter). The connection or disconnection state (pass or no) of the crosspoint switch is controlled by data (0 or 1) stored in 5T or 6T SRAM cells.

[0015] Alternatively, the crosspoint switch may include, for example, a multiplexer and a switching buffer. The multiplexer selects one of the n input data from n input metal lines based on data stored in a 5T or 6T SRAM cell and outputs one of the selected inputs to a switching buffer. The switching buffer, based on data stored in the 5T or 6T SRAM cell, connects the output data from the multiplexer to a metal line to the output of the switching buffer, with or without the data from the multiplexer. The switching buffer includes a two-stage inverter (buffer), a control N-MOS, and a control P-MOS. The data selected from the multiplexer is connected to the common (connection) gate terminal of the input stage inverter of the buffer. One of the m metal lines or traces is connected to the common (connection) drain terminal of the output stage inverter of the buffer. The output stage inverters are stacked and have a control PMOS located on top (between Vcc and the source of the P-MOS of the output stage inverter) and a control N-MOS located at the bottom (between Vcc and the source of the P-MOS of the output stage inverter). The connection or disconnection of the switching buffer (between ss and the source of the N-MOS of the output stage inverter) is controlled by data (0 or 1) stored in 5T or 6T SRAM cells.

[0016] The programmable interconnects of a standard commercial FPGA IC chip include one (or multiple) multiplexers located in the middle (or between) of interconnect metal lines. The data stored in each 5T or 6T SRAM cell of this multiplexer is selected from n metal interconnects and connected to one metal interconnect to the output of the multiplexer. For example, if the number of metal interconnects n=16, the 4-bit data stored in each of the four 5T or 6T SRAM cells needs to select any one of the 16 metal interconnects connected to the 16 inputs of the multiplexer and connect or couple the selected metal interconnect to a metal interconnect connected to the output of the multiplexer. A data is selected from the 16 inputs and coupled, or connected to the metal line connected to the output of the multiplexer.

[0017] Another aspect of the present invention provides a standard commercial logic driver in a multi-chip package, the multi-chip package including a plurality of standard commercial FPGA / HBM CSPs packages and one (or more) non-volatile memory IC chips, which are programmed for use in different algorithms, architectures and / or applications requiring computing and / or processing functions, wherein each of the plurality of standard commercial FPGA / HBM CSPs packages includes (i) a standard commercial FPGA IC chip, and (ii) an HBM chip bonded or disposed on the standard commercial FPGA IC chip or a package formed by stacking a plurality of HBM chips bonded or disposed on the standard commercial FPGA IC chip. Each standard commercial FPGA IC chip may have standard common features, quantities, or specifications: (1) logic blocks, including (i) system gates with a quantity greater than or equal to 2M, 10M, 20M, 50M, or 100M, (ii) logic units or elements with a quantity greater than or equal to 64K, 128K, 512K, 1M, 4M, or 8M, (iii) hard cores, such as DSP slices, microcontroller cores, multiplexer cores, fixed-line adders and / or fixed-line multipliers, and / or (iv) memory blocks with a quantity equal to or greater than 1M, 10M, 50M, 100M, 200M, or 500M; In some cases, the standard commercial FPGA IC chip may include logic blocks of system gates (such as logic units or elements in (i) and (iii), but not hard macros). (1) macros, the hard macros may be included in other chips of the logic driver, such as dedicated control chips, dedicated I / O chips, dedicated control and I / O chips, IAC chips or DPIIC chips included in the logic driver; (2) the number of inputs for each logic block or operator, which may be greater than or equal to 4, 8, 16, 32, 64, 128 or 256; (3) the power supply voltage: the voltage may be between 0.2V (volts) and 2.5V, between 0.2V and 2V, between 0.2V and 1.5V, between 0.1V and 1V or between 0.2V and 1V, or less than (below) or equal to 2.5V, 2V, 1.8V, 1.5V or 1V; (4) the layout, location, number and function of I / O pads; (5) the complex number of TSVs of silicon substrate in the FPGA IC chip in terms of layout, location, number and function. Because FPGA chips are standard commercial IC chips, the number of designs or products using FPGA chips per technology node is reduced to a very small number. Therefore, the expensive photomasks or photomask assemblies required for FPGA chips manufactured using advanced semiconductor nodes or generations can be reduced by at least a few. For example, for a specific technology node or generation of semiconductor technology, this can be reduced to 3 to 20 photomask assemblies, 3 to 10 photomask assemblies, or 3 to 5 photomask assemblies. This significantly reduces NRE (Network Replication) and production costs.With minimal design and product input, the manufacturing process can be tailored or optimized for a small number of chip designs or products, resulting in very high chip yields. This is similar to the design and production of current advanced standard commercial DRAM or NAND flash memory. Furthermore, chip inventory management becomes easier, more efficient, and more effective, thus reducing FPGA chip delivery time and making it highly cost-effective.

[0018] Another aspect of the present invention provides a standard commercial logic driver in a multi-chip package, comprising a plurality of standard commercial FPGA IC chips (located in an FPGA / HBM CSP package) and one (or more) non-volatile memory IC chips, for use by field programming for logic, computation and / or arithmetic functions required for different applications, wherein each of the plurality of standard commercial FPGA IC chips is located in an FPGA / HBM CSP package, and each standard commercial FPGA IC chip may have the standard common features or specifications as described above, similar to standard commercial DRAM IC chips used in DRAM modules. Each of the standard commercial FPGA IC chips in the logic driver further includes additional I / O pins or pads, such as: (1) a chip enable pin or pad, (2) two (or more) input select pins or pads, (3) two (or more) output select pins or pads, each standard commercial FPGA IC chip having the standard common features or specifications described above, similar to standard commercial DRAM IC chips used in DRAM modules. The IC chip may include, for example, four I / O ports, each of which may include 64 bidirectional I / O circuits. The additional I / O pins or pads are used to select one I / O port from the four I / O ports for each standard commercial FPGA IC chip in a standard commercial logic driver. The data, signal, and / or power / ground bus of the interconnection line structure (e.g., TISD and FOISD) on the FOIT multi-chip package structure for connecting two (or more) standard commercial FPGA IC chips in the logic driver may also include multiple bus lines corresponding to the multiple I / O ports (on the FPGA IC chip). Each bus line may include n bus lines or traces, where the number of n is greater than or equal to 4, 8, 16, 32, 64, 128, 256, 512, or 1024.

[0019] Another aspect of the present invention discloses a standard commercial logic driver within a multi-chip package, the multi-chip package comprising a plurality of standard commercial FPGA / HBM CSPs packages and one (or more) non-volatile memory IC chips. The standard commercial logic driver is field-programmable for logic, computation, and / or processing functions required for different applications. Each FPGA / HBM CSP package comprises a standard commercial FPGA IC chip and an HBM chip located on the standard commercial FPGA IC chip, or a package formed by stacking a plurality of HBM chips bonded or disposed on the standard commercial FPGA IC chip. Each of the plurality of standard commercial FPGA IC chips has the standard common features or specifications described above. Each standard commercial FPGA IC chip includes a plurality of logic blocks, wherein each logic block may, for example, include (1) 1 to 16 8x8 adders, (2) 1 to 16 8x8 multipliers, (3) 256 to 2K logic units, wherein each logic unit includes one register and four look-up tables. LUT), wherein each LUT includes 4 to 256 data or information bits, and the aforementioned 1 to 16 8x8 adders and / or 1 to 16 8x8 multipliers can be designed and formed by fixed metal lines or fixed lines (metal interconnects or fixed interconnects) on each FPGA IC chip.

[0020] Another aspect of the present invention provides a standard commercial logic driver in a multi-chip package, the multi-chip package comprising a standard commercial multiple FPGA / HBM CSPs package and one (or more) non-volatile memory IC chips, which are programmed for use in different algorithms, architectures and / or applications requiring computation and / or processing functions, wherein each FPGA / HBM CSPs package comprises a standard commercial FPGA IC chip and an HBM chip located on the standard commercial FPGA IC chip or a package formed by stacking multiple HBM chips bonded or disposed on the standard commercial FPGA IC chip, the standard commercial logic driver may have standard common features, quantities or specifications: (1) logic blocks, including (i) system gates with a number greater than or equal to 8M, 40M, 80M, 200M or 400M, (ii) logic units or elements with a number greater than or equal to 256K, 512K, 1M, 2M, 4M, 16M or 32M, (iii) hard cores, such as DSPs. (i) Slice, microcontroller core, multiplexer core, fixed-line adder and / or fixed-line multiplier and / or (iv) the number of memory blocks equal to or greater than 4M, 40M, 200M, 400M, 800M or 2G bits; (ii) power supply voltage: the voltage may be between 0.1V (volts) and 12V, between 0.1V and 7V, between 0.1V and 3V, between 0.1V and 2V, between 0.1V and 1.5V or between 0.1V and 1V; (iii) the layout, location, number and function of I / O pads in a multi-chip package of a standard commercial logic driver, wherein the logic driver may include I / O pads, metal bumps or metal pillars connected or coupled to one (or more, for example 2, 3, 4 or more) USB ports, one or more IEEE 10 ... The logic driver comprises multiple single-layer packaged volatile memory drivers with four ports, one or more Ethernet ports, one or more audio ports, or serial ports such as RS-32 or COM ports, wireless transceiver I / O ports, and / or Bluetooth transceiver ports. The logic driver may also include I / O pads, metal bumps, or metal pillars connecting or coupling to Serial Advanced Technology Attachment (SATA) or Peripheral Components Interconnect express (PCIe) terminals for memory driver applications. Therefore, this logic driver is a standard commercial product, making inventory management easy, efficient, and effective, thus shortening FPGA chip delivery time and becoming highly cost-effective.

[0021] On the other hand, the present invention discloses a commercial standard logic driver in a multi-chip package, which includes a dedicated control chip. This dedicated control chip is designed to implement and manufacture various semiconductor technologies, including older or mature technologies, such as those not advanced to, equal to, or greater than 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm, or 500 nm. Alternatively, this dedicated control chip may use prior semiconductor technologies, such as those advanced to or equal to, or less than or equal to 40 nm, 20 nm, or 10 nm. This dedicated control chip may use semiconductor technologies of generation 1, 2, 3, 4, 5, or greater than 5 generations, or use more mature or more advanced technologies within a standard commercial FPGA IC chip package in the same logic driver. The transistors used in the dedicated control chip may be FINFETs, fully depleted silicon-on-insulator (FDSOI) MOSFETs, partially depleted silicon-on-insulator MOSFETs, or conventional MOSFETs. The transistors used in the dedicated control chip can be different from those used in the standard commercial FPGA IC chip package in the same logic unit. For example, the dedicated control chip uses conventional MOSFETs, but the standard commercial FPGA IC chip package in the same logic driver FPGA / HBM CSP package structure can use FINFET transistors; or the dedicated control chip uses FDSOI MOSFETs, but the standard commercial FPGA IC chip package in the same logic driver can use FINFET. The dedicated control chip provides the following control functions: (1) downloading programming code from outside (outside the logic driver) to the non-volatile IC chip in the logic driver; (2) downloading programming code from the non-volatile IC chip in the logic driver to the 5T or 6T SRAM cell of the programmable interconnect line on the standard commercial FPGA IC chip, or, the programming code from the non-volatile IC chip in the logic driver can pass through the buffer or driver in the dedicated control chip before entering the 5T or 6T SRAM cell of the programmable interconnect line on the standard commercial FPGA IC chip, and the buffer or driver in the dedicated control chip can latch the data from the non-volatile chip and increase the bit width of the data.For example, if the data bit width from a non-volatile chip (under a SATA standard) is 1 bit, the buffer can latch that 1 bit of data in each SRAM cell in the buffer and output the data stored or latched in multiple SRAM cells in parallel while simultaneously increasing the data bit width; for example, equal to or greater than 4, 8, 16, 32 or 64 data bit widths. As another example, if the data bit width from a non-volatile chip (under a PCIe standard) is 32 bits, the buffer can increase the data bit width to be equal to or greater than 64, 128 or 256 data bit widths. The buffer located in the dedicated control chip can amplify the data signal from the non-volatile chip; (3) Input / output signals are used for a user application migration program; (4) Power management; (5) Downloading data from the non-volatile IC chip in the logic driver to the 5T or 6T SRAM cells of the LUTs on the standard commercial FPGA IC chip. Alternatively, data from a non-volatile IC chip in a logic driver can pass through a buffer or driver in a dedicated control chip or through LUTs on a standard commercial FPGA IC chip before being fed into a 5T or 6T SRAM cell. The buffer in the dedicated control chip can latch data from the non-volatile IC chip and increase data bandwidth. For example, if the data bandwidth from a non-volatile IC chip (in standard SATA) is 1 bit, the buffer can latch this 1 bit of data in each of multiple SRAM cells in the buffer and output the data stored or latched in multiple parallel SRAM cells while simultaneously increasing the data bit width, for example, equal to or greater than 4-bit bandwidth, 8-bit bandwidth, 16-bit bandwidth, 32-bit bandwidth, or 64-bit bandwidth. Another example is that if the data bit bandwidth from a non-volatile IC chip is 32 bits (in standard PCIs types), the buffer can increase the data bit bandwidth to greater than or equal to 64-bit bandwidth, 128-bit bandwidth, or 256-bit bandwidth. The driver in the dedicated control chip can amplify the data signal transmitted from the non-volatile IC chip.

[0022] Another aspect of the present invention provides a standard commercial logic driver in a multi-chip package that further includes a dedicated I / O chip. This dedicated I / O chip uses various semiconductor technology nodes or generations, including older or more mature technology nodes or generations, such as those below or equal to (or greater than or equal to) 20 nm, to design, implement, and manufacture the chip, or those with semiconductor technology nodes or generations equal to 40 nm, 50 nm, 90 nm, 130 nm, 250 nm, 350 nm, or 500 nm. This makes the semiconductor technology node or generation of the dedicated I / O chip greater than 1, 2, 3, 4, 5 generations or more than 5 generations of older or more mature technology nodes; more mature or advanced than the standard commercial FPGA IC chip packaged in the same logic driver (in an FPGA / HBM CSP package structure). The transistor used in the dedicated I / O chip can be a Fin Field-Effect Transistor (FIN). (FINFET)), Silicon-On-Insulator (FINFET SOI)), Thin-film fully depleted Silicon-On-Insulator (FDSOI) MOSFET, Partially Depleted Silicon-On-Insulator (PDSOI)), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or conventional MOSFET. The transistors used in this dedicated I / O chip may differ from the transistors in the standard commercial FPGA IC chip packaged in the same logic driver. For example, the transistors in the dedicated I / O chip may be conventional MOSFETs, while the standard commercial FPGA IC chip packaged in the same logic driver may use FinFETs. Alternatively, the transistors in the dedicated I / O chip and / or the dedicated control and I / O chip may be FDSOI MOSFETs, while the standard commercial FPGA IC chip packaged in the same logic driver may use FinFETs. The power supply voltage of the dedicated I / O chip may be greater than or equal to 1.5V, 2.0V, 2.5V, 3V, 3.5V, 4V, or 5V, while the power supply voltage of the standard commercial FPGA IC chip packaged in the same logic driver may be less than or equal to 2.5V, 2V, 1.8V, or 1.The power supply voltage for dedicated I / O chips and / or dedicated control and I / O chips may differ from the power supply voltage of standard commercial FPGA IC chips packaged in the same logic driver. For example, when the power supply voltage for dedicated I / O chips and / or dedicated control and I / O chips is 4V, the power supply voltage for standard commercial FPGA IC chips packaged in the same logic driver is 1.5V. Conversely, when the power supply voltage for dedicated I / O chips and / or dedicated control and I / O chips is 2.5V, the power supply voltage for standard commercial FPGA IC chips packaged in the same logic driver is 0.75V. The gate oxide (physical property) thickness of the FETs in the dedicated I / O chip may be greater than or equal to 5 nm, 6 nm, 7.5 nm, 10 nm, 12.5 nm, or 15 nm, while the gate oxide (physical property) thickness of the FETs in the standard commercial FPGA IC chip in the same logic driver may be thinner than 4.5 nm, 4 nm, or 3 nm. The gate oxide (physical property) thickness of the FETs in a dedicated I / O chip can differ from the gate oxide (physical property) thickness of the FETs in a standard commercial FPGA IC chip within the same logic driver. For example, the gate oxide (physical property) thickness of the FETs used in this dedicated I / O chip is 10 nm, while the gate oxide (physical property) thickness of the FETs in the standard commercial FPGA IC chip within the same logic driver is 3 nm; and the gate oxide (physical property) thickness of the FETs used in this dedicated I / O chip is, for example, 7 nm.The gate oxide (physical property) of the FETs in the standard commercial FPGA IC chip in the same logic driver is 2nm. This dedicated I / O chip provides input and output for the logic driver and ESD protection. The dedicated I / O chip can provide (i) large drivers or receivers, or I / O circuits for communication with external circuitry of the logic driver, and (ii) small drivers or receivers, or I / O circuits for communication between multiple chips in the logic driver. The drive capability, load, output capacitance (capacitance), or capacitance of the large drivers or receivers, or I / O circuits for communication with external circuitry of the logic driver, is greater than the capacitance of the small drivers or receivers used for communication within the chip in the logic driver. The drive capability, load, output capacitance (capacitance), or capacitance of the large I / O drivers or receivers, or those used for communication with external circuitry (outside the logic driver), can be between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, or between 2 pF and 15 pF. Small drivers or receivers for chip-to-chip communication in logic drivers, with drive capability, load, output capacitance (capacity) or capacitance between 0.1 pF and 10 pF, between 0.1 pF and 5 pF, or greater than 2 pF, 3 pF, 5 pF, 10 pF, 15 pF or 20 pF, between 0.1 pF and 10 pF, between 0.1 pF and 5 pF, between 0.1 pF and 2 pF or between 0.1 pF and 1 pF, or less than 10 pF, 5 pF, 3 pF, 2 pF or 1 pF. The ESD protector on this dedicated I / O chip is larger than the ESD protector on a standard commercial FPGA IC chip in the same logic driver. The size of the ESD protector in this large I / O circuit can be between 0.5 pF and 20 pF, between 0.5 pF and 15 pF, between 0.5 pF and 10 pF, between 0.5 pF and 5 pF, between 0.5 pF and 2 pF; or greater than 0.5 pF, 1 pF, 2 pF, 5 pF, or 10 pF. For example, bidirectional (or tridirectional) I / O pads or circuits used in large I / O drivers or receivers, or for I / O circuits communicating externally with logic drivers, may include an ESD circuit, a receiver, and a driver, with input and output capacitances ranging from 2 pF to 100 pF, from 2 pF to 50 pF, from 2 pF to 30 pF, from 2 pF to 20 pF, from 2 pF to 15 pF, from 2 pF to 10 pF, or from 2 pF to 5 pF; or greater than 2 pF, 3 pF, 5 pF, 10 pF, 15 pF, or 20 pF. pF, for example, the input and output capacitances of bidirectional (or tridirectional) I / O pads or circuits used in small I / O drivers or receivers, or in I / O circuits for communication between chips within logic drivers, can be between 0.05 pF and 2 pF, or between 0.1 pF and 1 pF; or less than 2 pF or 1 pF.

[0023] In a standard commercial logic unit, a dedicated I / O chip (or multiple chips) in a multi-chip package may include a buffer and / or driver circuitry as (1) downloading programmable software source code from a non-volatile IC chip in the logic unit to a 5T or 6T SRAM cell on a programmable interconnect on a standard commercial FPGA chip. The programmable software source code or data from the non-volatile IC chip in the logic unit may pass through a buffer or driver in the dedicated I / O chip before being accessed to a 5T or 6T SRAM cell on a programmable interconnect on a standard commercial FPGA chip. The buffer of the dedicated I / O chip can latch the data from the non-volatile chip and increase the data bandwidth. For example, if the data bandwidth from a non-volatile chip (in standard SATA) is 1 bit, the buffer can latch this 1 bit of data in each of multiple SRAM cells in the buffer and output the data stored or latched in multiple parallel SRAM cells while simultaneously increasing the data bit width, for example, equal to or greater than 4-bit bandwidth, 8-bit bandwidth, 16-bit bandwidth, 32-bit bandwidth, or 64-bit bandwidth. Another example is if the data bit bandwidth from a non-volatile chip is 32 bits (in standard PCIs types), the buffer can increase the data bit bandwidth to greater than or equal to 64-bit bandwidth, 128-bit bandwidth, or 256-bit bandwidth. The driver in the dedicated I / O chip can amplify data signals from the non-volatile chip; (2) data is downloaded from the non-volatile IC chip in the logic driver to the 5T or 6T SRAM cell of the LUTs on the standard commercial FPGA IC chip. Before the data from the non-volatile chip enters the 5T or 6T SRAM cell of the LUT on the standard commercial FPGA chip, the driver may pass through a dedicated I / O chip. Buffers or drivers in a dedicated I / O chip can latch data from a non-volatile chip and increase the bit width of that data. For example, if the data bandwidth from the non-volatile chip (in standard SATA) is 1 bit, the buffer can latch this 1 bit of data in each of multiple SRAM cells in the buffer and output the data stored or latched in multiple parallel SRAM cells while simultaneously increasing the data bit width, for example, equal to or greater than 4-bit bandwidth, 8-bit bandwidth, 16-bit bandwidth, 32-bit bandwidth, or 64-bit bandwidth. Another example is that if the data bit bandwidth from the non-volatile chip is 32 bits (in standard PCIs types), the buffer can increase the data bit bandwidth to greater than or equal to 64-bit bandwidth, 128-bit bandwidth, or 256-bit bandwidth. Drivers in a dedicated I / O chip can amplify the data signals transmitted from the non-volatile chip.

[0024] A dedicated I / O chip in a multi-chip package of a standard commercial drive may include I / O circuitry or pads (or micro-copper pillars or bumps) for connection or coupling to one (or more) (2, 3, 4 or more) USB ports, one or more IEEE multiple single-layer package volatile memory drive ports, one or more Ethernet ports, one or more audio ports or serial ports, such as RS-32 or COM ports, wireless transceiver I / O ports, and / or Bluetooth transceiver ports. The dedicated I / O chip may also include communication, connection, or coupling to a memory disk I / O circuitry or pads (or micro-copper pillars or bumps) for connection to SATA ports or PCIe ports.

[0025] Another aspect of the present invention provides a standard commercial logic driver in a multi-chip package, the standard commercial logic driver comprising a plurality of standard commercial FPGA / HBM CSP packages and one (or more) non-volatile IC chips for various applications requiring logic, computation, and / or processing functions via field programming, wherein the one (or more) non-volatile memory IC chips comprise bare die format or multi-chip format NAND flash chips, each NAND may have a standard memory density, internal capacity, or size greater than or equal to 64Mb, 512Mb, 1Gb, 4Gb, 16Gb, 64Gb, 128Gb, ​​256Gb, or 512Gb, where "b" represents bits, and the NAND flash chips may be designed and manufactured using advanced NAND flash technology or next-generation process technology, for example, technology advanced to or equal to 45nm, 28nm, 20nm, 16nm, and / or At 10nm, advanced NAND flash technology may include the use of single-level cells (SLC) or multiple-level cells (MLC) technologies (e.g., double-level cells (DLC) or triple-level cells (TLC)) in planar flash memory (2D-NAND) or 3D flash memory (3D NAND) structures. 3D NAND structures may include stacked layers (or levels) of multiple NAND memory cells, such as stacked layers with 4, 8, 16, 32, or 72 NAND memory cells or more.

[0026] Another aspect of the present invention provides a standard commercial logic driver in a multi-chip package, the standard commercial logic driver comprising multiple standard commercial FPGA / HBM CSP packages and one (or more) non-volatile IC chips for various applications requiring logic, computation and / or processing functions via field programming, wherein the one (or more) non-volatile memory IC chips comprise bare die format or multi-chip format NAND flash chips, the standard commercial logic driver may have a standard non-volatile memory density, capacity or size greater than or equal to 8MB, 64MB, 128MB, 512MB, 1GB, 4GB, 16GB, 64GB, 256GB or 512GB, wherein “B” is a byte, and each byte has 8 bits.

[0027] Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package, the commercial standard logic driver comprising multiple standard commercial FPGA / HBM CSPs packages, dedicated control and I / O chips and one (or more) non-volatile memory IC chips, which are field-programmed for logic, calculation and / or processing functions required for various applications. The communication between the multiple chips in the logic driver and the communication between each chip in the logic driver and external circuits or external circuits outside the logic driver are as follows: (1) The dedicated control and I / O chip communicates directly with other chips or multiple chips in the logic driver, and can also communicate with external circuits or external circuits outside the logic driver. The dedicated control and I / O chip includes two types of multiple I / O circuits. One type has a large drive capability, a large load, a large output capacitance or a large input capacitance for direct communication with external circuits or external circuits outside the logic driver, while the other type has a small drive capability, a small load, a small output capacitance or a small input capacitance for direct communication with other chips or multiple chips in the logic driver; (2) Each FPGA IC chip (in FPGA / HBM) In CSP packages, I / O circuits can communicate directly with other chips or multiple chips within the logic driver, but not with external circuits outside the logic driver. The I / O circuits within the multiple FPGA IC chips can communicate indirectly with external circuits outside the logic driver via (or through) the I / O circuits in dedicated control and I / O chips. The driving capability, load, output capacitance, or input capacitance of the I / O circuits in the dedicated control and I / O chips is significantly greater than that of the I / O circuits in one of the FPGA IC chips. The I / O circuits of one of the FPGA IC chips are connected or coupled to a large I / O circuit of the dedicated I / O chip (e.g., input or output capacitance greater than 2). (3) The dedicated control chip communicates only with other chips (or multiple chips) of the logic driver, but does not communicate directly with external circuits or does not communicate with external circuits; wherein one of the I / O circuits in the dedicated control chip does not communicate directly with the outside via one of the I / O circuits of the dedicated I / O chip; wherein the driving capability, load, output capacitance or input capacitance of the I / O circuit of the dedicated I / O chip is significantly greater than that of the I / O circuit of the dedicated control chip, wherein the dedicated control chip includes two I / O circuits, a small one and a large one, for these two types of communication; (4) Each non-volatile memory IC chip communicates directly with one (or more) other chips of the logic driver, but does not communicate directly with (the outside of the logic driver) or the outside; the I / O circuit of one (or more) non-volatile memory IC chip can communicate indirectly with the outside or the outside (logic driver) through the I / O circuit of the dedicated I / O chip.In this context, the driving capability, load, output capacitance, or input capacitance of the I / O circuit of the dedicated I / O chip is significantly greater than the driving capability of the I / O circuit of one (or more) non-volatile memory IC chips. Furthermore, one (or more) non-volatile memory IC chips can communicate directly with another (or more) chips in the logic driver, and can also communicate externally or directly with the logic driver. One (or more) non-volatile memory IC chips include small and large I / O circuits for both types of communication. Additionally, the dedicated control chip can communicate directly with other chips in the logic driver, and can also communicate directly with external circuits. The phrase "object X communicates directly with object Y" means that object X (e.g., the first chip in the logic driver) communicates or is coupled directly with object Y without needing to go through any chip in the logic driver. In the above context, "object X does not communicate directly with object Y" means that object X (e.g., the first chip in a logic driver) can communicate or be coupled to object Y indirectly, either without going through or through multiple chips in the logic driver. Conversely, "object X does not communicate with object Y" means that object X (e.g., the first chip in a logic driver) does not communicate or be coupled to object Y directly or indirectly. In other words, object X (e.g., the first chip in a logic driver) neither communicates or is coupled directly to object Y, nor does it communicate or be coupled indirectly to object Y.

[0028] Another aspect of the present invention discloses a commercial standard logic driver in a multi-chip package, the commercial standard logic driver including a dedicated control and I / O chip that provides the functions of the dedicated control chip and the dedicated I / O chip as described above in one chip.

[0029] Another example of the present invention discloses a development kit or tool for a user or developer to implement an innovative technology or application technology using (via) a commercial standard logic driver. A user or developer with an innovative technology, new application concept or idea can purchase a commercial standard logic driver and use the corresponding development kit or tool to develop, or write software source code or program and load it into multiple non-volatile memory chips in a commercial standard logic driver to realize his (or her) innovative technology or application concept idea.

[0030] Another aspect of the present invention discloses a type of logic driver in a multi-chip package, which further includes an innovative ASIC chip or COT chip (hereinafter referred to as IAC) as an intellectual property (IP) circuit, application specific (AS) circuit, analog circuit, mixed-mode signal circuit, radio frequency (RF) circuit and / or transceiver, receiver, transceiver circuit, etc. The IAC chip can be designed and manufactured using various semiconductor technologies, including older or mature technologies, such as those not advanced than, equal to, or greater than 20nm, 30nm, 40nm, 50nm, 90nm, 130nm, 250nm, 350nm, or 500nm. Alternatively, the IAC chip can be manufactured using advanced semiconductor technology nodes or generations, such as those more advanced than 40 nm, 20 nm, or 10 nm. This IAC chip can utilize semiconductor technologies of generation 1, 2, 3, 4, 5, or higher, or use more mature or advanced technologies within a standard commercial FPGA IC chip package in the same logic driver. The transistors used in the IAC chip can be FINFET, FDSOI MOSFET, PDSOI MOSFET, or conventional MOSFETs. The transistors used in the IAC chip can differ from those used in the standard commercial FPGA IC chip package within the same logic driver; for example, the IAC chip may use conventional MOSFETs, but the standard commercial FPGA IC chip package within the same logic driver may use FINFET transistors; or the IAC chip may use FDSOI MOSFETs, but the standard commercial FPGA IC chip package within the same logic driver may use FINFET transistors. IAC chips can be designed and manufactured using a variety of semiconductor technologies, including older or mature technologies, such as those that are not more advanced than, equal to or greater than 30nm, 40nm, 50nm, 90nm, 130nm, 250nm, 350nm or 500nm. Moreover, NRE costs are cheaper than existing or conventional ASIC or COT chips that use advanced IC processes or next-generation process technologies, such as those more advanced than 30nm, 20nm or 10nm technologies.Designing an existing or conventional ASIC or COT chip using advanced IC processes or next-generation processes, for example, compared to designs using 30nm, 20nm, or 10nm technologies, would cost over US$5 million, US$10 million, US$20 million, or even over US$50 million or US$100 million. For instance, the cost of photomasks required for 16nm technology or process generations of ASIC or COT IC chips exceeds US$2 million, US$5 million, or US$10 million. However, if the same or similar innovations or applications are achieved using logic drivers (including IAC chips), and older or less advanced technology or process generations are used, this NRE cost can be reduced to less than US$10 million, US$7 million, US$5 million, US$3 million, or US$1 million. For the same or similar innovative technologies or applications, compared with the development of existing conventional logic operation ASIC IC chips and COT IC chips, the NRE cost of developing IAC chips using the same or similar ideas and / or applications can be reduced by more than 2, 5, 10, 20, or 30 times. Innovators can save costs and implement innovation more easily by: (i) designing IAC chips using older and more mature technology nodes (e.g., 40 nm or greater than or equal to 20 nm mature nodes); and (ii) using standard commercial FPGA IC chips packaged in the same logic driver, wherein the standard commercial FPGA IC chips are manufactured using advanced technology nodes, such as 7 nm technology nodes, or technologies higher than 20 nm or higher than 7 nm.

[0031] The present invention further discloses a method for transforming the existing hardware industry model of logic ASIC chips or COT chips into a software industry model through a logic driver. In the same innovation and application, logic drivers should be better or the same as existing conventional ASIC chips or conventional COT IC chips in terms of performance, power consumption, engineering and manufacturing costs. Existing ASIC chip or COT IC chip design companies or suppliers can become major software developers or suppliers, using only older or less advanced semiconductor technologies or process generations to design IAC chips as described above. This disclosure may include (1) designing and owning IAC chips; (2) procuring multiple commercial standard FPGA chips and standard commercial non-volatile memory chips of bare-chip or packaged types from third parties; (3) designing and manufacturing (which may be outsourced to a third party of the manufacturing provider) logic drivers containing owned IAC chips; (4) installing internal development software into logic drivers and standard commercial non-volatile memory chips for innovative technologies or new application needs; and / or (5) selling pre-installed logic drivers to their customers, in which case they can still sell hardware that does not use traditional expensive ASIC IC chips or COT IC chips designed and manufactured using advanced semiconductor technologies. IC chips, such as those using technologies more advanced than 30nm, 20nm, or 10nm. They can write software source code to program multiple commercial standard FPGA IC chips in logic drivers for desired applications, such as artificial intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IoT), industrial computing, virtual reality (VR), augmented reality (AR), autonomous or driverless vehicles, automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC), or central processing unit (CP) functions, or any combination thereof.

[0032] Another example of the present invention discloses that the logic driver type in a multi-chip package may include a standard commercial FPGA / HBM CSP package and one (or more) non-volatile IC chips, and further includes an arithmetic IC chip and / or a computing IC chip, such as one (or more) central processing unit (CPU) chip, one (or more) graphics processing unit (GPU) chip, one (or more) digital signal processing (DSP) chip, one (or more) tensor processing unit (TPU) chip and / or one (or more) application-specific processor (APU) chip designed and manufactured using advanced semiconductor technology or advanced generation technology, such as semiconductor advanced processes that are more advanced or equivalent to, or smaller or the same as, 50 nanometer (nm), 20nm, 20nm or 10nm, or semiconductor advanced processes that are more advanced than FPGA IC chips used in the same logic driver. Alternatively, the logic driver may include a combination of the following computing and / or computational IC chips: (1) for example, 2, 3, 4 or more GPU chips; (2) one or more CPU chips and / or one or more GPU chips; (3) one or more CPU chips and / or one or more DSP chips; (4) one or more CPU chips and / or one or more TPU chips; or (5) one or more CPU chips and / or one or more GPU chips (or one or more TPU chips). In all of the above alternatives, the logic driver may include an OR processing IC chip and a computational IC chip, and one or more high-speed, wide-bandwidth and high-bandwidth cache SRAM chips or DRAM IC chips (HBM chips) for high-speed parallel operation and / or computational functions. For example, a logic driver may include multiple GPU chips, such as 2, 3, 4, or more than 4 GPU chips, and high-bandwidth cache SRAM chips or DRAM IC chips (HBM chips). The bit width of communication between one of the GPU chips and one of the high-bandwidth cache SRAM chips or DRAM IC chips (HBM chips) may be equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. As another example, a logic driver may include multiple TPU chips, such as 2, 3, 4, or more than 4 TPU chips, and multiple high-bandwidth cache SRAM chips or DRAM IC chips. The bit width of communication between one of the TPU chips and one of the SRAM or DRAM IC chips may be equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K.

[0033] The communication, connection, or coupling system between a logic chip, a processing chip, and / or a computing chip (e.g., FPGA, CPU, GPU, DSP, APU, TPU, and / or ASIC chip) and a high-speed, high-bandwidth SRAM, DRAM, or NVM RAM (e.g., MARM, RRAM) chip is via the TISD or FISD of the FOIT multi-chip package structure described below. The connection and communication methods are similar to or of the same type as the internal circuitry within the same chip. Furthermore, the communication, connection, or coupling system between a logic chip, a processing chip, and / or a computing chip (e.g., FPGA, CPU, GPU, DSP, APU, TPU, and / or ASIC chip) and a high-speed, high-bandwidth, and high-data-bit-width SRAM, DRAM, or NVM RAM chip is via the TISD or FISD of the FOIT multi-chip package structure described below, and can be used between the logic, processing, and / or computing chip and the SRAM, DRAM, or NVM RAM. The small I / O driver and small receiver of the RAM chip are connected or coupled, wherein the driving capability, load, output capacitance, or input capacitance of the small I / O driver, small receiver, or I / O circuit can be between 0.01pF and 10pF, between 0.05pF and 5pF, between 0.01pF and 2pF, between 0.01pF and 1pF, or less than 10pF, 5pF, 3pF, etc. pF, 2pF, 1pF, 0.5pF or less than 0.1pF, for example, a bidirectional I / O (or tridirectional) pad, I / O circuitry can be used for communication between a small I / O driver, receiver or I / O circuitry and a logic driver in a high-speed, high-bandwidth and high-data-bit-width logic operation chip and memory chip, and may include an ESD circuit, a receiver and a driver, and has input capacitance or output capacitance that may be between 0.01pF and 10pF, between 0.05pF and 5pF, between 0.01pF and 2pF, between 0.01pF and 1pF or less than 10pF, 5pF, 3pF, 2pF, 1pF, 0.5pF or less than 0.1pF.

[0034] An arithmetic IC chip or computing IC chip or a chip in a logic driver provides a fixed metal interconnect (non-field programmable) for use in (field programmable) functions, processors, and operations. This standard commercial FPGA IC chip provides (1) a programmable metal interconnect (field programmable) for use in (field programmable) logic functions, processors, and operations, and (2) a fixed metal interconnect for (non-field programmable) logic functions, processors, and operations. Once the field programmable metal interconnect in the FPGA IC chip is programmed, the programmed metal interconnect, together with the fixed metal interconnect in the FPGA chip, provides certain application-specific functions. Some FPGA chips can be operated together with computing IC chips and computing IC chips or chips in the same logic driver to provide flexible, programmable and powerful functions and applications, such as providing artificial intelligence (AI), machine learning, deep learning, big data database storage or analysis, Internet of Things (IoT), industrial computing, virtual reality (VR), augmented reality (AR), automotive electronic graphics processing (GP), digital signal processing (DSP), microcontroller (MC) or central processing unit (CP) functions or any combination thereof.

[0035] Another aspect of the present invention provides a standard commercial FPGA IC chip in an FPGA / HBM CSP package used in a multi-chip packaged logic driver. This standard commercial FPGA IC chip is designed, implemented, and manufactured using advanced semiconductor technology nodes or technologies (e.g., technologies more advanced than 20 nm or 10 nm). The standard commercial FPGA / HBM CSP package structure includes a standard commercial FPGA IC chip, wherein the standard commercial FPGA IC chip includes TPVs on a silicon substrate of the FPGA IC chip. The standard commercial FPGA IC chip with TPVs can be manufactured via the following steps:

[0036] (1) Provide a semiconductor substrate (e.g., a silicon substrate) or a silicon-on-insulator (SOI) substrate, wherein the wafer is of the form and size, for example, 8 inches, 12 inches or 18 inches, and the transistor is manufactured using advanced semiconductor technology generation processes. The transistor may be GAAFET, FINFET, FDSOI MOSFET, PDSOI MOSFET or conventional MOSFET. The process for forming the transistor can be used for MOSFET transistors (e.g. for logic gates, multiplexers, control circuits, etc.) and for MOSFET transistors used in FGCMOS NVM cells.

[0037] (2) A first interconnection scheme in, on or of the chip (FISC) is formed on the surface of a substrate (or wafer) or on a layer containing transistors via a wafer process. The FISC includes a plurality of interconnection metal layers and has an intermetallic dielectric layer between the plurality of interconnection metal layers. The FISC structure can be formed by performing a single damascene copper process and / or a double damascene copper process. The FISC may include 4 to 15 layers or 6 to 12 layers of interconnection metal layers.

[0038] The metal lines or traces in the FISC are coupled or connected to the transistor located below. The thickness of the metal lines or traces formed in the FISC via a single damascene process or via a dual damascene process is, for example, between 3 nm and 500 nm or between 10 nm and 1000 nm, or less than or equal to 5 nm, 10 nm, 30 nm, 50 nm, 100 nm, 200 nm, 300 nm, 500 nm, or 1,000 nm. The width of the metal lines or traces in the FISC is, for example, between 3 nm and 500 nm or between 10 nm and 1000 nm, or less than or equal to 5 nm, 10 nm, 30 nm, 50 nm, 100 nm, 200 nm, 300 nm, 500 nm, or 1,000 nm. nm, and the thickness of the intermetallic dielectric layer is, for example, between 3 nm and 500 nm or between 10 nm and 1000 nm, or less than or equal to 5 nm, 10 nm, 30 nm, 50 nm, 100 nm, 200 nm, 300 nm, 500 nm or 1,000 nm. The metal lines or traces of the FISC can be used as programmable interconnect lines.

[0039] (3) A passivation layer is deposited on the entire wafer and on the FISC structure. This passivation layer is used to protect the transistor and the FISC structure from moisture or contaminants from the external environment, such as sodium free particles. The passivation layer includes a free particle trapping layer, such as a SiN layer, a SiON layer and / or a SiCN layer. The thickness of the free particle trapping layer is greater than or equal to 100 nm, 150 nm, 200 nm, 300 nm, 450 nm or 500 nm, forming an opening in the passivation layer to expose the upper surface of the top layer of the FISC.

[0040] (4) Forming a second interconnection scheme in, on, or of the chip (SISC) on the FISC structure, the SISC includes a plurality of interconnection metal layers and an intermetallic dielectric layer between each of the plurality of interconnection metal layers, and optionally includes an insulating dielectric layer located on or above the protective layer and between the bottommost interconnection metal layer and the protective layer of the SISC. A polymer material can be used as the material of the intermetallic dielectric layer. This polymer material includes polyimide, benzocyclobutene (BCB), parylene, epoxy resin substrate material or its compound, photosensitive epoxy resin SU-8, elastomer or silicone, followed by an emboss copper electroplating process. A process can be performed to form a metal layer or metal plug in an SISC. The SISC may include, for example, 2 to 6 layers of multiple interconnect metal layers or 3 to 5 layers of multiple interconnect metal layers. The metal wires or interconnects of the multiple interconnect metal layers in the SISC have an adhesive layer (e.g., a Ti layer or a TiN layer) and a copper seed layer located only at the bottom of the metal wires or interconnects, but not on the sidewalls of the metal wires or interconnects. In this FISC, the metal wires or interconnects of the multiple interconnect metal layers have an adhesive layer (e.g., a Ti layer or a TiN layer) and copper seed layers located at the bottom and sidewalls of the metal wires or interconnects.

[0041] The metal lines or traces in the SISC are coupled or connected to the interlocking metal lines of the FISC or connected to the transistors in the wafer via metal plugs located in openings in the protective layer. The thickness of the metal lines or traces in the SISC is, for example, between 0.3 µm and 20 µm, between 0.5 µm and 10 µm, between 1 µm and 5 µm, between 1 µm and 10 µm, or between 2 µm and 10 µm, or the thickness is greater than or equal to 0.3 µm, 0.5 µm, 0.7 µm, 1 µm, 1.5 µm, 2 µm, or 3 µm; the width of the metal lines or traces in the SISC is, for example, between 0.3 µm and 20 µm, between 0.5 µm and 10 µm, between 1 µm and 5 µm, between 1 µm and 10 µm, or between 2 µm and 10 µm; or the width is greater than or equal to 0.3 µm, 0.5 µm, The thickness of the intermetallic dielectric layer is, for example, between 0.3 µm and 20 µm, between 0.5 µm and 10 µm, between 1 µm and 5 µm, or between 1 µm and 10 µm; or the thickness is greater than or equal to 0.3 µm, 0.5 µm, 0.7 µm, 1 µm, 1.5 µm, 2 µm, or 3 µm. The metal lines or traces of the SISC can be used as programmable interconnect lines.

[0042] (5) A micro copper pad formed on the FPGA IC chip for use with HBM IC chip or for packaging flip-chip package, through the upper surface of the top layer interconnect metal layer inside the opening of the top layer insulating dielectric layer of the SISC.

[0043] Alternatively, on the FPGA IC chip, micro-metal bumps or metal pillars with solder layers for use with HBM IC chips or flip-chip packages may be formed on (i) the upper surface of the top interconnect metal layer of the SISC (or FISC, if the SISC is omitted) and exposed by an opening in the insulating dielectric layer of the SISC, and / or (ii) on or above the top insulating dielectric layer of the SISC (or FISC, if the SISC is omitted). A gold plating process (as disclosed above) is performed to form micro-copper pads, metal bumps, or metal pillars with solder layers, which may be coupled or connected to the interconnect metal lines or traces of the SISC and FISC via metal plugs in the openings in the top insulating dielectric layer of the SISC (or FISC, if the SISC is omitted), and coupled to transistors on the chip. The height of the micro-metal bump or pillar is, for example, between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or the height is greater than or equal to 30µm, 20µm, 15µm, 5µm, or 3µm. The maximum lateral dimension of the cross-section of this micro-metal bump or pillar (e.g., the diameter of a circle or the diagonal of a square or rectangle) is between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or its maximum lateral dimension is less than or equal to 60µm or 50µm. The distance between two adjacent micro-metal bumps or metal pillars is, for example, between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or the distance is less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm.

[0044] (6) Forming TPVCs on the wafer (TPVC) of the FPGA IC chip. The TPVCs are formed at a location where there is no HBM IC chip or package. The HBM IC chip or package is flip-chip bonded to the FPGA IC chip. The TPVCs are made by a raised copper plating process and are used as signal, power and / or grounding interconnects for FISC and / or SISC, connecting to external circuits outside the FPGA / HBM CSP package structure (formed in a later step).

[0045] In this case, the copper pads exposed by the openings in the top insulating dielectric layer of the SISC or FISC can be used for flip-chip bonding of the HBM IC chip or package structure to the FPGA IC chip. The TPVCs formed by the floating copper plating process are formed on the copper pads exposed by the openings in the top insulating dielectric layer of the SISC or FISC (if SISC is omitted), but not at the locations used for flip-chip bonding of the HBM IC chip or package structure to the FPGA IC chip. In this case, the micro copper pads, metal bumps or metal pillars with solder layers are used for flip-chip bonding of the HBM IC chip or package. The process steps for forming the micro metal pads, metal bumps or metal pillars for flip-chip bonding are as follows: (i) Depositing an adhesive layer over the entire FPGA On the topmost insulating dielectric layer of the IC wafer (SISC or FISC (if SISC is omitted)) and on the topmost interconnect layer of the FISC or SISC exposed by the opening in the topmost insulating dielectric layer, the adhesive layer is, for example, a sputtered or CVD deposited titanium layer or titanium nitride layer (with a thickness, for example, between 1 nm and 200 nm or between 5 nm and 50 nm); (ii) then an electroplating seed layer is deposited on or above the adhesive layer by sputtering or CVD (with a thickness, for example, between 3 nm and 300 nm). (iii) Forming a first photoresist layer for forming micro copper pads, metal bumps, or metal pillars for flip-chip fabrication and patterning a plurality of openings in the first photoresist layer, wherein the thickness of the first photoresist layer is, for example, between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 15µm, between 3µm and 10µm, or greater than 30µm. (iv) An opening in the first photoresist layer is located above the opening of the top insulating dielectric layer of the SISC or FISC and may extend beyond the opening of the insulating dielectric layer, extending to the region or annular region of the insulating dielectric layer surrounding the opening in the insulating dielectric layer; then, a copper layer is electroplated on or above the seed layer in the patterned opening in the first photoresist layer, the thickness of which is between µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 15µm, between 3µm and 10µm, or greater than 30µm, 20µm, 15µm, 5µm or 3µm;

[0046] (v) Remove the remaining first photoresist layer to expose the surface of the electroplated copper seed layer; (vi) Deposit a second photoresist layer, and form patterned openings or holes in the second photoresist layer by coating, exposure and development, and expose the copper seed layer at the bottom of the openings and holes in the second photoresist layer for forming subsequent flip-chip TPVs. The thickness of the second photoresist layer may be, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm. The openings or holes in the photoresist layer are located between the wafers in the logic driver, and / or in the logic driver. (vii) The area surrounding the actuator package and outside the boundaries of the multiple wafers within the logic driver (in subsequent processes, these wafers are bonded to flip-chip microcopper pillars or bumps in flip-chip packaging); (vii) A copper layer (with a thickness, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm) is then plated on the copper seed layer within the patterned openings or vias of the second photoresist layer; (viii) The remaining second photoresist layer is removed to expose the copper seed layer; (ix) The copper seed layer and adhesive layer not beneath the plated copper of the TPVs and flip-chip microcopper pillars or bumps are removed or etched.Alternatively, micro-copper pillars or bumps can be formed at the locations of TPVs, simultaneously forming flip-chip micro-copper pillars or bumps, with the process steps described in (i) to (v) above. In this case, in step (vi), during the deposition of the second photoresist layer, and the formation of patterned openings or holes within the second photoresist layer via coating, exposure, and development, the surfaces of the micro-copper pillars or bumps at the locations of TPVs are exposed by the openings or holes of the second photoresist layer, while the surfaces of flip-chip micro-copper pillars or bumps not located at the locations of TPVs are not exposed; and in step (vii)... A copper layer is electroplated starting from the top surface of the micro copper pillars or bumps located at the TPVs. The height of the TPVs (the distance from the top surface of the top insulating layer to the top surface of the copper pillar or bump) is, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, or between 10µm and 60µm. Between 10µm and 40µm, between 10µm and 30µm, or greater than, higher than, or equal to 50µm, 30µm, 20µm, 15µm, or 5µm, the maximum diameter in the cross-sectional view of the TPVs (e.g., the diameter of a circle or the diagonal of a square or rectangle) is, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm. The minimum space (gap) between the nearest TPVs is between 0µm, 10µm and 100µm, 10µm and 60µm, 10µm and 40µm, or 10µm and 30µm, or greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm, for example, between 5µm and 300µm. Between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm.(v) Remove the remaining first photoresist layer to expose the surface of the electroplated copper seed layer; (vi) Deposit a second photoresist layer, and form patterned openings or holes within the second photoresist layer through coating, exposure, and development, exposing the copper seed layer at the bottom of the openings and holes within the second photoresist layer for subsequent flip-chip TPVCs. The thickness of the second photoresist layer may be, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm. The location of the openings or holes within the photoresist layer is within the HBM DRAM of the HBM DRAM in the HBM DRAM Stacked Chip Scale Packages (SCSP) in the FPGA / HBM CSP (to be formed in a later step) packaging structure. In the gaps or spaces between IC chips, that is, the area surrounding each FPGA IC chip, the opening in the second photoresist layer is located outside the boundary or sidewall of the HBM DRAM IC chip or the HBM DRAM stacked chip-level package. Micro copper pads, metal bumps, or metal pillars can be used for flip-chip bonding in subsequent processes, and their location is within the HBM DRAM IC chip or HBM DRAM... (vii) Then, a copper layer (with a thickness, for example, between 20µm and 300µm, between 30µm and 200µm, between 50µm and 150µm, between 50µm and 120µm, between 20µm and 100µm, between 20µm and 60µm, between 20µm and 40µm, or between 20µm and 30µm) is plated on the copper seed layer within the patterned openings or holes of the second photoresist layer; (viii) The remaining second photoresist layer is removed to expose the copper seed layer; (ix) The copper seed layer and adhesive layer not below the plated copper of the TPVCs and flip-chip micro-copper pads, metal pillars, or bumps are removed or etched. Alternatively, micro-copper pads, metal pillars, or bumps can be formed at the locations of TPVCs, while flip-chip micro-copper pillars or bumps are formed simultaneously, with the process steps described in (i) to (v) above. In this case, in step (vi), after depositing a second photoresist layer and forming patterned openings or holes within the second photoresist layer through coating, exposure, and development, the surfaces of the micro-copper pads, metal pillars, or bumps at the locations of TPVCs are exposed by the openings or holes of the second photoresist layer, while the upper surfaces of the flip-chip micro-copper pads, metal pillars, or bumps not located at the locations of TPVCs are not exposed; and in step (vii), a copper layer is electroplated starting from the upper surface of the micro-copper pads, metal pillars, or bumps located at the locations of TPVCs.

[0047] The height of the TPVCs (the distance from the top surface of the topmost insulation layer to the top surface of the TPVCs) is, for example, between 20µm and 300µm, between 30µm and 200µm, between 50µm and 150µm, between 20µm and 120µm, between 20µm and 100µm, between 20µm and 60µm, between 20µm and 40µm, between 20µm and 30µm, or greater than, higher than or equal to 100µm, 50µm, 30µm or 20µm. The maximum diameter in the cross-sectional view of the TPVCs (e.g., the diameter of a circle or the diagonal of a square or rectangle) is, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, or between 10µm and 10µm. The minimum space (gap) between the nearest TPVC is, for example, between 5µm and 300µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm. The height of the TPVCs is between 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm. The height of the TPVCs is greater than the height of the copper pad, copper pillar, or copper bump by approximately 20µm or 50µm.

[0048] FPGA IC wafers with FISC, SISC, flip-chip micro copper pads, bumps or metal pillars, and TPVCs can be used in subsequent flip-chip packaging or bonding processes to bond HBM DRAM IC wafers or HBM stacked wafer-level packages (HBM SCSP) to flip-chip micro copper pads, bumps or metal pillars to form an FPGA / HBM CSP package structure.

[0049] Another aspect of the present invention provides an HBM stacked chip-level package (HBM SCSP), which includes an ASIC or logic chip and a plurality of HBM IC chips (e.g., DRAM IC chips, cache SRAM chips, or high-speed non-volatile memory chips, such as magnetoresistive RAM (MRAM), resistive RAM (RRAM), or phase-shifted RAM (PRAM)) stacked on the ASIC or logic chip. A TSV system in a silicon substrate is used for electronic communication with other chips (or a plurality of chips stacked in the HBM SCSP and an FPGA IC chip in an FPGA / HBM CSP package structure). An HBM SCSP may include 2, 4, 8, 16, 24, or 32 HBM DRAM IC chips, or a number greater than 2, 4, 8, 16, 24, or 32 HBM DRAM IC chips. Each HBM... The memory density of the DRAM IC chip is 512 Mb, 1 Gb, 4 Gb, 8 Gb, 16 Gb, 32 Gb, 64 Gb, or greater than or equal to 256 Mb, 1 Gb, 8 Gb, 16 Gb, where "b" represents bits. The HBM DRAM IC chip is used to communicate / transmit data bits with the FPGA chip in the FPGA / HBM CSP package structure via TSVs in the HBM DRAM IC chip, ASIC, or logic chip within the FPGA / HBM CSP package structure. The data bit width is greater than or equal to 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. The HBM DRAM IC chip can be designed with small I / O drivers or receivers, or small-scale I / O circuitry, for communication with the FPGA / HBM CSP package structure. The FPGA chip in the CSP package structure has a communication / transmission drive capability, load, output capacitance, or input capacitance between 0.05 pF and 2 pF, or between 0.05 pF and 1 pF, or less than 2 pF or 1 pF. The ASIC or logic chip is used for buffers, DRAM memory control, or interface circuitry, and may be located at the bottom of the HBM SCSP package, which has solder bumps or copper pillars on its bottom. The HBM SCSP and HBM DRAM IC chips are designed according to standard general specifications and are characterized both physically and functionally.

[0050] Another aspect of the present invention provides a method for forming a standard commercial FPGA / HBM CSP package for use in a logic driver, wherein each FPGA / HBM CSP package includes a standard commercial FPGA IC chip and (i) an HBM DRAM IC chip disposed on the standard commercial FPGA IC chip, wherein the HBM IC chip may have TSVs located in its silicon substrate, or may not have TSVs located in its silicon substrate, or (ii) a stacked package of a plurality of HBM chips (HBM SCSP) disposed on the standard commercial FPGA IC chip, wherein the HBM DRAM IC chip may have TSVs located in its silicon substrate, the standard commercial FPGA IC chip including FISC, SISC, flip-chip micro copper pads, metal bumps or metal pillars or TPVCs, the TPVCs being located in the space outside the edge or sidewall of the HBM DRAM IC chip or the HBM DRAM stacked chip level (SCSP), for example located in the peripheral area of ​​each FPGA IC chip (where there is no HBM DRAM IC chip or HBM The SCSP structure flip-chip package is bonded on or above it. The flip-chip uses micro copper pads, metal bumps, or metal pillars for subsequent flip-chip bonding and is located within the edge of the HBM DRAM IC chip or HBM SCSP structure and perpendicular to the space. The standard commercial FPGA IC chip and HBM chip or HBM SCSP have been disclosed and described in the above description. The steps for forming an FPGA / HBM CSP package are as follows:

[0051] (1) Performing flip-chip assembly, bonding, and packaging: (a) First, a wafer having a plurality of standard commercial FPGA IC chips as described above is provided, wherein the standard commercial FPGA IC chip includes TSVCs, a plurality of transistors, FISCs, SISCs, and micro copper pads, metal bumps, or metal pillars, and HBM DRAM IC chips or HBM SCSP packages are provided. Then, the HBM DRAM IC chips or HBM SCSP packages are bonded to the micro copper pads, metal bumps, or metal pillars on each FPGA IC chip on the wafer through flip-chip assembly, bonding, or packaging. The FPGA IC wafer is formed as described above. The HBM DRAM IC chips or HBM SCSP packages are bonded to the above-mentioned FPGA wafer. All HBM DRAM IC chips or HBM SCSP packages can be disposed on the FPGA wafer having solder bumps or copper bumps disposed on the surface by flip-chip packaging method. Here, HBM (a) SCSPs, ASICs, or logic chips are located at the bottom of a stacked package. The copper pads used in the flip-chip packaging process can be provided and exposed on the upper surface of the FPGA wafer, or the solder bumps and micro-metal bumps or pillars used in the flip-chip packaging process can be provided and exposed on the upper surface of the FPGA wafer. The top surface of the solder bumps or micro-copper metal bumps or pillars has a horizontal plane located above the horizontal plane of the top insulating dielectric layer of the plurality of chips. Its height is, for example, between 3µm and 120µm, between 5µm and 75µm, between 5µm and 50µm, between 5µm and 25µm, between 5µm and 15µm, or between 3µm and 10µm, or greater than or equal to 30µm, 20µm, 15µm, or 3µm; (b) A plurality of HBM DRAM IC chips or HBM SCSP packages are flip-chip assembled, bonded, or packaged on an FPGA. On the corresponding micro-copper bumps or metal pillars of the wafer, the wafer surface or one side with the transistor faces upward, and the back side (i.e. the surface or one side without the transistor) of the silicon substrate of the HBM DRAM IC wafer or HBM SCSP package faces upward.(c) Underfill material is applied by dispensing to the gap between the FPGA wafer, HBM DRAM IC chip, or HBM SCSP package (and the micro-copper bumps or pillars of the IC chip and the FPGA wafer) using a dispensing machine. TPVCs are located in the gap between the HBM DRAM IC chip or HBM SCSP package structure. The underfill material must leave a gap between the TPVC and the edge of the HBM DRAM IC chip or HBM SCSP package structure. This underfill material includes epoxy resin or a compound, and can be cured at or above 100°C, 120°C, or 150°C. Alternatively, the HBM DRAM IC chip or HBM SCSP package structure can be bonded to the FPGA IC chip via thermocompression bonding or oxide-to-oxide and metal-to-metal direct bonding methods.

[0052] (2) For example, a material, resin, or compound is filled into the gap or space between the upper surface of the HBM DRAM IC chip or HBM SCSP package and TPVCs and covered on the back side of the HBM DRAM IC chip or HBM SCSP package by means of spin coating, screen printing, drop casting, or molding. The molding method includes pressure molding (using an upper mold and a lower mold) or casting molding (using a drop casting method). The material, resin, or compound can be a polymer material, such as polyimide, benzocyclobutene, parylene, epoxy resin substrate material or compound, photosensitive epoxy resin SU-8, elastomer or silicone. The polymer is photosensitive polyimide / PBO PIMEL™ provided by Asahi Kasei Corporation of Japan, or Nagase of Japan. ChemteX provides epoxy-based molding compounds, resins, or sealants that are applied (via coating, printing, dispensing, or molding) to an intermediate substrate and on the back side of an HBM DRAM IC chip or HBM SCSP package structure to a horizontal plane, such as (i) filling gaps or spaces between HBM DRAM IC chips or HBM SCSP packages; (ii) filling gaps or spaces between TPVCs; (iii) filling gaps or spaces between TPVCs and HBM DRAM IC chips or HBM SCSP package structures; (iv) covering the upper surface of TPVCs; and (v) covering the HBM DRAM IC chip or HBM SCSP package structure. The top back cover of the SCSP package is made of a material, resin, or compound that can be cured or cross-linked by heating to a specific temperature, such as 50°C, 70°C, 90°C, 100°C, 125°C, 150°C, 175°C, 200°C, 225°C, 250°C, 275°C, or 300°C. This material can be a polymer or molding compound. The surface of the material, resin, or compound is planarized using CMP polishing or grinding. The CMP or grinding process is performed until the back back of all HBM DRAM IC wafers or the top surface of the HBM SCSP package structure and the top surface of the TPVCs are fully exposed, or the top surface of the TSVs in the silicon substrate of the HBM DRAM IC wafer or the top surface of the TSVs in the topmost HBM DRAM IC wafer of the HBM SCSP package structure is exposed for coupling or connection to the interconnection line structure formed in subsequent steps.

[0053] (3) Solder bumps are formed on the exposed upper surface of the TPVCs, or an insulating dielectric layer is deposited on the polymer resin or compound planarized surface, the back of the HBM DRAM IC chip or HBM SCSP package structure and the exposed upper surface of the TPVCs (and in some cases, the upper surface of the TSVs in the silicon substrate of the HBM DRAM IC chip or the exposed upper surface of the TSVs in the topmost HBM DRAM IC chip of the HBM SCSP package structure), and then copper pads, copper pillars or solder bumps are formed on the upper surface of the TPVCs and TSVs exposed in the openings in the insulating dielectric layer. The copper pads, copper pillars or solder bumps on the TPVCs are connected or coupled to the power, ground and signal from external circuits other than the FPGA / HBM CSP to the FPGA IC chip and the HBM DRAM IC chip or the HBM SCSP package structure via the TPVCs. The power supply from external circuits other than the FPGA / HBM CSP is transmitted / connected to the HBM DRAM IC chip or the HBM SCSP package structure. The HBM DRAM IC chip in the SCSP package structure is powered from external circuitry outside the FPGA / HBM CSP via: (i) copper pads, pillars, or solder bumps on TPVCs, (ii) TPVCs, (iii) power / ground buses provided by metal lines or traces in the top metal layer of the SISC or FISC (e.g., the 1st, 2nd, 3rd, or 4th layer of the FISC on the FPGA IC chip), with a thickness greater than 0.5 micrometers or 1 micrometer, (iv) bonding pads, pillars, or bumps located between the FPGA IC chip and the HBM DRAM IC chip or the HBM SCSP package structure, and (v) power / ground buses on the HBM DRAM IC chip or the HBM SCSP package structure. The power / ground bus provided by the metal lines or traces in the FISC (layer 1, 2, 3 or 4 above) on the IC chip, with a thickness greater than 0.5 micrometers or 1 micrometer.

[0054] Alternatively, the backside metal interconnection scheme at the backside surfaces of HBM DRAM IC chips or HBM SCSP packages of the FPGA / HBM CSPs (hereinafter referred to as BISCSP) and package through-holes or polymer through-holes (TPVs) in the gaps between multiple chips in the logic driver, and / or in the area surrounding the FPGA / HBM CSPs package and in the boundary of multiple chips within the logic driver (IC chips with multiple transistors facing down), the BISCSP may include metal lines, interconnects or metal plates within the interconnection metal layer, and the BISCSP is formed on (i) the HBM DRAM IC chip or HBM SCSP package structure (HBM DRAM IC chips or DRAM chips with multiple transistors HBM SCSP package structure). On the back side of the IC wafer (with one side facing down), (ii) on the surface of the molding compound after the molding compound planarization step, (iii) the upper surface of the exposed TPVCs (and, in some cases, the upper surface of the TSVs in the silicon substrate of the HBM DRAM IC wafer or the upper surface of the exposed TSVs in the topmost HBM DRAM IC wafer of the HBM SCSP package structure), the BISCSP provides an additional interconnection line metal layer or a connection layer on the back side of the FPGA / HBM CSP package structure, including a position located vertically above the HBM SCSP package or HBM DRAM IC wafer (HBM DRAM IC wafer or DRAM IC wafer with multiple transistors, one side facing down) of the FPGA / HBM CSP package structure, the TPVCs are used to connect or couple the circuitry or components (e.g., FISC and / or SISC) of the FPGA IC wafer to the BISCSP on the back side of the FPGA / HBM CSP package structure, the BISCSP being located via the HBM DRAM IC wafer or HBM The surface of the SCSP package structure, on the back or top of the molding compound, on the exposed upper surface of TPVCs (and, in some cases, the upper surface of TSVs in the silicon substrate of the HBM DRAM IC wafer or the exposed upper surface of TSVs in the topmost HBM DRAM IC wafer of the HBM SCSP package structure), and on the surface of the molding compound after the planarization step, is formed by metal lines, traces, or planes of a plurality of interconnection metal layers (HBM DRAM IC wafer with a plurality of transistors or one side of the DRAM IC wafer facing down).The process steps for forming BISCSP are as follows: (a) Depositing a bottom insulating dielectric layer over the entire wafer and located on the exposed back side of the IC wafer, the exposed top surface of TPVCs, and the surface of the potting compound (and, in some cases, the top surface of TSVs in the silicon substrate of the HBM DRAM IC wafer or the exposed top surface of TSVs in the topmost HBM DRAM IC wafer of the HBM SCSP package structure). The bottom insulating dielectric layer can be a polymer material, such as polyimide, benzocyclobutene, etc. (BCB) , parylene, epoxy resin-based materials or compounds, photosensitive epoxy resin SU-8, elastomers or silicone, wherein the thickness of the cured bottom polymer layer is between 2µm and 50µm, between 2µm and 30µm, between 2µm and 20µm, or between 2µm and 15µm, or greater than (thicker than) or equal to 2µm, 3µm, 5µm, 10µm, 20µm or 30µm; (b) The process involves an emboss copper process to form metal plugs within openings in the bottommost polymer insulating dielectric layer, and the formation of the bottommost insulating dielectric layer using metal wires, connectors, or metal planes on the insulating dielectric layer to form the metal layer of the bottommost interconnecting lines in the BISCSP, along with its plurality of openings. The emboss copper process is used to form metal plugs within the metal wires, connectors, or metal plates at the bottommost end of the interconnecting line metal layer, and within the bottommost insulating dielectric layer, a metal layer that can be repeated to form the interconnecting line metal layer within the BISCSP; wherein the repeated bottommost... The end insulating dielectric layer is used as the inter-metal dielectric layer between the interconnecting metal layers of the BISCSP, and using the above-disclosed raised copper process, metal plugs in the bottommost insulating dielectric layer (now within the inter-metal dielectric layer) can be used as metal wires, connecting wires, or metal plates connecting or coupling the interconnecting metal layers of the BISCSP, forming a plurality of copper pads, solder bumps, and copper pillars on the metal layer exposed in the opening of the topmost insulating dielectric layer of the BISCSP. The positions of the copper pillars or solder bumps are: (i) HBM (a) On the space outside the sidewalls or boundaries of the DRAM IC chip or HBM SCSP package structure, such as on the peripheral area of ​​each FPGA IC chip (i.e., where there is no HBM DRAM IC chip or HBM SCSP package flip-chip bonding); (b) Located directly above the back of the HBM SCSP package structure of the HBM DRAM IC chip or FPGA / HBM CSPs, the BISCSP may include 1 to 10 layers of interconnect metal layers or 2 to 6 layers of interconnect metal layers, the metal lines, interconnects or metal plate interconnects of the BISCSP having an adhesive layer (e.g., a Ti layer or a TiN layer) and a copper seed layer located only at the bottom, but not on the sidewalls of the metal lines or interconnects.FISC interconnects have an adhesive layer (e.g., a Ti layer or a TiN layer) and a copper seed layer located on the sidewalls and bottom of the interconnect.

[0055] The thickness of the metal wires, connecting wires, or metal plates of BISCSP is, for example, between 0.3µm and 40µm, between 0.5µm and 30µm, between 1µm and 20µm, between 1µm and 15µm, between 1µm and 10µm, or between 0.5µm and 5µm, or thicker than (greater than) or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, 5µm, etc. The width of the metal wires or connectors in BISCSP is, for example, between 0.3µm and 40µm, between 0.5µm and 30µm, between 1µm and 20µm, between 1µm and 15µm, between 1µm and 10µm, or between 0.5µm and 5µm, or wider than or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, or 5µm. The thickness of the intermetallic dielectric layer of the BISCSP is, for example, between 0.3µm and 50µm, between 0.5µm and 30µm, between 0.5µm and 20µm, between 1µm and 10µm, or between 0.5µm and 5µm, or thicker than or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, or 5µm. The metal plate within the metal layer of the BISCSP's interconnecting lines can be used as a power / ground for power supply, and / or as a heat sink or heat dissipation diffuser, wherein the thickness of this metal is even greater, for example, between 5µm and 50µm, between 5µm and 30µm, between 5µm and 20µm, or between 5µm and 15µm, or thicker than or equal to 5µm, 10µm, 20µm, or 30µm, for power / ground and / or Heat sinks or heat dissipation diffusers can be arranged in an interlaced or cross-shaped manner in the interconnecting metal layer of BISCSP, for example, they can be arranged in a fork shape.

[0056] The interconnect metal lines or traces of the FISC and / or SISC of the FPGA chip used in the FPGA / HBM CSP package structure may be: (a) including a first interconnect wire network or structure located in the FPGA IC chip for connecting or coupling to the FISC and / or SISC of the transistor, a second interconnect wire network or structure of the metal lines or traces of the FPGA IC chip and / or one of the micro copper pads, bumps or metal pillars, the first interconnect wire network or structure located in the FPGA IC chip for connecting or coupling to the transistor may connect or couple to external circuits or components to the FPGA / HBM CSP package structure via TPVCs located in the FPGA / HBM CSP package structure, the first interconnect wire network or structure may connect or couple to the HBM DRAM IC chip or HBM located on or above the FPGA chip. The SCSP package, in which the first interconnect network or structure of the metal lines in the FISC and / or SISC can be a network or structure for signal, power supply or ground supply, in this case, the TPVCs are used as metal plugs or metal pillars for signal transmission, power supply or ground supply; (b) including direct or vertical connection points between the circuitry of the FPGA chip and the HBM DRAM IC chip or HBM SCSP package, these connection points being provided via stacked metal plugs / metal layers used in the FISC and SISC; solder bumps or copper pillars of the HBM DRAM IC chip or HBM SCSP package are flip-chip bonded to copper pads, copper bumps or copper pillars of the FPGA IC chip, wherein these copper pads, solder bumps or copper pillars are vertically positioned above the stacked metal plugs / metal layers of the FISC and / or SISC of the FPGA IC chip, located between the FPGA chip and the HBM DRAM IC chip or HBM The vertical connection points between SCSP packages have high bandwidth, high speed, and wide bit width communication transmission. The communication transmission between the HBM DRAM IC chip or HBM SCSP package and the FPGA chip has a data bit width equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K. The HBM DRAM IC chip or each HBM DRAM IC chip in the HBM SCSP package structure can be designed with small I / O drivers or receivers or small drive or receive capabilities for communication with the FPGA IC chip below it, wherein the load, output capacitance, or input capacitance is between 0.05 pF and 2 pF or between 0.The data bit width of the HBM DRAM IC chip, or the HBM DRAM IC chip in an HBM SCSP package structure, is between 0.05 pF and 1 pF, or less than 2 pF or 1 pF, and is equal to or greater than 64, 128, 256, 512, 1024, 2048, 4096, 8K, or 16K.

[0057] Then, copper pads or solder bumps are formed on or above the top surface of the top metal layer exposed by the opening in the top insulating dielectric layer of the BISCSP. The FPGA wafer is at the bottom and the HBM DRAM IC chip or HBM SCSP package is at the top. The front side of the FPGA chip (the side with the transistor) is now facing up. The potting compound and the back side of the HBM DRAM IC chip or HBM SCSP package are now at the top. The copper metal pillars or bumps can be formed by an emboss copper plating process. The copper pads, copper pillars or bumps are used in the next level package to form a logic driver.

[0058] (4) Cutting the completed FPGA wafer, including separating or cutting the material or structure between two adjacent HBM DRAM IC wafers or HBM SCSP packages, wherein the material (e.g., a polymer) filling the plurality of wafers between two adjacent HBM DRAM IC wafers or HBM SCSP packages is separated or cut into individual FPGA / HBM CSPs units.

[0059] Another example of the present invention provides an FPGA / HBM CSP package structure with TPVCs in a logic driver, the logic driver having a standard format or size, for example, the FPGA / HBM CSP package structure may have a square or rectangle with a certain width, length and thickness, and / or have copper pads, copper pillars or solder bumps distributed in standard positions on the BISCSP. An industry standard may set the diameter (size) or shape of the FPGA / HBM CSP package structure, for example, the standard shape of the FPGA / HBM CSP package structure may be a square with a width greater than or equal to 3 mm, 6 mm, 8 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm or 30 mm, and a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm. Alternatively, the standard shape of the FPGA / HBM CSP package structure can be rectangular, with a width greater than or equal to 3mm, 6mm, 8mm, 10mm, 12mm, 15mm, 20mm, 25mm or 30mm, a length greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm or 40mm, and a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm or 5mm.

[0060] Another example of the present invention provides Fan-Out Interconnection Technology (FOIT) for forming or manufacturing logic drivers (including FPGA / HBM CSP package structures) according to multi-chip packaging technology or processes. The FOIT is a multi-chip packaging technology based on fan-out interconnection lines or Re-Distribution Layer (RDL) for connecting chips or packages in the logic driver. The FOIT logic driver can be formed via three methods: (A) placing the chip or package in the process as a first step (Chip-First); (i) chip facing up; (ii) chip facing down; (B) forming reconfiguration lines in the process as a first step (RDL-First), and then bonding the chip or package onto the RDL in a flip-chip manner. The processing order of the three methods is different, but the structure is similar. The processing steps of method (A)(i) are described below:

[0061] (1) Provide a wafer carrier, support, mold or substrate, wherein the wafer carrier, support, mold or substrate may be a wafer type (e.g., a wafer with a diameter of 8 inches, 12 inches or 18 inches), or a square panel type or a rectangular panel type (e.g., a width or length greater than or equal to 20 cm, 30 cm, 50 cm, 75 cm, 100 cm, 150 cm, 200 cm or 300 cm), and the material of the wafer carrier, support, mold or substrate may be silicon material, metal material, ceramic material, glass material, steel metal material, plastic material, polymer material, epoxy resin-based polymer material or epoxy resin-based compound material. These chips or packages may be mounted, fixed, or adhered to a chip carrier, bracket, mold, or substrate. These chips or packages include: standard commercial FPGA / HBM CSP packages, non-volatile chips or packages, HBM IC chips or HBM SCSPs package structures, dedicated control chips, dedicated I / O chips, dedicated control chips and dedicated I / O chips, IAC, DCIAC, DCDI / OIAC chips and / or computing IC chips and / or computing ICs. The chip, such as a CPU chip, GPU chip, DSP chip, TPU chip, APU chip, or AI chip, is packaged entirely within the logic driver, along with a CSP package structure. The CSP package structure has micro-copper pillars or solder bumps on its upper surface. The height of the upper surface of these micro-bumps or pillars is higher than the height of the top surface of the top insulating dielectric layer of the chip or CSP package structure, and the height is, for example, between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or greater than or equal to 30µm, 20µm, 15µm, 5µm, or 3µm. These chips or packages may be mounted, fixed, or adhered to a chip carrier, bracket, mold, or substrate, wherein the back side of the silicon substrate of these chips (i.e., the side without transistors or the back side of the CSP package) or the back side of the FPGA / HBM CSP package structure faces down.

[0062] (2) For example, a material, resin, or compound is filled into the gaps or spaces between multiple wafers or CSP package structures and covered on the surface of multiple wafers by means of spin coating, screen printing, drop casting, or molding, such as pressure molding (using an upper and lower mold) or pouring molding (using a drop casting). The material, resin, or compound can be a polymer material, such as polyimide, benzocyclobutene, parylene, epoxy resin base material or compound, photosensitive epoxy resin SU-8, elastomer, or silicone. The polymer can be photosensitive polyimide / PBO PIMEL™ provided by Asahi Kasei Corporation of Japan, or epoxy resin-based molding compound, resin, or sealant provided by Nagase ChemteX Corporation of Japan. The material, resin, or compound is used (via coating, printing, drop casting, or molding). On a carrier, support, mold, or substrate and on the back side of a plurality of wafers to a horizontal plane, such as (i) filling the gaps or spaces of the plurality of wafers or CSPs package structure; (ii) covering the topmost surface of the plurality of wafers or CSPs package structure; (iii) filling the gaps or spaces between micro copper bumps or metal pillars located on the wafers or CSPs package structure; (iv) covering the upper surface of micro copper bumps or metal pillars located on the wafers or CSPs package structure, the filling material may be a polymer or a molding compound. The surface of micro-copper bumps or metal pillars, the materials used, resins, or compounds are planarized using CMP polishing or grinding. The CMP or grinding process is performed until the top surfaces of all micro-copper bumps or metal pillars on the wafer or CSP package structure are exposed, and then the carrier, support, mold, or substrate is: (i) removed after the CMP polishing or grinding process and before forming the Top Interconnection Scheme in, on, or of the logic drive (TISD) (disclosed in the following description); (ii) retained in subsequent manufacturing steps and removed after all manufacturing steps of the logic drive are completed in wafer or panel format; or (iii) retained as part of the final diced or split logic drive structure, and subjected to, for example, CMP grinding or wafer back-side grinding techniques to remove the carrier, support, mold, or substrate. Additionally, wafer or panel thinning processes, such as CMP polishing or grinding, wafer back-side grinding, or wafer or panel debonding or stripping processes, can be performed to remove portions of the wafer or panel to thin it. This thinning process can be performed during the wafer or panel manufacturing process, after all wafer or panel manufacturing processes are completed, and before the wafer or panel is diced and cut to produce multiple individual logic driver units.

[0063] (3) A TISD is formed on or above a planarized material, resin, or compound and located on the exposed upper surface of a micro metal bump or metal pillar in a wafer-level or panel-level manner. The TISD includes a plurality of metal layers and a plurality of inter-metal dielectric layers, the inter-metal dielectric layers being located between every two metal layers. The TISD may optionally include an insulating dielectric layer located on the planarized material, resin, or compound and located between the bottom interconnect metal layer of the TISD and the planarized material, resin, or compound. The metal lines of the interconnect metal layer of the TISD are attached above the wafer or CSP package structure and extend horizontally across the wafer. The metal lines of the TISD inter-chip or CSP package structure boundary, in other words, the metal lines pass through the gaps or spaces between the chip or CSP package structure of the logic driver. The metal lines of the TISD inter-chip or CSP package structure can connect or couple the circuits of two (or more) chips or CSP packages in the logic driver. The TISD is formed by the following steps: (i) forming an inter-metal dielectric layer: forming a polymer layer using spin coating, screen printing, drop casting or molding, etc. The material of this polymer layer is, for example, polyimide, benzocyclobutene, parylene, epoxy resin substrate or compound, photosensitive epoxy resin SU-8, elastomer or silicone. The polymer material can be photosensitive and can be used with a photoresist layer to form patterned openings therein, the patterned openings being used to form metal plugs; (ii) metal lines or traces formed by an interleaved wire metal layer via a raised copper electroplating process, the TISD may include 2 to 6 layers or 3 to 5 layers of interleaved wire metal layers, the interleaved wires or traces of the TISD having an adhesive layer (e.g., titanium or titanium nitride) and a copper seed layer at its bottom, and not located on the sidewalls of the metal lines or traces, the interleaved wires or traces of the FISC having an adhesive layer (e.g., titanium or titanium nitride) and a copper seed layer at its bottom and located on the sidewalls of the metal lines or traces.

[0064] The TISD interconnect metal lines or traces are coupled or connected via micro-metal bumps or pillars on the wafer to SISC interconnect metal lines or traces, FISC interconnect metal lines or traces, and / or transistors located on the wafer in the logic driver. The wafer or CSP package structure is surrounded by a filler material, resin, or compound filling the space between the wafers or between the CSP package structures. The wafer or CSP package structure may also be covered with a filler material, resin, or compound. The thickness of the TISD metal lines or traces is, for example, between 0.3µm and 30µm, between 0.5µm and 30µm. The width of the TISD metal wires or connectors is, for example, between 0.3µm and 20µm, between 0.5µm and 10µm, or between 0.5µm and 5µm, or thicker than (greater than) or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, 3µm, or 5µm. The thickness of the intermetallic dielectric layer of the TISD is, for example, between 0.3µm and 30µm, between 0.5µm and 20µm, between 1µm and 10µm, or between 0.5µm and 5µm, or thicker than or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, or 5µm. The metal lines or traces of the interconnect metal layer of the TISD can be used as programmable interconnect lines.

[0065] (4) Copper metal pillars or bumps are formed on or above the top insulating dielectric layer of the TISD and on the upper surface of the top layer interconnect metal layer of the TISD exposed by the opening in the top insulating dielectric layer of the TISD. The copper metal pillars or bumps serve to connect or couple the chips, such as the dedicated I / O chip of the logic driver to external circuits or components outside the logic driver. The height of the copper metal pillars or bumps is, for example, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm or between 10µm and 300µm, or greater than, higher than or equal to 50µm, 30µm, 20µm, 15µm or 5µm. The maximum cross-sectional dimension of the copper metal pillar or bump (e.g., the diameter of a circle or the diagonal length of a rectangle or square) is, for example, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm. The minimum space (gap) between two adjacent copper metal pillars or bumps is between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm.Copper pillars or bumps can be used in flip-chip packaging of logic drivers on substrates, flexible circuit boards, or motherboards, similar to flip-chip assembly or Chip-On-Film (COF) packaging technologies used in LCD driver packaging. The substrate, flexible circuit board, or motherboard can be, for example, a printed circuit board (PCB), a silicon substrate with interconnect structures, a metal substrate with interconnect structures, a glass substrate with interconnect structures, a ceramic substrate with interconnect structures, or a flexible circuit board with interconnect structures. The substrate, flexible circuit board, or PCB may include metal bonding pads or bumps on its surface, and the metal bonding pads or bumps may have a solder layer on their top surface for reflow soldering or thermoforming processes to bond the copper pillars or bumps on the logic driver. The copper pillars or bumps may be located on the front surface of the logic driver package and have a ball-grid array (BGA). The layout of a Block Grid Interface (BGA) includes metal pillars or bumps in the peripheral area for signal I / Os, and metal pillars or bumps near the center area for power / ground (P / G) I / Os. The bumps in the peripheral area for transmitting signals can form a ring-shaped area along the logic driver package boundary, such as 1 ring, 2 rings, 3 rings, 4 rings, 5 rings, or 6 rings. The spacing of the multiple signal I / Os in the ring area can be smaller than the spacing of the power / ground (P / G) I / Os near the center area.

[0066] Alternatively, solder bumps are formed via a raised copper / solder plating process, located on or above the top insulating dielectric layer of the TISD and on the upper surface of the top interconnect metal layer of the TISD exposed by an opening in the top insulating dielectric layer of the TISD. The solder bumps can be formed using a lead-free solder, which in commercial applications may include tin, copper, silver, bismuth, indium, zinc, antimony, or other metals. For example, the lead-free solder may include tin-silver-copper solder, tin-silver solder, or tin-silver-copper-zinc solder. The function is to connect or couple these chips, such as dedicated I / O chips of logic drivers, to external circuits or components outside the logic drivers. The height of the solder bumps (including copper barrier layers) is, for example, between 5µm and 150µm, 5µm and 120µm, 10µm and 100µm, 10µm and 60µm, 10µm and 40µm, or 10µm and 300µm, or greater than, higher than or equal to 75µm, 50µm, 30µm, 20µm, 15µm, or 10µm. The height of the solder bump (including the copper barrier layer) is the distance from the horizontal surface of the top insulating dielectric layer of the TISD to the highest surface of the solder bump. The maximum dimension of the cross-section of the solder bump (e.g., the diameter of a circle or the diagonal length of a rectangle or square) is, for example, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm. The minimum space (gap) between two adjacent solder bumps is between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm.Solder bumps can be used in flip-chip packaging of logic drivers on substrates, flexible circuit boards, or motherboards, utilizing flip-chip assembly technology or Chip-On-Film (COF) packaging technology in LCD driver packaging. This solder bump packaging process may include a soldering or reflow process with or without flux. The substrate, flexible circuit board, or motherboard can be, for example, a printed circuit board (PCB), a silicon substrate with interconnect structures, a metal substrate with interconnect structures, a glass substrate with interconnect structures, a ceramic substrate with interconnect structures, or a flexible circuit board with interconnect structures. The solder bumps can be located on the front surface of the logic driver package and have a ball-grid array (BGA). The layout of a (BGA) includes solder bumps in the peripheral area for signal I / Os, and solder bumps near the center area for power / ground (P / G) I / Os. The bumps in the peripheral area for transmitting signals can form a ring-shaped area along the logic driver package boundary, such as 1 ring, 2 rings, 3 rings, 4 rings, 5 rings, or 6 rings. The spacing of the multiple signal I / Os in the ring area can be smaller than the spacing of the power / ground (P / G) I / Os near the center area.

[0067] (5) Cutting a completed wafer or panel, including separating or cutting it by means of a material or structure between two adjacent logic drivers, the material (e.g., a polymer) filling the gap or space between the two adjacent logic drivers, and separating or cutting it into individual logic driver units.

[0068] Alternatively, the FOIT logic driver may be formed via the three methods described in (A)(ii) above: (A) placing the wafer in the process or packaging it as a chip-first; (ii) wafer facing down, the process steps of the method described in (A)(ii) are similar to those of the method described in (A)(i), except that:

[0069] (1') This process is similar to (1) in process step (A)(i), except that the wafers or CSPs package structures are disposed, fixed or adhered to a wafer carrier, bracket, mold or substrate, wherein the back side of the silicon substrate of the wafers (the surface or side without transistors) or the back side of the FPGA / HBM CSPs package structure faces upward, and a sacrifice bonding layer is formed on the wafer carrier, bracket, mold or substrate, which is used in (1) as a bonding layer to bond the wafers or FPGA / HBMs. (ii) as a substrate release layer for debonding or releasing from a substrate, support, mold, or encapsulating compound on which the CSPs or CSPs are packaged, whether before or after the formation of TISD and copper pillars or solder bumps, the material used for the sacrifice bond layer is a light-to-heat conversion (LTHC) material and is formed by screen printing, spin coating, or adhesive bonding. The LTHC can be in liquid form and deposited on the glass substrate by printing or spin coating, followed by heating or drying. The thickness of the sacrifice bond layer is greater than 1 micrometer or between 0.5 micrometers and 2 micrometers. The material of the LTHC can be a liquid ink containing carbon black and binder in a solvent mixture.

[0070] A resin or sealant, this material, resin, or compound being applied (via coating, printing, dispensing, or molding) to a horizontal surface on a wafer carrier, support, mold, or substrate and on the back side of a plurality of wafers and CSPs package structures, such as (i) filling gaps or spaces between the plurality of wafers and CSPs package structures; (ii) covering the back side of the plurality of wafers and the topmost surface of the CSPs package structures, and then performing a de-bonding or release process on the carrier, support, mold, or substrate on which the wafers or CSPs package structures and the potting compound are disposed, or, on which the wafers or CSPs package structures and the potting compound are disposed, the material, resin, or compound is applied to a horizontal surface on a wafer carrier, support, mold, or substrate, such as (i) filling gaps or spaces between the plurality of wafers and CSPs package structures; or (ii) covering the topmost surface of the plurality of wafers (the back side) and the CSPs package structures, and then performing a de-bonding or release process on the carrier, support, mold, or substrate on which the wafers or CSPs package structures and the potting compound are disposed, or, on which the wafers or CSPs package structures and the potting compound are disposed, the material, resin, or compound is applied to a horizontal surface on which the wafer carrier, support, mold, or substrate is disposed, the material, resin, or compound is applied to the back side of the wafer carrier, support, mold, or substrate ... The debonding or release process on the carrier, support, mold, or substrate of these wafers or CSPs package structures and potting compounds can be performed after the process of forming TISDs and copper metal pillars or solder bumps. Then, the structure having these wafers or CSPs package structures and potting compounds is flipped upside down (with the front side of the wafers or CSPs package structures facing up) to form TISDs on or above the exposed copper pads or metal pillars on the front side of the wafers or CSPs package structures.

[0071] Alternatively, the FOIT logic driver can be formed via the three methods described in (B) above: (B) forming an RDL layer in the process is the first step, and then flip-chip bonding the wafers or packages (CSPs) to the RDL layer. The process steps of the method in (B) are similar to those of the method in (A)(i), except that:

[0072] A temporary substrate (T-Sub) is provided having a fan-out interconnection scheme of the logic drive (FOISD). The FOISD includes fan-out interconnect metal lines or interconnects, micro metal pads, micro metal pillars, or micro metal bumps located on the surface of the temporary substrate. The micro metal pads, micro metal pillars, or micro metal bumps are used in flip-chip packaging processes when the logic drive is formed into a multi-chip package. The multi-chip package is flip-chip bonded onto the T-Sub using these micro metal pads, micro metal pillars, or micro metal bumps. The T-Sub can be wafer-type (e.g., 8-inch, 12-inch, or 18-inch wafer) or square or rectangular panel-type (its width or length is, for example, greater than or equal to...). (equal to 20cm, 30cm, 50cm, 75cm, 100cm, 150cm, 200cm, or 300cm), the temporary substrate can be made of silicon, metal, ceramic, glass, steel, plastic, polymer, epoxy resin-based polymer, or epoxy resin-based compound. The T-Sub is used as a temporary support in the wafer-level or panel-level process. After (a) the FOISD process described above, the substrate will be removed or peeled off; (b) flip-chip packaging and injection of the underfill layer; (c) molding. As an example, in forming FOISD on a glass substrate, the glass substrate can be used as a temporary substrate. The steps for forming FOISD are as follows:

[0073] (a) A sacrifice bonding layer is formed on the glass substrate, the sacrifice bonding layer being used to: (i) serve as a bonding layer to bond FOISD structures (high-density fan-out interconnect structure, micro metal pads, metal pillars or metal bumps) so that FOISD is disposed thereon; (ii) serve as a substrate release layer to disconnect or release the FOISD, flip-chip package / underfill layer and molding layer after the formation of FOISD, flip-chip package / underfill layer and molding layer is completed, thereby separating the glass substrate from these structures (FOISD, flip-chip package / underfill layer and molding layer), the sacrifice bonding layer being made of a light-to-heat conversion material. The LTHC is a liquid ink containing carbon black and a binder in a solvent mixture. It is formed by screen printing, spin coating or adhesive bonding. The LTHC can be a liquid ink deposited on the glass substrate by printing or spin coating, followed by heating and curing or drying. The thickness of the LTHC is greater than 1 micrometer or between 0.5 micrometer and 2 micrometer.

[0074] (b) Forming the aforementioned FOISD (Fan-out Interconnect Structure of Logic Driver) on or above the sacrifice bonding layer and on the T-Sub (Glass Substrate), the FOISD comprising a plurality of interconnect metal layers, wherein each pair of adjacent interconnect metal layers has an inter-metal dielectric layer located within each interconnect metal layer, the metal lines, interconnects and metal plugs being formed via mboss copper processes, the mboss copper processes disclosed or described in the description of metal lines, interconnects and metal plugs in the SISC of the FPGA IC chip. The FOISD first deposits a bottom dielectric layer on the sacrifice bonding layer, forming a plurality of openings in the bottom dielectric layer. Then, a bottom metal layer is formed on the bottom dielectric layer and in the openings of the bottom dielectric layer. The metal in these openings can serve as metal plugs. After removing the sacrifice bonding layer and the T-Sub (glass substrate), the bottom of the metal plug can be exposed (serving as a metal plug contact). The bottom dielectric layer, the metal plug in the bottom dielectric layer, and the bottom interconnect metal layer (metal line or interconnect line) of the FOISD can be formed by repeatedly using the floating copper process, forming (i) the bottom dielectric layer or the inter-metal dielectric layer; (ii) the bottom metal layer or the inter-metal metal layer; and (iii) the process or material of the metal plug in the inter-metal dielectric layer can be the same as the process or material used to form the SISC structure in the FPGA IC chip. The FOISD may include 1 to 7 layers or 1 to 4 layers of inter-metal metal layers.

[0075] The FOISD's interconnect metal lines or interconnects are connected to or coupled to the FOISD's interconnect metal lines or interconnects, or connected to the transistors within the chip via metal plugs in openings in the protective layer. The thickness of the FOISD's metal lines or interconnects is between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm, between 1µm and 10µm, or between 2µm and 10µm, or greater than or equal to the thickness of the interconnects. 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm or 3µm, while the width of the metal wire or connecting wire of the SISC is, for example, between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm, between 1µm and 10µm or between 2µm and 10µm, or the width is greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm or 3µm. The thickness of the intermetallic dielectric layer is, for example, between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm, between 1µm and 10µm, or between 2µm and 10µm, or greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, or 3µm. The metal lines or interconnects of FOISD are used as programmable interconnects.

[0076] (c) The micro copper pillars or solder bumps forming the FOISD are formed on the substrate by means of the raised plating metal process disclosed and described above, within the exposed openings of the top layer of the FOISD interconnect metal layer and the insulating dielectric layer in the FOISD.

[0077] The height of these micro-metal pillars or solder bumps on the substrate is between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or greater than or equal to 30µm, 20µm, 15µm, 5µm, or 3µm. The maximum diameter of the cross-section of the micro-metal pillars or bumps (e.g., the diameter of a circle or the diagonal length of a square or rectangle) is, for example, between 3µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, or between 5µm and 30µm. The spatial distance between the nearest adjacent metal pillars or bumps is between 3µm and 60µm, between 5µm and 20µm, between 5µm and 15µm, or between 3µm and 10µm, or less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm.

[0078] (d) Perform flip-chip assembly, bonding, and packaging: Then, multiple IC chips or CSP package structures are bonded or packaged onto the corresponding micro-copper pads, copper pillars, or copper bumps of the FOISD directly above or on the TS substrate using a flip-chip packaging method (wherein the surface or side of the chip with the transistor is facing down, or the front side of the CSP package structure with copper bumps or solder bumps is facing down), while the back side of the silicon substrate of the chip (on which no transistor is disposed) is facing up, or the back side of the CSP package structure is facing up, IC... Chip or CSP package structures are assembled, bonded, or packaged onto the substrate, including the plurality of chip or CSP package structures mentioned above: standard commercial FPGA chips, dedicated control chips, dedicated I / O chips, dedicated control chips and dedicated I / O chips, IAC chips and / or computing chips and / or complex arithmetic chips, such as CPU chips, GPU chips, DSP chips, TPU chips, APU chips, or AI chips. All the plurality of chip or CSP package structures are in a flip-chip package within a plurality of logic drivers. These chip or CSP package structures include micro-copper pillars or solder bumps located on the front side of the chip or CSP package structure. Underfill material is applied to the substrate, IC chip or CSP package structure (and IC) using a dispensing method. In the gaps or spaces between micro copper bumps or copper pillars and the substrate of a wafer or CSP package structure, the underfill material includes epoxy resin or compound, and the underfill material can be cured at or above 100°C, 120°C or 150°C.

[0079] (2) The filler material, resin or compound is applied (via coating, printing, dripping or molding) to a carrier, support, mold or substrate and to the back of a plurality of wafers or CSPs package structures to a horizontal plane, such as (i) filling the gaps or spaces between the plurality of wafers or CSPs package structures; (ii) covering the topmost surface of the plurality of wafers or CSPs package structures (the back of the wafer or CSPs package structure), and then a de-bond or release step may be performed on the carrier, support, mold or substrate on which the wafers or CSPs package structures and the potting compound are disposed, after which the bottom surface of the metal plug in the bottom dielectric layer is exposed and serves as the metal plug contact.

[0080] (3') Since FOISD is used as TISD, there is no need for the TISD fabrication process.

[0081] (4') The structure having the chip or CSP package structure, FOISD and potting compound is flipped upside down (the front side having the chip or CSP package structure is facing up, and the FOISD is located on or above the IC chip or CSP package structure) to form copper metal pillars or solder bumps located in the openings in the top insulating dielectric layer of the FOISD and exposed on the surface of the top metal layer of the FOISD.

[0082] The TISD or FOISD interconnect metal lines of the logic driver (formed via processes (A)(i), (A)(ii) or (B)) may include: (a) an interconnect metal wire mesh or structure of the TISD or FOISD metal lines or traces of the logic driver for connecting or coupling the transistors, FISCs, SISCs and / or micro copper pads, copper pillars or bumps (via the first BISCSP of the first BISCSP of the first BISCSP and the first TPVCs of the first FPGA / HBM CSP package structure, the first BISCSP, the metal lines or traces and the metal plugs of the first FPGA / HBM CSP package structure) of the first FPGA / HBM CSP package structure to the transistors, FISCs, SISCs and / or micro copper pads, copper pillars or bumps (via the second FPGA / HBM CSP package structure of the first BISCSP and the first TPVCs of the first FPGA / HBM CSP package structure) of the second FPGA IC chip in the second standard commercial FPGA / HBM CSP package structure of the logic driver (via the second FPGA / HBM CSP package structure of the second FPGA / HBM CSP package structure of the second FPGA IC chip. The first BISCSP and first TPVCs of the CSP package structure, the first BISCSP, the metal lines or traces, and the copper pillars or solder bumps on the metal plugs, the interconnection wire mesh or structure of the metal lines or traces of the TISD or FOISD can be connected or coupled to external circuits or components to logic drivers via metal pillars or bumps (copper pillars or bumps, solder bumps or gold bumps located on the TISD or FOISD), the interconnection wire mesh or structure of the metal lines or traces of the TISD or FOISD can be a connection mesh or structure for signal or for power supply or grounding, the interconnection wire mesh or structure of the metal lines or traces of the TISD or FOISD can be used as a power or ground bus for supplying power to: (i) via the power / ground bus and the first TPVCs of the first FPGA IC chip to the first FPGA IC chip and the first HBM IC chip or the first HBM IC chip of the first HBM SCSP in the first FPGA / HBM CSP package structure, and / or (ii) via the second FPGA The power / ground bus of the IC chip and the second TPVCs to the second FPGA IC chip and the second HBM IC chip or the second HBM IC chip in the second HBM SCSP in the second FPGA / HBM CSP package structure;(b) Includes a network or structure of interconnected metal lines or connections within the TISD or FOISD that connects to micro-copper pads, pillars, or bumps of the IC chip or CSP package structure within the logic driver. This network or structure of interconnected metal lines or connections within the TISD or FOISD can be connected via metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps located on the TISD or FOISD) to external or external multiple circuits or components outside the logic driver. The network or structure of interconnected metal lines or connections within the TISD or FOISD can be a mesh network or structure used for multiple signals, power supplies, or grounding. (c) Interconnect metal lines or interconnects within the TISD or FOISD included in the logic driver can be connected to external or external complex circuits or components outside the logic driver via metal pillars or bumps (copper pillars or bumps, solder bumps or gold bumps located on the TISD or FOISD) of the single-layer logic driver package. Interconnect metal lines within the interconnect network or structure in the TISD or FOISD can be used for multiple signals, power supplies or grounding. In this case, the metal pillar or bump can be connected, for example, to the I / O circuit of the dedicated I / O chip of the logic driver. The I / O circuit in this case can be a large I / O circuit, such as a bidirectional I / O (or tridirectional) pad. The I / O circuit includes an ESD circuit, a receiver and a driver, and has an input capacitance or output capacitance that can be between 2 pF and 100 pF, 2 pF and 50 pF, 2 pF and 30 pF, 2 pF and 20 pF, 2 pF and 15 pF, 2 pF and 10 pF or 2 pF and 5 pF, or greater than 2 pF, 5 pF, 10 pF, 15 pF or 20 pF.(d) An interconnect network or structure of metal wires or interconnects included in TISD or FOISD for connecting transistors, FISCs, SISCs, and / or micro copper pads (via copper pillars or solder bumps on or above the first BISCSP in the FPGA / HBM CSP package, metal wires or metal plugs of the first BISCSP, and first TPVCs) on the second FPGA IC chip in the second standard commercial FPGA / HBM CSP package in the logic driver to transistors, FISCs, SISCs, and / or micro copper pads (via the second FPGA / HBM CSP package) on the second FPGA IC chip in the logic driver. The CSP package structure includes copper pillars or solder bumps on or above the second BISCSP, metal lines or metal plugs of the second BISCSP, and second TPVCs, but no external or external complex circuits or components outside the logic driver. That is, no metal pillars or bumps (copper pillars or bumps, solder bumps or gold bumps) of the logic driver are connected to the interconnect network or structure of metal lines or interconnects in the TISD or FOISD. In this case, the interconnect network or structure of metal lines or interconnects in the TISD or FOISD can be connected or coupled to (i) the first I / O circuit of the first FPGA chip in the first standard commercial FPGA / HBM CSP package structure packaged in the logic driver; and (ii) the second standard commercial FPGA / HBM The second I / O circuit of the second FPGA chip in the CSP package structure; the first and second I / O circuits in this case can be small I / O circuits, such as a bidirectional I / O (or tridirectional) pad, the I / O circuit includes an ESD circuit, a receiver and a driver, and has an input capacitance or output capacitance that can be between 0.05pF and 2pF, between 0.05pF and 1pF, or less than 2pF or 1pF;(e) An interconnect network or structure of metal lines or connections within the TISD or FOISD of the logic driver is used to connect or couple to a plurality of micro copper pillars or bumps on the IC chip or package structure within the logic driver, but is not connected to external external or external multiple circuits or components outside the logic driver. That is, no metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps) of the logic driver are connected to the interconnect network or structure of metal lines or connections within the TISD or FOISD. In this case, the interconnect network or structure of metal lines or connections within the TISD or FOISD can be directly connected or coupled to internal circuitry, such as transistors, FISCs, or SISCs, without passing through any FPGA IC chip's I / O circuitry.

[0083] Another example of the present invention provides a logic driver including a plurality of single-layer packaged logic drivers, and each single-layer packaged logic driver in a multi-chip package as disclosed above. The number of the plurality of single-layer packaged logic drivers is, for example, 2, 5, 6, 7, 8 or more, and the type is, for example, (1) flip-chip packaged on a printed circuit board (PCB), a high-density fine metal line PCB, a BGA substrate or a flexible circuit board; or (2) a package-on-package (POP) technology, in which a single-layer packaged logic driver is packaged on top of other single-layer packaged logic drivers. This POP packaging technology may, for example, apply surface mount technology (SMT).

[0084] Another example of the present invention provides a method for forming a single-layer packaged logic driver suitable for stacked POP packaging technology. The process steps and specifications of the single-layer packaged logic driver for POP packaging are the same as those of the FOIT chip packaged logic driver described in the above paragraph, except that through-package-metal-visas (TPVs), through-polymer-metal-posts or through-polymer-metal-pillars or thought polymer-visas (TPVs) are formed between the gaps or spaces of the multiple chip or CSP package structure of the logic driver, and / or the peripheral area of ​​the logic driver package and the chip or CSP package structure boundary within the logic driver. TPVs are used to connect or couple to the front of the logic driver to the back of the logic driver package. Single-layer packaged logic drivers with TPVs can be used in stacked logic drivers. This single-layer packaged logic driver can be of standard type or standard size. For example, a single-layer packaged logic driver can be square or rectangular with a certain width, length and thickness. An industry standard can set the diameter (size) or shape of the single-layer packaged logic driver. For example, the standard shape of a single-layer packaged logic driver can be square, with a width greater than or equal to 4 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, and a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm. Alternatively, the standard shape of a single-layer packaged logic driver can be rectangular, with a width greater than or equal to 3 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, a length greater than or equal to 3 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, 45 mm or 50 mm, and a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm.Logic drivers with TPVs can be formed on the following components via forming copper pillars or bumps: (a) formed on a carrier, support, mold, or substrate, as in process step (1) of method (A)(i) or method (A)(ii) above, or (b) formed on a FOISD on a TS in process step (1) of method (B); The logic driver is formed using a FOIT package, and the process steps for forming copper pillars and bumps as TPVs are similar to those for forming TPVCs, including a raised copper plating process, wherein the height of the TPVs (from absolute) The distance between the top surface of the dielectric layer and the top surface of the copper pillar or bump, for example, is between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, between 10µm and 30µm, or greater than, higher than or equal to 50µm, 30µm, 20µm, 15µm or 5µm, the maximum diameter in the cross-sectional view of the copper pillar or bump ( For example, the diameter of a circle or the diagonal of a square or rectangle; for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm. The minimum space (gap) between the nearest copper pillars or bumps is, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 150µm, 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm.

[0085] Then, a wafer or panel having an insulating dielectric layer, copper pillars, bumps, or TPVs is used as a carrier, support, mold, substrate, or temporary substrate (TS) to form the above-described logic driver. All steps in forming the logic driver are the same as described above, and some process steps are listed again below: In process step (2) for forming the above-described logic driver, a filling polymer material, resin, or compound (i) is filled into the gaps or spaces between the wafers or CSPs package structures, (ii) is covered on the front or surface of the wafers or CSPs package structures in method (A)(i), or is covered on the back or surface of the wafers or CSPs package structures in method (A)(ii) or method (B); (iii) is filled into the gaps or spaces between the micro copper pillars or bumps of the wafers or CSPs package structures; (iv) is filled in method (A)(i) and method (A)(ii). (v) Covering the upper surface of the micro copper pillars or bumps on the wafer or CSP package structure; (v) Filling the gaps or spaces between TPVs located on the wafer, panel, or TS; (vi) Covering the upper surface of the copper pillars or bumps (TPVs) on the wafer, panel, or TS, and planarizing the surface of the material, resin, or compound used and the following components to a level using CMP polishing or grinding methods, for example: (i) grinding all the upper surfaces of the micro copper pillars or bumps on the wafer or CSP package structure (only used in methods (A)(i) and (A)(ii)) to planarize and fully expose them, and (ii) The grinding site is used to planarize and fully expose all the upper surfaces of TPVs on the wafer, panel, or TS. For methods (A)(i) and (A)(ii), the TISD structure is then formed on the planarized surface of the filler material, resin, or compound, and connected or coupled to the upper surfaces of all the micro copper pillars or bumps on the exposed wafer or CSP package structure and / or the upper surfaces of the TPVs on the wafer or panel. For methods (A)(i), (A)(ii), and (B), copper pillars or bumps, solder bumps, and gold bumps are then formed on the TISD or FOISD (wherein the TS and sacrificial bonding layer are already...). (Removed), used to connect or couple to the metal lines or traces in the plurality of interconnect metal layers in TISD or FOISD as described above, copper pillars or bumps on the wafer or panel are used as TPVs after curing with a filling polymer material, resin or compound, for connecting or coupling the circuit, interconnect metal structure (e.g. TISD or FOISD), copper pillars or bumps, solder bumps, gold bumps and / or metal pads located on the front side of the logic driver to the circuit, interconnect metal structure (e.g. TISD or FOISD), copper pillars or bumps, solder bumps, gold bumps and / or metal pads located on the back side of the logic driver package.For methods (A)(i) and (A)(ii), the wafer carrier, support, mold, or substrate can be removed after the CMP polishing or grinding process and before the formation of TISD, after which the bottom surface of the TPVs is exposed. For method (A) (i) Alternatively, the wafer carrier, support, mold, or substrate may be removed when all manufacturing steps are completed. The wafer carrier, support, mold, or substrate may be removed via a stripping process, a debonding process, a CMP process, a back-side grinding process, or a polishing process. After the wafer carrier, support, mold, or substrate is removed, the bottom surface of the TPVs is exposed. In method (B), the TS and sacrifice bonding layer are also removed to expose the bottom surface of the TPVs. The exposed bottom surface of the TPVs serves as a copper pad on the back of the logic driver for connecting or coupling transistors, circuits, interconnect metal structures, metal pads, metal pillars or bumps, and / or components located on the front (or top, still assuming the back of the IC chip or CSP package structure is facing up) of the logic driver package structure.

[0086] For example, a stacked logic driver is formed via the following process steps: (i) a first single-layer package logic driver is provided, which is a discrete, wafer, or panel type, having TPVs and copper pillars or bumps, solder bumps or gold bumps facing downwards, and the exposed TPVs having multiple copper pads facing upwards; (ii) a POP stacked package is formed via surface mount or flip-chip packaging, with a second discrete single-layer package logic driver or an IC chip package disposed on top of the provided first single-layer package logic driver. The surface mount process is similar to the SMT technology used on multiple component packages disposed on a PCB. This process involves printing a solder layer or solder paste or flux on the copper pads of the TPVs, and then using a flip-chip packaging process to connect or couple the copper pillars or bumps, solder bumps or gold bumps on the second discrete single-layer package logic driver or IC chip package to the copper pillars or bumps or solder bumps on the first discrete single-layer package logic driver. This process is similar to the process used on IC chip packages. The POP stacking technology connects or couples copper pillars or bumps, or solder bumps or gold bumps, to the copper pads on the TPVs of the first single-layer packaged logic driver to the copper pads on the second single-layer packaged logic driver or IC chip package. Underfill material is filled into the gap or space between the first and second single-layer packaged logic drivers. A third single-layer packaged logic driver is then connected or coupled to the exposed copper pads of the TPVs of the second single-layer packaged logic driver using a flip-chip package. This POP stacking packaging process can be repeated to assemble more single-layer packaged logic drivers (e.g., more than or equal to n single-layer packaged logic drivers, where n is greater than...). (or equal to 2, 3, 4, 5, 6, 7, 8) to form a complete stacked logic driver. When the first single-layer package logic driver is of the discrete type, it can be, for example, a first flip-chip package assembled to a carrier board or substrate, such as a PCB or BGA board, and then a POP process is performed. In the carrier board or substrate type, multiple stacked logic drivers are formed. Then the carrier board or substrate is cut to produce multiple discrete complete stacked logic drivers. When the first single-layer package logic driver is still of the wafer or panel type, when performing a POP stacking process to form multiple stacked logic drivers, the wafer or panel can be directly used as a carrier board or substrate. Then the wafer or panel is cut and separated to produce multiple discrete stacked complete logic drivers.

[0087] Another example of the present invention provides a method for a single-layer packaged logic driver suitable for stacked POP assembly technology. The single-layer packaged logic driver for POP packaging assembly follows the same process steps and specifications as the plurality of FOIT chip packages (with TPVs) described in the foregoing paragraph, except that a back metal interconnect structure (hereinafter referred to as BISD) is formed on the back of the single-layer packaged logic driver.

[0088] In method (A)(i), a sacrifice bonding layer is used to form the FOIT package structure on the wafer carrier, support, mold, or substrate. The sacrifice bonding layer serves to: (i) serve as a bonding layer to bond to the BISD structure (including high-density fan-out interconnect structures and micro-metal pads, metal pillars, or bumps) formed thereon; and (ii) serve as a substrate release layer to bond or release the substrate (which includes the BISD, IC wafer (or CSP package), molding compound, and TISD, after the steps of forming or setting the BISD, IC wafer (or CSP package), molding compound, TISD, and metal pads, metal pillars, or bumps). The material of the sacrifice bonding layer is a light-to-heat transfer layer. The LTHC (Liquid Thermal Adhesive) is formed using a conversion (LTHA) material and is deposited on a glass substrate via screen printing, spin coating, or adhesive bonding. It can be in liquid form and is deposited on the substrate via printing or spin coating, followed by heat curing or drying. The thickness of the sacrifice bonding layer is greater than 1 micrometer or between 0.5 and 2 micrometers. The LTHC material can be a liquid ink containing carbon black and adhesive in a solvent mixture. The BISD (Biologically Interchangeable Surface Mount) is formed on or above the sacrifice bonding layer on the wafer carrier, support, mold, or substrate. Before picking up, attaching, or securing the IC chips or CSPs package structures on the wafer carrier, support, mold, or substrate, copper pillars, bumps, or TPVs are formed on or above the BISD. The BISD is formed using the same or similar process steps as those used to form the TISD, and the process steps for forming TPVs on the BISD are the same or similar as those used to form metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps) on the TISD.The process steps for forming a BISD include: (i) forming metal lines or traces and metal plugs using a raised plating process; (ii) forming an intermetallic dielectric layer, wherein the intermetallic dielectric layer comprises a polymer material, such as polyimide, benzocyclobutene, parylene, epoxy resin substrate or compound, photosensitive epoxy resin SU-8, elastomer or silicone, the intermetallic dielectric layer being located between the two interconnect metal layers of the BISD and the metal plugs being located in the intermetallic dielectric layer, and the top interconnect metal layer of the BISD being the top layer of the BISD. The layer is covered by an insulating dielectric layer, and the top insulating dielectric layer has a plurality of openings exposing the upper surface of the top layer of the BISD interconnect metal layer. TPVs are formed on the top layer of the BISD interconnect metal layer with the plurality of openings exposed. The TPVs are located in the gap or space between the two-chip or CSP package structures of the logic driver, and / or in the peripheral area of ​​the logic driver package structure and outside the boundary of the chip or CSP package structure of the logic driver (the chip or CSP package structure will be removed, bonded or fixed in subsequent processes).

[0089] BISD may include 1 to 6 layers of interconnect metal layers or 2 to 5 layers of interconnect metal layers. The metal wires, interconnects or metal plate interconnects of BISD have an adhesive layer (e.g., Ti layer or TiN layer) and a copper seed layer located only at the bottom, but not on the sidewalls of the metal wires or interconnects. The interconnect metal wires or interconnects of FISC have an adhesive layer (e.g., Ti layer or TiN layer) and a copper seed layer located on the sidewalls and bottom of the metal wires or interconnects.

[0090] The thickness of the metal wires, connecting wires, or metal plates of BISD is, for example, between 0.3µm and 40µm, between 0.5µm and 30µm, between 1µm and 20µm, between 1µm and 15µm, between 1µm and 10µm, or between 0.5µm and 5µm, or thicker than (greater than) or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, 5µm, 7µm, or 10µm. The width of the metal wires or connecting wires of BISD is, for example, between 0.3µm and 40µm, between 0.5µm and 30µm, between 1µm and 20µm, between 1µm and 15µm, between 1µm and 10µm. The thickness of the intermetallic dielectric layer in BISD is, for example, between 0.3µm and 40µm, between 0.5µm and 30µm, between 1µm and 20µm, between 1µm and 15µm, between 1µm and 10µm, or between 0.5µm and 5µm, or wider than or equal to 0.3µm, 0.7µm, 1µm, 2µm, 3µm, 5µm, 7µm, or 10µm. The thickness or height of the metal plug in the bottom insulating dielectric layer of the BISD is, for example, between 3µm and 50µm, between 3µm and 30µm, between 3µm and 20µm, or between 3µm and 15µm, or greater than or equal to 3µm, 0.7µm, 1µm, 2µm, 3µm, or 5µm. The metal plates, with thicknesses of µm, 20µm, or 30µm, within the metal layer of the BISD interconnect metal layer can be used as power / grounding for power supply and / or as heat sinks or heat dissipation diffusers, wherein the thickness of this metal is thicker, for example, between 5µm and 50µm, between 5µm and 30µm, between 5µm and 20µm, or between 5µm and 15µm, or greater than or equal to 5µm, 10µm, 20µm, or 30µm. The power / grounding and / or heat sinks or heat dissipation diffusers within the BISD interconnect metal layer can be arranged in an interlaced or cross-shaped manner, for example, in a fork shape.

[0091] After the BISD formation step, copper pillars and bumps (to be used as TPVs) are formed on or above the top insulating dielectric layer of the BISD on the wafer carrier, support, mold, or substrate via a copper plating process, and are located on the upper surface of the top interconnect metal layer of the BISD exposed by the opening of the top insulating dielectric layer. The height of the copper pillars or bumps (the distance between the horizontal plane of the upper surface of the insulating dielectric layer and the horizontal plane of the upper surface of the copper pillars or bumps) is, for example, between 5µm and 300µm. The maximum diameter (e.g., the diameter of a circle or the diagonal of a square or rectangle) in a cross-sectional view of a copper pillar or bump is between µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than, higher than or equal to 50µm, 30µm, 20µm, 15µm, or 10µm. For example, the diameter of a circle or the diagonal of a square or rectangle is specified. Between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, between 10µm and 30µm, or greater than or equal to 150µm, between 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm, the closest copper pillar or bump. Minimum space (gap) is, for example, between 5µm and 300µm, between 5µm and 200µm, between 5µm and 150µm, between 5µm and 120µm, between 10µm and 100µm, between 10µm and 60µm, between 10µm and 40µm, or between 10µm and 30µm, or greater than or equal to 150µm, or between 100µm, 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, or 10µm.

[0092] Then, the wafer or panel having BISD, copper pillars or bumps (TPVs) is used as the wafer carrier, support, mold or substrate to form the above-mentioned logic driver. All the steps for forming the logic driver are the same as those described above. Some process steps are listed again below: In process step (2) for forming the above-mentioned FOIT logic driver, a filling polymer material, resin or compound is (i) filled into the gaps or spaces between the wafers or CSPs package structures, and (ii) covered with the wafers or CSPs. (iii) Filling the gaps or spaces between the micro-copper pillars or bumps of the wafer or CSP package structure; (iv) Covering the upper surface of the micro-copper pillars or bumps on the wafer or CSP package structure; (v) Filling the gaps or spaces between TPVs located on the wafer or panel; (vi) Covering the upper surface of the TPVs on the wafer or panel, and using CMP polishing or grinding to flatten the surface of the material, resin or compound used and the following components to a level, for example: (i) grinding all the upper surfaces of the micro-copper pillars or bumps on the wafer or CSP package structure to flatten and fully expose them; and (ii) The upper surface of all copper pillars or bumps (TPVs) on the wafer or panel is planarized and fully exposed by grinding, and then TISD is formed. Copper pads, copper pillars or solder bumps are then formed on or above the TISD. The sacrificed bonding layer and the wafer carrier, support, mold or substrate can be (i) removed after the CMP process, grinding process or polishing process and before the formation of TISD (planarizing the surface of the filler material, resin or compound); (2) retained in subsequent process steps and removed after all process steps are completed (in wafer or panel format). After the wafer carrier, support, mold or substrate is removed, the metal plug surface in the opening in the bottom insulating dielectric layer of the BISD is exposed. The plug surface is used as contact pads, which can be designed or arranged as a pad matrix on the bottom surface of the back surface of the logic driver; the contact pads in the peripheral area are used as signal pads, while the pads in or near the central area are used as power supply / ground reference (P / G) pads. These pads can be directly positioned under the chip carrier, support, mold, or substrate on which the chip or CSP package structure is set and attached. The signal pads in the peripheral area can form a ring-shaped area along the boundary of the logic driver package, for example, 1 ring, 2 rings, 3 rings, 4 rings, 5 rings, or 6 rings. The spacing of the multiple signal pads in the ring area can be smaller than the spacing of the power supply / ground (P / G) pads near the central area on the back surface of the logic driver package.The copper pads exposed on the back or bottom surface of the logic driver package can be connected to TPVs. Therefore, the copper pads and TPVs can be used to connect or couple transistors, circuits, interconnect metal structures (e.g., TISD), metal pads, metal pillars or bumps and / or components located on the front (or top, still assuming the back of the IC chip or CSP package structure is facing up) of the logic driver package structure to interconnect metal structures (e.g., BISD), metal pads, metal pillars or bumps and / or components located on the back (or bottom) of the logic driver package structure.

[0093] The BISD provides additional interconnection lines, metal layers, or bottom or back connection layers of the logic driver package structure and provides exposed metal pads or copper pads arranged in a matrix on the bottom of the single-layer package logic driver. These include the logic driver's IC chip or CSP package structure below and in a vertical position. TPVs are used to connect or couple circuitry or components on the upper side of the logic driver (e.g., TISD) to the back side of the logic driver package (e.g., BISD). The single-layer package logic driver with TPVs can be used in stacked logic drivers. This single-layer package logic driver can be of a standard type or standard size. For example, the single-layer package logic driver can be square or rectangular with a certain width, length, and thickness, and / or have multiple copper pads in a standard layout position. An industry standard can define the diameter (size) or shape of a logic driver. For example, the standard shape of a single-layer packaged logic driver can be a square with a width greater than or equal to 4 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, and a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm. Alternatively, the standard shape of a COIP-multichip packaged logic driver can be rectangular, with a width greater than or equal to 3 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, a length greater than or equal to 3 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, 45 mm or 50 mm, and a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm. Alternatively, the standard shape of a single-layer packaged logic driver can be rectangular, with a width greater than or equal to 3 mm, 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, a length greater than or equal to 5 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, 45 mm or 50 mm, and a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm.

[0094] In method (A)(ii) for forming the FOIT package structure, the disclosure and description of the BISD are similar to or the same as those disclosed and described in method (A)(i), except that TPVs and TISD are formed before the BISD, copper pillars or bumps are formed on or above the wafer carrier, bracket, mold or substrate as TPVs, the wafer or CSP package structure is attached or bonded to the wafer carrier, bracket, mold or substrate, and then the wafer carrier, bracket, mold or substrate is removed to expose the micro copper pads, copper pillars or bumps, and then the TISD is formed, followed by a CMP process, grinding process or polishing process to expose the upper surface of the TPVs (the TISD has been formed and is located at the bottom of the logic driver), and then the BISD is formed on or above the exposed upper surface of the TPVs.

[0095] In method (B) for forming the FOIT package structure, the disclosure and description of the BISD are similar to or the same as those disclosed and described in method (A)(i), except that the FOISD and TPVs are formed before the BISD, a CMP process, a grinding process or a polishing process is performed to expose the upper surface of the TPVs (the FOISD has been formed and is located at the bottom of the logic driver), and then the BISD is formed on or above the exposed upper surface of the TPVs.

[0096] In this paragraph, the BISD (or the back side of the logic drive) is located at the top of the logic drive, and the TISD or FOISD (or the front side of the logic drive) is located at the bottom of the logic drive, for any of the above three methods (A) (i), (A) (ii) and (B) form the FOIT logic driver. The BISD interconnect line system of the single-layer package logic driver is used to: (a) connect or couple the copper pads, copper pillars or solder bumps on the surface (surface of BISD) on the back (top) of the single-layer package logic driver to their corresponding TPVs, and via the corresponding TPVs, connect or couple the copper pads, copper pillars or solder bumps on the back of the single-layer package logic driver to the metal lines or interconnects of the TISD or FOISD on the front (or bottom) of the single-layer package logic driver, thus connecting or coupling the copper pads, copper pillars or solder bumps on the upper surface of the BISD to the transistors, FISCs, SISCs and micro copper pillars or bumps of the IC chip or CSP package structure in the single-layer package logic driver. (b) For connecting or coupling to copper pads, pillars, or solder bumps on the surface (surface of BISD) of the back (top) of the single-layer packaged logic driver and their corresponding TPVs, and via the corresponding TPVs, connecting or coupling the copper pads, pillars, or solder bumps on the back of the single-layer packaged logic driver to metal lines or interconnects on the front (or bottom) of the single-layer packaged logic driver TISD or FOISD, and the TISD or FOISD can be connected or coupled to metal pads, pillars, or bumps on and below the TISD or FOISD, thus, the copper pads, pillars, or solder bumps on the surface (surface of BISD) of the back (top) of the single-layer packaged logic driver are connected or coupled to metal pads, pillars, or bumps on the front of the single-layer packaged logic driver; (c) Connecting or coupling to the first FPGA chip (in the first FPGA / HBM) vertically positioned on the single-layer packaged logic driver via an interconnect network or structure using metal lines or interconnects within the BISD. Multiple copper pads, copper pillars, or solder bumps (located on or above the BISD) in the CSP package structure can be connected or coupled to multiple copper pads, copper pillars, or solder bumps (located on or above the BISD) of the second FPGA chip (in the second FPGA / HBM CSP package structure) vertically positioned in the single-layer package logic driver, and the interconnection network or structure can be connected or coupled to the TPVs of the single-layer package logic driver.(d) A network or structure using internal metal wires or interconnects to connect or couple a first copper pad, pillar, or solder bump (located on or above the BISD) on the FPGA chip (in the FPGA / HBM CSP package structure) vertically to a second copper pad, pillar, or solder bump on the same FPGA chip (in the same FPGA / HBM CSP package structure), to a second copper pad, pillar, or solder bump vertically to the same FPGA chip (in the same FPGA / HBM CSP package structure), this network or structure may connect to TPVs coupled to the single-layer package logic driver; (e) a power or ground plane and a heat sink or heat dissipation diffuser.

[0097] Stacked logic drivers using single-layer packaged logic drivers with BISD and TPVs can be formed using the same or similar steps described above.

[0098] Another embodiment of the present invention provides several alternative interconnect lines for TPVs of a single-layer packaged logic driver (now with the logic driver flipped down, the TISD or FOISD (back side of the logic driver) is located on the top side of the logic driver, while the BISD or FOISD (front side of the logic driver) is located on the bottom side of the logic driver): (a) The TPV is used as a through-hole connection between another single-layer packaged logic driver above and another single-layer packaged logic driver below the single-layer packaged logic driver, without connecting or coupling to any IC of the single-layer packaged logic driver. FISC, SISC, or micro copper pads, pillars, or bumps on the chip; in this case, the formation of a stacked structure from bottom to top consists of: (i) copper pads, pillars, or solder bumps located below the BISD; (ii) stacked interconnect layers and metal plugs in the dielectric layer of the BISD; (iii) TPVs; (iv) multiple stacked interconnect layers and metal plugs in the dielectric layer of the TISD or FOISD; (v) metal pillars or bumps located on or above the TISD or FOISD; (b) TPVs stacked in (a) such as a through TPV, but connected or coupled to one or more ICs of a single-layer packaged logic driver. (c) FISC, SISC, or micro copper pads, pillars, or bumps on a chip or CSP package structure, via metal lines or traces in TISD or FOISD; In the case where TPV is only stacked at the bottom and not at the top, the TPV connection structure is formed from bottom to top as follows: (i) copper pads, pillars, or solder bumps located below BISD; (ii) multiple stacked interconnect layers and metal plugs in the dielectric layer of BISD; (iii) TPV; (iv) the top of the TPV is connected or coupled to a single layer via an interconnect metal layer and metal plugs in the dielectric layer of TISD or FOISD. (v) FISC, SISC, or micro copper pads, pillars, or solder bumps on one or more IC chips in a packaged logic driver; but without any metal pillars or bumps vertically positioned at the top of the TPV, but connected or coupled to the TPV; (v) metal pads, pillars, or bumps located on or above the TISD or FOISD connected or coupled to the top of the TPV and not vertically positioned at the top of the TPV; (d) a structure for TPV connection is formed, the structure from bottom to top being: (i) copper pads, pillars, or bumps vertically positioned below the BISD of one IC chip or CSP package structure of a single-layer packaged logic driver; (ii) copper pads, pillars, or bumps connected or coupled to the bottom of the TPV via interconnect metal layers and metal plugs in the dielectric layer of the BISD (the TPV is located in the gap or space between these chip or CSP package structures or in a peripheral area where no chip or CSP package structure is located); (iii) TPV;(iv) The top of the TPV is connected or coupled to the FISC, SISC, or micro copper pads, pillars, or solder bumps of one or more IC chips in a single-layer packaged logic driver via interconnect metal layers and metal plugs in the dielectric layer of the TISD; (v) Metal pads, pillars, or bumps located on the TISD are connected or coupled to the top of the TPV, and are not positioned above the top of the TPV; (e) The TPV connection structure, from bottom to top, includes: (i) a copper pad, pillar, or bump vertically positioned below the IC chip or CSP package structure of the single-layer packaged logic driver; (ii) copper pads, pillars, or solder bumps are connected or coupled to the bottom of the TPV (located in the gap or space between multiple chips or packages, or in the peripheral area where no IC chip or CSP package structure is placed) via interconnect metal layers and metal plugs in the dielectric layer of the BISD; (iii) TPV; (iv) The top of the TPV is connected or coupled to the IC chip or CSP package structure of the single-layer package logic driver via interconnection metal layers and metal plugs within the TISD and / or FOISD dielectric layers. The interconnection metal layers and metal plugs within the TISD and / or FOISD dielectric layers may include an interconnection network or structure of metal lines or traces in the TISD or FOISD of the single-layer package logic driver, used for connecting or coupling to the IC chip or CSP package structure of the single-layer package logic driver. The CSP package structure includes transistors, FISCs, SISCs, and / or miniature copper pads, copper pillars, or bumps, but this interconnect network or structure does not connect to or couple to external circuitry or components outside the single-layer package logic driver. That is, the single-layer package logic driver does not have metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps) connected to the interconnect network or structure of metal lines or traces in the TISD and / or FOISD. Therefore, the single-layer package logic driver does not have metal pillars or bumps (copper pillars or bumps, solder bumps, or gold bumps) connected to the top of the TPV.

[0099] Another example of the present invention discloses an interconnection network or structure of metal lines or interconnects within the TISD and / or FOISD of a single-layer packaged logic driver, used as a connection or coupling to micro pads, copper pillars or bumps on the FISC, SISC and / or FPGA / HBM CSP packaged FPGA IC chip via copper pillars or solder bumps, but the interconnection network or structure is not connected or coupled to multiple circuits or components outside the single-layer packaged logic driver. That is, there is no interconnection network or structure of multiple metal pads, pillars or bumps (copper pads, multiple metal pillars or bumps, solder bumps or gold bumps) connected to the metal lines or interconnects within the TISD and / or FOISD on or above the TISD and / or FOISD, and the multiple copper pads, copper pillars or solder bumps on (or above) the BISD are not connected or coupled to the interconnection network or structure of the internal metal lines or interconnects of the TISD and / or FOISD.

[0100] Another example of the present invention discloses that the logic driver in a multi-chip package may further include one or more dedicated programmable interconnect IC chips (DPIICs), wherein the DPIIC chip includes 5T or 6T SRAM cells and cross-point switches, and programmable interconnects between multiple circuits or interconnects of a standard commercial FPGA IC chip used in the FPGA / HBM CSP package structure of the logic driver, wherein the programmable interconnects include standard commercial FPGAs located in the FPGA / HBM CSP package structure of the logic driver. Interconnections between IC chips (TISDs or FOISDs) or between other IC chips or CSP packages in a logic driver, wherein these interconnections have crosspoint switching circuits located within them. For example, n metal lines or connections of the TISD (or FOISD) are input to a crosspoint switching circuit, and m metal lines or connections of the TISD (or FOISD) are output from the switching circuit. The crosspoint switching circuit is designed to... Each of the n metal lines or connections in an OISD can be programmed to connect to any one of the m metal lines or connections in a TISD (or FOISD). The crosspoint switching circuit can be controlled via, for example, the programming source code stored in an SRAM cell within a DPIIC chip. This SRAM cell may include six transistors (6T for short), having two transmit (write) transistors and four data latch transistors. The two transmit (write) transistors are used to write programming code or data to two storage or latch nodes of the four data latch transistors. Alternatively, the SRAM cell may include five transistors (5T for short), having one transmit (write) transistor and four data latch transistors. The one transmit (write) transistor is used to write programming code or data to two storage or latch nodes of the four data latch transistors.The data stored (or programmed) in the 5T or 6T SRAM cell can be used as a “connection” or “non-connection” between metal lines or interconnects in the programming TISD (or FOISD). The crosspoint opening relationship in this part is the same as the crosspoint switch in the standard commercial FPGA IC chip disclosed above in the FPGA / HBM CSP package structure. The details of each type of crosspoint switch are disclosed or described in the FPGA IC chip section above. The crosspoint switch may include: (1) n-type and p-type transistor pair circuits; or (2) multiplexers and switching buffers. In (1), when the data latched in the 5T or 6T SRAM cell is programmed to “1”, the pass / fail circuit of an n-type and p-type transistor pair switches to the “conduct” state, and the two metal lines or interconnects of the TISD (or FOISD) connected to the two ends of the pass / fail circuit (the source and drain of the transistor pair, respectively) are in a connected state. When the data in the SRAM cell is programmed to "0", the pass / stop circuit of the n-type and p-type paired transistors switches to the "non-conducting" state, and the two metal lines or connecting lines of TISD (or FOISD) connected to the two terminals of the pass / stop circuit (the source and drain of the paired transistors, respectively) are disconnected. Alternatively, in (2), the multiplexer selects one of the n inputs as its output and then inputs the "output" into the switching buffer. When the data latched in the 5T or 6T SRAM cell is programmed to "1", the control N-MOS transistor and control P-MOS transistor in the switching buffer are switched to the "on" state. The data on the input metal line is conducted to the output metal line of the cross-point switch, and the two metal lines or connecting lines of the TISD (or FOISD) connected to the two terminals of the cross-point switch are connected or coupled. When the data stored in the 5T or 6T SRAM cell is programmed to "0", the control N-MOS transistor and control P-MOS transistor in the switching buffer are switched to the "off" state. The data on the input metal line is not conducted to the output metal line of the cross-point switch, and the two metal lines or connecting lines of the TISD (or FOISD) connected to the two terminals of the cross-point switch are not connected or coupled. The DPIIC chip includes 5T or 6T SRAM cells and cross-point switches for programmable interconnect lines of metal wires or interconnects between standard commercial FPGA chips (in FPGA / HBM CSP package structures) within the logic driver, which are TISD (or FOISD) interconnects.Alternatively, the DPIIC chip includes 5T or 6T SRAM cells and cross-point switches for programmable interconnect lines of metal lines or interconnects between a standard commercial FPGA chip and TPVs (e.g., the bottom surface of the TPVs) in an FPGA / HBM CSP package structure within the logic driver, as disclosed in the same or similar manner above, wherein the TISD or FOISD mentioned herein is located at the bottom of the logic driver and the BISD is located at the top of the logic driver. The (programming) data stored in the 5T or 6T SRAM cells is used to program the “connection” or “non-connection” between the two, for example: (i) a first metal line or connection line, a connection mesh of the TISD (or FOISD), the connection line or mesh is connected to one or more micro pads, copper pillars or bumps on one or more IC chips in the logic driver, and / or connected to one or more metal pads, metal pillars or bumps on (or below) the TISD (or FOISD), and (ii) a second metal line, connection line or mesh of the TISD (or FOISD) is connected to or coupled to a TPV (e.g., the bottom surface of the TPV), as disclosed in the same or similar manner above. According to the above disclosure, TPVs are programmable, that is, the above disclosure provides programmable TPVs. Programmable TPVs can be used in programmable interconnect lines, including 5T or 6T SRAM cells and cross-point switches on the FPGA chip in the FPGA / HBM CSP package structure of the logic driver. The programmable TPV can be programmed (software) to (i) connect or couple to one or more micro copper pillars or bumps in one or more IC chips of the logic driver (for this purpose, metal lines or interconnects connected to the SISC and / or FISC, and / or multiple transistors), and (ii) connect or couple to one or more copper pads, copper pillars or solder bumps on (or below) the metal plug contacts of the TISD (or FOISD) of the logic driver. When a metal pad, bump, or pillar located on the back of a logic driver is connected to a programmable TPV, metal pad, bump, or pillar (located on or above the BISD) to become a programmable metal bump or pillar (located on or above the BISD), the programmable metal pad, bump, or pillar located on the back of the logic driver (located on or above the BISD) can be programmed and connected via a programmable TPV without being connected or coupled to: (i) one or more micro copper pillars or bumps on the front (the side with the transistor) of one or more IC chips (metal lines or interconnects of FISC and / or SISC) of one or more logic drivers, and / or (ii) one or more metal pads, pillars, or bumps located on or above the TISD (or FOISD) of the logic driver.Alternatively, the DPIIC chip may include 5T or 6T SRAM cells and cross-point switches that can be used in the metal lines or interconnects of the TISD (or FOISD), which is located between the metal pads, metal pillars or bumps (copper pads, metal pillars or bumps or solder bumps or gold bumps) on or below the TISD (or FOISD) of the logic driver and one or more miniature copper metal pillars or bumps of one or more IC chips of the logic driver. The data stored in the 5T or 6T SRAM cells is used to program the “connection” or “non-connection” between the following: (i) a first metal line, connection line or mesh of the TISD (or FOISD) is connected to one or more micro copper metal pillars or bumps on one or more IC chips of the logic driver, and / or connected to metal pads, metal pillars or bumps on or below the TISD (or FOISD), and (ii) a second metal line, connection line or mesh of the TISD (or FOISD) is connected to or coupled to metal pads, metal pillars or bumps on or below the TISD (or FOISD). With respect to this aspect of the invention, the metal pads, pillars, or bumps located on or below the TISD (or FOISD) are programmable. That is, this aspect of the invention provides programmable metal pads, pillars, or bumps located on or below the TISD (or FOISD). These programmable metal pads, pillars, or bumps can be additionally used on programmable interconnect lines on the FPGA IC chip within the logic driver. The FPGA IC chip includes 5T or 6T SRAM cells and cross-point switches. The programmable metal pads, pillars, or bumps located on or below the TISD (or FOISD) can be programmed to connect or couple to one or more miniature copper pillars or bumps of one or more IC chips (with SISC or FISC metal lines or interconnects and / or transistors) of the logic driver.

[0101] The metal pads, bumps or pillars located on the back of the logic driver (located on or above the BISD) are programmable when connected to a programmable TPV, wherein the TISD or FOISD is located at the bottom of the logic driver and the BISD is located at the top of the logic driver. The programmable metal pads, bumps or pillars located on the back of the logic driver (located on or above the BISD) are programmable and connected via a programmable TPV without being connected or coupled to: (i) one or more miniature copper pillars or bumps on the front (the side with the transistor) of one or more IC chips or FPGA / HBM CSPs package structures (metal lines or interconnects of FISC and / or SISC) of one or more logic drivers, and / or (ii) one or more metal pads, pillars or bumps located on or above the TISD (or FOISD) of the logic driver.

[0102] The metal pads, metal pillars, or bumps located on or below the TISD or FOISD can be programmed using a cross-point switch located on the DPIIC chip, wherein the cross-point switch can be used as a programmable interconnect line in the metal line or interconnect line of the TISD (or FOISD), which is located between the metal pads, metal pillars, or bumps (copper pads, metal pillars, or bumps, solder bumps, or gold bumps) on or below the TISD (or FOISD) of the logic driver and one or more miniature copper pads, copper metal pillars, or bumps of one (or more) IC chips or FPGA / HBM CSP package structures of the logic driver. Data stored in 5T or 6T SRAM cells is used on cross-point switches to program the “connection” or “disconnection” between: (i) a first metal line, connection line or mesh of the TISD (or FOISD) connected to one or more micro copper pads, copper pillars or bumps on one or more IC chips or FPGA / HBM CSP packages of the logic driver, and / or connected to metal pads, pillars or bumps on or below the TISD (or FOISD), and (ii) a second metal line, connection line or mesh of the TISD (or FOISD) connected to or coupled to metal pads, pillars or bumps on or below the TISD (or FOISD). With respect to this aspect of the invention, the metal pads, pillars, or bumps located on or below the TISD (or FOISD) are programmable. That is, this aspect of the invention provides programmable metal pads, pillars, or bumps located on or below the TISD (or FOISD). These programmable metal pads, pillars, or bumps can be additionally used on programmable interconnect lines on the FPGA IC chip of the FPGA / HBM CSP package structure within the logic driver. The FPGA IC chip of the FPGA / HBM CSP package structure includes 5T or 6T SRAM cells and cross-point switches. The programmable metal pads, pillars, or bumps located on or below the TISD (or FOISD) can be programmed to connect or couple to one (or more) IC chips of the logic driver or one (or more) miniature copper pads, copper pillars, or bumps of the FPGA / HBM CSP package structure (with SISC or FISC metal lines or interconnects and / or transistors on the FPGA IC chip of the FPGA / HBM CSP package structure).

[0103] DPIIC chips can be designed and manufactured using various semiconductor technologies, including older or mature technologies, such as those not more advanced than, equal to, or greater than 40nm, 50nm, 90nm, 130nm, 250nm, 350nm, or 500nm. Alternatively, the manufacturing technology of DPIIC chips may include those using technologies more advanced than or equal to 30nm, 20nm, or 10nm. This DPIIC chip can use semiconductor technologies of generation 1, 2, 3, 4, 5, or greater than 5 generations, or use more mature or advanced technologies on multiple standard commercial FPGA IC chips in the same logic driver FPGA / HBM CSP package. The transistors used in the DPIIC chip can be FINFET, FDSOI MOSFET, partially depleted silicon insulator MOSFETs, or conventional MOSFETs. The transistors used in the DPIIC chip can be different from those used in the standard commercial FPGA IC chip package of the FPGA / HBM CSP package in the same logic driver. For example, the DPIIC chip uses conventional MOSFETs, but the standard commercial FPGA IC chip package of the FPGA / HBM CSP package can use FINFET transistors in the same logic driver, or the DPIIC chip uses FDSOI MOSFETs, but the standard commercial FPGA IC chip package of the same logic driver can use FINFET transistors.

[0104] Another example of the present invention provides a standardized layout or pin (position and size) of: (i) copper pads, copper pillars or solder bumps on or below the TISD or FOISD, and (ii) copper pads, multiple copper pillars or solder bumps on or above the BISD; (iii) TPVs in a logic driver, wherein the TISD or FOISD, a standard commercial logic driver, can be customized for different applications via software coding or programming, the TISD or FOISD is located at the bottom of the logic driver, and the BISD is located at the top of the logic driver, the standard commercial logic driver has a fixed layout and design, and can be customized for different applications via software coding or programming, wherein "programming" refers to the use of programmable TPVs, programmable metal pads, metal pillars or bumps located on or below the TISD or FOISD, and / or the use of programmable metal pads, metal pillars or bumps on or above the BISD disclosed above. As disclosed above, the loaded or programmed data of the 5T or 6T SRAM cells in the DPIIC chip can be used for programmable TPVs, programmable metal pads, metal pillars or bumps on or below the TISD or FOISD, and / or programmable metal pads, metal pillars or bumps located on or above the BISD. Similarly, the loaded or programmed data of the 5T or 6T SRAM cells in the FPGA IC chip of the FPGA / HBM CSP package structure can be used for programmable TPVs, programmable metal pads, metal pillars or bumps on or below the TISD or FOISD, and / or programmable metal pads located on or above the BISD. Each standard commercial logic driver has the same design, layout, or pin configuration of metal pads, pillars, or bumps on or under the TISD or FOISD, and copper pads, pillars, or bumps or solder bumps on or under the BISD can be used for different applications, purposes, or functions by means of software coding or "programming". "Programming" refers to the use of a plurality of programmable metal pads, pillars, or bumps on or under the TISD or FOISD, and / or programmable copper pads, pillars, or bumps or solder bumps on or under the BISD (via programmable TPVs) in the logic driver for different applications, purposes, or functions.

[0105] Another example of the present invention discloses an interposer (interposer) for flip-chip assembly or packaging of a multi-chip package for a logic driver. This multi-chip package is manufactured according to a flip-chip packaging method of multiple-chip-on-an-interposer (COIP). The interposer or substrate in the COIP multi-chip package includes: (i) high-density interconnect lines for bonding or packaging multiple chip or CSP package structures on the interposer for fan-out windings and interconnect lines; (ii) multiple micro metal pads and bumps or metal pillars on the high-density interconnect lines; and (iii) deep or shallow holes in the interposer or substrate. IC chips or packages can be flip-chip assembled, bonded, or packaged onto a substrate or interposer. The IC chips or packages include the aforementioned standard commercial FPGA / HBM CSP chips, non-volatile chips (e.g., NAND flash IC chips) or packages, dedicated control chips, dedicated I / O chips, dedicated control chips and dedicated I / O chips, IAC chips and / or computing IC chips and / or computational IC chips, such as CPU chips, GPU chips, DSP chips, TPU chips, APU chips, or AI chips. The steps for forming the interposer for the non-volatile chips are as follows:

[0106] (1) Provide a substrate, which may be a wafer type (e.g., a wafer with a diameter of 8 inches, 12 inches or 18 inches), or a square panel type or a rectangular panel type (e.g., a width or length greater than or equal to 20 cm, 30 cm, 50 cm, 75 cm, 100 cm, 150 cm, 200 cm or 300 cm). The material of the substrate may be silicon, metal, ceramic, glass, steel, plastic, polymer, epoxy resin-based polymer or epoxy resin-based compound. The following example uses a silicon wafer as a substrate to form a silicon material interposer.

[0107] (2) Forming TSV in the substrate: forming deep holes, shallow holes or through holes in the substrate, taking a silicon wafer as an example, forming metal plugs in the silicon substrate, the bottom surface of the metal plugs in the silicon wafer will be exposed in the logic driver final product junction, so the metal plugs will become through plugs, which are TSVs.

[0108] (3) A first interconnection metal line is formed on or of the interposer (FISIP). The metal line or interconnect and the metal plug of the FISIP are formed by a single copper damascene process or a double copper damascene process in the process of the metal line or interconnect and the metal plug in the FISC of the FPGA IC chip described above. The FISIP has 2 to 10 layers or 3 to 6 layers of interconnection metal layers. The metal line or interconnect in the interconnection metal layer of the FISIP has an adhesive layer (e.g., Ti layer or TiN layer) and a copper seed layer located on the bottom and sidewall of the metal line or interconnect.

[0109] The FISIP is a micro-copper bump or pillar in the IC chip or CSP package structure connected or coupled to a logic driver, and a TSV in the substrate connected or coupled to an interposer. The thickness of the metal lines or interconnects of the FISIP (whether manufactured using a single damascene process or a dual damascene process) is, for example, between 3nm and 2000nm, between 3nm and 500nm, between 10nm and 1000nm, or between 10nm and 2000nm, or less than 50nm, 100nm, 200nm, 300nm, 500nm, 1000nm, 1500nm, or 2000nm. The width of the metal lines or interconnects of the FISIP is, for example, less than or equal to 50nm, 100nm, 150nm, 200nm, 300nm, or 500nm. The minimum spacing of the metal lines or interconnects of FISIP is, for example, less than or equal to 100 nm, 200 nm, 300 nm, 400 nm, 600 nm, 1000 nm, 1500 nm or 2000 nm, and the thickness of the intermetallic dielectric layer is, for example, between 3 nm and 500 nm, between 10 nm and 1000 nm or between 10 nm and 2000 nm, or less than or equal to 50 nm, 100 nm, 200 nm, 300 nm, 500 nm, 1000 nm or 2000 nm. The metal lines or interconnects of FISIP can be used as programmable interconnects.

[0110] (4) Forming a second interconnection line structure (SISIP) on the interposer substrate. On the FISIP structure, the SISIP includes interconnection line metal layers, wherein each interconnection line metal layer has an inter-metal dielectric layer between it. The metal lines or interconnections and metal plugs are formed by a raised copper plating process. This raised copper plating process can refer to the description of forming metal lines or interconnections and metal plugs in the SISC of the FPGA IC chip mentioned above. The SISIP may include 1 to 5 interconnection line metal layers or 1 to 3 interconnection line metal layers. Alternatively, the SISIP on the interposer substrate may be omitted, and the COIP only has the FISIP interconnection line structure on the substrate of the interposer substrate. Alternatively, the FISIP on the interposer substrate may be omitted, and the COIP only has the SISIP interconnection line structure on the substrate of the interposer substrate.

[0111] The thickness of the metal wires or connectors in the SISIP is, for example, between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 10µm, between 2µm and 20µm, or between 2µm and 10µm, or greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, or 3µm. The width of the metal wires or connectors in the SISIP is, for example, between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm, between 1µm and 10µm, between 2µm and 20µm, or between 2µm and 10µm. The metal lines or interconnects of the SISIP can be used as programmable interconnects, with widths between 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, or 3µm, and the thickness of the intermetallic dielectric layer is, for example, between 0.3µm and 20µm, between 0.5µm and 10µm, between 1µm and 5µm, or between 1µm and 10µm, or with a thickness greater than or equal to 0.3µm, 0.5µm, 0.7µm, 1µm, 1.5µm, 2µm, or 3µm.

[0112] (5) Micro copper pillars or bumps are formed (i) by exposing the upper surface of the top interconnect metal layer of the SISIP through an opening in the top insulating dielectric layer of the SISIP; or (ii) by exposing the upper surface of the top interconnect metal layer of the FISIP through an opening in the top insulating dielectric layer of the FISIP, in which example, the SISIP may be omitted. Micro copper pads, copper pillars or bumps are formed on the interposer substrate via the raised copper plating process described above.

[0113] The height of the micro-metal pads, metal pillars, or bumps on the intermediate substrate is, for example, between 1µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 1µm and 15µm, or between 2µm and 10µm, or greater than or equal to 60µm, 50µm, 40µm, 30µm, etc. µm, 20µm, 15µm, 10µm, or 5µm, the maximum diameter (e.g., the diameter of a circle or the diagonal length of a square or rectangle) of a micro-metal pad, metal post, or bump in a cross-sectional view, for example, between 1µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 1µm and 15µm, or between 1µm and 10µm, or less than or equal to 60µm, 50µm, 40µm, or 30µm. The spatial distance between the nearest adjacent metal pads, pillars, or bumps is 20µm, 15µm, or 10µm, and is between 1µm and 60µm, between 5µm and 50µm, between 5µm and 40µm, between 5µm and 30µm, between 5µm and 20µm, between 1µm and 15µm, or between 1µm and 10µm, or less than or equal to 60µm, 50µm, 40µm, 30µm, 20µm, 15µm, 10µm, or 5µm.

[0114] Another example of the present invention provides a method, based on flip-chip assembly multi-chip packaging technology and process, using an intermediary substrate having FISIP, micro copper pads, bumps or copper pillars and metal plugs in the substrate, to form a logic driver in a COIP multi-chip package. The process steps for forming the COIP multi-chip package logic driver are as follows:

[0115] (1) Perform flip-chip assembly, bonding and packaging: (a) First, an interposer substrate is provided, which includes FISIP, SISIP, micro copper bumps or copper pillars and TSVs, and IC chips or packages. Then, IC chips or packages are flip-chip assembled, bonded or packaged onto the interposer substrate. The interposer substrate is formed as described above. IC chips or packages are assembled, bonded or packaged onto the interposer substrate, including the plurality of chips or packages mentioned above: standard commercial FPGA / HBM. CSP packages, non-volatile chips or packages, dedicated control chips, dedicated I / O chips, dedicated control chips and dedicated I / O chips, IAC chips and / or computing chips and / or complex operation chips, such as CPU chips, GPU chips, DSP chips, TPU chips, APU chips or AI chips, all multiple chips or packages are in multiple logic drivers in flip-chip packaging, including micro copper pads, copper pillars or bumps with solder layers on the top surface of the chip or CSP package structure; (b) multiple chips or CSP package structures are flip-chip assembled, bonded or packaged on corresponding micro copper bumps or metal pillars on an interposer via solder layer reflow bonding or thermoforming bonding, wherein the side with micro copper pads, copper pillars or bumps is facing down and the front side of these chips or CSP package structures (with micro copper pads, copper pillars or bumps) is facing up; (c) underfill material is filled into the interposer, IC chip or CSP package structure (and IC) by, for example by dispensing, a dispensing machine. Between the micro-copper bumps or pillars of the wafer and the intermediary substrate, this underfill material includes epoxy resin or a compound.

[0116] (2) For example, a material, resin, or compound is used to fill the gaps or spaces between multiple wafers (or CSP packages) and to cover the back of multiple wafers (or CSP packages) using spin coating, screen printing, drop casting, or molding methods. The material, resin, or compound is applied (via coating, printing, drop casting, or molding) to an intermediate substrate and to the back of multiple wafers (or CSP packages) to a horizontal plane. The molding method includes pressure molding (using upper and lower molds) or pouring molding (using drop casting). For example, (i) filling the gaps or spaces between multiple wafers (or CSP packages); (ii) covering the top of the back of multiple wafers (or CSP packages). The material may be a polymer or molding material. The surface of the material, resin, or compound is smoothed using CMP polishing or grinding. The CMP or grinding process is performed until the back of all IC wafers (or CSP packages) is fully exposed.

[0117] (3) Thinning the silicon substrate of the interposer to expose the bottom surface of TSVs on the back side of the silicon substrate, a wafer or panel thinning process, such as removing part of the wafer or panel by chemical mechanical polishing, polishing or wafer back-side polishing, to thin the wafer or panel and expose the surface of the TSVs on the back side of the interposer.

[0118] The interconnect metal lines or traces of the FISIP and / or SISIP of the interposer board used for the logic driver may have the same function as TISD or FOISD in the FOIT logic driver disclosed above. The interconnect metal lines or traces of the FISIP and / or SISIP of the interposer board used for the logic driver may include: an interconnect mesh or structure of interconnect metal lines or traces of the FISIP and / or SISIP of the logic driver, for connecting or coupling to the transistors, FISCs, SISCs and / or micro copper pads, copper pillars or bumps (wherein connected or coupled via copper pillars or solder bumps on or below the BISCSP of the first FPGA IC chip in a first standard commercial FPGA / HBM CSP package structure in the logic driver), and connecting or coupling to a second FPGA in a second standard commercial FPGA / HBM CSP package structure in the same logic driver. The transistors, FISCs, SISCs and / or micro copper pads, copper pillars or bumps of the IC chip (wherein they are connected or coupled via copper pillars or solder bumps on or below the BISCSP of the TPVCs, BISCSP, or second FPGA / HBM CSP package structure), the interconnection network or structure of the interconnection metal lines or traces in the FISIP and / or SISI can connect external circuits to logic drivers via TSVs in the substrate of the interposer, the interconnection network or structure of the interconnection metal lines or traces in the FISIP and / or SISI can be a connection network or structure for signal connection, or a connection for power supply or ground reference: (b) FISIP and / or SISI including logic drivers The interconnection network or structure of the interconnection metal lines or traces of P is connected to a plurality of miniature copper pillars or bumps in the IC chip or CSP package structure in the logic driver. The interconnection network or structure of the interconnection metal lines or traces of FISIP and / or SISIP can connect external circuits to the logic driver via TSVs in the substrate of the interposer. The interconnection network or structure of the interconnection metal lines or traces in FISIP and / or SISIP can be a connection network or structure for signal connection or connection for power supply or ground reference.(c) Interconnection metal lines or traces of FISIP and / or SISIP including a logic driver, used to connect external circuitry to the logic driver via TSVs in the substrate of an interposer, wherein the interconnection metal lines or traces in the FISIP and / or SISIP are for signal interconnection networks or structures, or for power supply or ground reference connections. In this case, one or more TSVs in the substrate of the interposer may be connected to the I / O circuitry of a dedicated I / O chip of the logic driver. The I / O circuitry in this case may be a large I / O circuitry, such as a bidirectional I / O (or tridirectional) pad. The I / O circuitry includes an ESD circuitry, a receiver, and a driver, and has input or output capacitance that may be between 2 pF and 100 pF, 2 pF and 50 pF, 2 pF and 30 pF, 2 pF and 20 pF, 2 pF and 15 pF, 2 pF and 10 pF, or 2 pF and 5 pF, or greater than 2 pF. pF, 10 pF, 15 pF, or 20 pF; (d) interconnection lines or traces of the FISIP and / or SISIP of the logic driver for connecting or coupling to the transistors, FISCs, SISCs, and / or micro copper pads, copper pillars, or bumps (wherein connected or coupled via TPVCs, BISCSPs, or copper pillars or solder bumps on or below the BISCSP of the first FPGA / HBM CSP package structure) of the first FPGA / HBM CSP package structure, and connecting or coupling to the transistors, FISCs, SISCs, and / or micro copper pads, copper pillars, or bumps (wherein connected or coupled via TPVCs, BISCSPs, or copper pillars or solder bumps on or below the BISCSP of the first FPGA / HBM CSP package structure) of the second FPGA IC chip in the logic driver. The copper pillars or solder bumps on or below the BISCSP of the CSP package structure are connected or coupled, but no external circuitry or components are connected to the logic driver. That is, there is no interconnection network or structure of metal lines or interconnects between TSVs and FISIP or SISIP in the substrate of the intermediate carrier of the logic driver. In this case, the interconnection network or structure of metal lines or interconnects in FISIP and SISIP can be connected or coupled to the off-chip I / O circuits of the first and second standard commercial FPGA / HBM CSP packages in the logic driver. Each I / O circuit in this case can be a small I / O circuit, such as a bidirectional I / O (or tridirectional) pad. The I / O circuit includes an ESD circuit, a receiver and a driver, and has an input capacitance or output capacitance that is between 0.05pF and 2pF or between 0.05pF and 1pF, or less than 2pF or 1pF.(e) An interconnect network or structure of interconnect metal lines or traces of the FISIP and / or SISIP of the logic driver is used to connect or couple to micro metal pillars or bumps in an IC chip or CSP package structure of the logic driver, but does not connect external circuitry or components to the logic driver. That is, the TSV in the substrate of the interposer in the logic driver is not connected to the interconnect network or structure of interconnect metal lines or traces of the FISIP and / or SISIP. In this case, the interconnect network or structure of interconnect metal lines or traces of the FISIP and / or SISIP can be connected or coupled to the transistors, FISCs, SISCs and / or micro copper pillars or bumps of the FPGA IC chip in the FPGA / HBM CSP package structure of the logic driver (connected via copper pillars or solder bumps on or below the BISCSP of TPVCs, BISCSP and FPGA / HBM CSP package structure), but not via any I / O circuitry of the FPGA IC chip.

[0119] (4) Forming metal bumps or metal pillars (e.g., copper pillars or solder bumps) on the bottom surface exposed by the plurality of TSVs, the copper pillars or solder bumps being disposed on the front (bottom) of the logic driver package having a ball-grid array (BGA) layout, wherein the solder bumps in the peripheral area are used for signal I / Os, while the power / ground (P / G) I / Os are near the center area, the signal bumps in the peripheral area may form a ring (circle) area near the logic driver package boundary, for example, 1 ring, 2 rings, 3 rings, 4 rings, 5 rings or 6 rings, the spacing of the plurality of metal pillars or bumps for signal I / Os functions in the ring area may be smaller than the spacing of the power / ground (P / G) I / Os near the center area.

[0120] (5) Cutting a completed wafer or panel, including separating or cutting it by means of a material or structure between two adjacent logic drivers, the material (e.g., a polymer) filling the gap or space between the wafers (or CSP package structures) of the two adjacent logic drivers, and separating or cutting it into individual logic driver units.

[0121] Another example of the present invention provides a standard commercial COIP multi-chip package logic driver. This standard commercial COIP logic driver can be a square or rectangle with a certain width, length and thickness. An industry standard can set the diameter (size) or shape of the logic driver. For example, the standard shape of the COIP multi-chip package logic driver can be a square with a width greater than or equal to 4 mm, 7 mm, 10 mm, 12 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm or 40 mm, and a thickness greater than or equal to 0.03 mm, 0.05 mm, 0.1 mm, 0.3 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm or 5 mm. Alternatively, the standard shape of a COIP-multichip packaged logic driver can be rectangular, with a width greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm, or 40mm, a length greater than or equal to 3mm, 5mm, 7mm, 10mm, 12mm, 15mm, 20mm, 25mm, 30mm, 35mm, 40mm, 45mm, or 50mm, and a thickness greater than or equal to 0.03mm, 0.05mm, 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm, or 5mm. In addition, the metal bumps or pillars on the interposer within the logic driver can be of standard size, such as an MxN array area, with a standard spacing or space between two adjacent metal bumps or pillars, and each metal bump or pillar is also located in a standard position.

[0122] The logic driver formed by COIP multi-chip package may further include TPVs and BISDs, both of which are similar to the TPVs or BISDs in the FOIT logic driver disclosed above. When forming the interposer, the TPVs are formed on the SISIP of the interposer (or on the FISIP, when the SISIP is omitted). The functions and descriptions of the TPVs or BISDs of the COIP logic driver are the same as those of the TPVs or BISDs in the FOIT logic driver.

[0123] All descriptions, functions and purposes of the structure and design disclosed above in the FOIT logic driver can be applied to the corresponding structure and design in the COIP logic driver.

[0124] Another aspect of the present invention provides the use of an Interconnect Substrate (IS) to form a logic driver in a Chip-On-Interconnection-Substrate (COIS) package, wherein the IS includes an interconnect structure of a PCB board or BGA substrate and embedded fine-line interconnect bridges (FIBs) on a silicon substrate. The FIBs use high-speed, high-density interconnects between multiple IC chips or multiple CSP packages on the IS substrate. The FIBs include first interconnect structure on the substrates of FIBs (FISIB) and / or second interconnect structure on the substrates of FIBs (SISIB). The FISIBs are formed via the copper-embedded process of the FISC process for forming FPGA IC chips disclosed above and the FPGA process disclosed above. The IC chip's SISC is formed by a raised copper plating process. The disclosure, manufacturing steps, description, and features of the FISIB used in the COIP logic driver are the disclosure and description of the aforementioned interposer substrate's FISIP. The disclosure, manufacturing steps, description, and features of the SISIB used in the COIP logic driver are the disclosure and description of the aforementioned interposer substrate's SISIP. Then, the FIBs are embedded in the IS, which is formed by a PCB or BGA process, for example, by a semi-additive copper process using a laminated dielectric insulating layer and copper foil. The dielectric insulating layer may include FR4 (containing epoxy resin or) or bismalleimide-triazine resin (BT resin).

[0125] COIS packaging is similar to COIP packaging, except that IS replaces the interposer substrate. The interconnection structure of the IS includes the interconnection line structure of the PCB substrate or BGA substrate and FIB embedded in the IS. The FIB includes FISIB and / or SISIB. The purpose and function of the interconnection line structure of the IS are the same as those of the interconnection line structure of the interposer substrate (FISIP and / or SISIP). The purpose and function of the interconnection line structure of the IS are also the same as those of the interconnection line structure of the TISD disclosed above in the FOIT logic driver. The IC chip or package can be assembled, bonded or packaged on the IS. The IC chip or package, as disclosed above, includes: standard commercial DRAM IC chips or FPGA / HBM CSP packages, dedicated control chips, dedicated I / O chips, dedicated control chips and dedicated I / O chips, IAC, DCIAC, DCDI / OIAC chips and / or computing IC chips and / or computing IC chips, such as CPU chips, GPU chips, DSP chips, TPU chips, APU chips or AI chips.

[0126] The logic driver is formed via a COIS multi-chip package, which may further include TPVs and BISDs similar to those in a COIP logic driver or a FOIT logic driver. In forming the IS, the TPVs are formed on or above the IS. The description and function of the TPVs and BISDs of this COIS logic driver are the same as those of the TPVs or BISDs in a COIP logic driver or a FOIT logic driver.

[0127] All descriptions, functions and purposes of the structure and design disclosed above in the COIP logic driver or FOIT logic driver can be applied to the corresponding structure and design in the COIS structure.

[0128] Another aspect of the present invention provides a logic driver having a wafer-level package (CSP) structure, the CSP including a processor, a computing or logic IC chip and an HBM IC chip or HBM SCSPs, the CSP being similar to FPGA / HBM CSPs except that other processor, computing or logic IC chips are used to replace the FPGA IC chip in the CSP package structure. The other processor, computing or logic IC chip in the CSP can be a CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip or AI chip, wherein the CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip or AI chip includes the TPVCs and copper pads, copper bumps or protrusions used in the FPGA IC chip, wherein the height of the TPVCs is greater than the copper pads, copper pillars or protrusions by 20 micrometers or 50 micrometers. Alternatively, the CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip, or AI chip includes TPVCs and copper pads exposed by openings in the top insulating dielectric layer of the SISC or FISC. The CSP package structure in the logic driver can be a CPU / HBM CSP package structure, GPU / HBM CSP package structure, TPU / HBM CSP package structure, APU / HBM CSP package structure, ASIC / HBM CSP package structure, or AI / HBM CSP package structure. The method for forming the CPU / HBM CSP package structure, GPU / HBM CSP package structure, TPU / HBM CSP package structure, APU / HBM CSP package structure, ASIC / HBM CSP package structure, or AI / HBM CSP package structure is the same as or similar to the method for forming FPGA / HBM CSPs package structures described above. The method for forming the CPU / HBM CSP package structure, GPU / HBM CSP package structure, TPU / HBM CSP package structure, APU / HBM CSP package structure, ASIC / HBM CSP package structure, or AI / HBM package structure is the same as or similar to the method for forming FPGA / HBM CSPs package structures described above. The method for forming a logic driver with a CSP package structure is the same as or similar to the method described above for forming a logic driver with an FPGA / HBM CSP package structure.

[0129] In another aspect, the present invention provides a logic driver having a chip-level package (CSP) structure, the CSP including a processor, a computing or logic IC chip and an HBM IC chip or HBM SCSP, the CSP being similar to FPGA / HBM CSPs, except that (i) the first IC chip includes other processors, computing or logic IC chips as FPGA IC chips in the FPGA / HBM CSP package structure; and (ii) a second IC chip or a package including a processor, computing or logic IC chip for use in the FPGA / HBM CSP package structure as an HBM IC chip or HBM SCSP package, the first IC chip being an FPGA IC chip, CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip or AI chip, wherein the FPGA IC chip, CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip or AI chip includes the above-mentioned FPGA used in the FPGA / HBM CSP package structure. TPVCs and copper pads, copper bumps or protrusions in IC chips, wherein the height of the TPVCs is 20 micrometers or 50 micrometers greater than the copper pads, copper pillars or protrusions.Alternatively, the FPGA IC chip, CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip, or AI chip includes TPVCs and copper pads exposed by openings in the top insulating dielectric layer of the SISC or FISC. The second IC chip or package structure can be an FPGA IC chip, CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip, AI chip, dedicated I / O chip, dedicated control chip, dedicated control and I / O chip, IAC chip, and / or DPIIC chip, wherein the FPGA IC chip, CPU chip, GPU chip, DSP chip, TPU chip, APU chip, ASIC chip, AI chip, dedicated I / O chip, dedicated control chip, dedicated control and I / O chip, IAC chip, and / or DPIIC chip may selectively have TSVs in their silicon substrate (in the HBM SCSP package structure). In IC chips, the dedicated I / O chip, dedicated control chip, dedicated control and I / O chip, IAC chip and / or DPIIC chip, as disclosed above, the CSP package structure in the logic driver can be an FPGA / CLC CSP package structure, a CPU / CLC CSP package structure, a GPU / CLC CSP package structure, a TPU / CLC CSP package structure, an APU / CLC CSP package structure, an ASIC / CLC CSP package structure, or an AI / CLC CSP package structure, where "CLC" is an abbreviation for "other processor, computing or logic IC chip". The method of forming the FPGA / CLC CSP package structure, CPU / CLC CSP package structure, GPU / CLC CSP package structure, TPU / CLC CSP package structure, APU / CLC CSP package structure, ASIC / CLC CSP package structure, or AI / CLC CSP package structure is the same as or similar to the method of forming the FPGA / HBM CSPs package structure described above. The method of forming the FPGA / CLC CSP package structure, CPU / CLC CSP package structure, GPU / CLC CSP package structure, and GPU / CLC CSP package structure is the same as or similar to the method of forming the FPGA / HBM CSPs package structure described above. The method for constructing logic drivers for CSP, TPU / CLC, APU / CLC, ASIC / CLC, or AI / CLC CSP packages is the same as or similar to the method described above for constructing logic drivers with FPGA / HBM CSP packages.

[0130] Another aspect of the present invention provides a logic driver in a 3D multi-chip package format, the logic driver comprising a plurality of IC chips and / or packages, wherein the plurality of IC chips and / or packages may include an FPGA IC chip, a CPU chip, a GPU chip, a DSP chip, a TPU chip, an APU chip, an ASIC chip, an AI chip, a NAND flash memory chip or package, an HBM chip or package, or an HBM SCSP packages, dedicated I / O chips, dedicated control chips, dedicated control and I / O chips, IAC chips, and / or DPIIC chips, the plurality of IC chips and / or packages may be packaged, bonded, connected, or coupled in the xy direction to (i) TISD or FOISD in a FOIT package structure, (ii) SISIP or FISIP in a COIP package structure, (iii) the interconnection line structure of IS in a COIS package, (iv) the interconnection line structure of a BGA substrate, or (v) the interconnection line structure of a PCB board. The plurality of IC chips and / or packages may be packaged, bonded, connected, or coupled in the z direction to each other stacked CSP packages, such as FPGA / HBM CSP packages, wherein the vertical interconnection lines are coupled or connected via TPVs on the bottom IC chip in the CSP package and / or TSVs in the silicon substrate of the IC chip on or above the bottom IC chip.

[0131] All descriptions, functions and purposes of the structure and design disclosed above in the COIP logic driver can be applied to the corresponding structure and design in the COIS structure.

[0132] These and other components, steps, features, benefits and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments, accompanying drawings and the claims.

[0133] The configuration of the invention will be more fully understood when the following description is read in conjunction with the accompanying drawings, which are to be regarded as illustrative rather than restrictive. The drawings are not necessarily drawn to scale, but rather to emphasize the principles of the invention.

Implementation Method

[0134] Description of Static Random Access Memory (SRAM) Units

[0135] (1) The first type of volatile memory unit

[0136] A circuit diagram of a first type of volatile memory cell according to an embodiment of the present invention is disclosed. Referring to Figure 1A, the first type of volatile memory cell 398 has a memory cell 446, that is, a static random access memory (SRAM) cell, which may have a memory cell 446 composed of four data latch transistors 447 and 448, that is, two pairs of P-type MOS transistors 447 and N-type MOS transistors 448 each have a drain terminal coupled to each other, a gate terminal coupled to each other, and a source terminal coupled to the power supply voltage Vcc and the ground reference voltage Vss. The gate terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair are coupled to the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair, serving as the first output point of memory cell 446 for a first data output Out1. The gate terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair are coupled to the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair, serving as the second output point of memory cell 446 for a second data output Out2.

[0137] Referring to Figure 1A, the first type of volatile memory cell 398 may further include two switching or transfer (write) transistors 449 (e.g., N-type or P-type MOS transistors), wherein the gate of the first transistor is connected to the word line 451, one terminal of its channel is coupled to the bit line 452, and the other terminal of the channel is coupled to the drain terminal of the P-type and N-type MOS transistors 447 and 448 in the left pair and the gate terminal of the P-type and N-type MOS transistors 447 and 448 in the right pair; the gate of the second transistor is coupled to the word line 451, one end of its channel is coupled to a bit bar 453, and the other end of the channel is coupled to the drain terminal of the P-type and N-type MOS transistors 447 and 448 in the right pair and the gate terminal of the P-type and N-type MOS transistors 447 and 448 in the left pair. The logic level on bit line 452 is opposite to the logic level on bit line 453. Switch (or transistor) 449 can be considered as a programmable transistor used to write programming code or data into the storage nodes of the four data latch transistors 447 and 448 (i.e., at the drain and gate terminals of the four data latch transistors 447 and 448). The word line 451 can control the switch (or transistor) 449 to open the connection between the word line 451 and the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair and the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair via the channel of the first switch (or transistor) 449. This will reload the logic level of the conductive line between the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair and the logic level of the conductive line between the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair onto the logic level of the word line 452. Furthermore, bit line 453 can be coupled via the channel of the second switch (or transistor) 449 to the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair and the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair, thereby reloading the logic level of the conductive line between the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair and the logic level of the conductive line between the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair onto the logic level of bit line 453.Therefore, the logic level on bit line 452 can be recorded or latched in the conductive lines between the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair and between the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair, and the logic level on bit line 453 can be recorded or latched in the conductive lines between the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair and between the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair.

[0138] (2) Type II volatile memory units

[0139] Figure 1B discloses a circuit diagram of a second type of volatile memory cell according to an embodiment of the present invention. Referring to Figure 1B, the second type of volatile memory cell 398 has a memory cell 446, that is, a static random access memory (SRAM) cell, which may have a memory cell 446 as shown in Figure 1A. The second type of volatile memory cell 398 may further have a switching or transfer (write) transistor 449 (e.g., an N-type or P-type MOS transistor), whose gate terminal is coupled to a word line 451 and a channel, one terminal of which is coupled to a bit line 452, and the other terminal of which is coupled to the drain terminal of the P-type and N-type MOS transistors 447 and 448 in the left pair and the gate terminal of the P-type and N-type MOS transistors 447 and 448 in the right pair. The switch (or transistor) 449 can be considered a programming transistor used to write programming code or data into the storage nodes of the four data latch transistors 447 and 448 (i.e., at the drain and gate terminals of the four data latch transistors 447 and 448). The switch (or transistor) 449 can be controlled via word line 451 to open the connection from word line 451 to the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair and the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair via the channel of the first switch (or transistor) 449, thereby reloading the logic level of the conductive line between the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair and the logic level of the conductive line between the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair onto the logic level of word line 452. Therefore, the logic level on bit line 452 can be recorded or latched in the conductive lines between the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair and in the conductive lines between the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair. The logic level opposite to the logic level on bit line 452 can be recorded or latched in the conductive lines between the gate terminals of the P-type and N-type MOS transistors 447 and 448 in the left pair and in the conductive lines between the drain terminals of the P-type and N-type MOS transistors 447 and 448 in the right pair.

[0140] Explanation of the pass / fail switch

[0141] (1) Type I pass / fail switch

[0142] Figure 2A is a circuit diagram of a first type pass / fail switch according to an embodiment of this application. Referring to Figure 2A, the first type pass / fail switch 258 includes an N-type metal-oxide-semiconductor (MOS) transistor 222 and a P-type MOS transistor 223. The N-type MOS transistor 222 and the P-type MOS transistor 223 are connected in parallel and coupled to each other. Each of the N-type MOS transistor 222 and the P-type MOS transistor 223 of the first type pass / fail switch 258 can be configured to form a channel. One end of the channel is located at (coupled to) node N21 of the pass / fail switch 258, and the other end of the channel is located at (coupled to) node N22 of the pass / fail switch 258. Therefore, the connection between node N21 and node N22 can be set to "on" or "off" by the first type pass / fail switch 258. The first type pass / fail switch 258 includes an inverter 533, whose data input at its input point is coupled to the gate and node SC-3 of the N-type MOS transistor 222, and whose output point is coupled to the gate of the P-type MOS transistor 223. The inverter 533 is adapted to invert its input to form its output.

[0143] (2) Second type of pass / fail switch

[0144] Figure 2B is a circuit diagram of a second type pass / no-pass switch according to an embodiment of this application. Referring to Figure 2B, the second type pass / no-pass switch 258 can be a multi-stage tri-state buffer 292 or a switching buffer. In each stage, there is a pair of P-type MOS transistors 293 and N-type MOS transistors 294, whose drain systems are coupled together, and whose sources are respectively connected to the power supply terminal Vcc and the ground terminal Vss. In this embodiment, the multi-stage tri-state buffer 292 is a two-stage tri-state buffer 292, that is, a two-stage inverter, consisting of a first stage and a second stage, each having a pair of P-type MOS transistors 293 and N-type MOS transistors 294. The gate terminals of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the first stage are located at node N21 of the pass / no-pass switch 258. The drains of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the first stage are coupled to the gates of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the second stage (i.e., the output stage), and the drains of the pair of P-type MOS transistors 293 and N-type MOS transistors 294 in the second stage are coupled to the other nodes N22 of the pass / fail switch 258.

[0145] Please refer to Figure 2B. The second type of pass / fail switch 258 also includes a switching mechanism that enables or disables the multi-stage tri-state buffer 292. The switching mechanism includes: (1) controlling the source terminal of the P-type MOS transistor 295 to be coupled to the power supply terminal (Vcc), and its drain terminal to be coupled to the source terminal of the first and second stage P-type MOS transistors 293; (2) controlling the N-type The source terminal of MOS transistor 296 is coupled to the ground reference voltage (Vss), and its drain terminal is coupled to the source terminal of the first and second stage N-type MOS transistor 294; and (3) inverter 297 is used to invert a data input SC-4 (located at the input point of inverter 297) of the pass / fail switch 258 coupled to the gate terminal of N-type MOS transistor 296, so as to serve as the data output of inverter 297 (located at the output point of inverter 297) coupled to the gate terminal of P-type MOS transistor 295.

[0146] For example, as shown in Figure 2B, when the pass / de-pass switch 258 is turned on by a data input SC-4 with logic level "1", the pass / de-pass switch 258 can amplify its data input and transmit its data input from the input point of node N21 to the output point of node N22 as data output. When the pass / de-pass switch 258 is turned off by a data input SC-4 with logic level "0", the pass / de-pass switch 258 may neither transmit data from itself nor pass data through its switch 258, nor transmit data from its node N22 to its node N21.

[0147] (3) Type III pass / fail switch

[0148] Figure 2C is a circuit diagram of a fifth type pass / fail switch according to an embodiment of this application. For the components indicated by the same reference numerals in Figures 2B and 2C, the component shown in Figure 2C can be referred to the description of the component in Figure 2B. Referring to Figure 2C, the fifth type pass / fail switch 258 may include a pair of multi-stage tri-state buffers 292 or switch buffers as shown in Figure 2B. The gate terminals of the P-type and N-type MOS transistors 293 and 294 of the first stage in the multi-stage tri-state buffer 292 on the left (located at node N21 of the pass / fail switch 258) are coupled to the drain terminals of the P-type and N-type MOS transistors 293 and 294 of the second stage (i.e., the output stage) in the multi-stage tri-state buffer 292 on the right. The gate terminals of the P-type and N-type MOS transistors 293 and 294 of the first stage in the multi-stage tri-state buffer 292 located on the right (located at node N22 of the pass / de-pass switch 258) are coupled to the drain terminals of the P-type and N-type MOS transistors 293 and 294 of the second stage (i.e., the output stage) in the multi-stage tri-state buffer 292 located on the left. For the multi-stage tri-state buffer 292 located on the left, its inverter 297 is used to invert a data input SC-5 (located at the input point of inverter 297) of the pass / de-pass switch 258 coupled to the gate terminal of the N-type MOS transistor 296, so as to serve as the data output of inverter 297 (located at the output point of inverter 297) coupled to the gate terminal of the P-type MOS transistor 295. For the multi-stage tri-state buffer 292 located on the right, its inverter 297 is used to invert a data input SC-6 (located at the input point of inverter 297) of the pass / fail switch 258 coupled to the gate of the N-type MOS transistor 296, so as to serve as the data output of inverter 297 (located at the output point of inverter 297) coupled to the gate of the P-type MOS transistor 295.

[0149] For example, please refer to Figure 2C. When the logic level (value) of a data input SC-5 of the pass / delete switch 258 is "1", the multi-level tri-state buffer 292 on the left side will be turned on, and when the logic level (value) of a data input SC-6 of the pass / delete switch 258 is "0", the multi-level tri-state buffer 292 on the right side will be turned off. The third type pass / delete switch 258 can amplify its data input and transmit its data from the input point at node N21 to the input point at node N22. At the output point at point N22, when the logic level (value) of one data input SC-5 of the pass / delete switch 258 is "0", the multi-level tri-state buffer 292 on the left side will be turned off, and when the logic level (value) of one data input SC-6 of the pass / delete switch 258 is "1", the multi-level tri-state buffer 292 on the right side will be turned on. This third type of pass / delete switch 258 can amplify its data input and transmit its data from the input point at node N22 to the output point at node N21. The pass / fail switch 258, used as a data output, disables the multi-level tri-state buffer 292 on the left when the logic level (value) of one data input SC-5 is "0". The third type of pass / fail switch 258 cannot transfer data from its node N21 to its node N22, nor from its node N22 to its node N21. When the logic level (value) of one data input SC-5 of the pass / fail switch 258 is "1", the multi-level tri-state buffer 292 on the left is enabled. When the logic level (value) of a data input SC-6 of the pass / delete switch 258 is "1", the multi-level tri-state buffer 292 on the right side will be turned on. The third type of pass / delete switch 258 can amplify its data input and transfer its data input from the input point at its node N21 to the output point at its node N22 as its data output, or amplify its data input and make it pass the data input from the input point at its node N22 to the output point at its node N21 as its data output.

[0150] Explanation of a crosspoint switch consisting of a pass / no pass switch.

[0151] (1) First type of crosspoint switch

[0152] Figure 3A is a circuit diagram of a first-type crosspoint switch consisting of four pass / no-pass switches according to an embodiment of this application. Referring to Figure 3A, the four pass / no-pass switches 258 can form a first-type crosspoint switch 379, wherein each pass / no-pass switch 258 can be any of the first to third types of pass / no-pass switches 258 as shown in Figures 2A to 2C. The first-type crosspoint switch 379 can include four contacts N23 to N26, each of the four contacts N23 to N26 being coupled to the other of the four contacts N23 to N26 through two of the six pass / no-pass switches 258. The center node of the first type crosspoint switch 379 is adapted to be coupled to its four contacts N23 to N26 via its four pass / no pass switches 258 respectively. One of the nodes N21 and N22 of each type of pass / no pass switch 258 is coupled to one of the four contacts N23 to N26, and the other node N21 and N22 is coupled to the center node of the first type crosspoint switch 379. For example, the first type crosspoint switch 379 can be turned on to allow data to be transmitted from its node N23 to its node N24 via its left and upper pass / no pass switches 258, coupled to its contact N25 via its upper and lower pass / no pass switches 258, and / or coupled to its contact N26 via its upper and right pass / no pass switches 258.

[0153] (2) Type II Crosspoint Switch

[0154] Figure 3B is a circuit diagram of a second type crosspoint switch consisting of six pass / no-pass switches according to an embodiment of this application. Referring to Figure 3B, the six pass / no-pass switches 258 can form a first type crosspoint switch 379, wherein each pass / no-pass switch 258 can be any of the first to third type pass / no-pass switches as shown in Figures 2A to 2C. The second type crosspoint switch 379 can include four contacts N23 to N26, each of which can be coupled to the other of the four contacts N23 to N26 through one of the six pass / no-pass switches 258. One of the nodes N21 and N22 of each pass / no-pass switch 258 is coupled to one of the four contacts N23 to N26, and the other of its nodes N21 and N22 is coupled to the other of the four contacts N23 to N26. For example, the second type crosspoint switch 379 can be turned on to allow data to be transmitted from its node N23 to its node N24 via the first of its six pass / no pass switches 258, the first of which is located between the contacts N23 and N24, and / or the contact N23 of the second type crosspoint switch 379 is adapted to be coupled to the contact N25 via the second of its six pass / no pass switches 258, the second of which is located between the contacts N23 and N25, and / or the contact N23 of the second type crosspoint switch 379 is adapted to be coupled to the contact N26 via the third of its six pass / no pass switches 258, the third of which is located between the contacts N23 and N26.

[0155] Multiplexers (MUXER) Description

[0156] Figure 4 discloses a circuit diagram of a multiplexer according to an embodiment of the present invention. Referring to Figure 4, the multiplexer (MUXER) 211 may have two input points of a first group arranged in parallel for a first input data group (e.g., A0 and A1), and four input points of a second group arranged in parallel for a second input data group (e.g., D0, D1, D2, and D3). The multiplexer (MUXER) 211 may select a data input (e.g., D0, D1, D2, or D3) from its second input data group located at the second input point, based on its first input data group (i.e., A0 and A1) located at the first input point of the first group, as the data output Dout at its output point.

[0157] Referring to Figure 4, the multiplexer 211 may include multiple stages of switching buffers (e.g., two stages of switching buffers 217 and 218) coupled to each other or sequentially coupled. To illustrate in more detail, the multiplexer 211 may include four pairs of parallel switching buffers 217 in a first stage (i.e., the input stage), each switching buffer 217 having a first input point for a first data associated with data A1 in a first input data group of the multiplexer 211, and a second input point for a second data associated with data (D0, D1, D2, or D3) in a second input data group of the multiplexer 211. Each of the four switching buffers 217 in the first stage can be turned on or off according to the first data input at its first input point, and its second data input extends from its second input point to its output point. Multiplexers 211 may include an inverter 207 having an input point for data A1 of a first input data group of multiplexers 211, wherein the inverter 207 is used to invert the data A1 of the first input data group of multiplexers 211 as a data output at an output point of the inverter 207. One of the two switching buffers 217 in each pair in the first stage can, based on first data input coupled at its first input point to one of the input and output points of the inverter 207, enable a second data input from its second input point to its output point, as a data output of the pair of switching buffers 217 in the first stage; and can, based on first data input coupled at its first input point to the other of the input and output points of the inverter 207, disable the other switching buffer 217 in each pair in the first stage, preventing the second data from passing from its second input point to its output point. The output points of the two switching buffers 217 in each pair in the first stage may be coupled to each other.For example, in the first stage, the first input point of the higher (top) of a pair of switch buffers 217 located at a higher position is coupled to the output point of the inverter 207 and to the second input point of the second data associated with data D0 of the second input data group of the input multiplexer 211; the first input point of the lower (bottom) of a pair of switch buffers 217 located at a higher position in the first stage is coupled to the output point of the inverter 207 and to the second input point of the second data associated with data D1 of the second input data group of the multiplexer 211. The input point can activate the higher of the two switch buffers 217 in the first stage, which is at the highest position, based on the first data input at its first input point, so that the second data input can pass from its second input point to its output point, which serves as the data output of the pair of switch buffers 217 at the highest position in the first stage; and can deactivate the lower of the two switch buffers 217 in the first stage, which is at the highest position, based on the first data input at its first input point, so that the second data input cannot pass from its second input point to its output point. Therefore, each of the two pairs of switch buffers 217 in the first stage can be switched based on its two first input points (which are respectively coupled to the input and output points of the inverter 207) to input one of its second data from one of its two second input points to its output point, wherein the output point is coupled to one of the second input points of one of the switch buffers 218 in the second stage (i.e., the output stage), as the data output of each of the two pairs of switch buffers 217 in the first stage.

[0158] Referring to Figure 4, the multiplexer 211 may include a pair of parallel dual-switch buffers 218 in the second stage (i.e., the output stage). Each switch buffer 218 has a first input point of a first data associated with data A0 of a first input data group to the multiplexer 211, and a second input point of a second data associated with the data output of one of the two pairs of switch buffers 217 in the first stage. In the second stage (i.e., the output stage), each of the two pairs of switch buffers 218 can be turned on or off according to the first data input at its first input point, and its second data input extends from its second input point to its output point. The multiplexer 211 may include an inverter 208 having an input point of data A0 of the first input data group of the multiplexer 211, wherein the inverter 208 is used to invert the data A0 of the first input data group of the multiplexer 211 as the data output at its output point. In the second stage (i.e., the output stage), one of the two switching buffers 218 in this pair can, based on first data input coupled at its first input point to one of the input and output points of the inverter 208, enable the second data input from its second input point to its output point, serving as a data output for the pair of switching buffers 218 in the second stage; and can, based on first data input coupled at its first input point to the other of the input and output points of the inverter 208, disable the other switching buffer 218 in the pair, preventing the second data from passing from its second input point to its output point. The output points of the two switching buffers 218 in this pair in the second stage (i.e., the output stage) can be coupled to each other. For example, in the second stage (i.e., the output stage), the first input point of the higher (top) of the pair of switch buffers 218 located at the top is coupled to the output point of the inverter 208, and to its second input point associated with the second data input to the data output of the top of the two pairs of switch buffers 217 in the first stage; in the second stage (i.e., the output stage), the first input point of the lower (bottom) of the pair of switch buffers 218 is coupled to the output point of the inverter 208, and to its second input point associated with the second data output of the bottom of the two pairs of switch buffers 218 in the first stage.The higher of the two switching buffers 218 in the second stage (i.e., the output stage) can be turned on based on the first data input at its first input point, so that the second data input passes from its second input point to its output point, which serves as the data output of the pair of switching buffers 218 in the second stage. Conversely, the lower of the two switching buffers 218 in the second stage (i.e., the output stage) can be turned off based on the first data input at its first input point, so that the second data input cannot pass from its second input point to its output point. Therefore, the pair of switching buffers 218 in the second stage (i.e., the output stage) can be switched based on their two first input points (which are respectively coupled to the input and output points of the inverter 207) to input one of their second data from one of their two second input points to their output point, which serves as the data output of the pair of switching buffers 218 in the second stage (i.e., the output stage).

[0159] Referring to Figure 4, the pass / no-pass switch or switch buffer 292 of the second type shown in Figure 2B can be coupled to the output point of the pair of switch buffers 218 of the multiplexer 211. The pass / no-pass switch or switch buffer 292 can be coupled to the output point of the pair of switch buffers 218 at its input point at node N21 in the last stage (e.g., in this case, the second stage or output stage). For components represented by the same component designations as shown in Figures 2B to 4, the description / specification of the component designations shown in Figure 4 can be referred to the description / specification of the component designations shown in Figure 2B. Thus, the multiplexer 211 shown in Figure 4 can select a data input from its second set of four input points (e.g., D0, D1, D2, and D3) as its data output Dout at its output point, wherein the selection is based on its first set of two input points (e.g., A0 and A1). The second type pass / no pass switch 292 can amplify its data input associated with the data output Dout of the pair of switch buffers 218 of the multiplexer 211, as its data output located at its node N22 (output point).

[0160] Large I / O Circuit Description

[0161] Figure 5A discloses a circuit diagram of a large I / O circuit according to an embodiment of the present invention. Referring to Figure 5A, a semiconductor wafer may include a plurality of I / O connection pads 272, each I / O connection pad 272 being coupled to its large ESD protection circuit or device 273, its large driver 274, and its large receiver 275. The large driver 274, the large receiver 275, and the large ESD protection circuit or device 273 may constitute a large I / O circuit 341. The large ESD protection circuit or device 273 may include a diode 282, the cathode of which is coupled to a power supply voltage Vcc, the anode of which is coupled to a node 281, and the diode 282 having a cathode coupled to node 281 and an anode coupled to a ground reference voltage Vss, the node 281 being coupled to one of the I / O connection pads 272.

[0162] Referring to Figure 5A, the large driver 274 may have a first input point for enabling the large driver 274 with a first data input L_Enable and a second input point for a second data input L_Data_out, and may be configured to amplify or drive the second data input L_Data_out as its data output at the output point of node 281, for transmission to circuitry outside the semiconductor wafer via the I / O connection pad 272. The large driver 274 may include a P-N type MOS transistor 285 and an N type MOS transistor 286, each having a drain terminal coupled to each other at node 281 as its output point, and source terminals coupled to the power supply voltage Vcc and the ground reference voltage Vss, respectively. The large driver 274 may have a NAND gate 287 having data output at the output point of the NAND gate 287 coupled to the gate terminal of the P type MOS transistor 285; and a NOR gate 288 having data output at the output terminal of the P type MOS transistor 285. NOR gate 288 is coupled to the gate of N-type MOS transistor 286. NAND gate 287 may have a first data input at its first input point associated with the data output of inverter 289 at the output point of inverter 289. The output of large driver 274 and a second data input at a second data input associated with the second data input L_Data_out of large driver 274 perform a NAND operation on its first and second data inputs, as its data output coupled to the gate of P-type MOS transistor 285 that outputs it. NOR gate 288 may have a first data input at its first input point associated with the second data input L_Data_out of large driver 274, and a second data input at a second input point associated with the first data input S_Enable. The first data input S_Enable of small driver 374 performs a NOR operation on its first and second data inputs, as its data output at the output point coupled to the gate of N-type MOS transistor 386. Inverter 389 can be used to invert its data input at its input point associated with the first data input S_Enable of the small driver 374, as a data output at its output point coupled to the first input point of the NAND gate 387.

[0163] Referring to Figure 5A, when the large driver 274 has its first data input L_Enable at logic level "1", the data output of the NAND gate 287 is always at logic level "1" to turn off the P-type MOS transistor 285, and the data output of the NOR gate 288 is always at logic level "0" to turn off the N-type MOS transistor 286. Thus, the large driver 274 can be disabled by the following: its first data input L_Enable and the large driver 274 may not transmit the second data input L_Data_out from its second input point to the output point of node 281.

[0164] Referring to Figure 5A, when the large driver 274 has a first data input L_Enable at logic level "0", the large driver 274 can be enabled. At the same time, if the large driver 274 has a second data input L_Data_out at logic level "0", the data outputs of NAND gate 287 and NOR gate 288 are at logic level "1" to turn off P-type MOS transistor 285 and N-type MOS transistor 286. Consequently, the data output of the large driver 274 at node 281 is at logic level "0" to transmit to one of the I / O connection pads 272. If the large driver 274 has a second data input L_Data_out at logic level "1", then the data outputs of NAND gate 287 and NOR gate 288 are at logic level "0" to turn on P-type MOS transistor 285 and turn off N-type MOS transistor 286, thereby causing the data output of the large driver 274 at node 281 to be at logic level "1" for transmission to one of the I / O connection pads 272. Therefore, the large driver 274 can be enabled by its first data input L_Enable to amplify or drive its second data input L_Data_out at its second input point as a data output at node 281 and its output point, for transmission to circuitry outside the semiconductor wafer via one of the I / O connection pads 272.

[0165] Referring to Figure 5A, the large receiver 275 has a first data input L_Inhibit at its first input point and a second data input at its second input point, the second data input being coupled to one of the I / O connection pads 272 to amplify or drive it as its data output L_Data_in via the large receiver 275. The large receiver 275 can be disabled / suppressed via its first data input L_Inhibit generated from its data output L_Data_in (which is associated with its second data input). The large receiver 275 may include a NAND gate 290 and an inverter 291 having a data input at the input point of the inverter 291 associated with a data output of the NAND gate 290. The NAND gate 290 has a first input point for its first data input (associated with a second data input of the large receiver 275) and a second input point for its second data input (associated with the first data input L_Inhibit of the large receiver 275) to perform a NAND operation at its first and second data inputs as a data output at its output point (which is coupled to the input point of its inverter 291), which can be used to invert its data input associated with the data output of the NAND gate 290 as a data output at its output point, and as its data output L_Data_in at the output point of the large receiver 275.

[0166] Referring to Figure 5A, when the logic level of the first data input L_Inhibit of the large receiver 275 is "0", the logic level of the data output of the NAND 290 is always "1", and the logic level of the data output L_Data_in of the large receiver 275 is always "0". Therefore, the large receiver 275 is prohibited from generating its data output L_Data_in associated with its second data input at node 281.

[0167] Referring to Figure 5A, when the large receiver 275 has a first data input L_Inhibit at logic level "1", the large receiver 275 can be activated. Simultaneously, if the large receiver 275 receives second data from an external circuitry on the semiconductor chip at logic level "1" via one of the I / O connection pads 272, the data output bit of the NAND gate 290 is at logic level "0". Furthermore, the data output L_Data_in bit of the large receiver 275 is at logic level "1". If the large receiver 275 receives second data from an external circuitry on the semiconductor chip at logic level "0" via one of the I / O connection pads 272, the data output bit of the NAND gate 290 is at logic level "1". Therefore, the large receiver 275 can be activated via its first data input L_Inhibit signal to amplify or drive second data input from circuitry outside the semiconductor wafer via one of the I / O connection pads 272 as its data output L_Data_in.

[0168] Referring to Figure 5A, the large I / O circuit 274 may provide its output capacitance or drive capability (or load) via a large driver 274, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 3 pF, 5 pF, 10 pF, 15 pF, or 20 pF. Additionally, the large I / O circuit 274 has input capacitance provided via its large receiver 275 and / or large ESD protection circuit 273, for example, between 2 pF and 100 pF, between 2 pF and 50 pF, between 2 pF and 30 pF, between 2 pF and 20 pF, between 2 pF and 15 pF, between 2 pF and 10 pF, or between 2 pF and 5 pF, or greater than 2 pF, 3 pF, 5 pF, 10 pF, 15 pF, or 20 pF. The size of the large ESD protection circuit or device 273 can be between 0.5 pF and 20 pF, between 5 pF and 15 pF, between 0.5 pF and 10 pF, between 0.5 pF and 5 pF, or between 0.5 pF and 2 pF, or greater than 0.5 pF, 1 pF, 2 pF, 3 pF, 5 pF, or 10 pF.

[0169] Small I / O Circuit Description

[0170] Figure 5B discloses a circuit diagram of a small I / O circuit according to an embodiment of the present invention. Referring to Figure 5B, a semiconductor wafer may include a plurality of I / O connection pads 372, each I / O connection pad 372 being coupled to its small ESD protection circuit or device 373, its small driver 374, and its small receiver 375. The small driver 374, the small receiver 375, and the small ESD protection circuit or device 373 may constitute a small I / O circuit 203. The small ESD protection circuit or device 373 may include a diode 382, ​​the cathode of which is coupled to a power supply voltage Vcc, the anode of which is coupled to a node 381, and the diode 383 having a cathode coupled to node 381 and an anode coupled to a ground reference voltage Vss, the node 381 being coupled to one of the I / O connection pads 372.

[0171] Referring to Figure 5B, the miniature driver 374 may have a first input point for enabling the miniature driver 374 with a first data input S_Enable and a second input point for a second data input S_Data_out, and may be configured to amplify or drive the second data input S_Data_out as its data output at the output point of node 381, for transmission to circuitry outside the semiconductor wafer via the I / O connection pad 372. The miniature driver 374 may include a P-N type MOS transistor 385 and an N type MOS transistor 386, each having a drain terminal coupled to each other at node 381 as its output point, and source terminals coupled to the power supply voltage Vcc and the ground reference voltage Vss, respectively. The miniature driver 374 may have a NAND gate 387 having data output at the output point of the NAND gate 387 coupled to the gate terminal of the P type MOS transistor 385; and a NOR gate 388 having data output at the output terminal of the P type MOS transistor 385. NOR gate 388 is coupled to the gate of N-type MOS transistor 386. NAND gate 387 may have a first data input at its first input point associated with the data output of inverter 389 at the output point of inverter 389. The output of miniature driver 374 and a second data input at a second data input associated with the second data input S_Data_out of miniature driver 374 perform a NAND operation on its first and second data inputs, as its data output coupled to the gate of P-type MOS transistor 385 that outputs it. NOR gate 388 may have a first data input at its first input point associated with the second data input S_Data_out of miniature driver 374, and a second data input at a second input point associated with noise. The st data input S_Enable of miniature driver 374 performs a NOR operation on its first and second data inputs, as its data output at the output point coupled to the gate of N-type MOS transistor 386. Inverter 389 can be used to invert its data input at its input point associated with the first data input S_Enable of the small driver 374, as a data output at its output point coupled to the first input point of the NAND gate 387.

[0172] Referring to Figure 5B, when the miniature driver 374 has its first data input S_Enable at logic level "1", the data output of the NAND gate 387 is always at logic level "1" to turn off the P-type MOS transistor 385, and the data output of the NOR gate 388 is always at logic level "0" to turn off the N-type MOS transistor 386. Thus, the miniature driver 374 can be disabled in the following way: its first data input S_Enable and the miniature driver 374 may not transmit the second data input S_Data_out from its second input point to the output point of node 381.

[0173] Referring to Figure 5B, when the miniature driver 374 has a first data input S_Enable at logic level "0", the miniature driver 374 can be enabled. At the same time, if the miniature driver 374 has a second data input S_Data_out at logic level "0", the data outputs of NAND gate 387 and NOR gate 388 are at logic level "1" to turn off P-type MOS transistor 385 and N-type MOS transistor 386. Consequently, the data output of the miniature driver 374 at node 381 is at logic level "0" to transmit to one of the I / O connection pads 372. If the miniature driver 374 has a second data input S_Data_out at logic level "1", then the data outputs of NAND gate 387 and NOR gate 388 are at logic level "0" to turn on P-type MOS transistor 385 and turn off N-type MOS transistor 386, thereby setting the data output of the miniature driver 374 at node 381 to logic level "1" for transmission to one of the I / O pads 372. Therefore, the miniature driver 374 can be enabled by its first data input S_Enable to amplify or drive its second data input S_Data_out at its second input point as a data output at node 381 and its output point, for transmission to circuitry outside the semiconductor wafer via one of the I / O pads 372.

[0174] Referring to Figure 5B, the miniature receiver 375 has a first data input S_Inhibit at its first input point and a second data input at its second input point, the second data input being coupled to one of the I / O connection pads 372 to amplify or drive it as its data output L_Data_in via the miniature receiver 375. The miniature receiver 375 can be disabled / suppressed via its first data input S_Inhibit generated from its data output L_Data_in (which is associated with its second data input). The miniature receiver 375 may include a NAND flash unit 390 and an inverter 391 having a data input at the input point of the inverter 391 associated with a data output of the NAND flash unit 390. The NAND device 390 has a first input point for its first data input (associated with a second data input of the miniature receiver 375) and a second input point for its second data input (associated with the first data input S_Inhibit of the miniature receiver 375) to perform a NAND operation at its first and second data inputs as a data output at its output point (which is coupled to the input point of its inverter 391), which can be used to invert its data input associated with the data output of the NAND device 390 as a data output at its output point, and as its data output L_Data_in at the output point of the miniature receiver 375.

[0175] Referring to Figure 5B, when the logic level of the first data input S_Inhibit of the small receiver 375 is "0", the logic level of the data output of the NAND 290 is always "1", and the logic level of the data output L_Data_in of the small receiver 375 is always "0". Therefore, the small receiver 375 is prohibited from generating its data output L_Data_in associated with its second data input at node 381.

[0176] Referring to Figure 5B, the small receiver 375 can be activated when it has a first data input S_Inhibit at logic level "1". Simultaneously, if the small receiver 375 receives second data from an external circuitry on the semiconductor chip at logic level "1" via one of the I / O pads 372, the data output bit of the NAND flash unit 390 is at logic level "0". Consequently, the data output L_Data_in bit of the small receiver 375 is at logic level "1". If the small receiver 375 receives second data from an external circuitry on the semiconductor chip at logic level "0" via one of the I / O pads 372, the data output bit of the NAND flash unit 390 is at logic level "1". Therefore, the small receiver 375 can be activated via its first data input S_Inhibit signal to amplify or drive second data input from circuitry outside the semiconductor wafer via one of the I / O connection pads 372 as its data output L_Data_in.

[0177] Referring to Figure 5B, the small I / O circuit 203 may provide its output capacitance or driving capability (or load) via a small driver 374, for example, between 0.05 pF and 2 pF, or between 0.1 pF and 1 pF, or less than 2 pF or 1 pF. Additionally, the small I / O circuit 374 has an input capacitance provided via its small receiver 375 and / or small ESD protection circuit 373, for example, between 0.05 pF and 2 pF, or between 0.1 pF and 1 pF, or less than 2 pF or 1 pF.

[0178] Description / Specification of Programmable Logic Blocks

[0179] Figure 6A is a schematic block diagram of a programmable logic unit according to an embodiment of the present invention. Referring to Figure 6A, a programmable logic block (LB) (or element) may include one (or more) programmable logic units (LC) 2014, each programmable logic unit (LC) 2014 being used to perform logical operations on its input data set at its input point. Each programmable logic unit (LC) 2014 may include multiple memory units (i.e., configuration programming memory (CPM) units), each memory unit 2014 being used to store or store one of the result values ​​(or data) of a lookup table (LUT) 210 and a multiplexer 211 having two input points (e.g., A0 and A1) arranged in parallel for a first input data group as shown in Figure 4 and four input points (e.g., D0, D1, D2, and D3) arranged in parallel for a second input data group as shown in Figure 4. Each memory unit 2014 is associated with one of the stored values ​​or result values ​​(or data) in the lookup table (LUT) 210, and the multiplexer 211 can be configured to select a data input (i.e., D0, D1, ..., D2) from its second input data group. D2 or D3), this selection is based on a first input data group associated with the input data group of each programmable logic unit (LC) 2014, the selected data input being a data output Dout located at an output point of each programmable logic unit (LC) 2014.

[0180] Referring to Figure 6A, each memory unit 490 (i.e., configuration programming memory (CPM) unit) may refer to memory unit 446 as shown in Figure 1A or Figure 1B. The multiplexer (MUXER) 211 may have its second set of input data (e.g., D0, D1, D2, and D3 as shown in Figure 4), each of which is associated with the data output (i.e., configuration programming memory (CPM) data) of one of the memory units 490 (i.e., the first data output Out1 and the second data output Out2 of the memory unit 446 as shown in Figure 1A or Figure 1B), wherein the data output is transmitted via a non-programmable interconnect line 364 (which is a non-programmable interconnect line). Alternatively, each programmable logic unit (LC) 2014 may further include a second type pass / delete switch or switch buffer 292 as shown in Figures 2B and 4, having an input point coupled to the output point of its multiplexer (MUXER) 211 to amplify the data output Dout of its multiplexer 211 as one of the data outputs of each programmable logic unit (LC) 2014 (located at an output point of each programmable logic unit (LC) 2014), wherein the second type pass / delete switch or switch buffer 292 may have a data input SC-4 associated with the data output (i.e., the configuration programming memory (CPM) data) of another memory unit 490 (i.e., the first data output Out1 and the second data output Out2 of memory unit 446 as shown in Figures 1A or 1B).

[0181] Referring to Figure 6A, each programmable logic unit (LC) 2014 may have a memory unit 490 (i.e., a configuration programming memory (CPM) unit) configured to be programmable to store or save the result value or programming code of lookup table (LUT) 210 to perform logical operations, such as AND, NAND, OR, NOR, EXOR, or other Boolean operations, or combinations of two (or more) arithmetic operations. In this case, each programmable logic unit (LC) 2014 may perform logical operations on its input data sets (e.g., A0 and A1) at its input points as data output Dout at its output points.

[0182] In more detail, each programmable logic unit (LC) 2014 may include 2n memory units 490 (i.e., configuration programming memory (CPM) units), each memory unit being used to store or store one of the result values ​​of a lookup table (LUT) 210, and multiplexers (MUXER) 211 having a first set of input data (e.g., A0-A1) arranged in parallel, and a second set of input data (e.g., D0-D3) having a second set of input points arranged in parallel, each input point being associated with one of the result values ​​or programming codes in the lookup table (LUT) 210, wherein in this case, the number n may be between 2 and 8, and in this example is 2. The multiplexer 211 can be configured to select a data input (i.e., one of D0-D3) from its second input data group to serve as a data output of each programmable logic unit (LC) 2014 at the output point of each programmable logic unit (LC) 2014, wherein the selection is based on a first input data group associated with the input data group of each programmable logic unit (LC) 2014.

[0183] Alternatively, as shown in Figure 6A, multiple programmable logic units (LCs) 2014 can be configured to be programmed and integrated into a programmable logic block (LB) or element 201 as shown in Figure 6B as a computational operator to perform computational operations (e.g., addition, subtraction, multiplication, or division). The computational operator can be an adder, multiplier, multiplexer, shift register, floating-point circuit, and / or division circuit. Figure 6B discloses a block diagram of a computational operator according to an embodiment of the present invention. For example, as shown in Figure 6B, the computational operator can multiply two binary data inputs (i.e., [A1, A0] and [A3, A2]) by a quaternary output data set (i.e., [C3, C2, C1, C0]) as shown in Figure 1C, and Figure 6C is a truth table for the logical operation shown in Figure 6B.

[0184] Referring to Figures 6B and 6C, four programmable logic units (LCs) 2014 (each LC may refer to one as shown in Figure 6A) can be programmed and integrated into a computing operator. Each of the four LCs 2014 may have its input data set at its four input points, which are respectively associated with the input data sets [A1, A0, A3, A2] of the computing operator. Each LC 2014 of the computing operator can generate a data output (e.g., C0, C1, C2, or C3) of the computing operator's quaternary data output based on its input data set [A1, A0, A3, A2]. When a binary bit set (i.e., [A1, A0]) is multiplied by a binary bit set (i.e., [A3, A2]), the programmable logic block (LB) 201 can generate its quaternary output data set (i.e., [C3, C2, C1, C0]) based on its input data set [A1, A0, A3, A2]. Each of the four programmable logic units (LC) 2014 may have its own memory unit 490, each memory unit may be referred to as memory unit 446 as shown in Figure 1A or Figure 1B, for programming to store or store the result value or programming code of lookup table 210 (i.e., Table-0, Table-1, Table-2 or Table-3).

[0185] For example, referring to Figures 6B and 6C, the first of the four programmable logic units (LCs) 2014 may have its memory unit 490 (i.e., a configuration programming memory (CPM) unit) for storing or storing result values ​​or programming codes. The lookup table (LUT) 210 of Table-0 and its multiplexers (MUXER) 211 are used to retrieve data from their multiplexers (MUXER) 211 according to the first input data set associated with the input data set [A1, A0, A3, A2] of the computing operator. The second input data group D0-D15 of (MUXER)211 selects a data input, wherein each of the second input data group D0-D15 is associated with the data output of one of its memory units 490, that is, one of the first data output Out1 and the second data output Out2 of memory unit 446 in Figure 1A or Figure 1B. The data output of one of the memory units 490 is associated with the result value of the lookup table (LUT) 210 of Table-0 or the programming code. The selected data input is used as the binary data output of the quaternary output data set (i.e., [C3, C2, C1, C0]) of the programmable logic block (LB) 201. The second of the four programmable logic units (LCs) 2014 may have its memory unit 490 (i.e., a configuration programming memory (CPM) unit) and its multiplexer 211. The memory unit 490 is used to store or save the result value or programming code of its lookup table (LUT) 210 of Table-2, and the multiplexer 211 is configured to work with the input data sets [A1, A0, A3, ...] in the computing operator respectively. A2] The first input data group of its multiplexer 211 is associated with a data input selected from the second input data group D0-D15 in its multiplexer 211. Each data input is associated with a data output of one of its memory units 490 (i.e., one of the first data output Out1 and the second data output Out2 of memory unit 446 in Figure 1A or Figure 1B). The data input is associated with either the result value of its lookup table (LUT) 210 of Table-1 or a programming code. The selected data input is the data output C1 of the four binary output data group (i.e., [C3, C2, C1, C0]) of the programming logic block (LB) 201.The third of the four programmable logic units (LCs) 2014 may have its memory unit 490 (i.e., a configuration programming memory (CPM) unit) and its multiplexer 211. The memory unit 490 is used to store or save the result value or programming code of its lookup table (LUT) 210 of Table-1, and the multiplexer 211 is configured to work with the input data sets [A1, A0, A3, ...] in the computing operator respectively. A2] The first input data group of its multiplexer 211 is associated with a data input selected from the second input data group D0-D15 in its multiplexer 211. Each data input is associated with a data output of one of its memory units 490 (i.e., one of the first data output Out1 and the second data output Out2 of memory unit 446 in Figure 1A or Figure 1B). The data input is associated with either the result value of its lookup table (LUT) 210 of Table-2 or a programming code. The selected data input is the data output C2 of a binary data output group (i.e., [C3, C2, C1, C0]) of the four binary output data group of the programming logic block (LB) 201. The fourth of the four programmable logic units (LCs) 2014 may have its memory unit 490 (i.e., a configuration programming memory (CPM) unit) and its multiplexer 211. The memory unit 490 is used to store or store the result value or programming code of its lookup table (LUT) 210 of Table-3, and the multiplexer 211 is configured to work with the input data sets [A1, A0, A3, ...] in the computing operator respectively. A2] The first input data group of its multiplexer 211 is associated with a data input selected from the second input data group D0-D15 in its multiplexer 211. Each data input is associated with a data output of one of its memory units 490 (i.e., one of the first data output Out1 and the second data output Out2 of memory unit 398 in Figure 1A or Figure 1B). The data input is associated with the result value of its lookup table (LUT) 210 of Table-3 or a programming code. The selected data input is the data output C3 of the four binary output data group (i.e., [C3, C2, C1, C0]) of the programming logic block 201.

[0186] Furthermore, referring to Figures 6B and 6C, the programmable logic block (LB) 201 used as a computing operator can be composed of four programmable logic units (LC) 2014, which generate their quaternary output data set, namely [C3, C2, C1, C0], based on their input data set [A1, A0, A3, A2].

[0187] Referring to Figures 6B and 6C, in the specific case of 3x3, each of the four programmable logic units (LC) 2014 can have its own multiplexer 211, which can select a data input from its multiplexer D0-D15. The selection is based on the first input data set of the multiplexer 211 associated with the input data set of the arithmetic operator (i.e., [A1, A0, A3, A2] = [1, 1, 1, 1]). Each data input associated with the result value of its lookup table (LUT) 210 (one of Table-0, Table-1, Table-2, and Table-3) or the programming code is its data output (i.e., one of C0, C1, C2, and C3), and serves as the four binary bit output data set (i.e., [C3, C2, ..., ...) of the programmable logic block (LB) 201. Output a binary data bit of [C1, C0] = [1, 0, 0, 1]). The first of the four programmable logic units (LC) 2014 can generate its data output C0 (i.e., [A1, A0, A3, A2] = [1, 1, 1 1]) based on its input data set at a logic level of "1"; the second of the four programmable logic units (LC) 2014 can generate its data output C1 (i.e., [A1, A0, A3, A2] = [1, 1, 1, 1]) based on its input data set at a logic level of "0"; the third of the four programmable logic units (LC) 2014 can generate its data output C2 (i.e., [A1, A0, A3, A2] = [1, 1, 1, 1]) based on its input data set at a logic level of "0"; and the fourth of the four programmable logic units (LC) 2014 can generate its data output C2 (i.e., [A1, A0, A3, A2] = [1, 1, 1, 1]) based on its input data set.

[0188] Alternatively, Figure 6D discloses a block diagram of a programmable logic block of a standard commercial FPGA IC chip according to an embodiment of the present invention. Referring to Figure 6D, a programmable logic block (LB) 201 may include (1) one or more units (A) 2011 for a fixed-line adder, the number of which is, for example, between 1 and 16; (2) one or more units (C / R) 2013 of caches and registers, each cache and register having a capacity, for example, between 256 and 2048 bits; and (3) programmable logic units (LC) 2014 as shown in Figures 6A to 6C, the number of which is between 64 and 2048. The programmable logic block (LB) 201 may further include a plurality of intra-block interconnects 2015, each intra-block interconnect 2015 extending in space between two adjacent units 2011, 2013 and 2014 in its array. For a programmable logic block (LB) 201, the interconnect lines 2015 within the block can be divided into programmable interconnect lines 361. The programmable interconnect lines 361 can be programmed for interconnect lines via their memory units 362 (as shown in Figures 3A, 3B and 7) and non-programmable interconnect lines 364 (as shown in Figures 6A and 7, the non-programmable interconnect lines 364 cannot be programmed).

[0189] Referring to Figure 6D, each programmable logic unit (LC) 2014 may have its memory unit 490 (i.e., configuration programming memory (CPM) unit), the number of which ranges from 4 to 256. Each memory unit 490 can be used to store or store one of the result values ​​of its lookup table 210 or programming codes, and its multiplexers (MUXER) 211 can select a data input as its data output from the second input data group of the multiplexers (MUXER) 211 having a bit width between 4 and 256. The selection is based on the first input data group of the multiplexers (MUXER) 211 having a bit width between 2 and 8, wherein the multiplexer (MUXER) The input point of 211 is coupled to at least one of the programmable interactive connection line 361 and the non-programmable interactive connection line 364 of the interactive connection line 2015 within the block, and the output point is coupled to at least one of the programmable interactive connection line 361 and the non-programmable interactive connection line 364 of the interactive connection line 2015 within the block.

[0190] Instructions for Programmable Interconnect Cable

[0191] Figure 7 discloses a circuit diagram of a programmable interactive connection line programmed by a third type of crosspoint switch according to an embodiment of the present invention. In addition to the first and second type crosspoint switches 379 as shown in Figures 3A and 3B, the third type crosspoint switch 379 shown in Figure 7 also includes four multiplexers 211 as shown in Figure 4. Each of the four multiplexers 211 can select a data input from its second set of input points (e.g., D0-D2) as its data output based on data at its first set of input points (e.g., A0 and A1) in its first set of input points. Each of the three input points in the second set of one of the four multiplexers 211 can be coupled to one of the three input points in the second set of one of the other two multiplexers 211, and coupled to the output points of the other multiplexers 211. Therefore, each of the four multiplexers (MUXER) 211 can select a data input from its second input data group (D0-D2) based on its first input data group (i.e., A0 and A1), coupled at its second set of three input points to three corresponding programmable interactive lines 361 extending in three different directions, and coupled to another corresponding three of the four multiplexers (MUXER) 211 as its data output (e.g., Dout), coupled at the output point of one of the four nodes N23-N26 of the third type crosspoint switch 379 to another programmable interactive line extending in directions other than the three different directions. For example, the highest multiplexer of the four multiplexers (MUXER) 211 can select a data input based on its first input data group (e.g., A0 and A1) from its second input data group (e.g., D0-D2). The three input points of the second group, located at nodes N24, N25, and N26 of the third group of cross-point switches 379 (that is, at the two output points on the left, bottom, and right sides of the four multiplexers 211 respectively), are respectively used as their data output points at node N23 of the third type of cross-point switch 379 at their output points.

[0192] Referring to Figure 7, four programmable interactive connection lines 361 can be coupled to the corresponding four nodes N23-N26 of a third-type crosspoint switch 379. Furthermore, data from one of the four programmable interactive connection lines 361 can be switched by the third-type crosspoint switch 379 to be transmitted to another, two, or three of the four programmable interactive connection lines 361. For the third-type crosspoint switch 379, each of the four multiplexers (MUXER) 211 as shown in Figure 4 has a data input (e.g., A0 and A1) of its first input data group, which is associated with a data output of a memory unit 362 (i.e., a configuration programming memory (CPM), such as one of the first data output Out1 and second data output Out2 of memory unit 398 in Figure 1A or Figure 1B). Each multiplexer (MUXER) as shown in Figure 4... (MUXER))211 has a data input SC-4, which is associated with a data output of another memory unit 362 (i.e., a configuration programming memory (CPM) unit), such as one of the first data output Out1 and the second data output Out2 of memory unit 446 in Figure 1A or Figure 1B. Alternatively, referring to Figure 7, the third type crosspoint switch 379 further includes four second type pass / miss switches or switch buffers 258, each having an input point coupled to the output point of one of the four multiplexers (MUXERs) as shown in Figure 4. For the third type crosspoint switch 379, each of the four pass / miss switches or switch buffers 258 is used to open or close a channel to the data output of one of the four multiplexers (MUXERs) 211, i.e., Dout, at its output point (i.e., nodes 23, 24). The data output of 25 or 26) is coupled to one of the four programmable interconnect lines 361. For example, for a third type crosspoint switch 379, the top of the four multiplexers 211 can be coupled to the top of the four pass / no-pass switches or switch buffers 258 to turn on or off the data output (i.e., Dout) of the top of the four multiplexers 211 as the data output of the top of the four pass / no-pass switches or switch buffers 258, i.e., node 23, which is coupled to the top of the four programmable interconnect lines 361.For the third type of crosspoint switch 379, each pass / fail switch or switch buffer 258 data input SC-4 is associated with a data output of another memory unit 362 (i.e., the configuration programming memory (CPM) unit) of one of the first data output Out1 and the second data output Out2 of memory unit 446 in Figure 1A or Figure 1B.

[0193] Furthermore, for the third type of crosspoint switch 379, each memory unit 362 (i.e., configuration programming memory (CPM) unit) can be programmed to store or save a programming code to control the data transmission between each of the three of the four programmable interconnect lines 361 coupled to its second group of three input points and the second group of three input points coupled to one of its four multiplexers 211, and the other of the other four programmable interconnect lines 361 (which are coupled to the output points of one of the four multiplexers 211), that is, to control whether or not the data input of the second input data group (e.g., D0, D1, or D2) is passed through the corresponding three input points of the second group of one of the four multiplexers 211, wherein the three input points of the second input data group (located in the four multiplexers 211) are... One of the output points of 211 is coupled to three of the four programmable interactive connection lines 361 as the data output (i.e., Dout) of one of the four multiplexers (MUXERs) 211, and the data output (i.e., Dout) at its output point is coupled to the other lines of the four programmable interactive connection lines 361.

[0194] For example, referring to Figure 7, for the third type crosspoint switch 379, the data inputs (e.g., A0 and A1) of the first input data group of the top of the four multiplexers (MUXER) 211 shown in Figure 4 are respectively associated with the data outputs (i.e., configuration programming memory (CPM) data) of two of its three memory units 362-1. Each memory unit can refer to one of the data outputs Out1 and Out2 of memory unit 446 shown in Figure 1A or Figure 1B, and the data input SC-4 of the top of the secon...

Claims

1. A multi-chip package structure, comprising: A first semiconductor integrated circuit (IC) chip includes a first silicon substrate, a plurality of first transistors located on a top surface of the first silicon substrate, and a first interconnect structure located above the first silicon substrate and coupled to the first transistors; a second semiconductor integrated circuit (IC) chip is located above the first semiconductor integrated circuit (IC) chip and coupled to the first semiconductor integrated circuit (IC) chip, wherein the second semiconductor integrated circuit (IC) chip includes a second silicon substrate, a plurality of second transistors located on a bottom surface of the second silicon substrate, and a second interconnect structure located below the second silicon substrate and coupled to the second transistors, wherein the second interconnect structure includes a first silicon oxide layer and a first bonding pad located at the bottom of the second semiconductor integrated circuit (IC) chip, wherein the first bonding pad is located within an opening in the first silicon oxide layer and coupled to the first transistors. The first semiconductor integrated circuit (IC) wafer is connected to a first bonding pad, wherein the first bonding pad includes a first copper layer located within the opening in a first silicon oxide layer, a first adhesive metal layer having a first portion located at a side wall of the first copper layer and a second portion located at a top of the first copper layer, wherein the bottom surface of the first copper layer and the bottom surface of the first silicon oxide layer are coplanar, wherein the second semiconductor integrated circuit (IC) wafer has a first boundary located above the first semiconductor integrated circuit (IC) wafer and a second boundary opposite to the first boundary, the second boundary also being located above the first semiconductor integrated circuit (IC) wafer; A sealing layer is located above the first semiconductor integrated circuit (IC) wafer and on the same horizontal plane as the second semiconductor integrated circuit (IC) wafer; a first metal via is located above the first semiconductor integrated circuit (IC) wafer and vertically positioned within the sealing layer; a second metal via is located above the first semiconductor integrated circuit (IC) wafer, vertically positioned within the sealing layer, and coupled to the first bonding pad of the second semiconductor integrated circuit (IC) wafer; a first metal pad is vertically positioned above the first metal via and coupled to the first metal via; a polymer layer is located above the second semiconductor integrated circuit (IC) wafer and the sealing layer, wherein an opening in the polymer layer is vertically positioned above the first metal pad and the first metal via; and a first metal bump is located on the first metal pad, vertically positioned above the first metal via, and located at the top of the multi-chip package structure, wherein the first metal bump is coupled to the first metal via via the first metal pad.

2. The multi-chip package structure claimed in claim 1 further includes a second metal pad and a second metal bump, the second metal pad being coupled to the second metal connection channel, the second metal bump being located at the top of the multi-chip package structure and on the second metal pad, and the second metal bump being coupled to the second metal connection channel via the second metal pad.

3. The multi-chip package structure claimed in claim 1 further includes a second metal pad vertically positioned above the second semiconductor integrated circuit (IC) chip, and a second metal bump positioned at the top of the multi-chip package structure, on the second metal pad, and vertically positioned above the second semiconductor integrated circuit (IC) chip.

4. The multi-chip package structure claimed in claim 3, wherein the second semiconductor integrated circuit (IC) chip includes a through silicon via vertically positioned in the second silicon substrate, wherein the second metal pad is coupled to the through silicon via.

5. The multi-chip package structure claimed in claim 1, wherein the second interconnection structure further includes an interconnection metal layer located below the second silicon substrate, wherein the interconnection metal layer includes a second copper layer and a second adhesive metal layer, wherein the second adhesive metal layer has a first portion located at a sidewall of the second copper layer and a second portion located at a top of the second copper layer, wherein the first bonding pad is located below the interconnection metal layer, and the second portion of the first adhesive layer is located between the first copper layer and the second copper layer and is in contact with the second copper layer.

6. The multi-chip package structure claimed in claim 1, wherein the first interconnect structure includes a second silicon oxide layer and a second bonding pad, wherein the second silicon oxide layer has an upper surface that is bonded to and contacts the bottom surface of the first silicon oxide layer, the second bonding pad is located in an opening of the second silicon oxide layer, wherein the second bonding pad includes a second copper layer and a second adhesive metal layer, the second copper layer is located in the opening of the second silicon oxide layer, and the second adhesive metal layer has a first portion located at a sidewall of the second copper layer and a second portion located at a bottom of the second copper layer, wherein the second copper layer has an upper surface that is bonded to and contacts the bottom surface of the first copper layer.

7. The multi-chip package structure as claimed in claim 1, wherein the first metal bump comprises tin.

8. The multi-chip package structure claimed in claim 1, wherein the second metal connection channel is configured to be coupled to a power supply voltage.

9. The multi-chip package structure as claimed in claim 1, wherein the second metal connection channel is configured to be coupled to a ground reference voltage.

10. The multi-chip package structure claimed in claim 1, wherein the second metal connection channel is coupled to the first bonding pad of the second semiconductor integrated circuit (IC) chip via the first interconnection line structure.

11. The multi-chip package structure claimed in claim 1, wherein the first metal interconnect channel includes a copper layer with a thickness between 20 micrometers and 100 micrometers.

12. The multi-chip package structure claimed in claim 1, wherein one sidewall of the sealing layer is substantially coplanar with one sidewall of the first semiconductor integrated circuit (IC) chip in the vertical direction, and the polymer layer does not extend beyond the sidewall of the first semiconductor integrated circuit (IC) chip in the horizontal direction.

13. The multi-chip package structure claimed in claim 1, wherein the second silicon substrate has an upper surface that is not on one of the upper surfaces of the sealing layer.

14. The multi-chip package structure claimed in claim 1, wherein the second semiconductor integrated circuit (IC) chip is a memory chip.

15. The multi-chip package structure claimed in claim 1, wherein the first semiconductor integrated circuit (IC) chip is a logic chip.

16. A multi-chip package structure, comprising: A first semiconductor integrated circuit (IC) chip includes a first silicon substrate, a plurality of first transistors located on a top surface of the first silicon substrate, and a first interconnect structure located above the first silicon substrate and coupled to the first transistors; a second semiconductor integrated circuit (IC) chip is located above the first semiconductor integrated circuit (IC) chip and coupled to the first semiconductor integrated circuit (IC) chip, wherein the second semiconductor integrated circuit (IC) chip includes a second silicon substrate, a plurality of second transistors located on a bottom surface of the second silicon substrate, and a second interconnect structure located below the second silicon substrate and coupled to the second transistors, wherein the second interconnect structure includes a first silicon oxide layer and a first bonding pad located at the bottom of the second semiconductor integrated circuit (IC) chip, wherein the first bonding pad is located within an opening in the first silicon oxide layer and coupled to the first transistors. The first semiconductor integrated circuit (IC) wafer is connected to a first bonding pad, wherein the first bonding pad includes a first copper layer located within the opening in a first silicon oxide layer, a first adhesive metal layer having a first portion located at a side wall of the first copper layer and a second portion located at a top of the first copper layer, wherein the bottom surface of the first copper layer and the bottom surface of the first silicon oxide layer are coplanar, wherein the second semiconductor integrated circuit (IC) wafer has a first boundary located above the first semiconductor integrated circuit (IC) wafer and a second boundary opposite to the first boundary, the second boundary also being located above the first semiconductor integrated circuit (IC) wafer; A sealing layer is located above the first semiconductor integrated circuit (IC) wafer and on the same horizontal plane as the second semiconductor integrated circuit (IC) wafer; a first metal via is coupled to the first semiconductor integrated circuit (IC) wafer and located above the first semiconductor integrated circuit (IC) wafer, and the first metal via is vertically positioned in the sealing layer; a third interconnect structure is located above the second semiconductor integrated circuit (IC) wafer, the sealing layer, and the first metal via; and a first metal bump is located on the third interconnect structure, at the top of the multi-chip package structure, and protruding from an upper surface of the third interconnect structure, wherein the first metal bump is sequentially coupled to the first bonding pad of the second semiconductor integrated circuit (IC) wafer via the third interconnect structure and the first metal via.

17. The multi-chip package structure claimed in claim 16 further includes a second metal bump located on the third interconnect structure, at the top of the multi-chip package structure, vertically positioned above the second semiconductor integrated circuit (IC) chip, and protruding from the upper surface of the third interconnect structure.

18. The multi-chip package structure claimed in claim 17, wherein the second semiconductor integrated circuit (IC) chip includes a through silicon via vertically positioned in the second silicon substrate, wherein the second metal bump is coupled to the through silicon via via the third interconnect structure.

19. The multi-chip package structure claimed in claim 17 further includes a second metal connection channel located above and coupled to the first semiconductor integrated circuit (IC) chip, wherein the second metal connection channel is located in the sealing layer, and wherein the second metal bump is coupled to the second metal connection channel via the third interconnection line structure.

20. The multi-chip package structure claimed in claim 16, wherein the second interconnection structure further includes an interconnection metal layer located below the second silicon substrate, wherein the interconnection metal layer includes a second copper layer and a second adhesive metal layer, wherein the second adhesive metal layer has a first portion located at a sidewall of the second copper layer and a second portion located at a top of the second copper layer, wherein the first bonding pad is located below the interconnection metal layer, and the second portion of the first adhesive layer is located between the first copper layer and the second copper layer and is in contact with the second copper layer.

21. The multi-chip package structure claimed in claim 16, wherein the first interconnect structure includes a second silicon oxide layer and a second bonding pad, wherein the second silicon oxide layer has an upper surface that is bonded to and contacts the bottom surface of the first silicon oxide layer, the second bonding pad is located in an opening of the second silicon oxide layer, wherein the second bonding pad includes a second copper layer and a second adhesive metal layer, the second copper layer is located in the opening of the second silicon oxide layer, and the second adhesive metal layer has a first portion located at a sidewall of the second copper layer and a second portion located at a bottom of the second copper layer, wherein the second copper layer has an upper surface that is bonded to and contacts the bottom surface of the first copper layer.

22. The multi-chip package structure claimed in claim 16 further includes a third semiconductor integrated circuit (IC) chip located above and coupled to the first semiconductor integrated circuit (IC) chip, wherein the third semiconductor integrated circuit (IC) chip, the second semiconductor integrated circuit (IC) chip, and the sealing layer are located on the same horizontal plane, wherein the third interconnection line structure is located above the third semiconductor integrated circuit (IC) chip.

23. The multi-chip package structure claimed in claim 16, wherein the first metal bump comprises tin.

24. The multi-chip package structure claimed in claim 16, wherein the first metal connection channel is configured to be coupled to a power supply voltage.

25. The multi-chip package structure claimed in claim 16, wherein the first metal connection channel is configured to be coupled to a ground reference voltage.

26. The multi-chip package structure claimed in claim 16, wherein the first metal connection channel is coupled to the first bonding pad of the second semiconductor integrated circuit (IC) chip via the first interconnection line structure.

27. The multi-chip package structure claimed in claim 16, wherein the first metal interconnect channel includes a copper layer with a thickness between 20 micrometers and 100 micrometers.

28. The multi-chip package structure claimed in claim 16, wherein the second semiconductor integrated circuit (IC) chip is a memory chip.

29. The multi-chip package structure claimed in claim 16, wherein the first semiconductor integrated circuit (IC) chip is a logic chip.

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