Processes and applications for catalyst influenced chemical etching

Abstract

A system for assembling fields from a native substrate onto a second substrate. The native substrate includes a plurality of fields. The system further includes a transfer chuck. The transfer chuck is used to pick up at least four fields to be transferred to the second substrate in parallel from the native substrate, wherein the relative positions of the at least four fields are predetermined.

Description

Technical Field

[0001] This case claims priority to U.S. Provisional Patent Application No. 63 / 167,462, filed on March 29, 2021, entitled "System and Process for Nanoscale Precision Pick-and-Place Assembly for Semiconductor Subcircuits," the entire contents of which are incorporated herein by reference.

[0002] This case further asserts priority to U.S. Provisional Patent Application No. 63 / 174,128, filed on April 13, 2021, entitled "Process and Application of Catalyst-Influenced Chemical Etching," the entire contents of which are incorporated herein by reference.

[0003] This case further asserts priority to U.S. Provisional Patent Application No. 63 / 215,807, filed on June 28, 2021, entitled "Tool and Process for Picking and Placing Components," the entire contents of which are incorporated herein by reference.

[0004] This case is primarily about etching, and more specifically about an apparatus and process technology for using catalysts to influence chemical etching. Prior Technology

[0005] In semiconductor device manufacturing, etching refers to any technique that selectively removes material from a thin film (with or without a prior structure on its surface) on a substrate and creates a pattern of that material on the substrate through this removal. This pattern can be defined by a mask used in the etching process. Once the mask is in place, the material not protected by the mask can be etched using wet chemical or "dry" physical methods.

[0006] One type of etching is catalyst-influenced chemical etching (CICE), a catalyst-based etching method used to create complex features in semiconductors such as silicon and germanium. These features possess high aspect ratios, low sidewall slopes, low sidewall roughness, and / or controllable porosity. This method is used to create higher density and more efficient static random access memory (SRAM) and low-loss waveguides.

[0007] Unfortunately, there are currently limitations in using CICE to fabricate features in semiconductors. Summary of the Invention

[0008] In one embodiment of this invention, a system for assembling fields from a native substrate to a second substrate includes a native substrate. The native substrate includes a plurality of fields. The system further includes a transfer chuck. The transfer chuck is used to pick up at least four fields to be transferred to the second substrate in parallel from the plurality of fields of the native substrate, wherein the relative positions of the at least four fields of the plurality of fields are predetermined.

[0009] In another embodiment of this invention, a transfer chuck includes a rectangular array of a plurality of adaptive chuck modules. The transfer chuck further includes a variable pitch mechanism for changing at least one X-pitch or at least one Y-pitch of the rectangular array of the plurality of adaptive chuck modules.

[0010] In another embodiment of this invention, a transfer substrate includes a plurality of fields previously picked up from a native substrate using a transfer chuck. The transfer substrate further includes a plurality of embedded structures oriented in the Z direction.

[0011] In another embodiment of this case, a method for creating multiple alignment marks in a multiple field during monolithization includes creating multiple alignment marks in a multiple field using an etching technique during monolithization, wherein the etching technique includes catalyst-influenced chemical etching or deep reactive ion etching.

[0012] Furthermore, in another embodiment of this invention, a method for preventing catalyst drift during catalyst-influenced chemical etching includes providing a semiconductor material. This method further includes patterning a catalyst on the surface of the semiconductor material, wherein the catalyst includes one or more isolation features, and wherein the one or more isolation features include a predetermined aperture. This method also includes exposing the patterned catalyst to an etchant, wherein the patterned catalyst and the etchant cause etching of the semiconductor material to form a plurality of buttresses corresponding to the predetermined aperture, wherein the plurality of buttresses prevent catalyst drift during catalyst-influenced chemical etching.

[0013] Furthermore, in another embodiment of this application, a method for fabricating nanostructures includes performing chemically influenced chemical etching on a polycrystalline silicon layer to create a complex silicon structure. This method further includes depositing one or more structural materials on the complex silicon structure, wherein the selected structural materials are used to enhance desired device characteristics. This method also includes creating a channel through the complex silicon structure. Additionally, this method includes selectively removing the complex silicon structure, thereby leaving substantially identical one or more structural materials.

[0014] In another embodiment of this invention, a fluid device comprises a multilayer stack of silicon micropillars and nanopillar arrays, wherein the silicon micropillars and nanopillar arrays are fabricated using catalyst-induced chemical etching, and wherein the multilayer stack is fabricated by depositing a plurality of polycrystalline silicon films and etching these polycrystalline silicon films using catalyst-induced chemical etching.

[0015] In another embodiment of this case, a method for bending one or more image sensors into a spherical shape includes using a transfer chuck to press the front side of one or more image sensors to produce the curvature of one or more image sensors.

[0016] The features and technical advantages of one or more embodiments of this application have been described in a fairly general manner above, so as to provide a better understanding of the following detailed description of this application. Additional features and advantages of this application will be described below, which may form the subject matter of the claims. Simple Explanation of the Diagram

[0017] A better understanding of this case can be obtained by considering the following detailed description in conjunction with the accompanying drawings, wherein:

[0018] [Figure 1] illustrates an exemplary tool for picking up and placing components according to an embodiment of this case; [Figures 2A and 2B] illustrate an exemplary design for a native / product / intermediate substrate chuck according to an embodiment of this invention; [Figure 3] illustrates an exemplary design of a native substrate chuck having an array of extreme ultraviolet light-emitting diodes for field release according to an embodiment of the present invention; [Figure 4A] illustrates a transfer chuck with an attached field according to an embodiment of the present invention; [Figure 4B] shows a cross-sectional view of a transfer chuck according to an embodiment of the present invention; [Figure 4C] shows a top view of the xy actuator layer according to an embodiment of this invention; [Figure 4D] shows a top view of a pneumatic valve layer according to an embodiment of this invention; [Figure 4E] shows an alternative top view of the pneumatic valve layer according to an embodiment of this invention; [Figure 5A] illustrates an exemplary diagram of a transfer chuck (TC) according to an embodiment of the present invention, comprising a customized layer for each new field type; [Figure 5B] shows an enlarged view of a transfer chuck comprising a customized layer for each new field type according to an embodiment of the present invention; [Figure 6A] illustrates an exemplary transfer chuck composed of compliant pins according to an embodiment of the present invention; [Figure 6B] shows a partial enlarged view of the top metal layer of a transfer chuck according to an embodiment of the present invention; [Figure 6C] shows an enlarged view of a thin film located on the bottom of the top metal layer of the transfer chuck as shown in Figure 6B, according to an embodiment of the present invention; [Figure 7] illustrates an exemplary labeling of multiple fields in a rectangular boundary region that can be assembled using an actuator mesh with nine labels (nine assembly steps) according to an embodiment of the present invention; [Figure 8] illustrates an exemplary manufacturing process for an intermediate substrate used for assembly according to an embodiment of this invention; [Figure 9] illustrates an exemplary diagram of multiple transfer chucks used during assembly according to an embodiment of the present invention; [Figure 10] illustrates an exemplary reconfigurable grid transfer chuck according to an embodiment of the present invention; [Figures 11A to 11B] illustrate an exemplary transfer chuck with a closed-bounded vacuum and / or pressure region according to an embodiment of the present invention; [Figures 12A to 12B] illustrate alternative embodiments of an exemplary transfer chuck having a closed-boundary vacuum and / or pressure region according to an embodiment of the present invention; [Figures 13A to 13C] illustrate yet another alternative embodiment of an exemplary transfer chuck having a closed-boundary vacuum and / or pressure region according to an embodiment of the present invention; [Figure 14] illustrates an exemplary sensor arrangement for an exemplary metering module according to an embodiment of this invention; [Figure 15] illustrates an alternative exemplary sensor arrangement for an exemplary metering module according to an embodiment of the present invention; [Figure 16] illustrates an exemplary reconfiguration grid sensor arrangement for an exemplary metering module according to an embodiment of the present invention; [Figure 17] illustrates the unfolding of the reconfigured grid sensor arrangement shown in Figure 16 according to an embodiment of this invention to obtain a complex field of 30 mm x 3 mm; [Figures 18A to 18D] illustrate an exemplary alignment metrology architecture for an exemplary metrology module according to an embodiment of this invention; [Figures 19A to 19C] illustrate an alternative exemplary alignment metrology architecture for an exemplary metrology module according to an embodiment of this invention; [Figures 20A to 20C] illustrate details of an exemplary metering module according to an embodiment of this invention; [Figure 21] illustrates an exemplary metering architecture according to an embodiment of this case; [Figure 22] illustrates an exemplary field of an array comprising 2 x 2 grains according to an embodiment of the present invention; [Figure 23] illustrates an exemplary metering architecture according to an embodiment of this case; [Figure 24] illustrates another embodiment of an exemplary metering architecture according to one embodiment of this case; [Figure 25] illustrates yet another embodiment of an exemplary metering architecture according to an embodiment of this case; [Figures 26A and 26B] illustrate an exemplary known-bad-die replacement chuck (KRC) according to an embodiment of this case; [Figures 27A to 27C] illustrate exemplary native substrate types according to an embodiment of this case; [Figures 28A and 28B] illustrate an exemplary field with an exemplary multilayer package according to an embodiment of the present invention; [Figures 29A to 29B] illustrate an exemplary face-to-back (F2B) and face-to-face (F2F) device stack according to an embodiment of the present invention; [Figure 30] illustrates an exemplary assembly of a static random access memory in a logical field according to an embodiment of this invention; [Figure 31] illustrates an exemplary assembly of multiple stacked static random access memories in a logical field according to an embodiment of the present invention; [Figure 32] illustrates an exemplary assembly of static random access memory in a logical field with an intermediate error correction intermediary layer according to an embodiment of the present invention; [Figure 33] illustrates an exemplary sequence for picking up and placing assembly according to an embodiment of this case; [Figure 34] illustrates an alternative exemplary sequence for pick-and-place assembly according to an embodiment of this case; [Figure 35] illustrates yet another alternative exemplary sequence for pick-and-place assembly according to an embodiment of this case; [Figures 36A to 36B] illustrate an exemplary transfer chuck according to an embodiment of the present invention; [Figures 37A to 37O] illustrate alternative exemplary transfer chucks according to an embodiment of the present invention; [Figures 38A to 38C] illustrate an exemplary reconfiguration transfer chuck according to an embodiment of the present invention; [Figures 39A to 39C] illustrate an exemplary transfer chuck according to an embodiment of the present invention, showing an array of multiple adaptive chucking modules (ACMs) that can move relative to each other using a variable pitch mechanism (VPM); [Figures 40A to 40B] illustrate an alternative exemplary transfer chuck according to an embodiment of the present invention, which shows an array of a plurality of elongated adaptive chuck modules that can move relative to each other using an adjustable spacing mechanism; [Figure 41] illustrates yet another alternative exemplary transfer chuck according to an embodiment of the present invention, showing an array of a plurality of elongated adaptive chuck modules that can move relative to each other using an adjustable spacing mechanism; [Figures 42A and 42B] illustrate an exemplary adaptive chuck module according to an embodiment of the present invention; [Figures 43A to 43C] illustrate another exemplary transfer chuck according to an embodiment of the present invention, which shows an array of multiple adaptive chuck modules that can move relative to each other using an adjustable spacing mechanism; [Figures 44A to 44F] illustrate an exemplary transfer substrate according to an embodiment of the present invention; [Figure 45] illustrates an alternative exemplary transfer substrate according to an embodiment of this case; [Figures 46A and 46B] illustrate an exemplary interference prevention method according to an embodiment of the present invention (during field assembly to a transfer substrate); [Figures 47A to 47E] illustrate an exemplary native substrate according to an embodiment of this case; [Figure 48] is a flowchart of a method for creating a native substrate for assembly from a substrate having a sacrificial layer according to an embodiment of the present invention; [Figures 49A to 49F] depict cross-sectional views of creating a native substrate for assembly from a substrate having a sacrificial layer using the steps described in Figure 48 according to an embodiment of the present invention; [Figures 50A to 50C] illustrate an exemplary yield management process according to an embodiment of this case; [Figures 51A to 51D] illustrate an exemplary method for creating cutting and alignment marks according to an embodiment of this invention; [Figure 52A] illustrates the localization of a field picked up on a transfer chuck to a stable reference grid according to an embodiment of this invention; [Figure 52B] illustrates the positioning of a complex adaptive chuck module relative to a stable reference grid according to an embodiment of this invention; [Figures 53A and 53B] illustrate an exemplary method for cutting using an inkjet catalyst based on metal-assisted catalytic etching (MACE) according to an embodiment of the present invention; [Figures 54A and 54B] illustrate an alternative exemplary method for cutting using an inkjet catalyst-based metal-assisted catalytic etching according to an embodiment of the present invention; [Figures 55A and 55B] illustrate an exemplary method for backside grinding after substrate cutting according to an embodiment of the present invention; [Figure 56] illustrates an exemplary method for creating grain cuts in a native substrate prior to backside grinding, according to an embodiment of the present invention; [Figure 57] is a flowchart of a method for creating metal fractures in substrate cutting using metal-assisted chemical etching according to an embodiment of this case; [Figures 58A to 58C] depict cross-sectional views of creating metal fractures in a substrate cutting process using metal-assisted chemical etching according to an embodiment of the present invention, following the steps described in Figure 57; [Figure 59] is a flowchart of a method for patterning a catalyst using selective atomic layer deposition (ALD) according to an embodiment of the present invention, wherein the catalyst is part of an "anti-collapse cap"; [Figures 60A to 60E] depict cross-sectional views of a catalyst patterned using selective atomic layer deposition according to an embodiment of the present invention, with the catalyst being part of a "collapse-resistant cap" as described in Figure 59; [Figure 61] is a flowchart of a method for creating anti-collapse caps and catalyst patterning by directional deposition and atomic layer etching of catalyst according to an embodiment of the present invention; [Figures 62A to 62D] depict cross-sectional views of creating a collapse-resistant cap and a catalyst patterning by means of directional deposition and atomic layer etching of the catalyst according to an embodiment of the present invention, using the steps described in Figure 61; [Figures 63A to 63D] illustrate the drift of the isolation catalyst during CICE according to an embodiment of the present invention; [Figures 64A to 64D] illustrate exemplary geometric structures for stabilizing patterns or support structures according to an embodiment of the present invention; [Figure 65] is a flowchart of a method for manufacturing isolated catalyst sites with circular catalyst walls using ruthenium (Ru) as a catalyst according to an embodiment of this invention; [Figures 66A to 66E] depict cross-sectional views of the fabrication of isolated catalyst points with circular catalyst support walls using ruthenium as a catalyst according to an embodiment of the present invention, following the steps described in Figure 65; [Figures 67A to 67E] depict a top view of the fabrication of isolated catalyst points with circular catalyst support walls using ruthenium as a catalyst according to an embodiment of the present invention, following the steps described in Figure 65; [Figure 68A] illustrates a catalyst according to an embodiment of the present invention and a nanostructure composed of porous silicon; [Figure 68B] illustrates a catalyst according to an embodiment of the present invention and a nanostructure composed of alternating layers of porous and non-porous silicon; [Figures 69A to 69D] illustrate the removal of silicon buttresses ("stabilization pattern") ("catalyst buttresses") after CICE using an isolation catalyst with buttresses to prevent drift, according to an embodiment of this invention; [Figures 70A to 70C] illustrate a design for a collapsed column according to an embodiment of the present invention, which is designed to inevitably collapse in a specific direction, for example by placing the buttress pattern toward the etched side; [Figure 71] is a flowchart of a method for manufacturing line / space patterns with lithographic links using CICE according to an embodiment of this case; [Figure 72] shows a top view of the desired line / space pattern using the steps described in Figure 71 according to an embodiment of this case; [Figures 73A to 73C] depict cross-sectional views of a line / space pattern with lithographic links fabricated using CICE according to an embodiment of the present invention, following the steps described in Figure 71; [Figures 74A and 74B] show an exemplary polycrystalline silicon nanowire array fabricated using CICE with gold as a catalyst according to an embodiment of this invention; [Figure 75] shows an exemplary geometry for converting silicon fins into pores using atomic layer deposition of silicon oxide according to an embodiment of this invention; [Figure 76] is a flowchart of a method for using CICE tone reversal process according to an embodiment of this case. [Figures 77A to 77D] depict a top view of a hue inversion process using CICE according to an embodiment of the present invention, following the steps described in Figure 76; [Figures 78A to 78D] depict cross-sectional views of a hue inversion process using CICE according to an embodiment of the present invention, following the steps described in Figure 76; [Figure 79] illustrates a method for performing a tone inversion process using polysilicon CICE according to an embodiment of this invention, which includes catalyst removal using selective chemical etching; [Figures 80A to 80D] depict a top view of a tone inversion process performed using polysilicon CICE according to an embodiment of the present invention, following the steps described in Figure 79, which includes catalyst removal using selective chemical etching; [Figures 81A to 81F] depict cross-sectional views of a tone inversion process performed using polysilicon CICE according to an embodiment of the present invention, following the steps described in Figure 79, which includes catalyst removal using selective chemical etching; [Figure 82] is a flowchart of a method for performing a tone inversion process using polysilicon CICE according to an embodiment of the present invention, which includes the removal of a catalyst using selective chemical etching, wherein the etch stop layer is removed in the final apparatus; [Figures 83A to 83D] depict a top view of a tone inversion process performed using polysilicon CICE according to an embodiment of the present invention, following the steps described in Figure 82, which includes catalyst removal using selective chemical etching, wherein the etch stop layer is removed in the final apparatus; [Figures 84A to 84G] depict cross-sectional views of a tone inversion process performed using polysilicon CICE according to an embodiment of the present invention, with the steps described in Figure 82, including catalyst removal using selective chemical etching, wherein the etch stop layer is removed in the final apparatus; [Figure 85] is a flowchart of a method for manufacturing metal interconnects and vias using a polysilicon CICE color-inverting process according to an embodiment of this invention; [Figures 86A to 86F] depict a top view of the fabrication of metal interconnects and vias using a polysilicon CICE color-inverting process according to an embodiment of this invention, following the steps described in Figure 85; [Figures 87A to 87L] depict cross-sectional views of metal interconnects and vias fabricated using a polysilicon CICE color-inverting process according to an embodiment of the present invention, following the steps described in Figure 85; [Figure 88] is a flowchart of a method for forming a CICE with inverted hue and a selectively grown superlattice according to an embodiment of the present invention; [Figures 89A to 89D] depict a top view of the formation of a superlattice with inverted CICE and selective growth according to an embodiment of the present invention, following the steps described in Figure 88; [Figures 90A to 90D] depict cross-sectional views of the formation of a superlattice with inverted CICE and selective growth according to an embodiment of the present invention, following the steps described in Figure 88; [Figure 91] is a flowchart of a method for manufacturing a silicon wafer using a deterministic lateral displacement (DLD) device according to an embodiment of this invention; [Figures 92A to 92G] depict cross-sectional views of a deterministic lateral displacement device for silicon wafer separation using CICE, following the steps described in Figure 91, according to an embodiment of this invention; [Figure 93] is a flowchart of a method for creating a DLD device by joining a cover plate to a DLD column after a CICE without causing the column to collapse, according to an embodiment of this case; [Figures 94A to 94E] depict cross-sectional views of joining a cover plate to a DLD column after a CICE without causing column collapse, according to an embodiment of the present invention, using the steps described in Figure 93, to create a DLD device; [Figure 95] is a flowchart of a method for increasing column height using porous stabilizing materials according to an embodiment of this case; [Figures 96A to 96C] depict cross-sectional views of increasing the column height using a porous stabilizing material according to an embodiment of the present invention, following the steps described in Figure 95; [Figure 97] is a flowchart of a method for engaging a cover plate for a DLD device after a CICE without causing column collapse, according to an embodiment of this invention; [Figures 98A to 98D] depict cross-sectional views of the joining of a cover plate for a DLD device after the CICE process without causing column collapse, according to an embodiment of the present invention, following the steps described in Figure 97; [Figure 99] is a flowchart of a method for improving the collapse of a thin column by starting with a thick column and reducing the column size after the cover plate is joined, according to an embodiment of the present invention; [Figures 100A to 100D] depict cross-sectional views illustrating the steps described in Figure 99 according to an embodiment of the present invention, starting with a thick column and reducing the column size after the cap plate is joined to improve the collapse of a thin column; [Figure 101] is a flowchart of a method for manufacturing a multi-stacked DLD device using polycrystalline silicon CICE according to an embodiment of this invention; [Figures 102A to 102F] depict cross-sectional views of a CICE fabrication of a multi-stacked DLD device using polycrystalline silicon according to an embodiment of the present invention, following the steps described in Figure 101; [Figure 103] shows a cross-sectional view of a multi-stacked DLD device for improving overall yield in the nano-region according to an embodiment of the present invention; [Figure 104] illustrates a metasurface according to an embodiment of the present invention, comprising an array of four pillars using silicon nanopillars manufactured by CICE and porous silicon nanopillars of oxide to focus light of different wavelengths; [Figure 105] illustrates an exemplary 3D stacked image sensor according to an embodiment of the present invention; and [Figure 106] shows an exemplary petal-shaped imager die according to an embodiment of the present invention. Implementation

[0019] As described in the prior art section, in semiconductor device manufacturing, etching refers to any technique that selectively removes material from a thin film on a substrate (with or without a prior structure on its surface) and creates a pattern of that material on the substrate through this removal. This pattern can be defined by a mask for an etch-resistant process. Once the mask is in place, the material not protected by the mask can be etched using wet chemical or "dry" physical methods.

[0020] One type of etching is catalyst-influenced chemical etching (CICE), a catalyst-based etching method used to create complex features in semiconductors such as silicon and germanium. These features possess high aspect ratios, low sidewall slopes, low sidewall roughness, and / or controllable porosity. This method is used to create higher density and more efficient static random access memory (SRAM) and low-loss waveguides.

[0021] Unfortunately, there are currently limitations in using CICE to fabricate features in semiconductors.

[0022] The principle of this invention provides a means of using the catalyst of this invention to influence chemical etching equipment and process technology to efficiently manufacture features in semiconductors using this CICE process.

[0023] Referring now to the drawings, Figure 1 illustrates an exemplary tool 100 for picking up and placing components according to an embodiment of this invention.

[0024] As shown in Figure 1, the tool 100 includes a nano-travel xy platform 101 to support a native substrate chuck 102 (for holding a native substrate 103) and a product substrate chuck 104 (for holding a product substrate 105).

[0025] The tool 100 further includes a precision pick-and-place module frame 106 for supporting the short-stroke XY platform 107. Additionally, as shown in FIG1, the tool 100 includes a selective metering module 108 on the short-stroke XY platform 107. Furthermore, the tool 100 includes a voice coil 109, a plasma unit 110, and a transfer chuck (TC) 111, which, as shown in FIG1, has picked up a subset of the field 112 from the native substrate 103.

[0026] Furthermore, as shown in Figure 1, a monomerization field 113 is left on the original substrate 103, wherein the field 114 contains known defective grains.

[0027] Additionally, as shown in Figure 1, layer 1 (element 115) with field 1 of product substrate 105 has been assembled.

[0028] Furthermore, Figure 1 specifically illustrates an exemplary tool 100 for pick-and-place assembly of fields from one or more native substrates 103 to a product substrate 105. As used herein, a "field" refers to the largest continuous portion of a substrate resulting after substrate dicing. A field may include one or more dies, wafers, or devices. In one embodiment, each native substrate 103 comprises a single type of field. In another embodiment, the native substrate 103 comprises multiple types of fields. In one embodiment, the size of a field in the native substrate 103 may range from 0.5 mm on one side to up to 200 mm on one side.

[0029] In one embodiment, the tool 100 for picking up and placing assembly incorporates one or more of the following components: native substrate chuck 102, product substrate chuck 104, intermediate substrate chuck (holding an intermediate substrate) (not shown in FIG1), transfer chuck 111, plasma unit 110 for pre-bonding surface activation, and metrology module (MM) 108.

[0030] Referring now to Figures 2A-2B and 3, Figures 2A-2B illustrate an exemplary design for a native substrate chuck / product substrate chuck / intermediate substrate chuck according to an embodiment of the present invention. Figure 3 illustrates an exemplary design of a native substrate chuck, such as native substrate chuck 102, having an array of extreme ultraviolet light-emitting diodes for field release according to an embodiment of the present invention.

[0031] As shown in Figure 2A, a transparent native / product / intermediate substrate 201 contacts a portion of a contact chuck 202 (representing a native substrate chuck 102, a product substrate chuck 104, or an intermediate substrate chuck). In one embodiment, such a substrate 201 includes a wafer 203.

[0032] In one embodiment, the native / product / intermediate substrate chuck 202 includes a selective light source 204 for field release (e.g., fiber-optic based) via an optical path 205. Additionally, in one embodiment, the native / product / intermediate substrate chuck 202 includes a selective imager 206 for real-time measurement. Furthermore, in another embodiment, the native / product / intermediate substrate chuck 202 includes a selective light source 207 for thermal actuation, a DMD assembly 208, and another selective light source 209 for field release (e.g., fiber-optic based).

[0033] In addition, in one embodiment, the native / product / intermediate substrate chuck 202 includes a selective projector 210 for projecting optical signals and another selective imager 211 for real-time measurement.

[0034] In another embodiment, the native / product / intermediate substrate chuck 202 includes a set of selective thermoelectric coolers 212, a selectively transparent, thermally conductive printed circuit board (PCB) 213, and a cooling assembly 214 with a transparent cover.

[0035] As shown in Figure 2B, Figure 2B illustrates a top view of an exemplary optional photonic waveguide substrate 215. This substrate 215 includes an external coupling grating 216 and an internal coupling grating 217. Additionally, Figure 2B shows that the photonic waveguide substrate 215 includes a two-dimensional photonic crystal path 218 for in-plane light transmission.

[0036] In addition, as shown in FIG3, the native substrate chuck 102 includes a selectively addressable ultraviolet (UV) light-emitting diode (LED) array 301 and a selective cooling system component 302.

[0037] The following discussion, in conjunction with Figure 1, provides further insights into Figures 2A-2B and 3.

[0038] In one embodiment, the primary function of the substrate chuck 202 is to maintain the native / product / intermediate substrates in a thermomechanically stable state during field assembly and to change the thermomechanical state of these substrates in a controlled manner (if necessary).

[0039] In one embodiment, the substrate chuck 202 is constructed using one or more of the following groups: silicon carbide (SiC), sapphire, fused silica, glass, silicon, or a flexible substrate (e.g., polycarbonate). In one embodiment, the substrate contact surface of the chuck is coated with a rigid material, such as one or more of the following groups: silicon nitride (SiN), silicon carbide, etc.

[0040] In one embodiment, one or more substrate chucks 202 have transparent portions. These transparent portions (in the relevant spectrum) allow light transmission through the chuck to facilitate field release / temporary bonding from / to the substrate and / or metering via the chuck. Light-based field release solutions are commercially available. Light is incident from the bottom surface of the substrate chuck 202, or alternatively from the side or a combination of both. In one embodiment, a waveguide-based solution is used to guide light from one side of the substrate chuck 202 to the bottom surface of the substrate. If the minimum feature size required in the waveguide substrate is greater than 100 nanometers (nm), the substrate can be patterned using a direct writing method (e.g., laser direct writing). If the minimum feature size is less than 100 nm, patterning can be performed using nanoimprint lithography (NIL) and a limited number of calibrated NIL templates. The calibration template can consist of quantized patterned patches, such as 1 mm vertical waveguide channels, 1 mm horizontal waveguide channels, +90° waveguide channels, -90° waveguide channels, etc. These can be used to pattern any custom waveguide pattern from the outer coupling grating 216 to the inner coupling grating 217. In one embodiment, the inner coupling grating 217 is placed peripherally, and this periphery satisfies the quantization X and Y separation constraint imposed by the quantized waveguide patch. In another embodiment, an addressable ultraviolet light-emitting diode array is used for field release from the native substrate 103.

[0041] In one embodiment, one or more substrate chucks 202 are combined with a metering module (e.g., metering module 108) to allow for on-the-fly metering.

[0042] In one embodiment, one or more substrate chucks 202 have embedded or other forms of thermal actuators. The thermal actuators can be used to control one or more of the following groups: temperature, field deformation, and field topography on the native / product / intermediate substrate. In one embodiment, an array of thermoelectric coolers (TECs) can be used to perform thermal actuation. A heat exchanger can be used to exchange heat with the thermal actuator. In one embodiment, the heat exchanger uses a liquid, such as water, as the working fluid. In one embodiment, the thermal actuator is mounted on a thermally conductive printed circuit board 213. In one embodiment, the printed circuit board 213 is transparent.

[0043] In another embodiment, thermal actuation is performed using incident spatially modulated radiation absorbed by the native / product / intermediate substrate, for example, using one or more digital micromirror devices (DMDs). The radiation may combine one or more of the following groups: short wavelength infrared radiation (SWIR), middle wavelength infrared radiation (MWIR), and long wavelength infrared radiation (LWIR).

[0044] In one embodiment, one or more substrate chucks 202 are inert to the native substrate sacrificial layer etchant. In another embodiment, one or more chucks 202 may be coated with a material inert to the sacrificial layer etchant, such as PTFE, high-density polyethylene (HDPE), etc.

[0045] In one embodiment, one or more native substrate chucks 102 are mounted on a motion platform. In another embodiment, one or more native substrate chucks 102 are mounted on a motion platform that moves independently of an n-MASC tool (a tool for nanoscale modular assembly of semiconductor wafers).

[0046] In one embodiment, the n-MASC tool incorporates multiple substrate chucks 202 to simultaneously process and / or process multiple native / product / intermediate substrates, each of which can move independently.

[0047] Referring now to Figures 4A through 4E, which show details of the exemplary transfer chuck 111.

[0048] As shown in Figure 4A, Figure 4A illustrates a transfer chuck 111 with an attached field 401 according to an embodiment of the present invention.

[0049] A cross-sectional view of the transfer chuck 111 according to an embodiment of this case is shown in FIG4B.

[0050] Referring to Figure 4B, the transfer chuck 111 includes silicon selective microfabrication needles 402, for example, to connect a fixed thermal actuator layer to a movable thermal actuator arm. In one embodiment, such microfabrication needles 402 have a diameter of 2 micrometers (µm) and a height of 10 micrometers.

[0051] In one embodiment, the transfer chuck 111 includes a heat exchanger fluid 403 and a thermally conductive printed circuit board 404. Furthermore, in one embodiment, the transfer chuck 111 includes a heat exchanger layer 405 and a thermal actuator layer 406, which may include a thermoelectric cooler 407. Additionally, in one embodiment, the transfer chuck 111 includes an xy actuator layer 408. In one embodiment, the xy actuator layer 408 is made of stainless steel. In one embodiment, the xy actuator layer 408 has a thickness of 5 mm. A top view of such an xy actuator layer 408 according to an embodiment of the present invention is shown in FIG. 4C.

[0052] Referring to Figure 4C, the xy actuator layer 408 includes a bending portion 409, a fixed portion 410, and a moving portion 411.

[0053] Referring again to Figure 4B, the transfer chuck 111 further includes a pneumatic valve and an xy-bending layer 412. This layer 412 includes a selectively soft layer 413 (e.g., polymer) that creates a valve seal within the pneumatic valve layer 412. Additionally, this layer 412 includes, for example, a flow valve 414 that can be electrostatically actuated.

[0054] A top view of a pneumatic valve layer 412 according to an embodiment of this invention is shown in FIG. 4D. As shown in FIG. 4D, the pneumatic valve layer 412 includes a fixed portion 415 and a movable portion 416. Furthermore, as shown in FIG. 4D, the pneumatic valve layer 412 includes an xy bend 417. In one embodiment, this xy bend 417 can be used to transfer vacuum and pressure from the fixed portion 415 to the movable portion 416.

[0055] Further schematic representations of an alternative top view of a pneumatic valve layer 412 according to an embodiment of this invention are shown in FIG. 4E. As shown in FIG. 4E, the pneumatic valve layer 412 includes an exemplary actuation grid 418, a selective pressure line 419, a selective vacuum source 420 at the layer edge, a selective pressure source 421, and a selective vacuum line 422. As shown in FIG. 4E, the pneumatic valve layer 412 may include vacuum and pressure distribution lines from the edge of the layer to each actuation unit. In one embodiment, the pressure and vacuum originate from channels etched into the layer substrate. In one embodiment, the vacuum and pressure distribution lines are located on different sides of the same substrate.

[0056] Referring again to FIG4B, in one embodiment, the transfer chuck 111 includes a Z-shaped bend layer 423 (two adhesive layers to form internal fluid channels). In one embodiment, each layer of the internal fluid channels has a thickness of 0.25 mm. In one embodiment, the Z-shaped bend layer 423 includes a Z-shaped bend 424.

[0057] In another embodiment, the transfer chuck includes a pressure manifold layer 425 for bending fields. In one embodiment, layer 425 has a thickness of 0.3 mm. In one embodiment, the pressure manifold layer 425 includes selective pressure lines 426.

[0058] Furthermore, in one embodiment, the transfer chuck 111 includes a vacuum adsorption layer 427. In one embodiment, the vacuum adsorption layer 427 has a thickness of 0.3 mm.

[0059] Additionally, Figure 4B shows the field contact pin 428. In one embodiment, this pin can be selectively coated with a hard material, such as SiN, SiC, etc. Furthermore, Figure 4B shows the field 401 and the selective vacuum line 429. Finally, Figure 4B shows the gap 430 between the actuation unit boundary and the xy movable layer.

[0060] Furthermore, as shown in Figure 4B, in one embodiment, during the fabrication of the transfer chuck, the lighter shaded areas may be filled with a sacrificial material, such as SiO2. In one embodiment, these areas provide structural stability during operations such as polishing the transfer chuck pins, but can be etched away, for example, using vapor HF after the transfer chuck 111 has been fabricated.

[0061] Additionally, as shown in Figure 4B, in one embodiment, the areas with darker shadows can be made of silicon.

[0062] Referring now to FIG5A, FIG5A shows an exemplary diagram of a transfer chuck 111 comprising a customized layer for each new field type according to an embodiment of the present invention.

[0063] As shown in Figure 5A, the transfer chuck (TC) 111 may optionally include a vacuum supply 501 in the transfer chuck vacuum manifold. Furthermore, as shown in Figure 5A, the transfer chuck 111 may optionally be secured to the frame 106 using annular contact points 502 around its perimeter.

[0064] Figure 5B shows an enlarged view of a transfer chuck 111 containing a custom layer for each new field type according to an embodiment of the present invention.

[0065] As shown in Figure 5B, the transfer chuck 111 includes a primary vacuum manifold 503 and a secondary vacuum manifold 504. In one embodiment, the primary and secondary vacuum manifolds 503 and 504 are selectively combined, for example, as shown at element 505.

[0066] In one embodiment, the transfer chuck 111 does not have a vacuum supply in areas where the assembly field will not be used, such as at element 506.

[0067] In one embodiment, the primary and secondary vacuum manifolds 503 and 504 are selectively designed in such a way that the needle does not interfere with the waveguide multilayer memory (WMM) beam path, for example as shown at element 507.

[0068] Furthermore, in one embodiment, the transfer chuck 111 includes a vacuum section 508 in the secondary vacuum manifold 504 that maintains the field to the manifold needle.

[0069] Additionally, Figure 5B shows an exemplary airflow direction 509.

[0070] In one embodiment, the secondary vacuum manifold 504 is manufactured from a standard silicon substrate. In another embodiment, the primary vacuum manifold 503 is manufactured using a thick silicon substrate to provide additional structural strength to resist gravity-induced sagging.

[0071] Referring now to FIG6A, FIG6A shows an exemplary transfer chuck 111 composed of compliant pins according to an embodiment of the present invention.

[0072] As shown in Figure 6A, the transfer chuck 111 includes a top metal layer 601 and a back transistor layer 602, and has an nMASC field 603 (multilayer Al2O3-SiO2 combination) between layers 601 and 602. Furthermore, as shown in Figure 6A, an exemplary particle 604 is located on the surface of the top metal layer 601.

[0073] An enlarged view of a portion of the top metal layer 601 according to an embodiment of the present invention is shown in FIG. 6B. FIG. 6C shows an enlarged view of a thin skin 605 located on the bottom of the top metal layer 601 as shown in FIG. 6B, according to an embodiment of the present invention.

[0074] The following provides a discussion of Figures 4A to 4E, Figures 5A to 5B, and Figures 6A to 6C.

[0075] The main function of the transfer chuck 111 is to pick up one or more fields from the native / product / intermediate substrate or place one or more fields onto the native / product / intermediate substrate in a thermomechanically stable manner, and to change the thermomechanical state of the fields in a controlled manner (if necessary).

[0076] In one embodiment, one or more transfer chucks 111 are constructed using one or more of the following group: silicon carbide (SiC), sapphire, fused silica, glass, silicon, flexible substrate (e.g., polycarbonate, etc.). In one embodiment, the substrate contact surfaces of one or more transfer chucks 111 are coated with a rigid material (e.g., silicon nitride (SiN), silicon carbide, etc.).

[0077] In one embodiment, one or more transfer chucks 111 have transparent portions. These transparent portions (in the relevant spectrum) allow light transmission through the transfer chucks to facilitate field release / temporary bonding from / to the substrate and / or metering via the transfer chucks. Light may be incident from the bottom surface of the substrate chuck, or alternatively from the side or a combination of both. In one embodiment, a waveguide-based solution is used to guide light from one side of the substrate chuck to the bottom surface of the substrate.

[0078] In one embodiment, the chuck, such as the transfer chuck 111, incorporates one or more metal layers, such as metal layer 601. The metal layer, such as metal layer 601, can provide structural stability to the transfer chuck 111. The metal layer, such as metal layer 601, can be processed using macroscopic processing techniques (e.g., computerized numerical control (CNC) machining). In one embodiment, the metal layer, such as metal layer 601, is made of a material with high thermal expansion. In one embodiment, the metal layer, such as metal layer 601, is made of a material with low thermal conductivity. In one embodiment, the metal layer, such as metal layer 601, is made of stainless steel.

[0079] In one embodiment, the transfer chuck 111 is coupled with a thick substrate (e.g., thick silicon, thick sapphire) with a thickness of 0.755 mm or more. This thick substrate can be used to provide structural stability for the transfer chuck 111.

[0080] In one embodiment, the transfer chuck 111 incorporates multiple layers to facilitate bonding of various TC layers (e.g., chromium films, polymer films, adhesive polymer films, etc.).

[0081] In one embodiment, the transfer chuck 111 incorporates multiple layers to prevent the n-MASC tool assembly (including the TC sub-assembly) from being contaminated by the sacrificial layer etchant (e.g., a chromium film, a polymer film, an adhesive polymer film, etc.).

[0082] In one embodiment, the multiple layers constituting the transfer chuck 111 are joined together using one or more of the following groups: anodic bonding, fusion bonding, hybrid bonding, air suction, adhesive, etc.

[0083] In one embodiment, the transfer chuck 111 utilizes vacuum suction to maintain the field 401. In one embodiment, the transfer chuck 111 incorporates an integrated valve assembly to turn the vacuum suction for each pickup field on and off. The transfer chuck 111 may also incorporate an integrated valve assembly to turn the pressure source corresponding to each pickup field on and off. The pressure source can be used to form a thin fluid lubricating layer before field pickup or field engagement. Deep etching processes, such as metal-assisted chemical etching (MACE), deep reactive ion etching (DRIE), etc., can be used to create the enabling vacuum and pressure supply for the holes and grooves required for the pickup fields. Furthermore, the transfer chuck 111 utilizes bending mechanisms machined into one or more TC layers to provide pressure and vacuum from the moving portion of the transfer chuck 111 to the stationary portion of the transfer chuck 111.

[0084] In one embodiment, the valve assembly (for opening and closing pressure / vacuum) comprises a transfer chuck with holes, a flexible diaphragm (e.g., made of a polymer), a diaphragm actuation mechanism (e.g., a voice coil and a magnetically sensitive material deposited or attached to the flexible diaphragm), and a relay (e.g., using a transistor) for opening and closing the valve mechanism. In one embodiment, the actuation mechanism utilizes thermal expansion.

[0085] In one embodiment, the transfer chuck 111 incorporates a porous layer to create a vacuum suction force in the field 401. In another embodiment, the transfer chuck 111 incorporates a layer having a hybrid porous and non-porous structure to create a vacuum suction force in the field 401.

[0086] In one embodiment, the transfer chuck 111 uses electrostatic force to hold the field 401. In another embodiment, the transfer chuck uses a Johnsen-Rahbek type electrostatic chuck to hold the field 401 only where it contacts the transfer chuck 111. In one embodiment, the chuck mechanism incorporates a switch array to adjust the electrostatic holding force. In one embodiment, the switch array is addressed using multiplexer electronics.

[0087] In one embodiment, the transfer chuck 111 utilizes an adhesive to retain the field 401. In another embodiment, the transfer chuck 111 utilizes a UV-release adhesive to retain the field 401.

[0088] In one embodiment, the transfer chuck 111 uses an array of needles, such as needles 428, to contact the field 401. The needles may be in the shape of a truncated cone. The needles may have one or more holes from which a vacuum or pressure originates. In another embodiment, the transfer chuck 111 uses a ring array to contact the field 401. The ring region may contain one or more holes to obtain a vacuum or pressure.

[0089] In one embodiment, the needle, such as needle 428, is aligned with the Z-axis.

[0090] In one embodiment, the transfer chuck contact surfaces are polished after the transfer chuck 111 is assembled. Any grooves in the TC layer may be filled with a fluid-etchable layer, such as silicon oxide (which can be etched using vapor HF). The fluid-etchable layer may be etched away after polishing.

[0091] In one embodiment, the transfer chuck 111 incorporates an integrated mechanical actuator (e.g., one or more piezoelectric actuators, thermal actuators, electrostatic actuators, etc.) to actuate one or more pick-up fields 401 in the X, Y, and / or θ axes. In one embodiment, the transfer chuck 111 incorporates a bending layer to facilitate in-plane movement of the field 401 and specific portions of the transfer chuck 111. In one embodiment, a thermal actuator is used to actuate the in-plane movement by appropriate heating and cooling of the bending arm. An array of thermoelectric elements can be used to generate thermal actuation of the bending arm. In one embodiment, the thermoelectric elements are used to transfer heat to the bending portion using an array of flexible pillars. Alternatively, the thermoelectric elements are used to transfer heat to the bending portion using a thin, low-friction material (e.g., a film of polytetrafluoroethylene (PTFE), a film of thermal paste, etc.). In another embodiment, thermal actuation of the bending arm is performed using spatially modulated radiation absorbed by the bending arm, for example, by using one or more digital micromirror devices (DMDs). In one embodiment, the piezoelectric transducer is regionally positioned around field 401 (arranged in a checkerboard pattern) to perform in-plane actuation of field 401. In one embodiment, thermal actuation is performed in a timing manner, wherein the desired control is maintained at a certain time ta after the thermal actuation begins and for a duration ∆ta.

[0092] In one embodiment, the integrated mechanical actuator described above is used to correct one or more components of a first-order stacking error. In another embodiment, the integrated mechanical actuator described above is used to correct one or more components of a higher-order stacking error.

[0093] In one embodiment, the transfer chuck 111 incorporates a pressurizable region to form an arc shape in the field 401 prior to engagement. In another embodiment, the transfer chuck 111 incorporates a pressurizable region to actuate the field 401 along the z-axis.

[0094] In one embodiment, the transfer chuck 111 incorporates one or more heat exchanger layers, such as heat exchanger layer 405, to transfer excess heat or cold from the transfer chuck 111.

[0095] In one embodiment, the transfer chuck 111 incorporates one or more layers that incorporate a curved portion constrained to move along the z-axis. The curved portion may have a range of motion of 10 micrometers or greater. In one embodiment, the curved portion is actuated using a thermal actuator, a piezoelectric actuator, and / or a pneumatic actuator.

[0096] In one embodiment, the thickness variation of field 401 is actively sensed. In another embodiment, the thickness variation of field 401 is sensed using a barometer.

[0097] In one embodiment, the transfer chuck 111 has an optically clear path to allow for instantaneous measurement via the transfer chuck 111. In another embodiment, the transfer chuck 111 has an optically clear path for infrared radiation.

[0098] In one embodiment, one or more custom transfer chucks 111 are used for each new field design, wherein the TC actuator grid (defined by an array of repeating actuator groups, each actuator group being used to actuate a single field of a preset size) matches the field size. In one embodiment, the custom transfer chucks 111 can be exchanged using a robotic arm and lifting pins.

[0099] In one embodiment, a transfer chuck 111 with a fixed grid (corresponding to a preset field size) is suitable for assembling fields of different sizes. The algorithm for achieving this is described below. l defines the boundary region W∈ [R, 2 ], which can be a circle with a diameter dsubstrate. l defines the following two blocks: A Tactuator is a set of tiles, each tile being of size (widthactuator, heightactuator), such that the Tactuator is nested within W. Tiles in the Tactuator can be transformed into a group between X and Y. Tfield is a set of tiles, each tile having a size of (widthfield, heightfield), such that Tfield is tessellated within W. For a given set of labels n, all tiles in Tfield are labeled such that the set of tiles shares a single label, the center-to-center distance between each field and its nearest tile in the Tactuator is minimized, and is completely below (widthactuator – widthfield) / 2 along the X-axis and completely below (heightactuator – heightfield) / 2 along the Y-axis. This labeling is established as follows: First, generate m0 random assignments of n labels for the tiles in Tfield, and examine each random assignment. The maximum center-to-center distance across all fields belonging to a label is determined by sliding the actuator tiles along the X and Y axes by small, fixed amounts until the region of (widthactuator, heightactuator) is covered. Then, a heuristic optimizer, such as a minimizer of a genetic algorithm type, is used to generate better label assignments, where the label assignments are crossovered, mutated, and selected as the minimum of the maximum center-to-center distance. l Run an overarching heuristic optimizer that minimizes the label set n.

[0100] One such label is shown in Figure 7 and will be discussed below.

[0101] Figure 7 shows an exemplary marking of a field 401 in a rectangular boundary region 701 that can be assembled using an actuator mesh 702 with nine labels (nine assembly steps) according to an embodiment of the present invention.

[0102] In one embodiment, the transfer chuck 111 is held by a thin ring-shaped structure that contacts the transfer chuck 111 in an annular region etched into the side of the transfer chuck 111.

[0103] In one embodiment, the sacrificial layer etchant originates from holes in the transfer chuck 111 that pass through etch-inert portions of the transfer chuck 111. In another embodiment, the sacrificial layer etchant originates from silicon-based portions of the transfer chuck 111.

[0104] The following discussion is based on Figure 8. Figure 8 illustrates an exemplary process for assembling an intermediate substrate according to an embodiment of the present invention. In one embodiment, cascaded transfer chucks 111 are used to transfer a field 401 from one native / intermediate / product substrate 103 / 801 / 105 to different native / intermediate / product substrates 103 / 801 / 105.

[0105] In one embodiment, cascaded transfer chucks 111 are used to transfer fields from native substrate 103 to product substrate 105. One or more transfer chucks 111 pick up a subset of fields 401 from native substrate 103 and transfer them (e.g., in a field-by-field manner) to intermediate substrate 801, while ensuring that the spacing of the fields along the X-axis and along the Y-axis matches the X and Y spacing of the fields 401 in product substrate 105. In one embodiment, one or more transfer chucks 111 are used to flip the orientation of a subset of fields 401 from either native substrate 103 or intermediate substrate 801 such that the correct side faces the product substrate 105 for bonding. In one embodiment, one or more transfer chucks 111 perform overlap control and mixed bonding on the subset of fields 401 that are being assembled onto product substrate 105.

[0106] In another embodiment, cascaded transfer chucks 111 are used to transfer fields 401 from the native substrate 103 to the product substrate 105. One or more transfer chucks 111 pick up subsets of fields 401 from the native substrate 103 and transfer them row by row to the intermediate substrate 801, while ensuring that the spacing of the fields along the X-axis matches the spacing of the fields 401 in the product substrate 105. In one embodiment, one or more transfer chucks 111 pick up subsets of fields 401 from the intermediate substrate 801 and transfer them column by column to different intermediate substrates 801, while ensuring that the spacing of the fields along the Y-axis matches the spacing of the fields 401 in the product substrate 105. In one embodiment, one or more transfer chucks 111 are used to flip the orientation of a subset of fields 401 from either the native substrate 103 or the intermediate substrate 801 such that the correct side faces the product substrate 105 for bonding. In one embodiment, one or more transfer chucks 111 perform stacking control and hybrid bonding on a subset of fields 401 that are assembled onto the product substrate 105.

[0107] In one embodiment, the interposer substrate 801 is made of silicon, silicon oxide, glass, polymer (e.g., polycarbonate), and / or sapphire. In one embodiment, the interposer substrate 801 has embedded metering marks. In one embodiment, the metering marks in the interposer substrate 801 are adapted to align the field to a known precision grid.

[0108] In one embodiment, the native substrate 103 is composed of monomerized fields on a diced tape frame. In one embodiment, the intermediate substrate 801 is composed of a glass substrate with embedded alignment marks. In one embodiment, a temporary bonding to the intermediate substrate 801 is performed using an inkjet UV-curable adhesive. Furthermore, in one embodiment, the final bonding is between the field 401 attached to the intermediate substrate 801 and the product substrate 105.

[0109] In one embodiment, the transfer chuck 111 is geometrically defined by a cylinder having a diameter of 300 mm. In another embodiment, the transfer chuck 111 is geometrically defined by a cuboid. In one embodiment, the transfer chuck 111 is defined by a cuboid with both sides greater than 300 mm.

[0110] Furthermore, as shown in FIG8, the native substrate 103 (identified as "native substrate 2") includes a downward-facing field 401. This field 401 is transferred to the intermediate substrate 801 by a transfer chuck 111. In one embodiment, an embedded alignment grid 802 is provided to help ensure that the spacing of the field along the X-axis and the spacing of the field along the Y-axis match the X and T spacings of the corresponding field 401 in the product substrate 105. In one embodiment, a selectively variable density adhesive 803 is provided to compensate for variations in field thickness.

[0111] Additionally, Figure 8 shows an exemplary field 401 from the native substrate 103 (identified as "native substrate 1"), which, as shown through element 804, has been assembled onto the product substrate 105. Furthermore, Figure 8 shows that the product substrate 105 is selectively plasma-treated, for example, prior to assembly.

[0112] Furthermore, Figure 8 shows an exemplary field 401 on the product substrate 105 from the native substrate 103 (identified as "native substrate 2"), as shown through element 805, where the product substrate 105 is selectively plasma-treated. Note that field 401 is face-up on the product substrate 105.

[0113] As shown through element 806, such field 401 of product substrate 105 is bonded to form assembled product substrate 105.

[0114] Referring now to FIG9, FIG9 shows an exemplary diagram of a plurality of transfer chucks 111 used during assembly according to an embodiment of the present invention.

[0115] As shown in Figure 9, multiple transfer chucks 111 are used in parallel to assemble fields representing dies 901 on the native wafer 902. In one embodiment, each transfer chuck 111 is used to pick up and assemble monolithic dies 901. Note that each transfer chuck 111 can be driven on the X, Y, and / or Z axes and has independently controllable pressure and vacuum supplies.

[0116] In one embodiment, a plurality of transfer chucks 111 are used to assemble fields 401 (e.g., dies 901) in parallel, wherein each transfer chuck 111 can pick up, stack, and join one or more fields 401. In one embodiment, a plurality of transfer chucks 111 are used to assemble fields 401 in parallel, wherein each transfer chuck 111 can pick up, stack, and join one field 401.

[0117] Referring now to FIG10, FIG10 illustrates an exemplary reconfigurable grid transfer chuck 111 (e.g., 300 mm x 300 mm) according to an embodiment of the present invention.

[0118] As shown in Figure 10, there is a pair of overlapping "base plates" 1001. These base plates may optionally be unconnected, which facilitates independent X and Y extensions. Furthermore, as shown in Figure 10, a Y reconfiguration array 1002 is optionally integrally manufactured. Link 1003 (darker shaded) is located in a different plane compared to the lighter shaded link 1004. The X reconfiguration array (not shown in Figure 10) can be manufactured separately and selectively overlapped on top of the Y reconfiguration array 1002.

[0119] Furthermore, Figure 10 shows an exemplary position 1005 for applying force to reconfigure the X grid of the transfer chuck. Additionally, Figure 10 shows an exemplary position 1006 for applying force to reconfigure the Y grid of the transfer chuck.

[0120] Additionally, Figure 10 shows a single actuation unit 1007 and a faulty actuation unit 1008 that can be replaced separately.

[0121] In one embodiment, a transfer chuck 111 with a reconfiguration actuation grid is used. In one embodiment, the reconfiguration mechanism is integrally manufactured. In one embodiment, the reconfiguration arrangement is constructed by stacking one or more layers, each layer being integrally manufactured. In one embodiment, the reconfiguration mechanism is manufactured using bulk metal, bulk polymer, thin coating, or any combination thereof. In one embodiment, the reconfiguration mechanism is manufactured using steel, stainless steel, chromium, or any combination thereof. In one embodiment, the reconfiguration mechanism consists of bending elements. In one embodiment, the bending elements are arranged to form a scissor mechanism between each pair of actuation units 1007. In one embodiment, separate reconfiguration mechanisms are used to extend along the X and Y directions. These mechanisms can be stacked on top of each other. Each mechanism can be actuated in one direction while being free to move in orthogonal directions. In one embodiment, actuation of the reconfiguration mechanism is generated using actuators (e.g., voice coil motors, piezoelectric actuators, thermal actuators, etc.) placed at one or more locations on or within the periphery of the reconfiguration mechanism. In one embodiment, the actuator is positioned on the axis of symmetry of the reconfiguration mechanism. In one embodiment, each actuation unit 1007 moves in the X and / or Y directions using one or more dedicated actuators. In one embodiment, a group of one or more actuation units moves in the X and / or Y directions using one or more actuator groups. In one embodiment, the reconfiguration mechanism is located on a fluid bearing. In one embodiment, the reconfiguration mechanism can be stepped and / or scanned across the associated substrate. In one embodiment, the reconfiguration grid is rectangular in shape, with its shorter arms smaller than the size of the native / product / intermediate substrate. In one embodiment, the reconfiguration grid is the shape of a single horizontal or vertical line of actuation units.

[0122] In one embodiment, the TC actuation unit 1007 is attached to a plate such that the spacing of the actuation units 1007 is an integer multiple of the field spacing on the native / product / intermediate substrate 103 / 105 / 801. The plate can be custom-manufactured for each new field design. The plate may have grooves or slots for positioning the actuation units 1007. In one embodiment, the plate has alignment features (e.g., pins) for aligning the actuation units 1007 on the X, Y, Z, θx, θy, and θz axes. In one embodiment, the actuation units 1007 are attached to the plate using adhesives, bending engagement mechanisms, magnets, electromagnets, vacuum, or any combination thereof.

[0123] Referring now to Figures 11A and 11B, Figures 11A and 11B illustrate an exemplary transfer chuck 111 with a closed-boundary vacuum and / or pressure region according to an embodiment of the present invention. Figures 12A and 12B illustrate an alternative embodiment of the exemplary transfer chuck 111 with a closed-boundary vacuum and / or pressure region according to an embodiment of the present invention. Figures 13A and 13C illustrate yet another alternative embodiment of the exemplary transfer chuck 111 with a closed-boundary vacuum and / or pressure region according to an embodiment of the present invention.

[0124] As shown in Figure 11A, there is a grid of transfer chuck 111 represented by transfer chuck assembly 1101 (identified as "ATC"). As further shown in Figure 11A, there is a selectively porous filtration membrane 1102 that filters particles in the airflow to prevent them from reaching the ATC (assembly of TCs) field interface. In addition, as shown in Figure 11A, there are pores 1103 in the filtration membrane 1102 for vacuum and / or pressure.

[0125] Additionally, as shown in Figure 11A, there is a needle 1104 for maintaining the field 401. In one embodiment, this needle 1104 may optionally taper at its bottom to reduce the contact area with the field 401.

[0126] Figure 11B shows the actual contact edge between the transfer chuck assembly 1101 and the field 401 of element 1105. Furthermore, Figure 11B shows a selective material 1106 for filling the vacuum orifice. For example, this material 1106 could be inkjet-based.

[0127] As shown in Figure 12A, a selectively porous filtration membrane 1102 filters particles in the airflow to prevent them from reaching the ATC field interface. Furthermore, as shown in Figure 12A, the filtration membrane 1102 contains pores 1103 that allow vacuum and / or pressure to pass through the thickness of the transfer chuck assembly 1101.

[0128] Furthermore, as shown in Figure 12A, there is a needle 1104 for maintaining the field 401. In one embodiment, this needle may optionally taper at its bottom to reduce the contact area with the field 401.

[0129] Additionally, as shown in Figure 12A, the filler material 1201 is dispensed and / or deposited on the top of the transfer chuck assembly 1101. This prevents the ATC field interface from being contaminated by this filler material 1201.

[0130] Furthermore, as shown in Figure 12A, ATC sub-assemblies 1202, such as thermal actuators, X / Y / Z bending sections, valve units, etc., are located around the vacuum / pressure port 1103.

[0131] Figure 12B shows the actual contact edge between the transfer chuck assembly 1101 and the field 401 of the element 1105.

[0132] As shown in Figure 13, in one embodiment, the top 1301 of the transfer chuck 111 can be attached to the bottom using vacuum suction and can be detached to cover the holes using inkjet printing.

[0133] In one embodiment, the bottom 1302 of the transfer chuck 111 (which contacts the picked-up grain) remains fixed. Furthermore, Figure 13A shows a hole 1103 for vacuum and a needle 1104 to hold the field 401. In one embodiment, this needle 1104 may optionally taper at its bottom to reduce the contact area with the field 401.

[0134] Furthermore, Figure 13A illustrates a selective porous filter membrane 1303 used to filter particles in an airflow to prevent them from reaching the TC field interface. In one embodiment, the porous filter membrane 1303 is made of porous silicon with a sub-100 nanometer pore size to serve as an effective medium. Alternatively, normally closed silicon cantilever arrays can be used to fabricate the porous filter membrane 1303.

[0135] In one embodiment, the top 1301 of the transfer chuck 111 can be restored to its preset unfilled state using wafer wet cleaning, UV cleaning, or the like. If the cleaning process is slow, multiple transfer chucks 111 can be used.

[0136] Figure 13B illustrates an inkjet printer 1304 dispensing UV-curable adhesive into a tapered aperture 1103. In one embodiment, to minimize surface area, the droplet can remain stably aloft at the top of the cone.

[0137] Figure 13C shows the filled vacuum hole 1103, as shown at element 1305.

[0138] Referring to Figures 11A-11B, 12A-12B, and 13A-13C, in one embodiment, the transfer chuck assembly 1101 has a closed-boundary vacuum and / or pressure region (compared to the conventional open-boundary vacuum region in a semiconductor pin chuck). The pin 1104 may have a tapered cross-section to reduce the contact area between the transfer chuck 111 and the pick-up field 401. The tapered shape can be created using etching techniques including crystal etching, isotropic etching, anisotropic etching (e.g., reactive ion etching), and any combination thereof. In one embodiment, the vacuum and / or pressure in the closed-boundary region is turned on or off by filling with a filling material 1201. An inkjet printer can be used to perform the filling. Alternatively, a masked plasma deposition process can be used to deposit the filling material 1201. In one embodiment, a mixture of SiLK-type volatile liquids and oxides is used for filling. The pore size of the porous oxide (remaining after the volatile components evaporate) can be optimized to minimize the flow through the oxide. The packing material 1201 can then be removed by plasma jetting, chemical etching (e.g., vapor HF), heating (to evaporate the packing material) to restore the transfer chuck 111 to its preset state, and any combination thereof. In one embodiment, the field size (X and / or Y) is limited to an integer multiple of the distance between the TC needles 1104. In one embodiment, the packing material dispenser is part of the pick-and-place tool. The transfer chuck 111 may further include a selectively porous diaphragm 1102, as shown in Figures 11A and 12A, to limit particle contamination from one part of the transfer chuck 111 to another. In one embodiment, the porous diaphragm 1102 may be made of a transparent (e.g., in IR radiation) porous polymer, porous silicon, or any combination thereof. The pore size of the porous membrane 1102 can be optimized to minimize airflow while simultaneously filtering out contaminants. Alternatively, a normally closed array of micromachined cantilevers placed on each vacuum / pressure pore 1103 can be used for contaminant filtration. These can be made of silicon, silicon oxide, transparent polymers, or any combination thereof. Optionally, the vacuum and / or pressure pores 1103 can have a conical geometry (partial or complete) such that the dispensed adhesive has a preferred residence site at the top of the conical geometry. The conical geometry can be constructed, for example, using crystal etching.

[0139] In one embodiment, a suction-generating layer (which contacts the pickup area) on the transfer chuck 111 may be custom-manufactured to match the grid of the pickup area 401. The custom suction-generating layer may be attached to the remainder of the transfer chuck 111 using vacuum suction, adhesives, electrostatic force, magnetic force, electromagnetic force, or any combination thereof.

[0140] In one embodiment, a plasma generating unit, such as plasma unit 110, is used to clean the bonding surfaces prior to bonding.

[0141] In one embodiment, the plasma generation unit, such as plasma unit 110, operates at atmospheric pressure. In another embodiment, the plasma generation unit is manufactured by Surfx® Technologies.

[0142] In one embodiment, plasma units, such as plasma unit 110, cover the entire area of ​​the native / product / intermediate substrate 103 / 105 / 801.

[0143] In one embodiment, plasma units are scanned over regions of native / product / intermediate substrates 103 / 105 / 801. Plasma units, such as plasma unit 110, may be mounted on a motion platform capable of traveling along the X, Y, and / or Z axes. In one embodiment, plasma units, such as plasma unit 110, are mounted on a retractable plate that retracts to avoid field 401 once plasma processing is complete.

[0144] In one embodiment, the plasma unit, such as plasma unit 110, faces upward to process the downward-facing field 401.

[0145] In one embodiment, the plasma unit, such as plasma unit 110, faces downward to process the upward-facing field 401.

[0146] In one embodiment, the upward-facing and downward-facing plasma heads are synchronized, such that when the upward-facing unit processes the downward-facing field 401, the downward-facing unit processes the upward-facing field 401.

[0147] In one embodiment, multiple native product / intermediate substrates 103 / 105 / 801 are plasma-processed in separate chambers of an n-MASC tool.

[0148] Referring now to FIG14, FIG14 illustrates an exemplary sensor arrangement for an exemplary metering module 108 according to an embodiment of the present invention.

[0149] As shown in Figure 14, the metrology module 108 includes an exemplary single interchangeable unit of the image sensor 1401. In one embodiment, the metrology module 108 has approximately 30 such units in total. In one embodiment, the image sensor 1401 may have a light-insensitive region surrounding the light-sensitive region.

[0150] Furthermore, as shown in FIG14, the metrology module 108 has an exemplary single "row" of imagers 1402. In one embodiment, the metrology module 108 has a total of approximately 2.5 rows of imagers. Additionally, FIG14 illustrates an exemplary scanning method for acquiring X and Y alignment data from all fields 401 picked up by the transfer chuck 111.

[0151] In one embodiment, the metering module 108 corresponds to a fully reconfigurable array of the 300 mm x 300 mm imager 1401.

[0152] In one embodiment, exemplary field 401 has a horizontal length of 25 mm and a vertical length of 30 mm. In one embodiment, field 401 has a total of up to eight alignment marks (four for X alignment and four for Y alignment). Furthermore, field 401 may have alignment marks in layer 0 or a cutout.

[0153] In one embodiment, the imaging device 1401 comprises short-wavelength infrared radiation sensors (SWIR) (e.g., Sony® IMX990-AABJ-C). In one embodiment, the metrology module 108 contains approximately 130 such sensors.

[0154] In one embodiment, an exemplary Y-scan for the metering module 108 travels approximately 300 mm. In one embodiment, an exemplary X-scan for the metering module 108 travels approximately 190 mm.

[0155] Referring now to Figure 15, Figure 15 illustrates an alternative exemplary sensor arrangement for an exemplary metering module 108 according to an embodiment of the present invention.

[0156] As shown in Figure 15, the metering module 108 includes exemplary interchangeable units of the imager 1401. In one embodiment, the metering module 108 has approximately 12 such units in total.

[0157] Furthermore, as shown in FIG15, the metering module 108 has an exemplary single "row" of imagers 1402. In one embodiment, the metering module 108 has only one row of imagers 1402.

[0158] In one embodiment, an exemplary Y-scan for the metering module 108 travels approximately 500 mm. In one embodiment, an exemplary X-scan for the metering module 108 travels approximately 3 x 190 mm (i.e., three X-scans of the metering module 108 are performed, each traveling 190 mm).

[0159] Figure 16 illustrates an exemplary reconfiguration grid sensor arrangement for an exemplary metering module 108 according to an embodiment of this case.

[0160] As shown in Figure 16, there may optionally be a pair of overlapping "base plates" 1601. These base plates 1601 may be selectively left unconnected, which facilitates independent X and Y expansion.

[0161] Furthermore, as shown in Figure 16, a Y-reconfiguration array 1602 is selectively integrally manufactured. Link 1603 (darker shaded) is located in a different plane compared to the lighter shaded link 1604. An X-reconfiguration array (not shown in Figure 16) can be manufactured separately and selectively overlapped on top of the Y-reconfiguration array 1602.

[0162] Furthermore, Figure 16 shows an exemplary position 1605 for applying a force to reconfigure the imager X grid. Additionally, Figure 16 shows an exemplary position 1606 for applying a force to reconfigure the imager Y grid.

[0163] Additionally, Figure 16 shows the fault imager 1401, which can be replaced separately.

[0164] In one embodiment, exemplary field 401 has a horizontal length of 20 mm and a vertical length of 20 mm. In one embodiment, field 401 has a total of up to eight alignment marks (four for X alignment and four for Y alignment).

[0165] In one embodiment, the imaging device 1401 comprises short-wavelength infrared radiation sensors (SWIR) (e.g., Sony® IMX990-AABJ-C). In one embodiment, the metrology module 108 contains approximately 20 such sensors.

[0166] In one embodiment, the metering module 108 corresponds to a fully reconfigurable array of the 300 mm x 300 mm imager 1401.

[0167] Referring now to Figure 17, Figure 17 shows the unfolding of the reconfigured grid sensor arrangement shown in Figure 16 according to an embodiment of the present invention to obtain a complex field of 30 mm x 3 mm.

[0168] Figure 17 shows an exemplary position 1701 for applying force to reconfigure the imager X grid. Additionally, Figure 17 shows an exemplary position 1702 for applying force to reconfigure the imager Y grid.

[0169] In addition, Figure 17 shows an X reconfiguration array 1703 superimposed on top of the Y reconfiguration array (not shown in Figure 17).

[0170] Referring now to Figures 18A to 18D, Figures 18A to 18D illustrate an exemplary alignment metering architecture for an exemplary metering module 108 according to an embodiment of the present invention.

[0171] As shown in Figure 18A, this architecture includes a top view of the SWIR imager sub-assembly 1801, which includes the light-sensitive area 1802 of the SWIR sensor. Both coarse (box-in-box) and fine (moiré) alignment marks are obtained using the same imager and optics. In one embodiment, a 1X magnifying optics element is used. In another embodiment, a reflective moiré pattern is used.

[0172] In addition, a telecentric focusing optical element 1803 is used. In one embodiment, such an optical element 1803 includes a numerical aperture of approximately 0.2, a resolution of approximately 4.2 micrometers at 1.4 micrometers, a depth of field of approximately 20 micrometers at 1.4 micrometers, and a magnification of 1X.

[0173] Additionally, Figure 18A shows an interleaved sensor design 1804, which ensures that back-reflected light from level 0 and level 1 does not ultimately contaminate adjacent imagers.

[0174] Figure 18B shows a cross-sectional view of an interleaved sensor design, such as the portion of transfer chuck assembly 1101 containing alignment marks and the portion of field 401 containing alignment marks.

[0175] Figure 18C shows a top view of an interlaced sensor design consisting of two counter-propagating overlapping markers 1805. In one embodiment, the total height is approximately 20 micrometers.

[0176] In addition, Figure 18C shows image-based markings 1806, for example in the picked-up field 1807, and shows an improved cut (approximately 5 micrometers) at location 1808, where the standard cut is approximately 60 micrometers at location 1809.

[0177] If the alignment mark is patterned in layer 0 or in an inter-grain cut (in the case of picking up the entire field consisting of multiple grains), the entire cut width may be used to create the alignment mark.

[0178] Alternatively, MAC-style cutting techniques can be used to create micron-thickness cuts with sharp angles. This allows previously inaccessible areas of the cut to be used for alignment mark placement.

[0179] Figure 18D illustrates normal back-diffraction grating measurement. As shown in Figure 18D, incident light 1810 is reflected from the grating 1811. For the first order returning along the grating normal toward the SWIR sensor, the following grating equation will be satisfied: sin(θ1) = sin(2θi) = sin(θi) + λ / ρ.

[0180] The detection accuracy using image-based markers (assuming a 5-micron SWIR pixel pitch and 1 / 10 subpixel detection) is approximately 0.5 microns. However, the detection accuracy using ridge markers (assuming ρ1, ρ2 = 3, 3.05 µm, 1 / 10 subpixel detection) is approximately 8 nanometers. Furthermore, the ridge phase-accurate capture range is approximately 1.5 microns.

[0181] Figures 19A to 19C illustrate alternative exemplary alignment metering architectures for exemplary metering module 108 according to an embodiment of this case.

[0182] Figure 19A shows a top view of the SWIR imaging subassembly 1901, which includes the light-sensitive region 1902 of the SWIR sensor. In one embodiment, a 1X magnifying optics element is used. In another embodiment, reflective imaging is used.

[0183] Furthermore, Figure 19A shows a focusing optical element 1903. This focusing optical element 1903 includes a numerical aperture of approximately 0.5, a resolution of approximately 1.8 micrometers at 1.4 micrometers, a depth of field of approximately 3.6 micrometers at 1.4 micrometers, and a magnification of 1X.

[0184] Additionally, Figure 19A shows that the focusing optical element 1903 includes an IR LED and the focusing optical element 1904.

[0185] Figure 19B shows a cross-sectional view of the metering plane, which includes the portion of the transfer chuck assembly 1101 containing alignment marks and the portion of the field 401 containing alignment marks.

[0186] Figure 19C shows a top view of the measurement plane composed of two counter-propagating overlapping markings 1905.

[0187] Furthermore, Figure 19C shows image-based markings 1906, for example, in the picked-up field 1907, and an improved cut (approximately 5 micrometers) at location 1908, where the standard cut is approximately 60 micrometers at location 1909.

[0188] If the alignment mark is patterned in layer 0 or in an inter-grain cut (in the case of picking up the entire field consisting of multiple grains), the entire cut width may be used to create the alignment mark.

[0189] Alternatively, MAC-style cutting techniques can be used to create micron-thickness cuts with sharp angles. This allows previously inaccessible areas of the cut to be used for alignment mark placement.

[0190] Furthermore, in such embodiments, the detection accuracy using image-based markers (assuming a 1-micron SWIR pixel pitch and 1 / 20th of a subpixel detection) is close to 90 nanometers.

[0191] Figures 20A to 20C illustrate details of an exemplary metering module 108 according to an embodiment of this case.

[0192] Figure 20A shows a flow cooler 2001 for the SWIR sensor and LED. Additionally, Figure 20A shows a custom 300mm thermally conductive printed circuit board 213 for the IR sensor and LED array. Furthermore, Figure 20A shows the PCB wiring and the heat exchanger fluid sling 2002.

[0193] Figure 20B shows the SWIR LED 2003 and SWIR sensor 2004 directly integrated onto a custom printed circuit board 213. Additionally, Figure 20B shows a machined metal frame 2005 serving as the LED / sensor housing. Furthermore, Figure 20B shows a planar lens 2006 forming a magnifying telecentric pair, microfabricated on a 300 mm glass substrate. Also, Figure 20B shows an off-axis LED focusing optics 2007 and a textured plane 2008.

[0194] Figure 20C shows an enlarged view of the transfer chuck assembly 1101 along the corrugated plane 2008. As shown in Figure 20C, incident light 2009 is reflected from the corrugated grating 2010. For the first order light returning along the grating normal towards the SWIR sensor, the following grating equation will be satisfied: sin(θ1) = sin(2θi) = sin(θi) + λ / ρ. For example, with an incident wavelength of 1.4 μm and a grating spacing of 5 μm, the incident angle θ that satisfies the above condition is approximately 18 degrees.

[0195] Figure 21 illustrates an exemplary metering architecture according to an embodiment of this case.

[0196] Referring to Figure 21, Figure 21 shows alignment measurements (using metrology module 108) between the transfer chuck assembly 1101 and the pick-up field through element 2101. Furthermore, Figure 21 shows global alignment 2102 between the transfer chuck assembly 1101 and the product wafer 105. Additionally, Figure 21 shows the product substrate 105 with assembled layer 1 and the product substrate chuck 104 for holding the product substrate 105.

[0197] Furthermore, Figure 21 shows that the positioning of field 401 on product wafer 105 is predefined (see element 2103), which may be outside the metering module tool 108.

[0198] Note that Figure 21 only shows the bounding box of the metering module 108. The actual metering module assembly can be located within this bounding box.

[0199] Figure 22 illustrates an exemplary field 401 comprising an array of 2 x 2 dies 2201 according to an embodiment of the present invention. Furthermore, Figure 22 shows alignment mark positions 2202.

[0200] Figure 23 illustrates an exemplary metering architecture according to an embodiment of this case.

[0201] As shown in Figure 23, the imager 2301 (e.g., a SWIR sensor) includes a reflective blazed grating 2302. Furthermore, as shown in Figure 23, the metrology architecture may include a focusing optics element 2303 to focus light from the light source 2304 onto an opaque housing wall 2305 on a transparent printed circuit board 213.

[0202] Furthermore, as shown in Figure 23, the Littrow angle 2306 is formed by reflected light from the textured plane 2008.

[0203] Figure 24 illustrates another embodiment of an exemplary metering architecture according to one embodiment of this case.

[0204] As shown in FIG24, the overall assembly 2401 including the light source 2402 (e.g., LED) has a focusing optics 2403 to focus the light emitted from the light source 2402 onto the transfer chuck assembly 1101.

[0205] In one embodiment, a diffraction element at the location indicated by element 2404 couples light into and out of the light guide at a specific angle. The photonic light guide 2405 patterned onto the transfer chuck assembly 1101 can be fabricated in a custom layer that is attached to the remainder of the transfer chuck assembly 1101 using adhesives, vacuum, electromagnetic force, magnetic force, electrostatic force, or any combination thereof.

[0206] In one embodiment, photonic light guide 2405 directs light to a pickup field 2406 on the transfer chuck assembly 1101 of the textured plane 2008.

[0207] Figure 25 illustrates yet another embodiment of an exemplary metering architecture according to one embodiment of this case.

[0208] Referring to Figure 25, Figure 25 shows a series of diffraction elements 2501 to guide light from the light source to the alignment marks.

[0209] Referring to Figures 14-17, 18A-18D, 19A-19C, 20A-20C, and 21-25, in one embodiment, the metrology module 108 is used to measure the stacking, alignment, in-plane and / or out-of-plane distortion errors of the picked-up field 401, transfer chuck 111, native substrate 103, intermediate substrate 801, and / or product substrate 105. In one embodiment, the metrology module 108 is used to measure the stacking of the field 401 before assembly to the product substrate 105. In one embodiment, the metrology module 108 is used to measure the in-plane distortion of one or more fields 401 on the native substrate 103, intermediate substrate 801, and / or product substrate 105.

[0210] In one embodiment, the measurement module 108 simultaneously measures all fields on the transfer chuck 111.

[0211] In one embodiment, the metering module 108 incorporates one or more imaging units 1401. In one embodiment, the imaging unit 1401 is sensitive to visible light radiation, infrared radiation, short-wavelength infrared radiation (SWIR), etc.

[0212] In one embodiment, one or more light sources 2402 are used to illuminate the measurement target. In one embodiment, the light source 2402 incorporates a light-emitting diode (LED), a laser diode, a light-guided light source, a vertical-cavity surface-emitting laser (VCSEL), or any combination thereof. Alternatively, edge illumination can be used as the measurement light source 2402, wherein light is injected from the side of the edge illumination substrate and transmitted to the relevant area using, for example, a photonic crystal light guide. In one embodiment, the light source 2402 is mounted on a printed circuit board. In one embodiment, the light source 2402 is mounted near the imaging unit 1401. In one embodiment, the light source 2402 uses an off-axis lens to send light to the measurement target at an angle. Alternatively, the light source 2402 uses one or more mirrors to send light to the measurement target at an angle. A reflective blazed grating can be used to construct the mirror assembly. The blazed grating can be coated with metal. The blazed grating can be fabricated on a silicon, sapphire, silicon oxide, glass, and / or polymer substrate. In one embodiment, light from light source 2402 is incident at a Littoral angle 2306. In another embodiment, light from light source 2402 is incident at an angle such that one of the first diffraction orders from the metrological marker returns towards the imager 1401 along the field normal direction.

[0213] In one embodiment, the imager unit 1401 is mounted on a printed circuit board. In one embodiment, the light source 2402 is mounted on the printed circuit board. In one embodiment, the imager unit 1401 and the light source 2402 are mounted together on the printed circuit board. In one embodiment, the light source 2402 and the imager unit 1401 mounted on the printed circuit board are selectively isolated using a dark-finished frame. In one embodiment, the printed circuit board is thermally conductive.

[0214] In one embodiment, a lens array patterned on a silicon, sapphire, glass, silicon oxide, and / or polymer substrate is used to guide light from the light source 2402 onto a metering mark and to focus light from the metering mark onto an image array. In one embodiment, the lens array incorporates annular lens-shaped regions etched into the lens array substrate. In one embodiment, the lens array incorporates a set of concentric metal rings. Alternatively, the lens array incorporates a metalens made of an etched substrate, metal, and a high-refractive-index material, such as titanium oxide. In one embodiment, the lens array forms a telecentric coupling for focusing light onto the image array.

[0215] In one embodiment, the metrology scheme is based on the principle of overlay spatial phase sensing. In one embodiment, the metrology scheme is based on on-axis overlay metrology. In one embodiment, the metrology scheme is based on circular overlay metrology. In one embodiment, pure image-based metrology (e.g., box-in-box alignment mark metrology) is used. In one embodiment, a zoom system is used to maintain focus on two or more different planes during metrology. For example, a zoom lens can be used to achieve zoom. In one embodiment, one or more methods mentioned in this paragraph are used simultaneously.

[0216] In one embodiment, metrology is performed in a reflection mode, wherein the light source 2402 and the imager unit 1401 are located on the same side of the metrology mark. In another embodiment, metrology is performed in a transmission mode, wherein the light source 2402 and the imager unit 1401 are located on opposite sides of the metrology mark.

[0217] In one embodiment, the metrology scheme uses visible light. In another embodiment, the metrology scheme uses infrared light.

[0218] In one embodiment, a reduced optical element is used to observe a substrate area larger than the size of the image sensor unit 1401. In another embodiment, a magnified optical element is used to observe a substrate area smaller than the size of the image sensor unit 1401. In one embodiment, subpixel edge detection technology is used to detect edges in the measurement signal.

[0219] In one embodiment, the metering module 108 is placed on a motion platform that moves along the X, Y, and / or Z axes. In one embodiment, the metering module 108 acquires information from all areas being assembled by taking appropriate steps and / or scanning along the X, Y, and / or Z axes.

[0220] In one embodiment, the metering marks are placed near one or more corners of the field 401 being assembled. The field 401 may have no circuitry in the layers above and below the metering marks. In one embodiment, the metering marks are placed in a notched region of the field 401. In one embodiment, the field 401 comprises two or more dies, each die separated from each other by a notched region, and this notched region between dies contains one or more alignment marks.

[0221] In one embodiment, metering is performed in real time as field 401 is bonded to product substrate 105. In another embodiment, metering is performed before bonding occurs. In one embodiment, a feedforward model is used to correct for repeatable components of field distortion.

[0222] In one embodiment, metrology module 108 measures the alignment between fields 401 picked up by transfer chuck 111, wherein transfer chuck 111 has embedded alignment marks that match the field grid. Metrology module 108 may then align transfer chuck 111 to product substrate 105 using metrology marks placed near edge and / or cutout areas of transfer chuck 111 and product substrate 105. In one embodiment, real-time topology mapping of picked-up fields 401 to product substrate 105 is performed, and prediction errors are compensated by a stacking control actuator (e.g., a thermal actuator). In one embodiment, individual topology measurements are performed on each field 401. A barometer (e.g.) may be used to perform topology mapping. For example, a barometer array may be mounted next to printed circuit board 213. Air curtains may also be used to cool product substrate 105 and picked-up fields 401 to prevent printed circuit board 213 from heating them significantly.

[0223] In one embodiment, an on-axis alignment method is used in the metering module 108.

[0224] In one embodiment, the transfer chuck 111 has a grating attached and / or patterned thereon to track XY displacement with high accuracy.

[0225] In one embodiment, the alignment mark is placed on field 401 in the half-cut region (as shown in Figures 18C and 19C). As an alternative to patterning the alignment mark within half (or half-cut) of the cut, a MACE-style cutting process can be used to enable alignment marks throughout the entire cut region. In one embodiment, the alignment mark is placed on field 401 in the metal O (MO) layer.

[0226] In one embodiment, a very large sensor is used for alignment detection in the metering module 108.

[0227] In one embodiment, photonic crystal-based optical guidance technology is used to illuminate alignment marks at the correct angle and position.

[0228] In one embodiment, multiple local data processors are integrated and placed adjacent to one or more image sensors 1401. These data processors can be used to perform local image processing for the sensors. In one embodiment, the data processors are manufactured as part of the image sensor 1401 (in-sensor computer).

[0229] In one embodiment, a fixed grid of image sensors 1401 is used. In one embodiment, image sensors 1401 are arranged in a linear array, a stepped array, or a combination thereof. In one embodiment, image sensors 1401 are arranged such that a region of substrate captured by one of the sensors overlaps with a region of substrate captured by the next nearest image sensor 1401, such that the entire array of sensors captures a continuous and uninterrupted swath of substrate. In one embodiment, image sensor 1401 includes a photosensitive region surrounding a light-insensitive region. In one embodiment, a light source 2402 is mounted in this light-insensitive region, angled if necessary, and covered on the sides with an opaque covering (to prevent stray light contamination of the sensor). Light from light source 2402 passes through focusing optics 2303 and is incident toward the metrology plane. Light source 2402 is designed such that the depth of the beam (along the Z-axis) is the same as the depth of image sensor 1401. If the incident light falls on the metering marks, the light is reflected toward the image sensor 1401 in a direction perpendicular to the substrate. A 1X magnified low numerical aperture optical element focuses the light incident from the metering mark plane toward the image sensor 1401 onto the sensor. A sensor array scans in the X direction (see Figures 14 and 15) to collect Y-pair data (e.g.) across the entire substrate. A second sensor array orthogonal to the first sensor array is used to collect X-pair data (e.g.) across the entire substrate. Alternatively, the sensor array used for Y-pair data collection can also be used to collect X-pair data by serpentine scanning, stepping to new locations, and scanning serpentine again.

[0230] In one embodiment, a reconfiguration arrangement of image sensor 1401 is used. In one embodiment, the reconfiguration arrangement is integrally manufactured. In one embodiment, the reconfiguration arrangement is constructed by stacking one or more layers, each layer being integrally manufactured. In one embodiment, the reconfiguration arrangement is manufactured using bulk metal, bulk polymer, thin coating, etc. In one embodiment, the reconfiguration arrangement is manufactured using steel, stainless steel, chromium, etc. In one embodiment, the reconfiguration arrangement consists of bending elements. In one embodiment, the bending elements are arranged to form a scissor mechanism between each pair of image sensors. In one embodiment, individual reconfiguration arrangements are used to reconfigure along the X and Y directions. These arrangements can be stacked on top of each other. Each arrangement can be actuated in one direction while being freely movable in orthogonal directions. In one embodiment, actuation of the reconfiguration arrangement is generated using actuators (e.g., voice coil motors, piezoelectric actuators, thermal actuators, etc.) placed at one or more locations on or around the reconfiguration arrangement. In one embodiment, the actuators are placed on the axis of symmetry of the reconfiguration arrangement. In one embodiment, each sensor is moved in the X and / or Y directions using one or more dedicated actuators. In one embodiment, a group of sensors is moved in the X and / or Y directions using a group of actuators. In one embodiment, the reconfiguration arrangement is located on a fluid bearing. In one embodiment, the reconfiguration arrangement can be stepped and / or scanned across the transfer chuck 111. In one embodiment, the reconfiguration arrangement is rectangular, with its shorter arm smaller than the dimensions of the native / product / intermediate substrate 103 / 105 / 801. In one embodiment, the reconfiguration arrangement is in the shape of a single row or column of sensors.

[0231] In one embodiment, the image sensor 1401 is attached to the plate such that the spacing of the image sensor 1401 is an integer multiple of the field spacing on the transfer chuck / native / product / intermediate substrate (111 / 103 / 105 / 801). The plate can be custom-manufactured for each new field layout. The plate may have grooves or slots for positioning the image sensor 1401. The plate may have alignment features (e.g., pins 1104) for aligning the image sensor 1401 on the X, Y, Z, θx, θy, and θz axes. The image sensor 1401 is attached to the plate using adhesives, bending engagement mechanisms, magnets, electromagnets, vacuum, etc.

[0232] In one embodiment, the metering module 108 is separated from the rest of the pick-and-place tool using a transparent window. In another embodiment, the metering module 108 is placed behind the transparent window, such that there is no massive transfer between the metering module 108 and the rest of the pick-and-place tool. In one embodiment, the metering module 108 is placed in an airtight sealed cavity having a transparent window facing the transfer chuck 111. In one embodiment, the airtight sealed cavity has a door for removing and / or placing the metering module 108.

[0233] In one embodiment, the topography (and alignment of field 401 to a known grid) on the product substrate 105 is measured before the picked-up field 401 is attached to one or more intermediate substrates. In one embodiment, the topography (and alignment of picked-up field 401 to a known grid) on the transfer chuck 111 is measured before the field 401 is attached to one or more intermediate substrates. In one embodiment, the measured topography and alignment information of the picked-up field 401 on the product substrate and the transfer chuck 111 are used to actuate the picked-up field 401 and partially or completely compensate for alignment errors that would occur if not compensated in the final bonding step (bonding the intermediate substrate to the product substrate) on the product substrate 105. Prediction of overlay errors based on topography and alignment data can be performed using mechanical modeling. In one embodiment, the temperature of field 401 on the transfer chuck 111 and the temperature of the product substrate 105 are maintained within a small window (e.g., 10 mK). In one embodiment, a single topography measurement is performed on each field on the transfer chuck 111 and the product substrate 105. Topography mapping can be performed using a barometer, for example.

[0234] In one embodiment, the group of image sensors 1401 (comprising one or more image sensors 1401) uses a dedicated and / or local data processor to process all or part of the image processing pipeline for determining measurement outputs (e.g., overlay, alignment, topography, etc.) from the captured images. In one embodiment, the data processor is a single-board computer.

[0235] In one embodiment, a patterned custom light path (transmitting light incident from light source 2402 to a position suitable for projection onto alignment marks) is transferred to transfer chuck 111. In one embodiment, the light path is a custom layer fabricated on the remainder of transfer chuck 111. In one embodiment, attachment is performed using adhesives, vacuum, electromagnetic force, magnetic force, electrostatic force, etc. In one embodiment, the light path consists of only transmission and reflection diffraction structures. In one embodiment, the light path is created using nanoimprint lithography (NIL). In one embodiment, the light path consists of repeating standardized sections, which can be patterned using a limited number of fixed masks or caliper sheets.

[0236] Block HF etchers are used to create tethers in sacrificial layers of one or more native substrates.

[0237] In one embodiment, the substrates are arranged horizontally on a multi-substrate chuck. In another embodiment, the substrates are arranged vertically on a multi-substrate holder.

[0238] In one embodiment, on-the-fly measurement is performed on one or more substrates being etched for endpoint and uniformity measurements.

[0239] The storage unit can be used to store multiple fully and partially filled virgin / product / intermediate substrates 103 / 105 / 801. The storage unit can also be used to store transfer chuck units 111 and metering units 108. In one embodiment, the transfer chucks 111 may have fields 401 attached to them. In one embodiment, the storage unit has a dedicated vacuum source with an emergency backup power supply to provide a vacuum to the stored transfer chucks 111.

[0240] In one embodiment, the storage unit has temperature and humidity control.

[0241] In one embodiment, one or more robotic handling units can be used to move individual substrates, substrate groups, transfer chuck 111, metering unit 108, etc., between various parts of the n-MASC tool.

[0242] Referring now to Figures 26A and 26B, Figures 26A and 26B illustrate an exemplary known-bad-die replacement chuck (KRC) 2601 according to an embodiment of this case.

[0243] As shown in Figure 26A, the buffer substrate 2602 is filled with known good grains 2603, wherein the buffer substrate 2602 is held by the buffer substrate chuck 2604.

[0244] Furthermore, as shown in FIG26A, the known defective grains 2605 on the original substrate 103 are replaced with known good grains, such as known good grains 2603.

[0245] Figure 26B is an enlarged cross-sectional view of the precision module frame 106, illustrating an exemplary manner of loading or unloading the known defective die replacement chuck 2601 using a robotic arm 2606 attached to the periphery of the chuck 2601. Note that the transfer chuck 111 can be loaded or unloaded in the same manner.

[0246] In addition, Figure 26B shows the voice coil post 2607 (the post to the voice coil 109) and the push rod 2608.

[0247] Further discussion is provided below regarding Figures 26A-26B.

[0248] The Known Defective Die Replacement Chuck (KRC) 2601 is used to replace known bad dies (KBDs) 2605 with known good dies (KGDs) 2603. One or more buffer substrates 2604 serve as the source of the known good dies 2603. The Known Defective Die Replacement Chuck 2601 can replace known bad dies 2605 (with known good dies 2603) on one or more native / intermediate / product substrates 103 / 801 / 105. The Known Defective Die Replacement Chuck 2601 is designed to be similar to a transfer chuck in terms of its clamping field, sensing and correcting of stacking, and maintaining thermal stability.

[0249] In one embodiment, a known defective die replacement chuck 2601 replaces known defective dies 2605 on the native substrate 103. Known defective dies 2605 are selectively released from the native substrate 103, for example, through localized UV exposure using UV release adhesive, and then replaced with known good dies 2603 using the known defective die replacement chuck 2601. In one embodiment, a transfer chuck 111 picks up groups of two or more dies from the native substrate 103, where one or more or all of the known defective dies 2605 have been replaced with known good dies 2603, and continues assembly onto the product substrate 105.

[0250] In one embodiment, a known defective die replacement chuck 2601 assembles a known good die 2603 onto a product substrate 105. The known defective die 2605 is removed directly after being picked up from the original substrate 103 by a transfer chuck 111, or the transfer chuck 111 avoids picking up the known defective die 2605 from the original substrate 103. The space on the product substrate 105 that would otherwise be occupied by the known defective die 2605 is filled by the known good die 2603 picked up from the buffer substrate 2602 and assembled onto the product substrate 105 using the known defective die replacement chuck 2601.

[0251] In one embodiment, a known defective die replacement chuck 2601 assembles a known good die 2603 onto an interposer substrate (not shown in Figures 26A-26B). A known defective die 2605 is removed directly after being picked up from the native substrate 103 by a transfer chuck 111, or the transfer chuck 111 avoids picking up the known defective die 2605 from the native substrate 103. The space on the interposer substrate that would otherwise be occupied by the known defective die 2605 is filled by the known good die 2603 picked up from the buffer substrate 2602 and assembled onto the interposer substrate using the known defective die replacement chuck 2601.

[0252] In one embodiment, the dies (e.g., known good dies 2603) on the buffer substrate 2602 are height-mapped such that the known bad die replacement chuck 2601 can pick up the known good dies 2603 at the correct height for placement on the native / intermediate / product substrates 103 / 801 / 105. Height mapping can be performed using various methods, such as barometers, confocal laser sensors, etc.

[0253] In one embodiment, a z-actuator assembly, independent of the z-actuator assembly of the transfer chuck 111, is used to attach the known defective die replacement chuck 2601 to the n-MASC tool. In another embodiment, the known defective die replacement chuck 2601 is mounted on the same z-actuator assembly as the transfer chuck 111 (the transfer chuck 111 is temporarily unloaded from the z-actuator assembly).

[0254] The pick-and-place tool can be designed to operate under various conditions of output, stack-up, and yield. Example output options are as follows – 1. At the high end of the production range: (a) full substrate assembly (parallel assembly of all fields 401), (b) half checkerboard assembly (parallel assembly of half of the fields 401 on the native substrate 103, wherein the fields 401 are arranged in a checkerboard pattern that includes one half of the fields 401 on the native substrate 103 and / or the product substrate 105. In the case of any consecutive 3 x 3 die array on the native substrate 103 and / or the product substrate 105, the half checkerboard consists of five fields that do not share edges or four fields that do not share edges and are closest to the center of the 3 x 3 array), (c) quarter checkerboard assembly (parallel assembly of one-quarter of all fields 401 on the native substrate 103, wherein the fields 401 are arranged in a checkerboard pattern that includes one-quarter of all fields 401 on the native substrate 103 and / or the product substrate 105). 2. At the lower end of the output range: (a) 9-field assembly, (b) 4-field assembly, (c) field-by-field assembly, (d) 6-field assembly, (e) 8-field assembly, (f) 12-field assembly, (g) 14-field assembly, (h) 16-field assembly, (i) 18-field assembly, (j) 20-field assembly, (k) 24-field assembly, (l) 25-field assembly, (m) 36-field assembly, (n) 50-field assembly, and (o) 64-field assembly. Examples of stacking options are as follows – 1. At the precise end of the stacking range: (a) next 10 nm (3σ) stacking control on the product substrate, (b) next 50 nm (3σ) stacking control on the product substrate, (c) next 100 nm (3σ) stacking control on the product substrate. 2. At less precise ends of the stacking range: (a) sub-200 nm (3σ) stacking control on the product substrate, (b) sub-500 nm (3σ) stacking control on the product substrate, (c) sub-1 μm (3σ) stacking control on the product substrate. Exemplary yield options are as follows – 1. Complete Replacement: Replace chuck 2601 with known defective chips and replace all known defective chips 2605 with known good chips 2603. 2. Half replacement: Replace chuck 2601 with known defective chips and replace nearly half of the known defective chips 2605 with known good chips 2603. 3. Quarter replacement: Replace chuck 2601 with known defective chips and replace nearly a quarter of the known defective chips 2605 with known good chips 2603. 4. No replacement: No known defective 2605 dies were replaced. Table 1: Exemplary Pick-and-Place Component Tool Patterns [Generation Amount] [Overlapping] [Yield Rate] [model] [1] Quarter chessboard assembly 1µm (3σ) Full replacement [model] [2] Quarter chessboard assembly Next 100nm (3σ) Full replacement [model] [3] Quarter chessboard assembly Next 50nm (3σ) Full replacement [model] [4] One-eighths chessboard (parallel assembly of one-eighths of the field on the native substrate, wherein the field is arranged in a chessboard pattern that includes one-eighths of the field on the native substrate and / or the product substrate) assembly Next 50nm (3σ) Full replacement [model] [5] 9-Field Assembly Next 50nm (3σ) Full replacement [model] [6] 4-Field Assembly Next 50nm (3σ) Full replacement [model] [7] Field-by-field assembly Next 50nm (3σ) Full replacement

[0255] Referring now to Figures 27A to 27C, Figures 27A to 27C illustrate exemplary native substrate types according to an embodiment of this case.

[0256] Referring to Figure 27A, Figure 27A shows a "native substrate type 1", which consists of a bulk silicon layer 2701, a buried oxide layer 2702 (corresponding to a sacrificial layer for assembly) located on the bulk silicon 2701, a silicon (Si) layer 2703 located on the buried oxide layer 2702, a buried oxide layer 2704 located on the silicon layer 2703, and a silicon layer 2705 for device located on the buried oxide layer 2704.

[0257] Figure 27B shows a "native substrate type 2", which consists of a bulk silicon layer 2706, a buried oxide layer 2707 created by a layer of heavily doped p-type material (p++), a very lightly doped n-type material (n-) layer 2708 (hereinafter referred to as "low-doped n-type layer 2708") located on the buried oxide layer 2707, a heavily doped p-type material (p++) layer 2709 (hereinafter referred to as "high-doped p-type layer 2709") located on the low-doped n-type layer 2708 for device function, and a silicon layer 2710 located on the high-doped p-type layer 2709 for device function.

[0258] Figure 27C shows "native substrate type 3", which consists of a layer 2711 of heavily doped (p++) bulk silicon, a very lightly doped n-type material (n-) layer 2712 on top of layer 2711, a heavily doped p-type material (p++) layer 2713 (hereinafter referred to as "highly doped p-type layer 2713") on top of layer 2712 for device function, and a silicon layer 2714 on top of the highly doped p-type layer 2713 for device function.

[0259] Figures 28A and 28B illustrate an exemplary field 401 with an exemplary multilayer package according to an embodiment of the present invention.

[0260] As shown in Figure 28A, Figure 28A illustrates an enlarged cross-section of a field 401 including a device stack 2801 located on a silicon crystal 2802. In one embodiment, the field 401 is approximately 30 millimeters wide. In one embodiment, the device stack 2801 is approximately 3 micrometers wide. In one embodiment, the silicon crystal 2802 is approximately 1 micrometer wide.

[0261] Figure 28B shows a field 401 with multilayer encapsulation, which includes a thin chemical protective layer 2803 (e.g., chemical vapor deposition of carbon) and a structural encapsulation layer 2804 (e.g., chemical vapor deposition of silicon dioxide).

[0262] Furthermore, as shown in Figure 28B, the encapsulation layer in region 1 2805 only needs to match the thin underlying silicon layer, thus allowing for low effective hardness. Note that the patterning of region 1 2805 can be performed in the same manner as creating the access vias to the buried sacrificial layer (e.g., lithography).

[0263] Additionally, as shown in Figure 28B, a stiffer encapsulation layer (region 2 2806) may be required to compensate for greater bending tendency.

[0264] Figures 29A and 29B illustrate an exemplary face-to-back (F2B) and face-to-face (F2F) device stack according to an embodiment of the present invention.

[0265] As shown in Figure 29A, a typical F2B stack includes device layers 2901A-2901N (as shown in Figure 29A, 2901A is identified as "Device Layer 1", 2901B as "Device Layer 2", 2901C as "Device Layer 3", and 2901N as "Device Layer N"), wherein these device layers are connected in a face-to-back manner through vertical electrical connections 2902 (through silicon vias, TSVs) . Device layers 2901A-2901N can be collectively or individually referred to as multiple device layers 2901 or device layer 2901.

[0266] As shown in Figure 29B, a typical F2F stack includes device layers 2903A-2903N (as shown in Figure 29B, 2903A is identified as "Device Layer 1", 2903B as "Device Layer 2", 2903C as "Device Layer 3", 2903N-1 as "Device Layer N-1", and 2903N as "Device Layer N"), wherein these device layers are connected face-to-face through vertical electrical connections 2904 (through silicon vias, TSVs). Device layers 2903A-2903N can be collectively or individually referred to as multiple device layers 2903 or device layer 2903.

[0267] Figure 30 illustrates an exemplary assembly of a static random access memory (SRAM) in a logical field according to an embodiment of the present invention.

[0268] As shown in Figure 30, a logic field 3001 and an SRAM field 3002 with a sacrificial layer 3003 are assembled using an n-MASC device 3004 face-to-back to form an assembled product 3005 consisting of an SRAM field 3002 located on top of the logic field 3001.

[0269] Subsequently, silicon via forming and encapsulation connection are performed to form a device 3006 including a connection 3007 to the package and silicon via 3008.

[0270] Referring now to Figure 31, Figure 31 illustrates an exemplary assembly of multiple stacked static random access memories in a logical field according to an embodiment of the present invention.

[0271] As shown in Figure 31, device 3006 now includes multiple SRAMs 3101 stacked on logic field 3001. Further discussion of the stacked SRAMs is provided below.

[0272] Referring now to Figure 32, Figure 32 illustrates an exemplary assembly of static random access memory in a logical field having an error correction intermediary layer in the middle, according to an embodiment of the present invention.

[0273] As shown in Figure 32, the intermediate field 3201 is used to identify good bit cells in the logic field 3001 and the SRAM field 3002, and to manufacture custom error correction procedures, such as electrical connectivity and heat dissipation. The intermediate field 3201 can reside between the logic field 3001 and the SRAM field 3002 after being assembled by the n-MASC device 3004 (F2B).

[0274] The following discussion is based on Figures 27A-27C, 28A-28B, 29A-29B, and 30-32.

[0275] In one embodiment, the native substrate 103 includes buried oxide layers 2702 and 2707. In one embodiment, the buried oxide layers 2702 and 2707 are silicon oxide. In one embodiment, the starting substrate for the native substrate including the sacrificial layer is composed of low-doped n-type layers (hereinafter referred to as N-) 2708 and 2712 and high-doped p-type layers (hereinafter referred to as P++) 2709 and 2713. The high-doped p-type layers 2709 and 2713 can be first converted into porous silicon (e.g., using silicon anodizing) and then oxidized to create a buried sacrificial layer of silicon oxide. The low-doped n-type layers 2708 and 2712 remain unaffected during anodizing and limit anodizing only to the high-doped layers. In one embodiment, epitaxial growth can be used to produce layers with low n-type and high p-type doping. In one embodiment, the bulk silicon itself is highly p-doped (e.g., layer 2711).

[0276] In one embodiment, the native substrate 103 comprises background devices on a carrier substrate. The carrier substrate may be bulk silicon, a glass substrate, a frame, etc., depending on the process used to create the background devices and the desired device orientation. In one embodiment, the carrier substrate is transparent. In one embodiment, the carrier substrate is attached to the background field using a UV-release adhesive. In one embodiment, the carrier substrate is attached to the background field using a sublimation polymer. In one embodiment, a MACE process is used to perform backside polishing.

[0277] In one embodiment, a light-to-heat conversion (LTHC) adhesive layer is used to attach the background field to the carrier substrate. In one embodiment, after pickup (through one or more transfer chucks 111), the field 401 can be cleaned on the transfer chuck 111 itself using oxygen plasma, etchant vapor (e.g., vapor HF), and / or etchant liquid.

[0278] In one embodiment, a structural encapsulation layer with a certain thickness and material is used to control the deformation of the thin field 401 caused by residual stress, such that the hardness of the encapsulation layer is close to or equal to the hardness of the underlying field 401. In one embodiment, the encapsulation layer consists of a chemical protective layer 2803 (to prevent chemical damage) and a structural encapsulation layer 2804 (to prevent deformation caused by residual stress). In one embodiment, the patterned structural encapsulation layer 2804 is used to counteract the deformation tendency of variations across the region of field 401. In one embodiment, wavefront-based methods, laser-based optical domain scanning methods, capacitive methods, etc., are used to sense residual deformation in the encapsulation field.

[0279] In one embodiment, for face-to-back assembly, the encapsulation layer on the pick-up field 401 is not removed prior to bonding. In one embodiment, the residual stress-compensating structural encapsulation layer is included within the device itself. In one embodiment, metal interconnects pass through the structural encapsulation layer 2804.

[0280] In one embodiment, the encapsulation layer includes a compliant element to prevent field deformation caused by embedded particles. In one embodiment, the compliant element is in the form of a compliant pin in a compliant pin chuck. In one embodiment, the encapsulation layer includes a compliant polymer layer to prevent field deformation caused by embedded particles.

[0281] In one embodiment, the encapsulation layer includes a scratch-resistant layer, for example, made using a diamond-like layer or a hard coating, such as aluminum oxide.

[0282] In one embodiment, the encapsulation layer consists of three layers: carbon, silicon oxide, and carbon (with silicon oxide sandwiched between two carbon layers).

[0283] In one embodiment, nanoimprint lithography, photolithography, electron beam lithography, etc., are used to pattern the encapsulation layer. In another embodiment, a lithography process similar to that used to create field entry / exit holes is used to pattern the encapsulation layer.

[0284] In one embodiment, field 401 includes a nanowire cluster at the interface to facilitate electrical connection. In one embodiment, the nanowire cluster incorporates copper nanowires.

[0285] In one embodiment, the through-silicon vias (TSVs) 2902, 2904 that form the electrically connected bonding field 401 after bonding have a multi-shell structure that may contain metal interconnects (e.g., at the center of the TSV) and have a ring-shaped low-k dielectric material around the metal interconnects.

[0286] In one embodiment, the field 401 assembled on the product substrate 105 comprises a memory layer (e.g., 3002) and a logic layer (e.g., 3001). In another embodiment, the field 401 on the product substrate 105 includes an interposer layer (e.g., interposer field 3201) that can be used to create electrical connectivity, heat dissipation, etc.

[0287] In one embodiment, for face-to-back assembly, the field contact pins on the transfer chuck have a cross-sectional area larger than the size of the selective access holes in field 401.

[0288] In one embodiment, the starting substrate having the sacrificial layer is attached to the carrier substrate with an adhesive, and the sacrificial layer is peeled off, such that the native substrate 103 is composed of the field 401 on the carrier substrate.

[0289] The field 401 on the incoming background substrate can first be transferred to the intermediate substrate 801, then transferred to the second intermediate substrate 801 using the transfer chuck 111, and finally flipped and bonded to the product substrate 105. The incoming background monomerized field can be on a transparent carrier (e.g., glass, quartz, sapphire, and / or polymer). The first intermediate substrate 801 can be a transparent substrate (e.g., glass, quartz, sapphire, and / or polymer). The second intermediate substrate 801 can be a transparent substrate (e.g., glass, quartz, sapphire, and / or polymer) or a non-transparent substrate (in the visible spectrum), such as silicon. The adhesive used to bond the field 401 to the carrier substrate in the native substrate 103 can be UV-released, heat-released, etc. The adhesive used to bond the field 401 to the first intermediate substrate 801 in the native substrate 103 can be UV-released, heat-released, etc. In one embodiment, the field 401 from the native substrate 103 is released by UV exposure of the UV release adhesive on the native substrate side after being flipped and attached to the first intermediate substrate 801.

[0290] Figure 33 illustrates an exemplary sequence for pick-and-place assembly according to an embodiment of this case.

[0291] Referring to Figure 33, a series of pre-flipped native wafers 3301A-3301N (note that the terms "wafer" and "substrate" are used interchangeably herein) (3301A is identified as "pre-flipped native wafer 1", 3301B as "pre-flipped native wafer 2" and 3301N as "pre-flipped native wafer N") reside on carrier substrates 3302A-3302N, respectively. The pre-flipped native wafers 3301A-3301N may be collectively or individually referred to as a plurality of pre-flipped native wafers 3301 or pre-flipped native wafers 3301. The carrier substrates 3302A-3302N may be collectively or individually referred to as a plurality of carrier substrates 3302 or carrier substrate 3302.

[0292] Furthermore, as shown in Figure 33, the metal structure (grain) 3303 faces the adhesive 3304.

[0293] In one embodiment, wafer 3301 is flipped with a temporary bond and the pre-flipped carrier 3302 is separated, for example, by using a transfer chuck 111, thereby forming native wafers 3305A-3305N as shown in FIG33 (3305A is identified as "native wafer 1", 3305B is identified as "native wafer 2" and 3305N is identified as "native wafer N"). Native wafers 3305A-3305N may be collectively or individually referred to as a plurality of native wafers 3305 or native wafers 3305.

[0294] Subsequently, there may be a collective transfer of dies to intermediate wafers 3306A-3306N (3306A identified as "intermediate wafer 1", 3306B identified as "intermediate wafer 2" and 3306N identified as "intermediate wafer N"), while the spacing in the X and / or Y directions may be adjusted using transfer chuck 111, as shown in FIG33. Intermediate wafers 3306A-3306N may be collectively or individually referred to as a plurality of intermediate wafers 3306 or intermediate wafers 3306. In one embodiment, the thickness of the adhesive 3304 of each die 3303 may be adjusted to compensate for height mismatch, as shown by element 3307. Furthermore, FIG33 shows an exemplary adhesive island 3308 in which individual dies 3303 are bonded to intermediate wafers 3306.

[0295] Furthermore, as shown in Figure 33, the transfer chuck 111 can then be used to transfer the entire intermediate wafers to the transfer wafer 3309. In one embodiment, the overlay can be corrected during this step. Additionally, in one embodiment, the grain spacing can be adjusted in the X and / or Y directions during such a step.

[0296] Additionally, as shown in Figure 33, the transfer wafer 3309 is bonded (e.g., hybrid bonded) to the product wafer 3310.

[0297] Referring now to Figure 34, Figure 34 illustrates an alternative exemplary sequence for pick-and-place assembly according to an embodiment of the present invention.

[0298] As shown in Figure 34, compared to Figure 33, a transfer chuck 111 is used to collectively transfer to the transfer wafer 3309 without using the intermediate wafer 3306. Furthermore, as shown in Figure 34, exemplary adhesive islands 3401 may exist on the native wafer 3305, in which individual dies 3303 are bonded to the native wafer 3305. Additionally, it is noted that the thickness of the adhesive 3304 in each field 401 can be adjusted to compensate for field mismatch, as shown by element 3402.

[0299] Referring now to Figure 35, Figure 35 illustrates yet another alternative exemplary sequence for pick-and-place assembly according to an embodiment of the present invention.

[0300] As shown in Figure 35, compared to Figures 33 and 34, the pre-flipped native wafer 3301 is not flipped, and no intermediate wafer 3306 is used. Instead, a transfer chuck 111 is used to collectively transfer all pre-flipped native wafers 3301 to transfer wafer 3309. In one embodiment, overlay correction can be performed during this step. Furthermore, in one embodiment, the grain spacing can be adjusted in the X and / or Y directions during such a step.

[0301] After the transfer, the transfer wafer 3309 is temporarily bonded and flipped, and the carrier substrate 3302 is separated, for example by using the transfer chuck 111, thereby forming structure 3501.

[0302] Furthermore, as shown in Figure 35, an exemplary adhesive island 3502 may be present on the transfer wafer 3309, wherein individual dies 3303 are bonded to the transfer wafer 3309.

[0303] Referring now to Figures 36A and 36B, Figures 36A and 36B illustrate an exemplary transfer chuck 111 according to an embodiment of the present invention.

[0304] As shown in Figure 36A, the transfer chuck 111 can be composed of multiple miniature transfer chucks 3601.

[0305] Furthermore, Figure 36A shows an exemplary position 3602 for applying force to reconfigure the X grid of the transfer chuck. Additionally, Figure 36A shows an exemplary position 3603 for applying force to reconfigure the Y grid of the transfer chuck.

[0306] Furthermore, Figure 36A shows the Y reconfiguration array 3604. The X reconfiguration array (not shown in Figure 36A) can be manufactured separately and superimposed on top of the Y reconfiguration array 3604.

[0307] In one embodiment, the transfer chuck 111 comprises a fully reconfigurable array of 300 mm x 300 mm miniature transfer chucks 3601. An enlarged cross-section of the miniature transfer chuck 3601 is shown in Figure 36B.

[0308] As shown in Figure 36B, the micro-transfer chuck 3601 includes electrodes 3605 and a custom-designed thin-film transistor (TFT) backplane 3606. Additionally, as shown in Figure 36B, a layer of dielectric 3607 can be utilized between the micro-transfer chuck 3601 and the field 401, wherein the dielectric 3607 can selectively leak to generate a Johnsen-Rahbek (JR) type clamping effect.

[0309] Figures 37A to 37O illustrate alternative exemplary transfer chucks according to an embodiment of this case.

[0310] Referring to Figure 37A, Figure 37A shows an enlarged cross-section of the microtransfer chuck 3601. As shown in Figure 37A, "Option 1" is to reuse the thin-film transistor backplate 3701 from the micro LCD display. For example, the microtransfer chuck 3601 would include the reusable thin-film transistor backplate 3701. Furthermore, the space 3702 between the electrodes is maintained at atmospheric pressure using an in-plane grid of channels 3704.

[0311] Additionally, Figure 37A shows a vacuum inlet 3705, where the vacuum is generated using an in-plane grid of the vacuum channel (not shown in Figure 37A). Furthermore, Figure 37A shows a vacuum outlet 3706 to field 401.

[0312] As shown in Figure 37B, the structure of Figure 37B includes a reusable thin-film transistor backplate 3701 and transistor wires 3707.

[0313] Referring now to Figure 37C, Figure 37C includes process steps for reusing the thin-film transistor backplane 3701 from a micro LCD display, including vacuum channel patterning 3708, metal deposition and patterning (for fixed electrodes) 3709, oxide deposition 3710, metal deposition and patterning (for movable electrodes) 3711, flexible film deposition 3712, TSV patterning and backside etching 3713, and bump creation 3714, thereby producing the structure shown in Figure 37D.

[0314] As shown in Figure 37D, the structure includes an electrode 3703 and a channel 3704.

[0315] Referring now to Figure 37E, the process steps for reusing the thin-film transistor backplane 3701 from the micro LCD display include vacuum channel patterning 3715, oxide deposition 3716, TSV patterning and backside etching 3717, porous film deposition 3718, oxide deposition 3719, and pin polishing 3720, thereby producing the structure 3721 shown in Figure 37F.

[0316] Referring now to Figure 37G, the structures shown in Figures 37B, 37D and 37F are joined together (see element 3722) by performing bump bonding, fusion bonding and oxide release using vHF (vapor phase hydrofluoric acid) to produce structure 3723 as shown in Figure 37H.

[0317] Referring now to Figure 37I, Figure 37I shows an enlarged cross-section of the micro transfer chuck 3601. As shown in Figure 37I, "Option 2" uses a custom backplane 3724 in the TFT wafer foundry. The micro transfer chuck 3601 further includes a moving electrode 3725 and a fixed electrode 3726. In addition, as shown in Figure 37I, a selective porous filter membrane 3727 is used to filter out particles in the airflow to prevent them from reaching the TC field interface.

[0318] Referring now to Figure 37J, which includes the process steps of using a custom backplane 3724 in a TFT wafer foundry, including TFT patterning 3728, vacuum channel patterning 3729, metal deposition and patterning (for fixed electrode 3726) 3730, oxide deposition 3731, metal deposition and patterning (for moving electrode 3725) 3732, and soft film deposition 3733, thereby producing the structure shown in Figure 37K.

[0319] As shown in Figure 37K, the structure includes a custom backplate 3724 and movable and fixed electrodes 3725 and 3726.

[0320] Referring now to Figure 37L, which includes additional process steps in a TFT wafer foundry using a custom backplane 3724, including vacuum channel patterning 3734, oxide deposition 3735, TSV patterning and backside etching 3736, porous film deposition 3737, oxide deposition 3738, and pin polishing 3739, to produce the structure 3740 shown in Figure 37M.

[0321] Referring now to Figure 37N, the structures shown in Figure 37K and Figure 37M are joined together (see element 3741) by performing bump bonding, fusion bonding, and oxide release using vHF (vapor phase hydrofluoric acid) to produce structure 3742 as shown in Figure 37O.

[0322] Referring now to Figures 38A to 38C, Figures 38A to 38C illustrate an exemplary reconfiguration transfer chuck 111 according to an embodiment of this case.

[0323] Figure 38A shows an XZ-plane cross-sectional view of the transfer chuck 111, depicting the optical electromagnetic actuator 3801. Furthermore, the transfer chuck 111 includes a slider 3802 and a selective bending system 3803 that constrains the slider 3802 in θx and θy. Additionally, the transfer chuck 111 includes a selective frictionless pivot 3804 between the bending system 3803 and the optical electromagnetic actuator.

[0324] In one embodiment, δy, δz, θz, and θx are controllable. In one embodiment, the transfer chuck 111 includes a selective bending bearing with a selective frictionless rotary bearing.

[0325] Figure 38B shows a top view of the transfer chuck 111.

[0326] Figure 38C shows an enlarged top view of the transfer chuck 111.

[0327] As shown in Figures 38B and 38C, selective pressure and / or vacuum 3805 are present to guide and / or fix slider 3802 onto linear track 3806. Furthermore, Figure 38C shows a selective transparent core port 3807 of slider 3802 to allow measurement. Additionally, Figure 38C shows a selective encoder sensor 3808. Figure 38C further shows a selective permanent magnet / voice coil 3809.

[0328] Further discussion is provided below regarding Figures 33-35, 36A-36B, 37A-37O, and 38A-38C.

[0329] Please find a list of definitions for the terms discussed in this article below. ● SiP – System-in-Package, in which individually manufactured dies are integrated into higher-order components. ● Field – A single grain or a small group of grains arranged side by side in SiP. ● SPP – SiP pitch on product-wafer (SPP) that includes SPPx and SPPy. ● Transfer chuck – A system for transferring a field and / or grain from one substrate to another while maintaining the thermomechanical stability of the field and / or grain.

[0330] In one embodiment, a monomerized field (obtained after back-side polishing) on ​​the native substrate 103 is first transferred to an intermediate substrate 801 using a transfer chuck 111, and then to a transfer substrate 3309. In one embodiment, during the transfer from the native substrate 103 to the intermediate substrate 801, the field 401 is displaced along the X and / or Y axes such that the field spacing matches the grid spacing along the X and / or Y axes on the product substrate 105. In one embodiment, during the transfer from the intermediate substrate 801 to the transfer substrate 3309, the field 401 is displaced along the X and / or Y axes such that the field spacing matches the grid spacing along the X and / or Y axes on the product substrate 105. In one embodiment, during the transfer from the intermediate substrate 801 to the transfer substrate 3309, the predicted overlap error of the fields on the product substrate 105 is fully or partially compensated by actuators (thermal or mechanical) on the transfer chuck 111 and / or the transfer substrate chuck. In one embodiment, field 401 is transferred from transfer substrate 3309 to product substrate 105 as a whole substrate. In one embodiment, transfer substrate 3309 is separated from the temporarily bonded field using heating (to release the adhesive) or UV exposure (to use a transparent or perforated substrate and UV-cured adhesive). In one embodiment, transfer substrate 309 is separated from field 401 after being temporarily bonded to product substrate 105 (e.g., using room temperature hybrid bonding to perform the bonding). After separation of transfer substrate 3309, residual adhesive and / or UV-cured planarization material is removed using oxidative wet cleaning, oxygen plasma ashing, etc. The cleaning can be performed after the temporary bonding between oxide surfaces and before permanent bonding, wherein permanent bonding is performed using thermal curing of the hybrid bonding surfaces.

[0331] One or more of the native / intermediate / transfer substrates 103 / 801 / 3309 may be composed of a glass substrate, a roll of glass substrate, aluminum, a roll of aluminum, a foil of aluminum, a polymer, a roll of polymer, stainless steel, and / or a roll of stainless steel. In one embodiment, one or more of the native / intermediate / transfer substrates 103 / 801 / 3309 have through holes that serve as light guides for passing through the substrate.

[0332] In one embodiment, the intermediate and transfer substrates 801 and 3309 are made of a transparent substrate (e.g., silicon oxide, fused silica, glass, etc.), a non-transparent substrate (e.g., silicon), and / or a partially transparent substrate (e.g., silicon with perforations). The silicon substrate with perforations can be manufactured using deep etching processes, such as deep reactive-ion etching (DRIE), metal-assisted chemical etching (MACE), etc.

[0333] In Figure 33, during the transfer of fields from one or more native wafers 3305 to one or more intermediate wafers 3306, the spacing of the fields 401 can be changed only along a single axis (either X or Y) using the transfer chuck assembly 1101. The fields 401 can then be transferred to a second set of intermediate wafers (not shown in Figure 33), where the field spacing is changed along a direction orthogonal to the previous step.

[0334] In one embodiment, the transfer chuck 111 is reconfigurable and includes optical elements attached to each individual or group of actuation units (to focus light from and to the light source 2402 and the photosensor onto the metering module 108). In one embodiment, the transfer chuck includes one or more light sources attached to each individual or group of actuation units 1007. In one embodiment, the optical elements and light source 2402 associated with an individual actuation unit 1007 may themselves be displaced relative to the actuation unit 1007 in the X, Y, and / or Z axes. Actuation can be performed using magnetic, electromagnetic (e.g., voice coil), thermal, piezoelectric, and / or pneumatic actuation methods.

[0335] In one embodiment, the directional mirror, along with one or more light sources 2402, is used to direct the light from the measurement head onto the transfer chuck 111. In one embodiment, the directional mirror is composed of a mirror having a reflectivity that starts at a predetermined amount and gradually increases and / or decreases as the light travels along the path from the light source 2402. In one embodiment, the directional mirror is composed of a transparent substrate coated with a patterned film of a reflective material, having varying pattern spacing to match reflectivity requirements at specific locations.

[0336] In one embodiment, a laser method can be used to remove and / or evaporate the filling material 1201. The laser can be used to heat a portion of the transfer chuck directly surrounding the filling material 1201. In one embodiment, the laser operates at an ultraviolet frequency. In one embodiment, the laser has a wavelength of 257 nanometers. In one embodiment, the laser is a continuous wavelength laser, a pulsed laser, or an ultrashort pulse laser. In one embodiment, wet cleaning is used to etch the filling material 1201. The cleaning material may be applied only in the vicinity of the location of the filling material 1201.

[0337] In one embodiment, the filling material 1201 is a transient material. In one embodiment, the filling material 1201 is end-capped polyoxymethylene.

[0338] In one embodiment, two or more transfer chucks 111 are used, wherein one of the transfer chucks 111 is used for picking up and placing components, and the remaining transfer chucks 111 are cleaned and returned to their preset states for vacuum switching. In one embodiment, the transfer chucks 111 are attached to an indexing mechanism. In another embodiment, the transfer chucks 111 are attached to a mechanism for reversing their orientation and indexing them for cleaning.

[0339] In one embodiment, a thermally stabilized optical plate is used as a reference to measure positioning errors in the field on the native substrate 103, the intermediate substrate 801, the transfer substrate 3309, and / or the product substrate 105. In one embodiment, a custom-manufactured optical plate is used to measure the positioning of different grains. In another embodiment, the optical plate consists of a dense array of alignment marks that maintain the same alignment for novel grains.

[0340] In one embodiment, the adhesive 3304 used for attaching the attachment field 401 to the native substrate 103, intermediate substrate 801, transfer substrate 3309, and / or product substrate 105 may consist of two or more layers. These layers may be UV-curable adhesives, nanoparticle pastes, thermosetting adhesives, pressure-sensitive adhesives, and / or transient materials. In one embodiment, the nanoparticle paste absorbs radiation within a narrow wavelength range. In one embodiment, the nanoparticle paste absorbs radiation within a narrow wavelength range, and one or more of the substrates and chucks in the n-MASC system exhibit minimum or zero absorptivity within this narrow wavelength range. In one embodiment, one component of the adhesive 3304 is a transient material that becomes gaseous upon heating. Heating can be performed using radiative (e.g., using laser), convective, or conductive heat transfer. In one embodiment, the transient material comprises polyethylene oxide. In one embodiment, adhesive 3304 is dispensed in the form of adhesive islands (e.g., adhesive islands 3308, 3401, 3502) onto the native substrate 103, the intermediate substrate 801, the transfer substrate 3309, and / or the product substrate 105. The size of the adhesive islands (e.g., adhesive islands 3308, 3401, 3502) can range from less than 10 micrometers to 300 millimeters.

[0341] In one embodiment, the native substrate 103, intermediate substrate 801, transfer substrate 3309, and / or product substrate 105 have a fixed and dense grid of alignment marks. For example, the alignment mark grid can be used as a fixed and stable reference to measure misalignment of the field picked up on the transfer chuck 111.

[0342] In one embodiment, the adhesive 3304 applied to the native substrate 103, the intermediate substrate 801, the transfer substrate 3309, and / or the product substrate 105 is performed outside of an n-MASC tool.

[0343] In one embodiment, the inventory of one or more buffer substrates of each type (required for product substrate 105) is maintained in a storage unit within the n-MASC tool. If the current inventory of buffer substrates is partially filled and does not contain all the dies required in the correct positions to create the desired field layout on product substrate 105, new buffer substrates can be added for a specific field type until a preset limit number of buffer substrates is reached. At this point, one or more buffer substrates from the inventory are used to achieve die-by-die or small-batch die pick-and-place.

[0344] In one embodiment, one or more of the encapsulation layers used during n-MASC include conductive elements. In one embodiment, the conductive elements are connected to a potential source to form an electrostatic attraction between the transfer chuck 111 and the field 401 at the location of the encapsulation layer. In one embodiment, one or more of the encapsulation layers and the device structure are located on opposite surfaces of the field 401.

[0345] In one embodiment, one or more micro-transfer chucks 3601 are used to pick up one or more dies 901. The micro-transfer chuck 3601 is positioned on a track 3806 and can be driven by electromagnetic attraction and / or repulsion between the track 3806 and the slider 3802. An exemplary system is shown in Figures 38A-38C. The track 3806 and / or the slider 3802 (on which the micro-transfer chuck 3601 is attached) may have embedded electromagnets to produce controlled motion on the X, Y, Z, θx, θy, and / or θz axes. In one embodiment, an orthogonal system of tracks is used: one or more Y tracks stop and are guided on orthogonal pairs of X tracks. One or more sliders 3802 may be guided on the Y tracks. By providing air cushions and / or magnetic cushions, the sliders 3802 may be constrained on the X, Y, Z, θx, θy, and / or θz axes. Slider 3802 and / or track 3806 may include perforations and / or holes to generate vacuum and / or pressure to create a cushioning effect. In one embodiment, slider 3802 and / or track 3806 may comprise porous ceramic (e.g., porous SiC) to generate pressure and / or vacuum. In one embodiment, a soft covering is used to cover the pressure and / or vacuum emanating from the perforations and / or holes in slider 3802 and / or track 3806. In one embodiment, a horizontal air curtain is formed on the surface of micro-transfer chuck 3601 and / or on the substrate on which the transfer is being performed. In one embodiment, the air curtain is used to reduce particulate contamination. In one embodiment, pressure is distributed only in two opposite directions (e.g., simultaneously toward the top and bottom of slider 3802) to create a reaction cushioning pad for slider constraint. In one embodiment, a combination of magnetic cushioning and air cushioning is used to constrain slider 3802. A mechanism similar to that used for slider 3802 can be used to constrain the Y track to the X track. In one embodiment, vacuum preload is used to constrain slider 3802 and / or one or more of the Y-tracks. In one embodiment, the bend is positioned in a plane parallel to and / or orthogonal to the transfer chuck 111, and can be used to constrain the micro transfer chuck 3601 along the X, Y, Z, θx, θy, and / or θz axes. In one embodiment, an out-of-plane scaling mechanism is used to provide the accommodation. In one embodiment, a scissor mechanism is used for the constraint on each Y-track. In one embodiment, a cable (for electrical and / or pneumatic connection of slider 3802 and / or micro transfer chuck 3601) is supported by the slider constraint bend.

[0346] In one embodiment, TC reconfiguration can be feedback-controlled. Global accuracy can be achieved using an encoder board. In one embodiment, the encoder board is used only at the start of assembly for a particular native wafer set. The encoder board can be loaded onto the native wafer chuck 102, the reconfigured transfer substrate 111, and then removed. Each micro-transfer chuck 3601 can reference a global precision encoder board. Real-time feedback can be achieved by incorporating an encoder board into the native wafer chuck 102 or a potential metrology module 108.

[0347] In one embodiment, a micro-transfer chuck 3601 is positioned on a positioning disk that slides on an electromagnetic plate, the electromagnetic plate being capable of controlling the movement of the positioning disk along the X, Y, Z, θx, θy, and / or θz axes. The micro-transfer chuck 3601 can face upwards, with the die 901 and / or field 401 to be picked up and placed facing downwards (so that the picking process separates the die and / or field from the substrate in a downward direction).

[0348] In one embodiment, the micro-transfer chuck 3601 is positioned on a clamping surface of 300 mm or greater. In one embodiment, the micro-transfer chuck 3601 is attached to the clamping surface using vacuum, electromagnetic force, and / or chemical adhesives. During pick-and-place assembly, the micro-transfer chuck 3601 can be picked up from the clamping surface using a micro-transfer chuck pick-up mechanism, and before being placed onto the intermediate wafer 801, transfer wafer 3309, or product wafer 105, the micro-transfer chuck 3601 expands or contracts in the X and / or Y axes to match the SPPx or SPPy of the product substrate 105. The expansion can be performed in one or two steps. In the case of expansion in one step, the pick-up mechanism may include a bending mechanism, such as a scissor mechanism that can expand independently in the X and Y directions. In the case of two steps, the pick-up mechanism first expands the spacing of all the micro-transfer chucks 3601 in one direction. Subsequently, the mechanism is rotated 90 degrees, or a separate mechanism arranged in the orthogonal direction to the first mechanism is used, to extend the spacing of the micro transfer chucks 3601 in the orthogonal direction. The pickup mechanism may use the above-described track system, or a scissor mechanism, or a combination thereof, to extend the spacing of the micro transfer chucks 3601.

[0349] Referring now to Figures 39A to 39C, Figures 39A to 39C illustrate an exemplary transfer chuck 111 according to an embodiment of the present invention, which shows an array of multiple adaptive chucking modules (ACMs) that can move relative to each other using a variable pitch mechanism (VPM).

[0350] As shown in Figure 39A, the transfer chuck 111 includes a curved pivot 3901. Figure 39B provides a cross-sectional view of the transfer chuck 111, depicting a selective transparency window 3902, an adaptive chuck module 3903 attached to a slider 3802, and a selective air bearing 3904.

[0351] In addition, Figure 39C provides a top view of the transfer chuck 111, which depicts the voice coil actuator 3905 and the adaptive chuck module 3903 fixed in the center.

[0352] Figures 40A and 40B illustrate an alternative exemplary transfer chuck 111 according to an embodiment of the present invention, showing an array of a plurality of elongated adaptive chuck modules 3903 that can move relative to each other using an adjustable spacing mechanism.

[0353] Referring to Figure 40A, which shows a top view of the transfer chuck 111, it depicts the X track 4001 and the Y track 4002, and the elongated adaptive chuck module 3903 fixed to the Y track 4002. In one embodiment, the width of the Y track 4002 is approximately 15 mm.

[0354] Figure 40B depicts an enlarged cross-sectional view of the Y-track 4002. As shown in Figure 40B, the end of the Y-track 4002 is supported by the X-track 4001 using an air bearing 4003. In one embodiment, the end of the Y-track 4002 is made of porous silicon carbide. In another embodiment, the end of the Y-track 4002 is made of a perforated metal to create the air bearing 4003. In one embodiment, actuation along the X-direction can be provided using an electromagnetic actuator system.

[0355] Figure 41 shows another alternative exemplary transfer chuck 111 according to an embodiment of the present invention, which shows an array of a plurality of elongated adaptive chuck modules 3903 that can move relative to each other using an adjustable spacing mechanism.

[0356] As shown in Figure 41, the transfer chuck 111 includes a curved portion 4101 in the X direction.

[0357] Figures 42A and 42B illustrate an exemplary adaptive chuck module 3903 according to an embodiment of the present invention.

[0358] Referring to Figure 42A, Figure 42A shows a cross-section of the adaptive chuck module 3903. Specifically, Figure 42A shows an exemplary connection 4201 to the switch, fixed electrode 4202, moving electrode 4203, and the 5-micron gap 4204 between these electrodes 4202, 4203. Furthermore, Figure 42A shows the position 4205 in the atmosphere and the ACM needle 4206 on the die 901. Additionally, Figure 42A shows a needle pitch of approximately 100 microns. Furthermore, Figure 42A shows a double seal 4207, a polycrystalline silicon membrane 4208, and a vacuum inlet 4209.

[0359] Figure 42B depicts a top view of the adaptive chuck module 3903 showing the path of the vacuum inlet 4209.

[0360] Further discussion is provided below regarding Figures 39A-39C, 40A-40B, and 42A-42B.

[0361] In one embodiment, the transfer chuck 111 may be composed of an array of adaptive chuck modules 3903, each of which can be used to pick up and place one or more fields 401 from the native / intermediate / product substrate 103 / 801 / 105. In one embodiment, the adaptive chuck module 3903 is composed of an array of valve units. In one embodiment, an electrostatic actuation mechanism is used to actuate the valve. In one embodiment, a seal 4207 consisting of one or more chambers is used to isolate the vacuum inlet 4209 from the outlet. In one embodiment, the air volume contained within the seal 4207 consisting of one or more chambers is used to cushion the impact of the diaphragm 4208 when the valve is closed.

[0362] The adaptive chuck module 3903 can move relative to each other using a variable pitch mechanism. The variable pitch mechanism can consist of bending bearings, air bearings, electromagnetic bearings, and pneumatic or electromagnetic actuators. In one embodiment, the adaptive chuck module 3903 is mounted on a planar motor that provides actuation along six axes. Some exemplary designs are shown in Figures 39A-39C, 40A-40B, and 41.

[0363] In one embodiment, the adaptive chuck module 3903 includes theta actuation for the adaptive chuck module 3903 relative to a variable pitch mechanism. In one embodiment, the theta actuation mechanism is curved. In one embodiment, a thermal actuator comprising thermal expansion in the curved arm is used to actuate the theta-actuated bend. In one embodiment, the spacing between the pickup areas in the transfer chuck 111 is increased to accommodate a longer bend for thermal actuation, thereby producing a greater theta displacement.

[0364] In one embodiment, one or more imagers 1401 are used to detect errors in the field of pickup and placement by the adaptive chuck module 3903. In one embodiment, the imager 1401 is a visible light imager or an IR imager. In one embodiment, each imager 1401 observes a single adaptive chuck module 3903 or each imager 1401 observes multiple adaptive chuck modules 3903. An automatic fault detection algorithm can use the image stream from the imager 1401 to mark errors in the pickup and placement process. The error detection algorithm can be based on artificial neural networks (ANNs), convolutional neural networks (CNNs), etc.

[0365] Figures 43A to 43C illustrate another exemplary transfer chuck 111 according to an embodiment of the present invention, showing an array of multiple adaptive chuck modules 3903 that can move relative to each other using an adjustable spacing mechanism.

[0366] Referring to Figure 43A, the transfer chuck 111 includes a scissor mechanism 4301 for Y-expansion / retraction of the adaptive chuck module 3903.

[0367] Figure 43B is an enlarged cross-sectional view of the scissor mechanism 4301. As shown in Figure 43B, a fixed point 4303 on the adjustable pitch mechanism 4302 is illustrated. Furthermore, the adjustable pitch mechanism 4302 includes an actuator arm 4304 coated with a photothermal conversion material (e.g., light-absorbing nanoparticle links, light-to-heat conversion (LTHC) release coating, etc.). Additionally, the adjustable pitch mechanism 4302 includes a thermally insulated connector 4305.

[0368] Figure 43C shows another enlarged view of the cross-section of the scissor mechanism 4301. As shown in Figure 43C, Figure 43C shows the selective cantilever bending section 4306, which is allowed to move on the X, Y, and θ axes but with minimal movement in the Z plane.

[0369] Figure 43C further illustrates the selectively insulating frame 4307 connected to the adaptive chuck module 3903 using a selectively insulating adhesive.

[0370] Referring to Figures 43A-43C, in one embodiment, the adaptive chuck module 3903 is connected to the adjustable pitch mechanism 4302 using a mechanism actuating one or more of the X, Y, and θ axes. In one embodiment, the X or Y displacement ranges from at least 100 nanometers, while the θ ranges from at least 10 microradians. In one embodiment, the actuation mechanism is connected to the fixed point 4303 of the adjustable pitch mechanism 4302 and the adaptive chuck module 3903. In one embodiment, the connection between the aforementioned mechanism and the fixed point 4303 of the adjustable pitch mechanism 4302 and the adaptive chuck module 3903 is achieved using a thermally insulating material. In one embodiment, the thermally insulated connector also has low overall thermal expansion (less than 25 nanometers or even less than 10 nanometers). This low overall thermal expansion can be achieved using connector materials with a low coefficient of thermal expansion (CTE) or using thin (micrometer-scale) connectors or a combination of low CTE and thin connectors. These connector materials may include thermally insulating adhesives, polymer connectors with low overall thermal expansion, fused silica, or stainless steel. In one embodiment, the actuator arm 4304 is coated with a photothermal conversion material (e.g., a light-absorbing nanoparticle paste, an LTHC layer). In one embodiment, heating of the actuator arm 4304 is performed by using one or more of the following groups: scanning light source, digital micromirror array, LED array, and microLED array. In one embodiment, a heat sink is used to maintain a stable reference temperature for the actuator arm 4304. The heat sink may consist of a fluid flow (e.g., air) across the actuator arm 4304 and / or embedded fluid microchannels. In one embodiment, the variable pitch mechanism 4302 has a range of motion of at least one millimeter.

[0371] Referring now to Figures 44A to 44F, Figures 44A to 44F illustrate an exemplary transfer substrate 3309 according to an embodiment of the present invention.

[0372] As shown in Figure 44A, Figure 44A illustrates the transfer substrate 3309. Figure 44B shows an enlarged cross-sectional view of the transfer substrate 3309. Figure 44B illustrates a selective mesa 4401 (an area of ​​the substrate 3309 on the transfer substrate 3309 that has not yet been etched away) for capillary pinning of the adhesive. In one embodiment, the mesa 4401 is fabricated using a polymer and patterning, for example, by photolithography. In one embodiment, the mesa 4401 is transparent to UV light (e.g., for example, a photoresist material). In one embodiment, the material of the mesa 4401 is index-matched to the waveguide layer. The refractive index of the mesa material can be adjusted to allow only a portion of the light in the waveguide to leak through the mesa 4401 into the adhesive (e.g., for UV curing).

[0373] Furthermore, as shown in Figure 44B, after being picked up from the native substrate 103, a small amount of native substrate adhesive 4402 may be selectively left on the bottom side of the field 401.

[0374] Furthermore, Figure 44B illustrates two exemplary adjacent fields 401. In one embodiment, fields 401 are positioned with their active sides facing upwards (away from the transfer substrate 3309). Variations in the height of fields 401 can be compensated for by compliant bends, adhesive droplet volume adjustments, and cantilevered edges of fields 401 near their edges, as shown in element 4403.

[0375] Additionally, Figure 44B shows UV-curable adhesive 4404.

[0376] Furthermore, Figure 44B illustrates a selective waveguide layer 4405. Waveguide layer 4405 may be located on top of and / or beneath the z-bend structures. In one embodiment, waveguide layer 4405 is made using SiO2, silicon nitride, and / or a UV-transmitting polymer (e.g., acrylic acid).

[0377] Furthermore, Figure 44B depicts an internal coupling grating 4406 for coupling light (e.g., UV 4407) into the lateral waveguide structure 4405. These can be located near the periphery of the transfer substrate 3309 and / or the cut-out region between the field 401. These can be selectively patterned on the imprinted photoresist system using Jet and Flash Imprint Lithography.

[0378] Additionally, Figure 44B shows the bulk portion 4408 of the transfer substrate 3309 (e.g., a bulk silicon approximately 775 micrometers thick). This can be selectively perforated using etching techniques, such as catalyst-affected chemical etching (CICE) or deep reactive ion etching (DRIE), to allow the adhesive 4404 to be UV exposed from the bottom side of the transfer substrate 3309.

[0379] Furthermore, Figure 44B illustrates a selective encapsulation layer 4409 for the z-compliant structure 4410. In one embodiment, the encapsulation layer 4409 separates the internal structure of the z-compliant structure 4410 from the pickup field 401. In one embodiment, the z-compliance amount of the encapsulation layer 4409 is varied by changing its thickness. In one embodiment, the encapsulation layer 4409 is made using silicon, polycrystalline silicon, silicon oxide, polymers, and / or metals (e.g., chromium).

[0380] Additionally, Figure 44B shows the selective external coupling grating 4411.

[0381] Referring now to Figure 44C, which is an enlarged view of the z-compliant structure 4410, the z-compliant structure 4410 includes a bending rod 4412. In one embodiment, the bending rod 4412 is designed to bend whenever the force acting on the field thereon exceeds a certain value. Furthermore, Figure 44C shows a groove 4413 in the z-compliant structure 4410, which can be filled with a selective sacrificial material (e.g., silicon oxide, porous carbon, polyvinyl alcohol (PVA), etc.), wherein the sacrificial material can be removed at the end of manufacturing using a suitable etchant.

[0382] Figure 44D is an enlarged view of the top of the z-compliant structure 4410. As shown in Figure 44D, the secondary bend 4414 allows the center pad 4415 to bend in the z-direction while preventing substantial movement in the XY plane. In one embodiment, the platform 4401 and adhesive 4404 may optionally be positioned above the center pad 4415.

[0383] Figure 44E is an enlarged view of the central portion of the compliant structure 4410. As shown in Figure 44E, the bent bar layer 4412 may be made of silicon (e.g.) and bonded to the remainder of the compliant layer using a suitable bonding technique (e.g., covalent bonding).

[0384] Furthermore, Figure 44F is an enlarged top view of the inner coupling grating 4406 (e.g., for UV light). Additionally, Figure 44F shows a top view of a cross-section near the adhesive droplets 4416, illustrating the droplet staggering to allow the UV radiation coupled to the waveguide layer 4405 to reach maximum droplet quantity before being absorbed or scattered.

[0385] Figure 45 illustrates an alternative exemplary transfer substrate 3309 according to an embodiment of this case.

[0386] Referring to Figure 45, Figure 45 illustrates a selective mesa 4401 for capillary pinning of adhesive 4404. In one embodiment, mesa 4401 is made of a polymer and patterned using photolithography. In one embodiment, mesa 4401 is transparent to IR light 4501. Optionally, mesa 4401 may embed nanoparticles that selectively absorb light of a specific wavelength (e.g., infrared light). These can be used for localized heating and curing of both parts of adhesive 4404.

[0387] Figure 45 further illustrates the selective two-part adhesive 4404 (similar to the adhesive shown in Figure 44B, except that it is cured by IR radiation). In one embodiment, adhesive 4404 is stored separately and dispensed together prior to the field attachment step (e.g., using inkjet printing). In one embodiment, adhesive 4404 may selectively embed nanoparticles that selectively absorb light of a specific wavelength (e.g., infrared light 4501). These can be used for localized heating and curing of the two-part adhesive 4404.

[0388] Referring to Figures 44A-44F and 45, the transfer substrate 3309 is an intermediate substrate 801 on which the field 401 is temporarily assembled immediately before being mixed and bonded to the product substrate 105 (in the integration sequence). The field 401 is typically transferred from the transfer substrate 3309 to the product substrate 105 as a whole substrate.

[0389] In one embodiment, the transfer substrate 3309 includes an embedded structure that selectively conforms in the Z direction while being rigid in the X and Y directions. Exemplary structures are shown in Figures 44A-44F and Figure 45. This structure can be assembled by bonding multiple 2D fabricated layers together using techniques such as laser processing, lithography, etching, etc. The recesses 4413 in the embedded structure can be filled with sacrificial materials such as SiO2, water-soluble polyvinyl alcohol (PVA), porous carbon, etc. The filler layer can be used to support the internal structure to prevent collapse and damage, and any subsequent layers that can be grown on top of the fabricated layers. At the end of the manufacturing process, the filler layer can be etched away using a suitable etchant (e.g., HF for SiO2, water for PVA, etc.). The filler layer and the internal structure can be coated with an encapsulation layer 4409 consisting of SiO2, spin-on-glass (SOG), metal, polymer, silicon, and / or polycrystalline silicon. In one embodiment, the encapsulation layer 4409 is covered by a metal layer that facilitates internal reflection of light within the waveguide layer.

[0390] In one embodiment, the in-plane deformation of the transfer substrate 3309 is controlled using thermal actuation (e.g., Peltier coolers, infrared radiation localized heating sources) and mechanical actuation techniques. In one embodiment, thermal actuation is used to remove any excess heat generated during the use of, for example, UV radiation curing adhesives. Alternatively, a high thermal conductivity adhesive may be used to facilitate the heat transfer process.

[0391] In one embodiment, the transfer substrate 3309 is customized for each new SiP. In another embodiment, the encapsulation layer 4409, the mesa layer 4401, and the inner coupling grating layer 4406 are patterned custom-designed for each SiP.

[0392] In one embodiment, to prevent interference between the transfer substrate facing surface of the transfer chuck 111 and the pre-existing field 401 on the transfer substrate 3309 (when the field 401 picked up by the transfer chuck 111 is placed onto the transfer substrate 3309), a short plasma stripping step can be used to reduce the thickness of the encapsulation layer 4409 on the pre-existing field 401. The plasma can be atmospheric pressure plasma.

[0393] In one embodiment, to prevent interference between the transfer / native / intermediate substrate facing surface of the transfer chuck 111 and a pre-existing field 401 on the transfer / native / intermediate substrate 3309 / 103 / 801 (when the field 401 picked up by the transfer chuck 111 is placed onto the transfer / native / intermediate substrate 3309 / 103 / 801), a repulsive force can be generated between the pre-existing field 401 on the transfer / native / intermediate substrate 3309 / 103 / 801 and the transfer / native / intermediate substrate facing surface of the transfer chuck 111. This force can be generated by expelling air from the adaptive chuck module 3903 at the location of the pre-existing field, creating a thin air cushion that separates the pre-existing field 401 from the substrate facing surface of the transfer chuck 111. Alternatively, the force can be generated by charging the substrate-facing surface of the transfer chuck 111 and the transfer chuck-facing surface of the pre-existing field 401 with similar polarity charges to create electrostatic repulsion between the surfaces. In one embodiment, the compliance of the z-bending structure 4412 (also referred to as a "bending bar") inside the transfer / native / intermediate substrate 3309 / 103 / 801 can be altered to help create a gap between the transfer chuck and the field during the placement step.

[0394] In one embodiment, one or more of the mesa layer 4401, waveguide layer 4405, encapsulation layer 4409, and z-compliant structure in the transfer substrate 3309 may be made of a material with high thermal conductivity (e.g., metal, silicon, high thermal conductivity composite polymer containing high thermal conductivity filler) to allow heat to be transferred vertically and laterally from the field 401 to the body of the transfer / native / intermediate substrate 3309 / 103 / 801 and the transfer chuck 111.

[0395] In one embodiment, the thickness of the mesa structure 4401 is increased to increase the local X and Y compliance of the transfer / native / intermediate substrate 3309 / 103 / 801. In another embodiment, the volume of the adhesive droplets 4416 is increased to increase the pinning height of the adhesive 4404, thereby increasing the effective local X and Y compliance of the transfer / native / intermediate substrate 3309 / 103 / 801.

[0396] Figures 46A and 46B illustrate an exemplary interference prevention method according to an embodiment of the present invention (during field assembly to transfer substrate 3309).

[0397] Referring to Figure 46A, Figure 46A shows an exemplary field 4601 already assembled on the transfer substrate 3309. The illustrated field 401 has, for example, a greater thickness than the field 401 being assembled. Without an interference prevention method, this would be hindered by the adaptive chuck module 3903 attempting to assemble the field 401 onto the transfer substrate 3309.

[0398] In addition, Figure 46A shows the field 4602 that is currently being assembled onto the transfer substrate 3309.

[0399] Figure 46B is an enlarged view of a portion of the transfer substrate 3309. As shown in Figure 46B, localized air pressure and / or electrostatic repulsion 4603 are generated by the adaptive chuck module 3903 (at the location of the assembled field 4601) to prevent interference between the assembled field and the transfer chuck / adaptive chuck module 111 / 3903.

[0400] Furthermore, as shown in Figure 46B, the curved structure in the transfer substrate 3309 helps to reduce interference.

[0401] Referring now to Figures 47A to 47E, Figures 47A to 47E illustrate an exemplary native substrate 103 according to an embodiment of this case.

[0402] As shown in Figure 47A, Figure 47A illustrates the native substrate 103. Figure 47B shows an enlarged cross-sectional view of the native substrate 103. Figure 47B illustrates selective mesa 4701 (areas of the native substrate 103 that have not yet been etched away) for capillary pinning of the adhesive. In one embodiment, mesa 4701 is made using a polymer and patterned, for example, by photolithography. In one embodiment, mesa 4701 is transparent to IR light. In one embodiment, mesa 4701 may embed nanoparticles that selectively absorb light of a specific wavelength (e.g., infrared light). These can be used for localized heating and curing of both parts of the adhesive.

[0403] Furthermore, as shown in Figure 47B, after being picked up from the native substrate 103, a small amount of native substrate adhesive 4702 may be selectively left on the bottom side of the field 401.

[0404] Furthermore, Figure 47B illustrates two exemplary adjacent fields 401. In one embodiment, the fields 401 are positioned with their active sides facing upwards (away from the native substrate 103). Variations in the height of the fields 401 can be compensated for by compliant bends, adhesive droplet volume adjustments, and cantilevered edges of the fields 401 near their edges.

[0405] Additionally, Figure 47B shows selective UV radiation 4703 for transient material activation.

[0406] In addition, Figure 47B shows the bulk portion 4704 of the native substrate 103 (e.g., a bulk silicon layer approximately 775 micrometers thick or a perforated silicon layer made using a suitable etching technique).

[0407] Furthermore, Figure 47B illustrates a selective encapsulation layer 4705 for the z-compliant structure 4706. In one embodiment, the encapsulation layer 4705 separates the internal structure of the z-compliant structure 4706 from the pickup field 401. In one embodiment, the z-compliance amount of the encapsulation layer 4705 is varied by changing its thickness. In one embodiment, the encapsulation layer 4705 is made using silicon, polycrystalline silicon, silicon oxide, polymers, and / or metals (e.g., chromium).

[0408] Additionally, Figure 47B illustrates a selective transient material (adhesive) 4707. In one embodiment, the transient material 4707 is inkjet-sprayed onto the top of the mesa layer 4701. A phase transition can be induced, for example, by heat or UV radiation. Optionally, the transient material 4707 may embed nanoparticles that selectively absorb light of specific wavelengths (e.g., infrared light). These can be used for locally heated materials.

[0409] Referring now to Figure 47C, which is an enlarged view of the z-compliant structure 4706, the z-compliant structure 4706 includes a bending rod 4708, as shown in Figure 47C. In one embodiment, the bending rod 4708 is designed to bend whenever the force acting on the field thereon exceeds a certain value. Furthermore, Figure 47C shows a groove 4709 in the z-compliant structure 4706, which may be filled with a selective sacrificial material (e.g., silicon oxide, porous carbon, polyvinyl alcohol (PVA), etc.), wherein the sacrificial material can be removed at the end of manufacturing using a suitable etchant.

[0410] Figure 47D is an enlarged view of the top of the z-compliant structure 4706. As shown in Figure 47D, the secondary bend 4710 allows the center pad 4711 to bend in the z-direction while preventing substantial movement in the XY plane. In one embodiment, the platform 4701 and the adhesive 4707 may optionally be positioned above the center pad 4711.

[0411] Figure 47E is an enlarged view of the central portion of the compliant structure 4706. As shown in Figure 47E, the bent bar layer 4708 may be made of silicon (e.g.) and bonded to the remainder of the compliant layer using a suitable bonding technique (e.g., covalent bonding).

[0412] In one embodiment, the native substrate 103 may consist of a field 401 attached to a transparent carrier substrate (e.g., glass, fused silica, sapphire) or a framed carrier membrane using an adhesive (e.g., adhesive 4707). The adhesive may be a continuous film with varying thickness to compensate for variations in the thickness of the field 401, or it may be separated into islands whose X / Y range and thickness vary depending on the different X / Y ranges and thicknesses of the field 401. In one embodiment, such a native substrate 103 is formed by starting with a field 401 of a substrate having a sacrificial layer, such as silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), flipping it over and attaching it to a suitable carrier substrate as a whole, and separating the body of the starting substrate using a suitable etchant. In one embodiment, the starting substrate consists of a field 401 fabricated on top of a sacrificial silicon-germanium (SiGe) layer. This SiGe layer can be grown using epitaxial deposition techniques. Etching of the sacrificial silicon-germanium layer can be performed using wet etching, plasma etching, atomic layer etching, and hybrid etching methods. In one embodiment, an etchant composed of vapor HF, vapor H2O2, and vapor acetic acid is used.

[0413] Figure 48 is a flowchart of a method 4800 for creating a native substrate for assembly from a substrate having a sacrificial layer according to an embodiment of the present invention. Figures 49A to 49F depict cross-sectional views of creating a native substrate for assembly from a substrate having a sacrificial layer using the steps described in Figure 48 according to an embodiment of the present invention.

[0414] Referring to Figure 48 in conjunction with Figures 49A-49F, in step 4801, partial etching of the sacrificial layer 4903 is performed to create tethers as shown in Figures 49A-49B. Figure 49A shows the monomerization field 4901 with an active layer on top. Furthermore, Figure 49A shows the inlet / outlet holes 4902 for the sacrificial layer etchant and the sacrificial layer 4903 on the bulk substrate 4904. Additionally, Figure 49A shows the field cutout 4905.

[0415] As described above, in step 4801, partial etching of the sacrificial layer 4903 is performed to create the chain 4906 as shown in FIG49B.

[0416] In step 4802, the bulk substrate 4904 is flipped and temporarily attached to the intermediate substrate 4907 via adhesive 4908, as shown in FIG49C. In one embodiment, the intermediate substrate 4907 is made of silicon, silicon carbide, silicon oxide, fused silica, sapphire, polymer film and / or frame.

[0417] In step 4803, sacrificial layer etching is used to separate the bulk substrate 4904, as shown in FIG49D. In one embodiment, the bulk substrate 4904 (also referred to as the "carrier substrate") is always attached to a carrier substrate chuck. The carrier substrate chuck may optionally be etch-resistant, for example made of polytetrafluoroethylene (PTFE) and / or sapphire.

[0418] In step 4804, the intermediate substrate 4907 is flipped over and temporarily attached to the native substrate 4909 (e.g., native substrate 103) for assembly using adhesive islands 4910, as shown in FIG49E. In one embodiment, the native substrate 4909 is made of silicon, silicon carbide, silicon oxide, fused silica, sapphire, polymer film, and / or frame.

[0419] In step 4805, the intermediate substrate 4907 (together with the adhesive 4908) is removed, for example by etching, leaving the native substrate 4909 with the field 4901, as shown in FIG49F.

[0420] Further discussion on method 4800 is provided below.

[0421] In one embodiment, fields 401 and 4901 include access vias distributed throughout the entire area of ​​fields 401 and 4901. Etch for the sacrificial layer (e.g., sacrificial layer 4903) may originate from the edges of fields 401 and 4901, as well as from access vias 4902 (during chain-forming etching and substrate separation). In one embodiment, the XY spacing of access vias 4902 is 20 micrometers. In one embodiment, the silicon layer above sacrificial layer 4903 is approximately 300 nanometers thick. In one embodiment, sacrificial layer 4903 is approximately 0.5 micrometers thick if a vapor etchant is used, and approximately 5 micrometers thick if a wet etchant is used, wherein the selected values ​​allow for sufficient lateral transport of the sacrificial layer etchant.

[0422] In one embodiment, the thickness of the mesa structure 4401 (shown in FIG. 45) is increased to increase the local X and Y compliance of the native substrates 103 and 4909. In another embodiment, the volume of the adhesive droplets 4416 (see FIG. 44F) is increased to increase the pinning height of the adhesive 4404, thereby increasing the effective local X and Y compliance of the native substrates 103 and 4909.

[0423] In one embodiment, during back-side polishing or during the native wafer creation process (on the intermediate carrier substrate) shown in Figures 47A-47E, when fields 401 and 4901 are with their active sides facing down, their thicknesses can be modulated using one or more of subtractive (e.g., inkjet planarization) and additive (e.g., adding material to the back side using inkjet, chemical vapor deposition, spin coating, etc.). In one embodiment, a carrier substrate 4904, which may be made of silicon, silicon oxide, sapphire, fused silica, etc., is polished to a highly flat surface and serves as a reference for fields 401 and 4901 attached to the substrate. The field height on the carrier substrate 4904 can be measured using a suitable morphology measurement technique that measures the morphology variation between the notch 4905 and the edge of each field 401, 4901. In one embodiment, a barometric thickness measurement method is used to measure the thickness of fields 401 and 4901.

[0424] The adhesive described herein can be used to attach fields 401 and 4901 to native, intermediate, transfer, and carrier substrates 103, 801, 3309, and 4904, as well as transfer chuck 111. The adhesive may be composed of UV-release adhesives, thermal-release adhesives, photothermal conversion (LTHC) coatings, liquid crystal (LC) adhesives, UV phase-switching liquid crystal adhesives, etc.

[0425] In one embodiment, the adhesive layer comprises one or more layers of a first light-absorbing layer and a transient material layer. The light-absorbing layer may be a pure polymer layer (e.g., an LTHC coating manufactured by 3M®), or a polymer-nanoparticle composite optimized for light absorption. In one embodiment, an adhesive coating (e.g., VALMat) that adheres to the transient material may be applied to the bottom side and / or the entirety of fields 401, 4901.

[0426] In one embodiment, adhesive droplets 4416 are dispensed at a suitable distance from the edges of fields 401, 4901, such that the cantilevered fields (near the edges of fields 401, 4901) bend to accommodate any residual height differences between adjacent fields 401, 4901 during the mixing and bonding process. If the thickness of fields 401, 4901 is small, this bending may not necessarily result in any significant overlap error.

[0427] In one embodiment, the photothermal conversion (LTHC) layer is used for localized heating and / or evaporation of the adhesive. The LTHC layer may consist of one or more resonant absorption layers. In one embodiment, the LTHC comprises embedded nanoparticles designed to absorb radiation in a narrow wavelength range, ideally at wavelengths exhibiting minimum or zero light absorption at one or more of the transfer chuck 111, native substrate 103, and transfer substrate 3309. In one embodiment, the adhesive is composed of polyimide. In one embodiment, the adhesive consists of a polyimide-LTHC-based release layer.

[0428] In one embodiment, the nanoparticles used for light absorption in the LTHC layer are made of gold, silicon, ruthenium, noble metals, titanium, and / or tungsten. In one embodiment, the size of the nanoparticles is increased to raise their melting point (e.g., the melting point of gold nanoparticles decreases as the size of the nanoparticles decreases).

[0429] Figures 50A to 50C illustrate an exemplary yield management process according to an embodiment of this case.

[0430] Referring now to Figure 50A, Figure 50A shows an exemplary SIP 5001 on a transfer substrate 3309, which shows four exemplary known defective dies 2605 that need to be replaced with known good dies 2603 from a buffer substrate.

[0431] Referring to Figure 50B, Figure 50B shows known good grains 2603 on various active buffer substrates 5002A-5002N, where N is a positive integer (5002A is identified as "active buffer substrate 1", 5002B is identified as "active buffer substrate 2", and 5002N is identified as "active buffer substrate N"). Active buffer substrates 5002A-5002N may be referred to collectively or individually as multiple active buffer substrates 5002 or active buffer substrate 5002.

[0432] At any given time point, N (N being a positive integer) active buffer substrates 5002 are maintained. In one embodiment, these are kept at a low depletion level at all time points, such that a known defective die replacement step for any given transfer wafer 3309 can be completed in at most one or two pick-and-place steps.

[0433] Figure 50C shows a series of inert buffer substrates 5003-5003N, where N is a positive integer (5003A is identified as "inert buffer substrate 1", 5003B as "inert buffer substrate 2", and 5003N as "inert buffer substrate N"). The inert buffer substrates 5003A-5003N can be collectively or individually referred to as multiple inert buffer substrates 5003 or inert buffer substrates 5003.

[0434] As shown in Figure 50C, the die 901 from the most depleted inert buffer substrate 5003 (e.g., inert buffer substrate 5003N) is assembled onto the least depleted inert buffer substrate 5003 (e.g., inert buffer substrate 5003A) in a die-by-die manner using a die-by-die transfer chuck, as indicated by arrow 5004 in Figure 50C.

[0435] Furthermore, as shown in Figures 50B and 50C, once one of the active buffer substrates 5002 reaches a pre-specified depletion level, the least depleted inert buffer substrate 5003 (e.g., inert buffer substrate 5003A) can be sent to the active group of buffer substrates 5002, as indicated by arrow 5005.

[0436] Figures 51A to 51D illustrate an exemplary method for creating cutting and alignment marks according to an embodiment of this case.

[0437] Figure 51A shows an uncut field 5101, in which the device layer is oriented towards the adhesive 5102 on the carrier substrate 3302.

[0438] Furthermore, Figure 51B is an enlarged view of the layer above the carrier substrate 3302 shown in Figure 51A. As shown in Figure 51B, Figure 51B shows the device structure 5103 located on the encapsulation layer 5104. Additionally, Figure 51B shows the adhesive layer 5102, which may optionally be an etch stop layer. Furthermore, Figure 51B shows the layer 5105 used to create metal fractures. Additionally, Figure 51B shows the selective catalyst 5106 used to create alignment marks using CICE. Furthermore, Figure 51B shows the notched region 5107, with an enlarged view of the notched region 5107 shown in Figure 51C.

[0439] As shown in Figure 51C, the cut area 5107 includes alignment marks 5108.

[0440] Furthermore, the plasma etching used for field cutting is shown in Figure 51D. As shown in Figure 51D, alignment marks 5109 are created using CICE. As further shown in Figure 51D, the cutting edge 5110 is created using plasma etching.

[0441] In one embodiment, alignment marks 5108, 5108 are created in the field during monomerization.

[0442] In one embodiment, alignment marks 5108 and 5109 are created on the back side of the field. For example, photolithography (PL) or nanoimprint lithography (NIL) can be used to pattern marks 5108 and 5109. In another embodiment, deep reactive ion etching (DRIE) can be used for dry etching of marks 5108 and 5109. In yet another embodiment, CICE can be used for etching marks 5108 and 5109. Markers 5108 and 5109 may be placed below the circuit pattern or near the cutout region 5107 away from the circuit area. Markers 5108 and 5109 may be etched through the thickness of the field or partially etched.

[0443] Monomerization of a field can be performed using a separate set of patterning and etching techniques (compared to the alignment mark creation step). Photolithography (PL) or nanoimprint lithography (NIL) can be used for patterning. Dry etching (e.g., DRIE) can be used for etching. Additionally, wet etching (e.g., CICE) can be used for etching. Alternatively, laser methods, such as laser cutting or stealth cutting, can be used to perform monomerization.

[0444] Referring now to FIG52A, FIG52A illustrates the positioning of a field 401 picked up on a transfer chuck 111 to a stable reference grid according to an embodiment of the present invention. In particular, FIG52A illustrates an upward-viewing microscope 5201 for positioning the picked-up field 401 relative to the stable reference grid and / or relative to the transfer chuck 111.

[0445] Figure 52A further illustrates the selectively coupled microscope position on a separate variable-pitch mechanism 5202, which can be calibrated against a stable reference grid.

[0446] Referring now to Figure 52B, Figure 52B shows the position of the complex adaptive chuck module 3903 relative to a stable reference grid 5203 (e.g., a stable grid plate) according to an embodiment of the present invention.

[0447] As shown in Figure 52B, the integrated light source and sensor pairs 5204A-5204B and 5204C-5204D are used to transmit the displacement of the adaptive chuck module 3903 relative to the stable reference grid 5203 (e.g., a stable grid plate). The integrated light source and sensor pairs 5204A-5204D may be collectively or individually referred to as multiple integrated light source and sensor pairs 5204 or integrated light source and sensor pairs 5204.

[0448] Referring to Figures 52A-52B, in one embodiment, an upward-facing microscope 5201 is used to measure the position of the field 401 relative to a global grid, or the alignment of the transfer chuck 111 relative to the alignment mark position on the field 401 when it is picked up onto the transfer chuck 111. In one embodiment, the upward-facing microscope 5201 is placed on a reconfigurable variable-pitch mechanism, such as a variable-pitch mechanism 5202. In one embodiment, the position of the upward-facing microscope 5201 can be measured relative to a stable 2D grid and a grid encoder attached to the microscope 501. The position of the microscope 5201 on the variable-pitch mechanism, such as the variable-pitch mechanism 5202, can be calibrated intermittently once, or actively observed during each pick-and-place step. Alternatively, a textured measurement method can be used to measure the position of the upward-facing microscope 5201, where one set of textured marks is placed on the microscope 5201 and another set of textured marks is placed on a stable reference substrate. The textured microscope is then used to observe the relative positions of the corresponding mark sets on the upward-facing microscope 5201 and the reference substrate. In one embodiment, the native substrate 103 is used to assemble a plurality of transfer substrates 3309, such that the variable pitch mechanism for the upward-facing microscope 5201, such as the variable pitch mechanism 5202, must only be reconfigured when a new native substrate is loaded.

[0449] In one embodiment, an upward-looking microscope 5201 is used to sample areas 401 from the native substrate 103 that have been picked up by the transfer chuck 111 at a limited set of locations to measure the positions of those areas 401 relative to the stable reference grid 5203 and / or relative to the transfer chuck 111. Suitable position extrapolation techniques can be used to extrapolate the positions of the remaining picked-up areas 401 on the transfer chuck 111.

[0450] Alignment marks on the field can be observed from the bottom side of the transfer chuck 111, directly above the transfer chuck 111, or above the transfer chuck 111 which has an alignment signal originating from the internally coupled grating 4406 (which is used to deliver UV light for adhesive curing). Interference from alignment signals and circuit elements (e.g.) on the field 401 can be filtered out using calculation methods or by designing the position of the alignment marks to avoid interfering structures.

[0451] In one embodiment, the position of the variable-pitch mechanism, such as the adaptive chuck module 3903 on the variable-pitch mechanism 4302, can be directly observed relative to a stable 2D grid. A small grid encoder can be integrated into the adaptive chuck module 3903 and used to view the 2D grid plate to measure the displacement of the adaptive chuck module 3903 in real time during assembly.

[0452] In one embodiment, the transfer substrate 3309 includes a grid of alignment marks. The grid of alignment marks may be selectively patterned on a mesa (e.g., mesa 4401) in the transfer substrate 3309 using the same technique (e.g., i-line lithography) as the mesa (e.g., mesa 4401) is fabricated. In one embodiment, an incoming field 401 is aligned with the grid of alignment marks on the transfer substrate 3309. Field position errors from a selectively upward-facing microscope 5201 and from an alignment microscope used to measure the alignment between the transfer substrate 3309 and the field 401 can be corrected by a thermal actuator assembly on the transfer substrate chuck.

[0453] In one embodiment, the zero layer of all fields 401 is created on the same lithography tool (this includes different kinds of fields, not just different fields of the same kind).

[0454] In one embodiment, the field-facing surface of the transfer chuck 111 is polished to a highly flat surface to serve as a reference plane for the pick-up and place-down field 401. In another embodiment, the surface of the transfer chuck 111 is actively adjusted in the z-direction to achieve a flat or desired non-flat profile.

[0455] In one embodiment, the product wafer chuck 104 includes an actuator to flatten the surface of the product wafer 105 prior to mixing and bonding. The sensing of the topography on the product wafer 105 can be performed using laser methods, barometers, etc. Actuation of the wafer chuck can be performed using piezoelectric actuators, thermal actuators, and / or electromagnetic actuators.

[0456] Referring now to Figures 53A and 53B, Figures 53A and 53B illustrate an exemplary method for cutting using an inkjet catalyst based on metal-assisted catalytic etching (MACE) according to an embodiment of the present invention.

[0457] As shown in Figure 53A, the cut area 5107 includes alignment marks 5301, selective cutting edge stabilization structure 5302, and cutting edge 5303.

[0458] Figure 53B is an enlarged view of the layer above the adhesive layer 5102. As shown in Figure 53B, there is a selective shallow etched groove 5304 to improve etchant containment, an etchant droplet 5305 containing a meniscus, and an inkjet catalyst 5306. Furthermore, Figure 53B shows that the cut thickness 5307 can be selectively submicron level.

[0459] Referring now to Figures 54A and 54B, Figures 54A and 54B illustrate an alternative exemplary method for cutting using an inkjet catalyst based on metal-assisted catalytic etching according to an embodiment of the present invention.

[0460] As shown in Figure 54A, a blade cutting machine frame 5401 with a catalyst-coated blade 5402 is used to cut the cutting field 401. Figure 54B shows an enlarged view of this process.

[0461] As shown in Figure 54B, the blade cutting machine frame (e.g., silicon) may include an etchant inlet 5403 and an etchant outlet 5404. Furthermore, as shown in Figure 54B, a selective protective layer 5405 (e.g., carbon) is present for the cutting machine frame 5401. Additionally, as shown in Figure 54B, etchant droplets 5406 comprising menisci and a catalyst film 5407 are present, wherein the cutting thickness 5408 may selectively be sub-micron level.

[0462] The following discussion is based on Figures 53A-53B and 54A-54B.

[0463] MACE can be used to cut substrates into field 401.

[0464] In one embodiment, the cutting edge is straight. In another embodiment, the cutting edge may have one or more curved or angular elements (e.g., 90° turns, etc.).

[0465] In one embodiment, one or more inkjet printers are used to dispense the MACE catalyst onto an uncut substrate (e.g., uncut field 5101). In one embodiment, the catalyst is gold. After cutting, an etchant (e.g., aqua regia for gold catalysts) can be used.

[0466] In another embodiment, the blade cutting frame 5401 is used to etch into a substrate (e.g., substrate 3302). In one embodiment, the blade 5402 is coated with a MACE catalyst. In one embodiment, the blade 5402 is coated with a protective layer (e.g., a carbon layer). In one embodiment, the blade 5402 has a discontinuous stabilizing structure.

[0467] In one embodiment, the MACE etchant covers the entire substrate (e.g., substrate 3302). In one embodiment, an inkjet printer is used near the notch region 5107 of field 401 to dispense the MACE etchant. In one embodiment, a groove pre-etched before cutting and located near the notch region 5107 is used to contain the MACE etchant. In one embodiment, surface tension near the notch region 5107 is used to contain the MACE etchant.

[0468] In one embodiment, the MACE etchant is circulated to prevent etching stagnation. In one embodiment, etchant circulation is performed in the neighborhood of the cut region 5107.

[0469] In one embodiment, field 401 is coated with a protective layer to prevent chemical damage during cutting and catalyst removal.

[0470] In one embodiment, the blade cutter frame 5401 has a bending mechanism to provide compliance along the Z-axis. In another embodiment, the blade cutter frame 5401 has a bending mechanism to provide compliance along the Z-axis for each field 401.

[0471] In one embodiment, the cut edge has a cross-section optimized to reduce the tendency for indentation and etching stagnation. In another embodiment, the cut edge has a trapezoidal cross-section in the etched area. The trapezoidal cross-section can be created using crystal etching (e.g., KOH-based etching).

[0472] In one embodiment, the cut edge has an orthogonal structure to provide mechanical support.

[0473] In one embodiment, an etching-based cutting technique (e.g., MACE-based cutting) is used to create non-linear field edges. In another embodiment, an etching-based cutting technique (e.g., MACE-based cutting) is used to single out field 401 such that alignment marks 5301 on the cut region 5107 are retained after cutting.

[0474] Referring now to Figures 55A and 55B, Figures 55A and 55B illustrate an exemplary method for backside grinding after substrate cutting according to an embodiment of the present invention.

[0475] As shown in Figure 55A, the cut area 5107 (e.g., 40 micrometers wide) includes a full-size alignment mark 5301 (e.g., 38 micrometers wide) as well as a selective cut edge stabilization structure 5302 and a cut boundary / edge 5303 (e.g., 1 micrometer).

[0476] Figure 55B is an enlarged view of the layer above the adhesive layer 5102. As shown in Figure 55B, there is catalyst 5501 at the cut boundary.

[0477] Referring now to FIG56, FIG56 illustrates an exemplary method for creating grain cuts in a native substrate 103 prior to backside grinding, according to an embodiment of the present invention.

[0478] Specifically, Figure 56 is an enlarged view of the layer above the adhesive layer 5102. As shown in Figure 56, there is an encapsulation layer 5601 above the device structure 5103 and a catalyst 5501 at the cut boundary 5602, which is now located below the device structure 5103, rather than at the same level as layer 5105 to create the metal fracture shown in Figure 55B. The cut boundary 5602 is created by timed etching.

[0479] Referring now to FIG. 57, FIG. 57 is a flowchart of a method 5700 for creating metal fractures by cutting a substrate using metal-assisted chemical etching according to an embodiment of the present invention. FIGS. 58A to 58C depict cross-sectional views of creating metal fractures by cutting a substrate using metal-assisted chemical etching according to an embodiment of the present invention, following the steps described in FIG. 57.

[0480] Referring to Figure 57 and then to Figures 58A-58C, in step 5701, ultraviolet (UV) curing is performed to cure the catalyst fracture layer 5802 shown in Figures 58A-58B. As shown in Figure 58A, the UV-cured layer for catalyst fracture 5802 is located on top of the substrate 5801 to be cut. Furthermore, as shown in Figure 58A, a template having mesa 5803, such as mesa 5804, is located on the catalyst fracture layer 5802. After UV curing, the catalyst fracture layer 5802 is cured, thereby producing layer 5805, as shown in Figure 58B.

[0481] Furthermore, in step 5701, selective plasma etching may be performed to improve the profile of the catalyst fracture layer 5802, thereby resulting in the removal of the template 5803, as shown in FIG58B.

[0482] In step 5702, catalyst 5806 is deposited on a UV-cured layer for catalyst breakage 5805 and substrate 5801, as shown in FIG58C.

[0483] The following discussion covers Figures 55A-55B, 56, 57, and 58A-58C.

[0484] In one embodiment, the dicing process is performed from either the front or back side of the native substrate 103. In another embodiment, the process is performed from either the front side of the native substrate 103 that has been bonded to the carrier substrate 3302 or the back side of the native substrate 103 that has been bonded to the carrier substrate 3302. In yet another embodiment, the process is performed on a back-grounded substrate attached to the carrier substrate 3302.

[0485] In one embodiment, the etching process for the silicon-containing regions of the device stack is CICE. In one embodiment, the etching process for the silicon components of the device stack is silicon electrochemical etching. In one embodiment, the etching process for the non-silicon-containing regions of the device stack (e.g., silicon oxide, metals, such as germanium, gallium arsenide, and silicon carbide non-silicon substrates) is a physical etching process, such as deep reactive ion etching (DRIE) or a wet etching process (e.g., etching using an etchant containing liquid or gaseous hydrofluoric acid).

[0486] In one embodiment, unetched portions of the device stack, such as metal lines that may remain unetched after exposure to HF etching (e.g.), are etched at the end using a more aggressive cleaning etching process, such as using aqua regia, nitric acid, etc. In one embodiment, copper-containing unetched portions of the device stack are etched using ferric chloride, copper chloride, alkaline etchants, mixtures of hydrogen peroxide and sulfuric acid, chromium-sulfuric acid, sodium chlorate, citric acid, ammonium persulfate, etc. In one embodiment, the etchant used for the unetched portions of the device stack is appropriately diluted such that it has reduced or no activity against the device encapsulation layers, oxide layers, and other functional device layers. In one embodiment, a diluent spray (e.g., water) is used to remove the etchant after etching.

[0487] In one embodiment, during the etching process, an encapsulation layer, such as encapsulation layer 5601, is used to protect the device layer within field 401. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is composed of noble metals, non-noble metals, and / or polymers. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is composed of CVD carbon. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is composed of parylene, fluoropolymers (e.g., PTFE), and / or carbon (e.g., CVD deposition or spin coating). In one embodiment, the encapsulation layer, such as encapsulation layer 5601, comprises silicon oxide.

[0488] In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is patterned using photolithography or nanoimprint lithography. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is deposited using inkjet printing. In one embodiment, the encapsulation layer, such as encapsulation layer 5601, is patterned using a discontinuous film created by fluid pinning through a patterning template.

[0489] In one embodiment, the etchant used in a chemical cutting process (e.g., using MACE) is dispensed only near the area to be etched (e.g., using an inkjet printer) or held in a chamber to cover the entire substrate containing the area to be etched. In one embodiment, an inkjet printer is used for etchant dispensing, and all wetted areas of the inkjet printer are coated with an etching inert layer (e.g., a fluoropolymer such as PTFE, parylene, etc.).

[0490] For MACE-based cutting, in one embodiment, the etching catalyst, such as catalyst 5106, is composed of noble metals, non-noble metals, non-metals, polymers, and / or ceramics. In one embodiment, the catalyst, such as catalyst 5106, is composed of Au, Ag, Ru, Pt, Pd, C, Ta, W, Cu, Al, and / or Ni. In one embodiment, the catalyst, such as catalyst 5106, is a gold and silver bilayer, wherein the silver is not beneath the gold and is encapsulated by the gold. In one embodiment, the etching catalyst, such as catalyst 5106, is dispensed as a nanoparticle slurry using an inkjet printer. In one embodiment, the etching catalyst, such as catalyst 5106, is electroplated. In one embodiment, the etching catalyst, such as catalyst 5106, is deposited using physical vapor deposition techniques, such as sputtering, electron beam deposition, etc. In one embodiment, the etchant is deposited using techniques that produce sidewalls with a line edge roughness (LER) of less than 10 nanometers (1σ or 3σ), such as physical vapor deposition (e.g., electron beam, focused ion beam, sputtering), electroplating, and / or electroless plating. In one embodiment, the catalyst, such as catalyst 5106, comprises a thin film of silicon oxide underneath to improve etching uniformity. In one embodiment, the thickness of the silicon oxide film is between 10 nanometers and 100 nanometers. In one embodiment, the etching rate of the catalyst, such as catalyst 5106, is determined by temperature, pH of the etchant solution (using a buffer solution, such as HF and NH4OH or NH4F), plasma treatment of the etchant, and the use of a combined sputtering alloying of the catalyst with a material (e.g., carbon) having low activity for MACE.

[0491] In one embodiment, a catalyst, such as catalyst 5106, is dispensed on top of a discontinuous polymer film created by fluid pinning (of a UV-curable polymer) through a patterned template and subsequent UV exposure (of a UV-curable polymer). In one embodiment, the catalyst, such as catalyst 5106, contains fractures at the edge between the polymer and the substrate, such as substrate 3302. In one embodiment, plasma cleaning is used to clean the edges of the polymer to create improved metallic fractures.

[0492] In one embodiment, the MACE-based cutting is stopped in a timed manner, or, if an adhesive film, such as adhesive film 5102, is available (in the case where the substrate is attached to a carrier substrate), the adhesive film serves as an etch stop layer. In one embodiment, the adhesive film, such as adhesive film 5102, is coated with an etch-resistant material, such as carbon.

[0493] Once the cutting is complete, the catalyst, such as catalyst 5106, is removed using a suitable etchant, such as aqua regia for gold (or an etchant containing potassium iodide, cyanide, etc.), or an atomic layer etching process, or in certain cases, when a partial cut is performed before back-side grinding, the back-side grinding process can also remove the catalyst by grinding it away.

[0494] In one embodiment, the geometry of the cut edge along the straight edge of field 401 is composed of curved and / or angular components. In one embodiment, alignment marks, such as mark 5301, are included in the curved portion of the cut edge 5303. In one embodiment, the cut edge 5303 includes a support structure, such as structure 5302, to prevent drift. This support structure may be present on the exterior or interior of the cut edge 5303. The alignment mark, such as mark 5301, includes grooves to accommodate the support structure, such as structure 5302. In one embodiment, image processing techniques are used to filter out any loss of alignment signal caused by the grooves in the alignment mark, such as mark 5301. The grooves created in the alignment mark, such as mark 5301, can be filled after cutting using suitable material deposition techniques, such as CVD (silicon, silicon oxide, etc.), ALD, etc.

[0495] In one embodiment, a catalyst film, such as catalyst 5106, deposited on the metal fracture layer 5105 is used to generate electrostatic attraction between the grains and the transfer chuck 111.

[0496] CICE can be used to fabricate semiconductor nanostructures with high aspect ratios, no porosity, and no taper. CICE is also described as metal-assisted chemical etching (MACE). For CICE of silicon, the catalyst comprises one or more of the following groups: (in alloy form if necessary) Au, Pt, Pd, Ag, Ru, Ir, W, Cu, TiN, Ti, graphene, carbon, etc., which catalyze the reduction of H₂O₂ and inject the resulting holes into silicon, thereby altering the oxidation state of silicon. In one embodiment, HF selectively etches the silicon, and the catalyst sinks into the etched region to continue the local redox reaction, thereby generating silicon nanostructures in regions without catalyst. The properties of the resulting silicon nanostructures are highly dependent on the balance between reaction rate, charge transfer, etchant mass transfer, and catalyst movement. In one embodiment, the substrate for CICE comprises one or more of the following groups: a single-crystal bulk silicon wafer, a polycrystalline silicon layer deposited on a substrate, an amorphous silicon layer deposited on a substrate, a silicon-on-insulator (SOI) wafer, silicon-on-glass, silicon-on-sapphire, epitaxial silicon on a substrate, alternating layers of semiconductor materials with different doping levels and dopants, highly doped silicon and lightly doped silicon, undoped silicon or doped silicon or germanium, silicon and SixGe1-x, differently doped silicon and / or SixGe1-x, differently doped silicon and / or germanium, or silicon and germanium.

[0497] In one embodiment, collapse of the CICE-etched nanostructure is delayed or eliminated by using an "anti-collapse cap" or "anti-collapse feature" on the tip of the nanostructure. In one embodiment, the anti-collapse cap prevents collapse by electrostatic repulsion between the nanostructures.

[0498] Figure 59 is a flowchart of a method 5900 for patterning a catalyst using selective atomic layer deposition (ALD) according to an embodiment of this invention, in which the catalyst is part of an "anti-collapse cap". In this process, the catalyst does not grow on a portion of the patterned mask. ALD chemistry is listed in Table 2: Table 2: Precursors for atomic layer deposition (ALD). [Catalyst Materials] [Precursor] [A] [gas] [B] [ALD] [Chemical] [Substrate used for deposition] platinum Trimethyl(methylcyclopentadienyl)platinum(IV) oxygen Plasma enhancement, thermal combustion chemistry SiO2, silicon with natural oxides palladium Pd(hfac)2 Formaldehyde, H2 Thermal-hydrogen reduction chemistry gold Trimethylphosphinotrimethylgold(III) oxygen plasma TiN Tetra(diethylamino)titanium (IV), Tetra(dimethylamino)titanium (IV), Titanium tetrachloride, Titanium isopropoxide (IV) NH3 Plasma enhancement, thermal TaN Tris(diethylamino)(tert-butylamino)tantalum(V) Hydrogen, NH3 Plasma enhancement, thermal Ru Bis(ethylcyclopentadienyl)ruthenium(II) NH3,O2 Plasma, thermal combustion chemistry Ir Ir(acac)3 O2 Thermal Combustion Chemistry Ag Ag(fod)(PEt3) hydrogen Plasma Enhancement Cu (Cu(thd)2); Copper β-diketone: Cu(II) 1,1,1,5,5,5-hexafluoroacetyl acetone (Cu(hfac)2) Methanol, ethanol, formalin Thermal-hydrogen reduction chemistry Co Co(MeCp)2 H2 or NH3 Plasma Enhancement Bis(N-tert-butyl,N'-ethylpropanediamine)cobalt(II) H2O hot W bis(tert-butylamino)bis(dimethylamino)tungsten(VI),WF6 Si2H6 Thermal-fluorosilane elimination chemistry

[0499] As described above, Figure 59 is a flowchart of a method 5900 for patterning a catalyst using selective atomic layer deposition (ALD) according to an embodiment of the present invention, wherein the catalyst is part of an "anti-collapse cap". Figures 60A to 60E depict cross-sectional views of a catalyst patterned using selective atomic layer deposition according to an embodiment of the present invention, wherein the catalyst is part of an "anti-collapse cap" by the steps described in Figure 59.

[0500] In one embodiment, the catalyst is patterned using one or more of the following groups: nanoimprint lithography, photolithography, focused ion beam milling, electron beam lithography, laser interferometry, nanosphere lithography, block copolymer lithography, and directional self-assembly. In another embodiment, CICE patterning includes etching into the carbon using thermally stable carbon, using nanoimprint lithography (NIL) resists, photoresists, etc., and using metal fracture to strip any polymer resists prior to catalyst deposition.

[0501] Referring to Figures 60A-60E and Figure 59, in step 5901, the ALD barrier material 6002 is deposited on the substrate 6001, as shown in Figure 60A.

[0502] In step 5902, ALD reinforcing material 6003 is patterned on ALD blocking material 6002, as shown in Figure 60B.

[0503] In step 5903, a portion of the ALD blocking material 6002 not covered by the ALD reinforcing material 6003 and a portion of the substrate 6001 not covered by the ALD reinforcing material 6003 are etched, as shown in FIG60C.

[0504] In step 5904, catalyst 6004 is selectively deposited on the exposed substrate 6001 and ALD reinforcement material 6003 by ALD, as shown in Figure 60D.

[0505] In step 5905, CICE is performed to produce a nanostructure 6005 with a collapse-resistant cap 6006, wherein the collapse-resistant cap 6006 is made of a catalyst 6004 and an ALD reinforcing material 6003.

[0506] Referring now to Figure 61, Figure 61 is a flowchart of a method 6100 for creating an anti-collapse cap and catalyst patterning by directional deposition and atomic layer etching of the catalyst according to an embodiment of the present invention. Figures 62A to 62D depict cross-sectional views of creating an anti-collapse cap and catalyst patterning by directional deposition and atomic layer etching of the catalyst according to an embodiment of the present invention, using the steps described in Figure 61.

[0507] Referring to Figure 61 in conjunction with Figures 62A-62D, in step 6101, the mask 6202 is patterned on the substrate 6201, as shown in Figure 62A.

[0508] In step 6102, catalyst material 6203 is directionally deposited on the mask 6202 and the exposed areas of the substrate 6201 (i.e., those areas of the substrate 6201 not covered by the mask 6202), as shown in FIG62B. In one embodiment, the directional deposition of catalyst material 6203 is performed using methods such as thermal evaporation, electron beam evaporation, or physical vapor deposition. In one embodiment, catalyst material 6203 is Ru.

[0509] In step 6103, catalyst material 6203 is removed from the sidewall of mask 6202, for example by dry etching, as shown in FIG62C. In one embodiment, etching of catalyst material 6203, such as Ru, is used to remove a thin layer of metal deposited on the sidewall of mask 6202.

[0510] In step 6104, CICE is performed to produce a nanostructure 6204 with a collapse-resistant cap 6205, wherein the collapse-resistant cap 6205 is made by means of a catalyst material 6203 and a mask 6202.

[0511] During the CICE process, the isolated metal catalyst may drift and produce undesirable non-perpendicular etch paths. In the CICE process, discontinuous catalyst features tend to drift and lead to defects. CICE with pores in the isolated catalyst may drift due to van der Waals forces on the catalyst and random variations in the applied force caused by localized etchant concentration or etching rate, as shown in Figures 63A-63B.

[0512] Figures 63A to 63D illustrate the drift of the isolation catalyst during CICE according to one embodiment of the present invention.

[0513] Referring to Figures 63A-63D, Figure 63A shows the isolation catalyst 6301 drifting into the substrate 6302. Figure 63B shows a top view of the isolation catalyst 6301. Figure 63C shows a cross-sectional view of the isolation catalyst 6301. Furthermore, Figure 63D shows the random variation of the etching rate at the center of the catalyst.

[0514] To prevent catalyst drift, such as catalyst 6301, stabilizing patterns can be inserted into the isolating catalyst – thereby providing a support structure to the catalyst during CICE. These stabilizing patterns can be predetermined holes of different cross-sections patterned within the isolating catalyst structure. The support structure can be removed after CICE to achieve vertical drift-free CICE. Figures 64A to 64D show exemplary geometries for stabilizing patterns or support structures (referred to herein as "catalyst buttresses") according to an embodiment of the present invention.

[0515] Referring to Figure 64A, Figure 64A shows a top view of catalyst 6301 containing stabilizing pattern 6401. Figure 64B shows a cross-sectional view of catalyst 6301 containing stabilizing pattern 6401. Figure 64C shows a cross-sectional view of catalyst 6301 where stabilizing pattern 6401 has been removed after CICE execution. Furthermore, Figure 64D shows various stabilizing patterns 6401 to be inserted into catalyst 6301.

[0516] In one embodiment, the patterning and fabrication of the catalyst buttress design shown in FIG64D is performed using photolithography, imprint lithography, electron beam lithography, EUV lithography, self-aligned patterning, spacer patterning, etc.

[0517] Figure 65 is a flowchart of a method 6500 for manufacturing isolated catalyst points with circular catalyst support walls using ruthenium (Ru) as a catalyst according to an embodiment of the present invention. Figures 66A to 66E depict cross-sectional views of manufacturing isolated catalyst points with circular catalyst support walls using ruthenium as a catalyst according to an embodiment of the present invention, following the steps described in Figure 65. Figures 67A to 67E depict top views of manufacturing isolated catalyst points with circular catalyst support walls using ruthenium as a catalyst according to an embodiment of the present invention, following the steps described in Figure 65.

[0518] Referring to Figure 65 in conjunction with Figures 66A-66E and 67A-67E, in step 6501, catalyst 6301 is deposited on substrate 6601, as shown in Figures 66A and 67A. In one embodiment, the material of catalyst 6301 is Ru.

[0519] In step 6502, a dot pattern 6602 is inserted into the catalyst 6301, for example by photolithography, imprint lithography, electron beam lithography, EUV lithography, self-aligned patterning, spacer patterning, etc., as shown in Figures 66B and 67B. In one embodiment, the dot pattern 6602 is an oxide material.

[0520] In step 6503, spacer pattern 6603 is deposited around dot pattern 6602, as shown in Figures 66C and 67C.

[0521] In step 6504, the dot pattern 6602 is removed, for example by various etching techniques, as shown in Figures 66D and 67D. In one embodiment, the dot pattern 6602 is an oxide material that is removed by etching. In one embodiment, the etchant used for etching comprises one or more of the following groups: fluorides, oxidants, alcohols and protic solvents, aprotic solvents, polar solvents and nonpolar solvents. In one embodiment, the etchant comprises two or more of the following groups: fluorinated chemicals HF or NH4F, oxidants H2O2, KMnO4, or dissolved oxygen, alcohols ethanol, isopropanol, or ethylene glycol, protic solvents, aprotic solvents, polar solvents and nonpolar solvents, such as deionized water or dimethyl sulfoxide (DMSO).

[0522] In step 6505, the spacer pattern 6603 and the exposed portion of the catalyst 6301 (i.e., the portion of the catalyst 6301 not covered by the spacer pattern 6603) are removed by etching, for example by various etching techniques (e.g., dry etching), thereby creating isolation points, as shown in Figures 66E and 67E.

[0523] In one embodiment, the silicon nanostructure is porous after CICE. The porosity in silicon (Si) enhances the diffusion of the etchant and further prevents the drift of the isolating catalyst 6301. In another embodiment, the silicon nanostructure is an alternating layer of porous and non-porous silicon nanostructures fabricated using silicon superlattice etching to create exemplary applications in 3D NAND flash memory, as shown in Figures 68A-68B.

[0524] Figure 68A shows a catalyst 6301 according to an embodiment of the present invention and a nanostructure composed of porous silicon 6801. Figure 68B shows a catalyst 6301 according to an embodiment of the present invention and a nanostructure composed of alternating layers of porous silicon 6801 and non-porous silicon 6802.

[0525] Figures 69A to 69D illustrate the removal of silicon buttresses ("stabilizing patterns") ("catalyst buttresses") after CICE according to one embodiment of the present invention, using an isolating catalyst 6301 with buttresses, such as buttresses 6401, to prevent drift. In one embodiment, the buttresses, such as buttresses 6401, collapse due to capillary forces and adhesive forces. Patterning of the etch mask and anisotropic plasma etching of silicon are used to remove the collapsed silicon buttresses, such as buttresses 6401.

[0526] Referring to Figure 69A, Figure 69A shows a top view of a catalyst 6301 with a buttress design 6401 (e.g., silicon buttress). The buttress design 6401 (e.g., silicon pillar) is then removed to produce the structures shown in Figures 69C and 69D. Figure 69C shows a top view of the structure resulting after the removal of the buttress design 6401. Figure 69D shows a cross-sectional view of the structure resulting after the removal of the buttress design 6401.

[0527] In one embodiment, shown in Figures 70A-70C, a collapsed column (collapsed buttress 5401, e.g., a silicon buttress) is designed according to an embodiment of the present invention to necessarily collapse in a particular direction, for example by placing the buttress pattern toward the etched side. The collapsed buttress structure, such as buttress 6401, is removed using plasma etching with an etch mask whose geometry is biased to expose the collapsed area.

[0528] Referring to Figure 70A, which illustrates a collapsed silicon buttress 6401 designed to inevitably collapse in a specific direction, such as towards the etched side. Figure 70B shows the placement of an etch mask 7001, and Figure 70C shows the removal of the collapsed silicon buttress 6401 with the etch mask 7001, the geometry of which is biased to expose the collapsed area.

[0529] Similar to etching vias using CICE, etching lines and spaces requires long isolation lines for the catalyst, which tend to drift during the CICE process. In one embodiment, a lithographic link between the line and space is used to connect the isolation catalyst lines. The size and location of the lithographic link are designed to minimize interference with the final device requirements. A filler material is deposited using methods such as CVD, ALD, or physical vapor deposition (PVD) to fill the gaps etched by CICE in the areas with the lithographic link. In one embodiment, the lithographic link is orthogonal to the desired line and space direction, and a low-k dielectric material, such as silicon oxide ALD, is used to fill the gaps, as discussed below in conjunction with Figures 71, 72, and 73A-73C.

[0530] Figure 71 is a flowchart of a method 7100 for manufacturing a line / space pattern with lithographic links using CICE according to an embodiment of the present invention. Figure 72 shows a top view of a desired line / space pattern using the steps described in Figure 71 according to an embodiment of the present invention. Figures 73A to 73C depict cross-sectional views of manufacturing a line / space pattern with lithographic links using CICE according to the steps described in Figure 71 according to an embodiment of the present invention.

[0531] Referring to Figure 72, Figure 72 shows a top view of the desired line / space pattern 7201. Referring to Figure 73A, Figure 73A shows a long isolation line of catalyst 6301, which has a photolithographic link 7301 for connecting the isolation catalyst line 6301 surrounding the region of substrate 6302.

[0532] Referring now to Figure 71 in conjunction with Figures 73A-73C, in step 7101, CICE is performed to remove the lines of catalyst 6301 and photolithography link 7301, as shown in Figure 73B.

[0533] In step 7102, filling material 7302 is deposited, for example, through CVD, PVD, etc., in the lines of the previously removed catalyst 6301 and the photolithography link 7301, as shown in FIG73C.

[0534] Using CICE to fabricate high aspect ratio structures in polycrystalline silicon enables applications such as stacked capacitors in DRAM. Figures 74A and 74B show exemplary polycrystalline silicon nanowire arrays fabricated using CICE with gold as a catalyst according to an embodiment of this invention.

[0535] CICE for creating high aspect ratio holes is challenging due to the drift of the isolating catalyst, such as isolating catalyst 6301. In one embodiment, the etched nanostructure can be used with a characteristic hue – from pillars to holes – to partially fill the gaps between pillars using atomic layer deposition (ALD). Figure 75 shows an exemplary geometry for converting silicon fins into holes using atomic layer deposition of silicon oxide according to an embodiment of the present invention. In one embodiment, the silicon fin regions are used to create transistors, and the hole regions are used to create capacitors for DRAM devices.

[0536] The hue-inverting process using CICE can be further extended to include any material, wherein polycrystalline silicon or silicon structures are fabricated using CICE, and the gaps between the structures are filled with a structural material. In one embodiment, the material is an insulator. In one embodiment, the structural material is carbon, amorphous carbon, silicon dioxide, silicon nitride, metal oxides, tin oxide, and / or indium tin oxide. In one embodiment, the deposited material is one or more of the following group: SiO2, TiO2, Al2O3, Pd, Pt, W, TiN, TaN, Cu, SiNx, SnOx, ZnOx, etc. Silicon is selectively removed to create the hue-inverted structure within the structural material. In one embodiment, etched polycrystalline silicon and / or silicon structures are removed using methods such as selective wet etchants (e.g., KOH, TMAH, EDP), dry etchants (e.g., XeF2 vapor), and plasma etching (e.g., substances such as Cl2, SF6, BCl3, etc. in plasma). Optionally, the desired material can be deposited in the silicon-removed region to create arbitrary geometries with high aspect ratios in any material. Alternatively, the structural material can be a conductor, while the desired material can be an insulator, depending on the application requirements. Figures 76, 77A-77D, and 78A-78D discuss the process using CICE with inverted color.

[0537] In one embodiment, the etch stop layer is selected such that it will not be etched during the CICE process discussed in Figures 79, 80A-80D, and 81A-81F. In another embodiment, the etch stop layer is removed during the tone inversion fabrication process discussed in Figures 82, 83A-83D, and 84A-84G. As discussed in Figures 82, 83A-83D, and 84A-84G, the thickness of the etch stop layer can be optimized to reduce the likelihood of undercutting. The thickness of the etch stop layer can range from 1 nanometer to 100 nanometers. In one embodiment, the etch stop material comprises carbon, Cr, chromium oxide, aluminum oxide, silicon nitride, silicon oxide, ruthenium, etc., or any combination thereof. In one embodiment, the etch stop layer is optimized for anisotropic and selective etching; for example, the removal of the carbon layer is performed using oxygen plasma etching, chemical etching using ozone, etc.

[0538] Referring now to FIG. 76, FIG. 76 is a flowchart of a method 7600 for a hue inversion process using CICE according to an embodiment of the present invention. FIGS. 77A to 77D depict top views of a hue inversion process using CICE according to the steps described in FIG. 76 according to an embodiment of the present invention. FIGS. 78A to 78D depict cross-sectional views of a hue inversion process using CICE according to the steps described in FIG. 76 according to an embodiment of the present invention.

[0539] Referring to Figure 76 in conjunction with Figures 77A-77D and 78A-78D, in step 7601, CICE is performed to generate a structure with silicon pillars 7701 located on a substrate 7702, as shown in Figures 77A and 78A.

[0540] In step 7602, oxide 7703 is deposited on silicon pillar 7701 and substrate 7702, as shown in Figures 77B and 78B.

[0541] In step 7603, various etching techniques, such as CICE, are used to remove silicon pillars 7701, as shown in Figures 77C and 78C.

[0542] In step 7604, the desired material 7704 is deposited in the region where the silicon pillar 7701 has been removed, for example through CVD, PVD, ALD, etc., thereby producing an arbitrary geometry with a high aspect ratio, as shown in Figures 77D and 78D.

[0543] Referring now to FIG. 79, FIG. 79 is a method 7900 for performing a tone inversion process using CICE with polysilicon according to an embodiment of the present invention, which includes catalyst removal using selective chemical etching. FIGS. 80A to 80D depict top views of performing a tone inversion process using CICE with polysilicon according to an embodiment of the present invention, with the steps described in FIG. 79, which includes catalyst removal using selective chemical etching. FIGS. 81A to 81F depict cross-sectional views of performing a tone inversion process using CICE with polysilicon according to an embodiment of the present invention, with the steps described in FIG. 79, which includes catalyst removal using selective chemical etching.

[0544] Referring to Figure 79 in conjunction with Figures 80A-80D and 81A-81F, in step 7901, an etch stop layer 8101 and a layer of polysilicon 8102 are deposited on a desired device, such as a device comprising a layer of desired material 8103 located on a substrate 8104, as shown in Figures 81A-81B.

[0545] In step 7902, CICE is performed to etch a portion of the polysilicon 8102, leaving the polysilicon pillars 8105, as shown in Figures 80A and 81C.

[0546] In step 7903, oxide 8106 is deposited on the pillars 8105 and the exposed areas of the etch stop layer 8101 (i.e., those areas not covered by the polysilicon pillars 8105), as shown in Figures 80B and 81D.

[0547] In step 7904, the oxide 8106 is etched back to the top layer of pillar 8105 and pillar 8105 is removed, for example by various etching techniques (e.g., ALE), as shown in Figures 80C and 81E.

[0548] In step 7905, the desired material 8107 is then deposited in the area previously occupied by the removed column 8105, for example through CVD, PVD, ALD, etc., as shown in Figures 80D and 81F.

[0549] Referring now to FIG82, FIG82 is a flowchart of a method 8200 for performing a tone inversion process using polysilicon CICE according to an embodiment of the present invention, which includes catalyst removal using selective chemical etching and wherein the etch stop layer is removed in a final apparatus. FIG83A to FIG83D depict top views of performing a tone inversion process using polysilicon CICE according to an embodiment of the present invention with the steps described in FIG82, which includes catalyst removal using selective chemical etching and wherein the etch stop layer is removed in a final apparatus. FIG84A to FIG84G depict cross-sectional views of performing a tone inversion process using polysilicon CICE according to an embodiment of the present invention with the steps described in FIG82, which includes catalyst removal using selective chemical etching and wherein the etch stop layer is removed in a final apparatus.

[0550] Referring to FIG82 in conjunction with FIG83A-83D and FIG84A-84G, in step 8201, an etch stop layer 8401 and a layer of polysilicon 8402 are deposited on a desired device, such as a device comprising a layer of desired material 8403 located on a substrate 8404, as shown in FIG84A-84B.

[0551] In step 8202, CICE is performed to etch a portion of the polysilicon 8402, leaving the polysilicon pillars 8405, as shown in Figures 83A and 84C.

[0552] In step 8203, various etching techniques, such as ALE, are used to remove the exposed portions of the etch stop layer 8401 (i.e., those portions of the etch stop layer 8401 not covered by the pillars 8405), as shown in FIG84D.

[0553] In step 8204, oxide 8406 is deposited on pillar 8405 and the exposed areas of the desired device, such as material 8403 (i.e., those areas not covered by etch stop layer 8401), as shown in Figures 83B and 84E.

[0554] In step 8205, the oxide 8406 is etched back to the top layer of pillar 8405 and pillar 8405 and etch stop layer 8401 are removed, for example by various etching techniques (e.g., ALE), as shown in Figures 83C and 84F.

[0555] In step 8206, the desired material 8407 is then deposited in the area previously occupied by the removed pillar 8405 and the removed etch stop layer 8401, for example through CVD, PVD, ALD, etc., as shown in Figures 83D and 84G.

[0556] Referring now to FIG85, FIG85 is a flowchart of a method 8500 for manufacturing metal interconnects and vias using a polysilicon CICE color-inversion process according to an embodiment of the present invention. FIGS86A to 86F depict top views of manufacturing metal interconnects and vias using a polysilicon CICE color-inversion process according to an embodiment of the present invention, following the steps described in FIG85. FIGS87A to 87L depict cross-sectional views of manufacturing metal interconnects and vias using a polysilicon CICE color-inversion process according to an embodiment of the present invention, following the steps described in FIG85.

[0557] Referring to FIG85 in conjunction with FIG86A-86F and FIG87A-87L, in step 8501, an etch stop layer 8701 and a layer of polysilicon 8702 are deposited on a desired device, such as a device comprising a layer of desired material 8703 located on a substrate 8704, as shown in FIG87A-87B.

[0558] In step 8502, a portion of the polysilicon 8702 is etched, for example, through CICE, leaving polysilicon pillars 8705, as shown in Figures 86A and 87C.

[0559] In step 8503, catalyst 8706 (e.g., Ru) is deposited in the exposed portions of etch stop layer 8701 (i.e., those portions of etch stop layer 8701 not covered by pillar 8705), for example through ALD, CVD, PVD, electroplating, or thermal evaporation, as shown in Figures 86A and 87C.

[0560] In step 8504, catalyst 8706 is removed, for example by various etching techniques (e.g., dry etching, wet etching), as shown in FIG87D.

[0561] In step 8505, the exposed portions of the etch stop layer 8701 (i.e., those portions of the etch stop layer 8701 not covered by the pillars 8705) are removed, for example, through an etching technique (e.g., ALE), as shown in FIG87E.

[0562] In step 8506, oxide 8707 is deposited on pillar 8705 and the exposed areas of the desired device, such as material 8703 (i.e., those areas not covered by etch stop layer 8701), as shown in Figures 86B and 87F.

[0563] In step 8507, the oxide 8707 to the top layer of pillar 8705 is etched back and pillar 8705 and etch stop layer 8701 are removed, for example by various techniques (e.g., dry etching, wet etching), as shown in Figures 86C and 87G.

[0564] In step 8508, the desired material 8708 is deposited in the area previously occupied by the removed pillar 8705 and the removed etch stop layer 8701, for example through CVD, PVD, ALD, etc., as shown in Figures 86D and 87H.

[0565] In one embodiment, in step 8509, for hue inversion CICE, step 8501 is repeated, wherein an etch stop layer 8709 and a layer of polysilicon 8710 are deposited on the device structure shown in FIG86D and FIG87H to obtain the structure shown in FIG87I.

[0566] In step 8510, step 8502 is repeated, wherein a portion of the polysilicon 8710 is etched, for example through CICE, leaving polysilicon pillars 8711, as shown in Figures 86E and 87J.

[0567] In step 8511, steps 8503-8507 are repeated to obtain the structure with oxide 8712 as shown in FIG87K.

[0568] In step 8512, step 8508 is repeated, wherein the desired material 8713 is subsequently deposited in the area occupied by the previously removed pillar 8711 and the removed etch stop layer 8709, for example by CVD, PVD, ALD, etc., to form the structure shown in Figures 86F and 87L, wherein the formed structure includes the desired materials 8713, 8708 and oxides 8712, 8707.

[0569] Steps 8509-8512 can be repeated continuously for the required number of metal layers and / or insulating layers.

[0570] In one embodiment, method 8500 is used for a metal layer in an interconnect, wherein the structural material is a low-k dielectric, such as silicon oxide or silicon oxynitride, and the desired material is a conductor, such as Cu, Mo, W, Ru, TiN, TaN, Pd, etc. In one embodiment, CICE is used for the fabrication of the metal interconnect, and the catalyst used for CICE, for example catalyst 8706, is Ru. In one embodiment, after CICE, the catalyst, such as catalyst 8706, is not removed, and Ru is used as a seed layer for Cu electroplating to create Cu interconnects using a dual damascene process. Other metals that can be deposited into interconnects include Ru, Cu, Mo, TiN, Cu, W, TaN, etc. The metal can be deposited using ALD, CVD, PVD, electroplating, or thermal evaporation. In one embodiment, Cu is deposited using electroplating and polished using CMP.

[0571] Color-inverted CICE can be used to selectively grow superlattice structures within high aspect ratio holes, thereby enabling the fabrication of vertical, taper-free superlattice nanostructures without the use of plasma etching for the superlattice material. The superlattice material can be deposited using selective atomic layer deposition, epitaxial growth, selective electrodeposition, etc., such that each layer grows only on top of the previously deposited layer, rather than on the structural material. Figures 88, 89A-89A, and 90A-90D illustrate exemplary fabrication processes for these structures. In one embodiment, alternating layers are epitaxially grown Si and SiGe for application in nanosheet FETs, and the structural material is an insulator.

[0572] Figure 88 is a flowchart of a method 8800 for forming a superlattice with hue-inverted CICE and selective growth according to an embodiment of the present invention. Figures 89A to 89D depict top views of the formation of a superlattice with hue-inverted CICE and selective growth according to an embodiment of the present invention, following the steps described in Figure 88. Figures 90A to 90D depict cross-sectional views of the formation of a superlattice with hue-inverted CICE and selective growth according to an embodiment of the present invention, following the steps described in Figure 88.

[0573] Referring to Figure 88 in conjunction with Figures 89A-89A and 90A-90D, in step 8801, CICE is performed on the polycrystalline silicon layer located on the substrate 8902 to generate columnar polycrystalline silicon 8903, as shown in Figures 89A and 90A.

[0574] In step 8802, oxide 8904 is deposited on the exposed areas of pillar 8903 and substrate 8902, as shown in Figures 89B and 90B.

[0575] In step 8803, the oxide 8904 is etched back to the top layer of pillar 8903 and pillar 8903 is removed, for example through various process techniques (e.g., ALE), as shown in Figures 89C and 90C.

[0576] In step 8804, the desired material 8905 is then deposited in the area occupied by the previously removed column 8903, as shown in Figures 89D and 90D.

[0577] Roll-to-roll (R2R) processes can be used for R2R deposition, R2R patterning, and the fabrication of silicon nanostructures using R2R CICE. In one embodiment, polycrystalline silicon is deposited on a stainless steel roller and patterned using R2R nanoimprint lithography, followed by removal of the residual layer thickness (RLT). Other substrates include metal foils and metals and gold, polymer films, and other flexible substrates. In another embodiment, a barrier layer is deposited between the roller substrate and the polycrystalline silicon. The barrier layer is chemically resistant to CICE etchants and can serve as an etch-stopping layer. Cr, carbon, and Al2O3 are examples of materials used for the barrier layer.

[0578] The binder material and catalyst material are deposited using electron beam evaporation, thermal evaporation, physical vapor deposition, chemical vapor deposition, etc. Examples of deposited thin films include Ti, Au, Pt, Pd, Ag, Ru, RuO2, Ir, IrO2, TiN, W, Cu, etc., or any combination thereof. The catalyst patterned on polycrystalline silicon on an R2R substrate is then exposed to wet etching by CICE. In one embodiment, the rollers are arranged vertically, and the etchant is sprayed onto the patterned side of the rollers. In another embodiment, a vapor phase etchant is used to perform the CICE process. In one embodiment, the polycrystalline silicon nanowires are fabricated using an R2R process for high-density anodes in battery and supercapacitor applications.

[0579] Deterministic lateral displacement (DLD) is a microfluidic technique that uses a specific arrangement of pillar arrays placed in microfluidic channels to separate particles in a fluid medium based on their size. The spacing between the pillars and their placement determine the separation mechanism. The pillar array required for DLD can be fabricated using nanolithography, such as nanoimprint lithography combined with a catalyst-influenced chemical etching (CICE) process. In one embodiment, as shown in Figures 91 and 92A-92G, the silicon pillars for DLD are fabricated on a silicon source substrate. In another embodiment, the catalyst is not removed after CICE, and the DLD device is encapsulated. CICE etchant flows through the device inlet to further etch the pillars in the encapsulated DLD device.

[0580] In one embodiment, a thin layer of silicon is peeled off to remove it from the silicon pillar, allowing the remaining silicon substrate to be polished and reused. This process can reduce the cost of DLD manufacturing and is discussed in “Design of a Workflow for Peeling Single-Crystal Microscale Silicon Films” by Ward et al., April 5, 2019, the entire contents of which are incorporated herein by reference.

[0581] Referring to FIG91, FIG91 is a flowchart of a method 9100 for manufacturing a DLD using a CICE and silicon wafer stripping apparatus according to an embodiment of the present invention. FIGS92A to 92G depict cross-sectional views of a DLD manufactured using a CICE and silicon wafer stripping apparatus according to an embodiment of the present invention, following the steps described in FIG91.

[0582] Referring to FIG91 in conjunction with FIGS. 92A to 92G, in step 9101, silicon wafer substrate 9201 is etched, for example by CICE to form silicon nanowires (pillars) 9202 (also referred to herein as "silicon nanopillars"), as shown in FIG92A.

[0583] In step 9102, the support material 9203 is deposited in the grooves between the silicon nanowires 9202, as shown in Figure 92B.

[0584] In step 9103, nickel 9204 is deposited on top of the support material 9203 for peeling, as shown in Figure 92C.

[0585] In step 9104, at least most of the silicon wafer substrate 9201 is peeled off, leaving a thin layer of silicon wafer substrate 9201, as shown in FIG92D.

[0586] In step 9105, the support substrate 9205 is then bonded to the remaining portion of the silicon wafer substrate 9201, as shown in FIG92E.

[0587] In step 9106, nickel 9204 and support material 9203 are removed, for example by etching technology (e.g., ALE), thereby forming a DLD device, as shown in FIG92F.

[0588] In step 9107, the encapsulation layer 9206 is deposited on the silicon nanowires 9202 of the DLD device, as shown in Figure 92G.

[0589] In one embodiment, pillars in the packaged DLD device, such as silicon nanowires 9202, may be further etched, for example, through CICE, to increase the pillar height. For example, CICE etchant may flow through the device inlet to further etch the pillars, such as silicon nanowires 9202, in the packaged DLD device.

[0590] The collapse of silicon nanopillars in a DLD array, such as silicon nanopillar 9202, limits the maximum height of the pillars. In one embodiment, the pillar height is increased by creating a ceiling structure on the silicon nanopillars using materials that are chemically resistant to etchants, such as carbon, Cr, etc., which is discussed in "Instantaneous Thermal Stability Analysis of Amorphous Carbon Films with Different Sp3 Contents" by Rouhani et al., Vol. 130, pp. 401-409, Carbon, April 1, 2018, the entire contents of which are incorporated herein by reference.

[0591] In another embodiment, the ceiling structure or stabilizing material is created by co-sputtering an HF-resistant material and an HF-consuming material to produce a porous mesh. In one embodiment, carbon and silicon dioxide are co-sputtered to create a ceiling structure. When exposed to a CICE etchant, the silicon dioxide is etched away, resulting in a porous carbon mesh. The porous carbon mesh structurally stabilizes the silicon nanopillars, while the CICE etchant further increases their height.

[0592] Figure 93 is a flowchart of a method 9300 for creating a DLD device by joining a cover plate to a DLD column after a CICE without causing the column to collapse, according to an embodiment of the present invention. Figures 94A to 94E depict cross-sectional views of joining a cover plate to a DLD column after a CICE without causing the column to collapse, according to an embodiment of the present invention, using the steps described in Figure 93.

[0593] Referring to Figures 94A-94E and Figure 93, in step 9301, CICE is performed on the silicon wafer substrate 9401 to form DLD pillars 9402, as shown in Figure 94A.

[0594] In step 9302, a stable material 9403 is deposited on top of the DLD column 9402 using various deposition techniques, such as CVD, PVD, ALD, etc., as shown in Figure 94B.

[0595] In step 9303, the stabilizing material 9403 is etched back to the top of the DLD pillar 9402 (referred to herein as "DLD pillar cap 9404"), as shown in Figure 94C.

[0596] In step 9304, the DLD pillar cap 9404 is removed, for example by various etching techniques (e.g., ALE), leaving a small portion of the DLD pillar 9402 (identified as element 9405) above the etched stabilizing material 9403, as shown in Figure 94D.

[0597] In step 9305, the cover plate 9406 is joined to the remaining portion of the DLD column 9405 after the removal of the DLD column 9404, as shown in Figure 94E. This joining can be performed using anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, adhesives, etc.

[0598] Figure 95 is a flowchart of a method 9500 for increasing column height using a porous stabilizing material according to an embodiment of the present invention. Figures 96A to 96C depict cross-sectional views of increasing column height using a porous stabilizing material according to an embodiment of the present invention, following the steps described in Figure 95.

[0599] Referring to Figures 96A-96C and Figure 95, in step 9501, CICE is performed on the silicon source substrate 9601 on which the DLD pillar 9602 is formed.

[0600] In step 9502, the DLD pillar 9602 is etched, for example, by various etching techniques (e.g., ALE) to shorten the height of the DLD pillar 9602, as shown in FIG96A.

[0601] In step 9503, a layer 9603 having etchant-resistant and etchant-soluble components is deposited on the exposed areas of the DLD pillar 9602 and the silicon wafer substrate 9601, as shown in FIG96B.

[0602] In step 9504, further CICE is performed on the silicon wafer substrate 9601 below layer 9603 to extend the height of the DLD pillar 9602, thereby producing the structure shown in FIG96C.

[0603] In step 9505, a porous resistant layer 9604, such as a porous HF-resistant layer, is selectively deposited on layer 9603 at approximately the midpoint of the DLD column 9602 to stabilize the DLD column 9602, as shown in Figure 96C.

[0604] Figure 97 is a flowchart of a method 9700 for attaching a cover plate for a DLD device after a CICE without causing column collapse, according to an embodiment of the present invention. Figures 98A to 98D depict cross-sectional views of attaching a cover plate for a DLD device after a CICE without causing column collapse, according to an embodiment of the present invention, using the steps described in Figure 97.

[0605] Referring to Figures 97 and 98A-98D, in step 9701, CICE is performed on the silicon source substrate 9801 on which the DLD pillar 9802 is formed. This DLD pillar 9802 includes a DLD pillar cap 9803, which refers to the top of the DLD pillar 9402.

[0606] In step 9702, sacrificial material 9804 (e.g., polyvinyl alcohol (PVA)) is deposited along the wall of DLD column 9802, as shown in Figure 98B.

[0607] In step 9703, the DLD pillar cap 9803 is removed, for example by various etching techniques (e.g., ALE), as shown in Figure 98C.

[0608] In step 9704, the cover plate 9805 with the etchant-resistant film 9806 is joined to the remaining top of the DLD pillar 9802, as shown in Figure 98C. This joining can be performed using anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, adhesives, etc.

[0609] In step 9705, a sacrificial etchant (e.g., deionized water) flow is performed to remove sacrificial material 9804, as shown in Figure 98D. Optionally, CICE and oxide growth and removal may be further performed to fabricate finer lines.

[0610] Figure 99 is a flowchart of a method 9900 for improving the collapse of a thin column by starting with a thick column and reducing the column size after the cover plate is joined, according to an embodiment of the present invention. Figures 100A to 100D depict cross-sectional views of improving the collapse of a thin column by starting with a thick column and reducing the column size after the cover plate is joined, according to an embodiment of the present invention, using the steps described in Figure 99.

[0611] Referring to Figures 100A-100D and Figure 99, in step 9901, CICE is performed on the silicon source substrate 9801 on which the DLD pillar 9802 is formed, as shown in Figure 100A. This DLD pillar 9802 includes a DLD pillar cap 9803, which refers to the top of the DLD pillar 9402.

[0612] In step 9902, sacrificial material 9804 (e.g., polyvinyl alcohol (PVA)) is deposited along the wall of DLD column 9802, as shown in Figure 100B.

[0613] In step 9903, the DLD pillar cap 9803 is removed, for example by various etching techniques (e.g., ALE), as shown in Figure 100C.

[0614] In step 9904, the cover plate 9805 with the etchant-resistant film 9806 is joined to the remaining top of the DLD pillar 9802, as shown in Figure 100C. This joining can be performed using anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, adhesives, etc.

[0615] In step 9905, an oxide etchant (e.g., dilute hydrofluoric acid) flow is performed to remove the sacrificial material 9804 and a portion of the DLD pillars 9802 to make them thinner, as shown in Figure 100D.

[0616] In another embodiment, the multiple layers of the DLD device are fabricated using polycrystalline silicon deposition and CICE, as discussed below in conjunction with Figures 101, 102A-102F, and 103. Polycrystalline silicon can be recrystallized using a laser recrystallization method. In one embodiment, the structural material is a water-soluble polymer, such as PVA, and this material is removed after fabrication by passing water through the device. The encapsulation layer can be made of glass, Cr, polymers, silicon, oxide-coated polymers, etc. In another embodiment, multiple stacked DLD pillars are fabricated in nanoscale feature-size DLD regions, as shown in Figure 103. This allows for matching of flow resistance of fluid samples in both the micrometer and nanometer regions of the DLD device. In one embodiment, porous layers between the multilayer stacks are created by co-sputtering an anti-HF material and an HF-consuming material, thereby producing a porous mesh. In one embodiment, carbon and silicon dioxide are co-sputtered to create a porous layer. When exposed to a CICE etchant, the silicon dioxide is etched away, resulting in a porous carbon mesh. The porous carbon mesh structurally stabilizes the silicon nanopillars and allows fluid samples to be transported through different layers of the DLD device.

[0617] Figure 101 is a flowchart of a method 10100 for manufacturing a multi-stacked DLD device using CICE with polysilicon according to an embodiment of the present invention. Figures 102A to 102F depict cross-sectional views of a multi-stacked DLD device manufactured using CICE with polysilicon according to an embodiment of the present invention, following the steps described in Figure 101.

[0618] Referring to Figures 101 and 102A-102F, in step 10101, CICE is performed on the silicon source substrate 10201 on which the DLD pillar 10202 is formed, as shown in Figure 102A.

[0619] In step 10102, structural material 10203 is deposited in the grooves between DLD pillars 10202, as shown in Figure 102B.

[0620] In step 10103, the encapsulation layer 10204 is deposited on the structural material 10203 and the DLD pillar 10202, as shown in Figure 102B.

[0621] In step 10104, a polycrystalline silicon layer 10205 is deposited on the encapsulation layer 10204, as shown in Figure 102C.

[0622] In step 10105, CICE is performed, which etches a portion of the polycrystalline silicon layer 10205 to form pillars 10206, as shown in Figure 102D.

[0623] In step 10106, structural material 10207 is deposited in the grooves between the pillars 10206, as shown in Figure 102E.

[0624] In step 10107, the encapsulation layer 10208 is deposited on the structural material 10207 and the pillar 10206, as shown in Figure 102E.

[0625] Note that steps 10104-10107 can be repeated to increase the number of DLD stacks.

[0626] In step 10108, structural materials 10207 and 10203 are removed, for example, through various etching techniques (e.g., CICE), as shown in Figure 102F.

[0627] Figure 103 shows a cross-sectional view of a multi-stacked DLD device for improving overall output in the nano-region according to an embodiment of the present invention.

[0628] As shown in Figure 103, the substrate 10301 includes micron-scale DLD pillars 10302 and nano-scale DLD pillars 10303. Furthermore, as shown in Figure 103, a porous layer 10304 and flow and etch stop layers 10305A-10305B are respectively located beneath the polycrystalline silicon layers 10306A-10306B. Additionally, Figure 103 shows a cover plate 10307 placed on the polycrystalline silicon layer 10306B and the nano-scale DLD pillars 10303 located next to the top polycrystalline silicon layer 10306B.

[0629] In one embodiment, spectroscopic methods, such as surface-enhanced Raman spectroscopy (SERS), can be used to detect particles separated by a DLD device on a wafer. The SERS substrate is integrated into the DLD wafer with porous silicon to filter the carrier liquid, ensuring that the particles to be detected are on the porous silicon. Particle detection can be enhanced by patterning SERS enhancement structures, such as gold nanostructures. In one embodiment, the porous silicon used for the SERS detector is fabricated using CICE, wherein the regions with porous silicon are ion-implanted. Alternatively, the regions with porous silicon can be patterned with a high-CICE catalytic activity catalyst, such as Pt, Pd, or Ru, and the regions with a non-porous silicon DLD column array can be patterned with a low-CICE catalytic activity catalyst, such as Au.

[0630] The ability to generate nanostructures with vertical sidewalls and varying critical dimensions and shapes can be used in applications such as metalenses and metasurfaces. In one embodiment, the metasurface comprises an array of pillars with different silicon nanopillar shapes and geometries, allowing the metasurface to focus light of specific wavelengths, such as near-infrared and mid-infrared light. Alternatively, the array can also be made of porous silicon oxide, enabling the focusing of visible wavelengths. Figure 104 shows an exemplary pixel geometry in which a portion of the pillars is silicon oxide. In particular, Figure 104 illustrates a metasurface according to an embodiment of the present invention, comprising an array of four pillars using silicon nanopillars fabricated by CICE and porous silicon oxide nanopillars to focus light of different wavelengths. The porous silicon pillars can be fabricated by intentionally increasing the silicon doping concentration in desired areas of the pixel using lithography and ion implantation. The CICE process is optimized to create porous silicon pillars in highly doped regions and non-porous silicon pillars in low-doped regions of the material to be etched. In one embodiment, the oxidation of porous silicon nanopillars completely transforms them into porous oxide silicon nanopillars, and a thin oxide shell grows on the non-porous pillars.

[0631] In one embodiment, a 3D integration method, such as nMASC, is used for the integration of III-V detectors in a metasurface.

[0632] Figure 105 illustrates an exemplary 3D stacked image sensor according to an embodiment of the present invention.

[0633] Figure 106 shows an exemplary petal-shaped imager die according to an embodiment of the present invention.

[0634] The following discussion is based on Figures 105 and 106.

[0635] In one embodiment, the tool for picking up and placing components is used to assemble two or more fields, wherein at least one field is a photosensitive pixel array, and at least one pair of fields is assembled on top of another. In one embodiment, the tool for picking up and placing components is used to assemble two or more fields, wherein at least one field is a photosensitive pixel array, and at least one field consists of logic circuitry. In one embodiment, the tool for picking up and placing components is used to assemble two or more fields, wherein at least one field is a photosensitive pixel array, and at least one field consists of logic circuitry, and at least one field consists of memory circuitry.

[0636] In one embodiment, the total thickness of the imager assembly is less than 25 micrometers. In one embodiment, logic circuitry physically located below the pixels is used to address groups of one or more pixels.

[0637] In one embodiment, one or more image sensors are bent into a spherical shape. The curvature of the image sensor can be generated by pressing the front side of the image sensor using a transfer chuck, while the back side of the image sensor conforms to a spherical mold. The mold may optionally be transparent. In one embodiment, the mold has an adhesive to hold the bent image sensor in place. The adhesive may be micro-UV cured. UV curing can be performed from the back side of the transparent mold. In one embodiment, the adhesive is inkjet-sprayed before the image sensor is bent. In one embodiment, multiple image sensors are picked up from a native substrate, such as native substrate 103, and simultaneously placed and bent onto a group of molds. In one embodiment, the group of molds is a single continuous part made of a transparent polymer. In one embodiment, the edges of the image sensor chips are fixed during assembly. In one embodiment, the edges of the image sensor chips are unconstrained during assembly. In one embodiment, the image sensor has a petal-shaped structure. In one embodiment, after the bending process, one or more edges of one or more petals are positioned behind adjacent petals.

[0638] In one embodiment, the output of a DLD device can be increased by stacking multiple DLD devices and running samples in parallel. In one embodiment, the DLD devices are stacked using 3D integration technology. In one embodiment, the 3D integration technology is n-MASC.

[0639] In summary, the principle of this case provides a means of using the catalyst of this case to influence the chemical etching apparatus and process technology to efficiently manufacture features in semiconductors using this CICE process.

[0640] The various embodiments described herein are presented for illustrative purposes and are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is for the purpose of best explaining the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0641] 100: Tools 101: Nano-progression XY platform 102: Native substrate chuck (native wafer chuck) 103: Native substrate (substrate) 104: Product substrate chuck (product wafer chuck) 105: Product substrate (product wafer) 106: Framework 107: Short-stroke XY platform 108: Metering Module (Metering Module Tool) 109: Voice Coil 110: Plasma Unit 111: Transfer chuck (transfer chuck unit) 112: Field 113: Individualized Field 114: Field 115: Components 201:Substrate 202: Chuck 203: Small chip 204: Light source 205: Optical Path 206: Imager 207: Light Source 208: DMD Components 209: Light Source 210: Projector 211: Imager 212: Thermoelectric cooler 213: Printed Circuit Board 214 Cooling Components 215:Substrate 216: Externally Coupled Grating 217: Internally Coupled Grating 218: Photonic Crystal Path 301: Ultraviolet Light Emitting Diode Array 302: Cooling system components 401: Field 402: Microfabrication Needle 403: Heat exchanger fluid 404: Thermally conductive printed circuit board 405: Heat Exchanger Layer 406: Thermal Actuator Layer 407: Thermoelectric Cooler 408:xy actuator layer 409: Bending section 410: Fixed part 411: Moving part 412: Floor 413: Soft layer 414: Flow valve 415: Fixed part 416: Moving part 417: Bending section 418: Actuated Mesh 419: Pressure Line 420: Vacuum source 421: Pressure Source 422: Vacuum Wire 423: Z-shaped curved layer 424: Bending section 425: Floor 426: Resistance Line 427: Vacuum Adsorption Layer 428: Needle 429: Vacuum Line 430: Gap 501: Vacuum Supply Unit 502: Annular contact point 503: Main vacuum manifold 504: Secondary vacuum manifold 505: Component 506: Component 507: Components 508: Vacuum Section 509: Airflow direction 601: Floor 602: Floor 603:nMASC field 604: Particle 605:Thin skin 701: Rectangular boundary region 702: Actuator Mesh 801: Intermediate substrate (intermediate wafer) 802: Embedded Alignment Mesh 803: Variable Density Glue 804: Component 805: Component 806: Component 901: Grain 902: Native Wafer 1001: Base Plate 1002:Y Reconfiguration Array 1003: Connecting rod 1004: Linkage 1005: Location 1006: Location 1007: Actuation Unit 1008: Fault Actuation Unit 1101: Transfer cassette assembly 1102: Diaphragm 1103: Hole 1104: Needle 1105: Components 1106: Materials 1201: Filling material 1202: ATC subcomponent 1301: Top 1302: Bottom 1303: Porous filter membrane 1304: Inkjet printer 1305: Component 1401: Imager (Imager Unit) (Image Sensor) 1402: Imager 1601: Base Plate 1602:Y Reconfiguration Array 1603: Connecting rod 1604: Connecting rod 1605: Location 1606: Location 1701: Location 1702: Location 1703:X Reconfiguration Array 1801: SWIR Imaging Sub-assembly 1802: Light-sensitive area 1803: Optical Components 1804: Interleaved Sensor Design 1805: Overlapping Mark 1806: Image-based marking 1807: Field 1808: Location 1809: Location 1810: Incident light 1811: Folded Grating 1901: SWIR Imaging Sub-component 1902: Light-sensitive area 1903: Focusing Optical Components 1904: Focusing Optical Components 1905: Overlapping Mark 1906: Image-based marking 1907: Field 1908: Location 1909: Location 2001: Flow cooler 2002: Heat Exchanger Fluid Suspension 2003: SWIR LED 2004: SWIR sensor 2005: Processing metal frames 2006: Plane Lens 2007: Off-axis LED focusing optics 2008: Overlay Plane 2009: Incident Light 2010: Folded Grating 2101: Components 2102: Global Alignment 2103: Components 2201: Grain 2202: Align with marker position 2301: Imager 2302: Reflective Blazed Grating 2303: Focusing Optical Components 2304: Light Source 2305: Opaque outer casing wall 2306: Cape Litro 2401: Overall Component 2402: Light Source 2403: Focusing Optical Components 2404: Component 2405: Photonic Light Guide 2406: Field 2501: Diffraction element 2601: Replacement chuck for known defective grains 2602: Buffer substrate 2603: Known for good grain size 2604: Buffer base plate chuck 2605: Known defective grains 2606: Robotic Arm 2607: Voice Coil Post 2608: Top Rod 2701: Massive silicon layer (massive silicon) 2702: Embedded oxide layer 2703: Silicon layer 2704: Embedded oxide layer 2705: Silicon layer 2706: Massive silicon layer 2707: Embedded oxide layer 2708: Low-doped n-type layer 2709: Highly doped p-type layer 2710: Silicon layer 2711: Floor 2712: Highly doped p-type layer 2713: Highly doped p-type layer 2714: Silicon layer 2801: Device Stacking 2802: Crystalline Silicon 2803: Chemical protective layer 2804: Structural encapsulation layer 2805: Area 1 2806: Area 2 2901A-2901N: Device Layer 2902: Vertical electrical connection (through-silicon via) 2903A-2903N: Device Layer 2904: Vertical electrical connection (through-silicon via) 3001: Logical Field 3002: SRAM Field 3003: Sacrificial Layer 3004: n-MASC device 3005: Assembled Products 3006: Device 3007: Connection 3008:Through Silicon Via 3101:SRAM 3201: Intermediary Field 3301A-3301N: Native Wafers 3302A-3302N: Carrier substrate (substrate) 3303: Metallic structure (grains) 3304: Adhesive 3305A-3305N: Native Wafers 3306A-3360N: Intermediate Wafer 3307: Component 3308: Adhesive Island 3309: Transfer wafer (transfer substrate) (substrate) 3310: Product Wafer 3401: Adhesive Island 3402: Component 3501: Structure 3502: Adhesive Island 3601: Miniature Transfer Champ 3602: Location 3603: Location 3604:Y Reconfiguration Array 3605: Electrode 3606: Thin-film transistor backplane 3607: Dielectric 3701: Thin Film Transistor Backplane 3702: Space 3703: Electrode 3704: Channel 3705: Vacuum Inlet 3706: Vacuum outlet 3708: Vacuum Channel Patterning 3709: Metal deposition and patterning (for fixed electrodes) 3710: Oxide Deposition 3711: Metal Deposition and Patterning 3712: Soft film deposition 3713: TSV pattern with etching from the back side 3714: Bump Creation 3715: Vacuum Channel Patterning 3716: Oxide Deposition 3717: TSV pattern with etching from the back side 3718: Porous membrane deposition 3719: Oxide Deposition 3720: Needle polishing 3721: Structure 3722: Component 3723: Structure 3724: Backplate 3725: Electrode 3726: Electrode 3727: Porous filter membrane 3728: TFT Patterning 3729: Vacuum Channel Patterning 3730: Metal deposition and patterning (for fixing electrodes) 3731: Oxide Deposition 3732: Metal deposition and patterning (for moving electrodes) 3733: Soft film deposition 3734: Vacuum Channel Patterning 3735: Oxide Deposition 3736: TSV pattern with etching from the back side 3737: Porous membrane deposition 3738: Oxide Deposition 3739: Needle polishing 3740: Structure 3741: Component 3742: Structure 3801: Optical Electromagnetic Actuator 3802: Slider 3803: Bending System 3804: Frictionless Pivot 3805: Pressure and / or Vacuum 3806: Track 3807: Transparent Core Port 3808: Encoder Sensor 3809: Permanent magnet / voice coil 3901: Bending Pivot 3902: Transparent Window 3903: Adaptive Chuck Module 3904: Air bearing 3905: Voice Coil Actuator 4001:X orbital 4002: Y orbital 4003: Air Bearing 4101: X-direction bending section 4201: Connection 4202: Electrode 4203: Electrode 4204: Gap 4205: Location 4206: ACM needle 4207: Sealing 4208: Diaphragm 4209: Vacuum Inlet 4301: Scissor mechanism 4302: Adjustable spacing mechanism 4303: Fixed point 4304: Actuator Boom 4305: Thermal Insulation Connector 4306: Cantilever bending section 4307: Insulation frame 4401: Countertop (Countertop Layer) (Countertop Structure) 4402: Native substrate adhesive 4403: Component 4404: Adhesive 4405: Waveguide layer (waveguide structure) 4406: Internal coupling grating (internal coupling grating layer) 4407:UV 4408: Block Part 4409: Encapsulation layer 4410:z compliant structure 4411: Externally Coupled Grating 4412: Bending bar (bending bar layer) (bending structure) 4413: Groove 4414: Secondary bending section 4415: Center Pad 4416: Adhesive droplets 4501: IR light 4601: Field 4602: Field 4603: Local air pressure and / or electrostatic repulsion 4701: Countertop (Countertop Layer) 4702: Native substrate adhesive 4703: UV radiation 4704: Block Part 4705: Encapsulation layer 4706:z conforming structure 4707: Transient materials (adhesives) 4708: Bending bar (bending bar layer) 4709: Groove 4710: Secondary bending section 4711: Center Pad 4800: Method 4801-4805: Steps 4901: Field 4902:Manhole 4903: Sacrificial Layer 4904: Block substrate (carrier substrate) 4905: Incision 4906: Chain 4907: Intermediate substrate 4908: Adhesive 4909: Native substrate 4910: Adhesive Island 5001:SIP 5002A-5002N: Active buffer substrate 5003A-5003N: Inert buffer substrate 5004: Arrow 5005: Arrow 5101: Field 5102: Adhesive (adhesive layer) (adhesive film) 5103: Device Structure 5104: Encapsulation layer 5105: Floor 5106: Catalyst 5107: Incision area 5108: Mark 5109: Mark 5110: Cutting the edge 5201: Microscope 5202: Variable pitch mechanism 5203: Stable Reference Mesh 5204A-5204D: Integrated light source and sensor pair 5301: Marker 5302: Structure 5303: Cutting edge (cutting boundary) 5304: Shallow etched grooves 5305: Etching agent droplets 5306: Inkjet Catalyst 5307: Cutting Thickness 5401: Cutting machine frame 5402: Blade 5403: Etching agent inlet 5404: Etching agent export 5405: Protective layer 5406: Etching agent droplets 5407: Catalyst membrane 5408: Cutting Thickness 5501: Catalyst 5601: Encapsulation layer 5602: Cutting Boundary 5700: Method 5701-5702: Steps 5801:Substrate 5802: Catalyst fracture layer (catalyst fracture) 5803: Countertop (template) 5804: Countertop 5805: Layer (catalyst breakage) 5806: Catalyst 5900: Method 5901-5905: Steps 6001:Substrate 6002: ALD blocking material 6003: ALD reinforced material 6004: Catalyst 6005: Nanostructure 6006: Anti-collapse cover 6100: Method 6101-6104: Steps 6201:Substrate 6202: Mask 6203: Catalyst Materials 6204: Nanostructure 6205: Anti-collapse cover 6301: Catalyst (Catalyst Line) 6302:Substrate 6401: Stable Pattern (Buttress) (Buttress Design) 6500: Method 6501-6505: Steps 6601:Substrate 6602: Dot pattern 6603: Spacer Pattern 6801: Porous Silicon 6802: Non-porous silicon 7001: Etching Mask 7100: Method 7101-7102: Steps 7201: Line / Space Pattern 7301: Lithography Link 7302: Filler material 7600: Method 7601-7604: Steps 7701: Silicon Pillar 7702:Substrate 7703: Oxide 7704: Required Materials 7900: Method 7901-7905: Steps 8101: Etching Stop Layer 8102: Polycrystalline Silicon 8103: Required Materials 8104:Substrate 8105: column 8106: Oxide 8107: Required Materials 8200: Method 8201-8206: Steps 8401: Etching Stop Layer 8402: Polycrystalline Silicon 8403: Materials 8404:Substrate 8405: column 8406: Oxide 8407: Required Materials 8500: Method 8501-8512: Methods 8701: Etching Stop Layer 8702: Polycrystalline Silicon 8703: Materials 8704:Substrate 8705: column 8706: Catalyst 8707: Oxide 8708: Required Materials 8709: Etching Stop Layer 8710: Polycrystalline Silicon 8711: column 8712: Oxide 8713: Required Materials 8800: Method 8801-8804: Steps 8902:Substrate 8903: Columnar (column) 8904: Oxides 8905: Required Materials 9100: Method 9101-9107: Steps 9201: Silicon wafer substrate 9202: Silicon nanowires (silicon nanopillars) 9203: Supporting material 9204: Nickel 9205: Support substrate 9206: Encapsulation layer 9300: Method 9301-9305: Steps 9401: Silicon wafer substrate 9402: DLD column 9403: Stabilized Materials 9404: DLD pillar cap 9405: Component (DLD pillar) 9406: Cover plate 9500: Method 9501-9505: Steps 9601: Silicon wafer substrate 9602: DLD column 9603: Floor 9604: Porous resistance layer 9700: Method 9701-9705: Steps 9801: Silicon wafer substrate 9802: DLD column 9803: DLD Pillar Cap 9804: Sacrificial Material 9805: Cover plate 9806: Anti-etchant film 9900: Method 9901-9905: Steps 10100: Method 10101-10108: Steps 10201: Silicon wafer substrate 10202: DLD column 10203: Structural Materials 10204: Encapsulation layer 10205: Polycrystalline silicon layer 10206:Column 10207: Structural Materials 10208: Encapsulation layer 10301:Substrate 10302: Micron-scale DLD column 10303: Nanoscale DLD pillar 10304: Porous layer 10305A-10305B: Flow and Etching Stop Layers 10306A-10306B: Polycrystalline silicon layer 10307: Cover plate

Claims

1. A method for creating a plurality of alignment marks in a plurality of fields during a monolithization process, the method comprising: creating the alignment marks in the fields using an etching technique during the monolithization process, wherein the etching technique comprises catalyst-influenced chemical etching or deep reactive ion etching.

2. The method as described in claim 1, wherein the alignment marks are created on the back side of the fields.

3. The method as described in claim 1, wherein the alignment marks are created at locations remote from all mouth regions.

4. The method of claim 1, wherein the alignment marks are completely etched over the entire thickness of at least one of the fields.

5. The method of claim 1, wherein the alignment marks are partially etched over the entire thickness of at least one of the fields.

6. The method of claim 1 further comprises: using a first lithography process and a first etch to stop creating the alignment marks in the fields; and using a second lithography process and a second etch to stop performing monolithization.

7. A method for preventing catalyst drift during catalyst-influenced chemical etching (CICE), the method comprising: providing a semiconductor material; patterning a catalyst on the surface of the semiconductor material, wherein the catalyst includes one or more isolation features, and wherein the one or more isolation features include a predetermined aperture; and exposing the patterned catalyst to an etchant, wherein the patterned catalyst and the etchant cause etching of the semiconductor material to form a plurality of buttresses corresponding to the predetermined aperture, wherein the buttresses include a cross-section configured to prevent catalyst drift during catalyst-influenced chemical etching; wherein, These buttresses are configured to remain substantially intact throughout the entire period of the catalyst-induced chemical etching (CICE) process, until the selective removal step following etching.

8. The method of claim 7, wherein the buttresses are selectively removed after the chemical etching is influenced by the catalyst.

9. The method as described in claim 7, wherein the buttresses are patterned to necessarily collapse in a predetermined direction.

10. The method of claim 7, wherein the semiconductor material comprises silicon, and wherein the method further comprises: etching the semiconductor material to create a structure of alternating layers of porous silicon and non-porous silicon.

11. The method as described in claim 10, wherein the structure is for a three-dimensional anti-blocking and fast-flash device.

12. The method as described in claim 10, wherein the structure is for metal interconnects.

13. The method of claim 7, wherein the catalyst comprises one of the following groups: gold, platinum, palladium, silver, ruthenium, iridium, tungsten, copper, titanium nitride, titanium, graphene, and carbon.

14. The method of claim 7, wherein the one or more isolation features are inserted into the catalyst in one of the following groups: lithography, imprint lithography, electron beam lithography, extreme ultraviolet lithography, self-aligned patterning, and spacer patterning.

15. The method of claim 7, wherein the etchant comprises one or more of the following groups: fluorides, oxidants, alcohols and protic solvents, aprotic solvents, polar solvents and nonpolar solvents.

16. The method of claim 7 further comprises: depositing the catalyst on a plurality of nanostructures created in a nanoimprinting resist or a photoresist using a metal fracture process.

17. The method of claim 16 further comprises: patterning the catalyst using thermally stable carbon; etching the thermally stable carbon using the nanoimprint photoresist or the photoresist; and removing any polymeric resist using a metal fracture prior to catalyst deposition.

18. A fluid device comprising: a multilayer stack of silicon micropillars and nanopillar arrays, wherein the silicon micropillars and nanopillar arrays are fabricated using a catalyst-influenced chemical etching, wherein the multilayer stack is fabricated by depositing a plurality of films comprising a plurality of polycrystalline silicon films and etching the polycrystalline silicon films using the catalyst-influenced chemical etching.

19. The fluid device as claimed in claim 18, wherein the multilayer stack of the silicon micropillars and nanopillar arrays is used as a deterministic lateral displacement array for particle separation.

20. The fluid device of claim 18, wherein the membranes further comprise a plurality of etch stop layers, a plurality of porous layers, and a plurality of layers that become porous upon exposure to a catalyst affecting a chemical etchant.

21. The fluid device as claimed in claim 20, wherein the porous layers are formed by co-sputtering a hydrogen fluoride-resistant material and a hydrogen fluoride-consuming material.

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