INTEGRATED CIRCUITS (ICs) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS

Abstract

Integrated circuits (ICs) including capacitors and inductors, employing directly coupled metal lines between vertically adjacent interconnect layers to reduce coupling resistance, and related manufacturing methods. Direct coupling refers to the absence of intermediate vertical interconnect via (via) layers, where vias connect metal lines in vertically adjacent interconnect layers. Correspondingly, the upper and lower metal lines in corresponding vertically adjacent upper and lower interconnect layers are directly coupled to each other without the need for intermediate via layers. For example, direct coupling metal lines in adjacent interconnect layers of an IC can reduce contact resistance between metal lines and reduce the overall height of the IC. An insulating layer can be provided in a selective recessed region between the upper and lower interconnect layers to insulate upper metal lines that are not intended to be electrically coupled together from another vertically intersecting lower metal line.

Description

Technical Field

[0001] This disclosure relates to integrated circuits (ICs) and associated semiconductor dies (“dies”) employing interconnect structures for interconnecting semiconductor elements within the die, manufactured via back-end-of-line (BEOL) processes. Prior Technology

[0002] Computing devices have become increasingly ubiquitous in modern society. Early computers were the size of a room and used vacuum tubes to provide basic mathematical calculations. In contrast, modern computing devices rely on integrated circuits (ICs) to provide countless multimedia, telephone, word processing, and other functions in relatively small packages. The industry is feeling market pressure to offer more and more processing options for increasingly smaller products. While ICs generally follow Moore's Law, the continued advancements in IC functionality within smaller packages are putting pressure on manufacturing capabilities.

[0003] Current IC manufacturing processes rely on a sequence of masking steps used in stages to create multi-level ICs. ICs provided in the form of semiconductor dies (“dies”) include active semiconductor layers typically fabricated in front-end-of-line (FEOL) manufacturing processes. The active semiconductor layers include semiconductor elements (e.g., transistors). ICs also include interconnect structures typically formed adjacent to the semiconductor layers via back-end-of-line (BEOL) manufacturing processes. The interconnect structures include multiple metallization layers, each with metal lines (e.g., metal traces) disposed within the respective metallization layer to provide interconnections between different semiconductor elements and / or external interconnects (e.g., solder balls). Vertical interconnect vias (vias), such as metal pillars and through-silica vias (TSVs), are disposed within the metallization layers to provide interconnections between adjacent metal lines in adjacent metallization layers.

[0004] As the density of semiconductor components in IC chips increases, the need for more power and ground connections within the IC chip also increases. A traditional technique for providing power in ICs is through a power distribution network (PDN) in the interconnect structure, which uses multiple metal lines above multiple metallization layers to distribute power. However, this network is negatively impacted because the physical size of the metal lines within the metallization layers decreases due to the shrinking size of the IC chip and its associated package. Specifically, as the physical size of the conductive material in the metal lines of the IC chip's interconnect structure decreases, the contact resistance of the metal lines increases. To mitigate this increased resistance, multiple vias can be provided to couple adjacent metal lines in adjacent metallization layers together as part of the same node to reduce contact resistance. Even so, the metal lines may have a higher resistance than desired. If these metal lines are used in the PDN of the IC chip, the increased resistance leads to a higher current-resistance (IR) drop than expected in the PDN. Summary of the Invention

[0005] Exemplary aspects disclosed in the detailed description include integrated circuits (ICs) employing directly coupled metal lines between vertically adjacent interconnect layers to reduce coupling resistance. Related manufacturing methods are also disclosed. The IC may include capacitors and / or inductors employing directly coupled metal lines between vertically adjacent interconnect layers. Direct coupling means that there are no intermediate vertical interconnect access (via) layers where vias(s) interconnect the metal lines in the vertically adjacent interconnect layers. For example, the vertically adjacent interconnect layers in the IC may be provided as adjacent metallization layers in a back-end (BEOL) interconnect structure manufactured as part of a back-end (BEOL) manufacturing process. The BEOL interconnect structure is fabricated on the front side of the active semiconductor layer of the IC. For example, it may be necessary to provide coupling metal lines (e.g., metal traces) in the adjacent metallization layers of the BEOL interconnect structure as part of a distribution network (PDN) in the IC to reduce contact resistance and thereby reduce current (I) resistance (R) drop (IR). As another example, it may be necessary to electrically couple metal lines in adjacent metallization layers of a BEOL interconnect structure as part of a capacitor (e.g., a metal-oxide-metal (MoM) capacitor) or a coil inductor to reduce resistance and / or the area required to provide such components in the interconnect structure. In another example, vertically adjacent interconnect layers of an IC may be disposed in a semiconductor substrate, wherein buried metal lines are vertically adjacent to a metallization layer formed on the back side of the semiconductor substrate.

[0006] Providing coupling metal lines between vertically adjacent interconnect layers in an IC avoids the need to fabricate separate via layers between adjacent interconnect layers, each with corresponding adjacent metal lines that are electrically coupled to each other to form an interconnect for the desired application. Therefore, separate via layer masks may not be required to form vias in separate via layers between adjacent interconnect layers designed to have metal lines directly coupled to each other. Providing direct coupling metal lines between adjacent interconnect layers in an IC can also reduce the overall height of the semiconductor die (“die”) stack in the IC. This height reduction can be achieved or consumed by additional metallization layers to support higher density components and interconnects within the die.

[0007] In one exemplary aspect, to provide a direct coupling metal line between adjacent interconnect layers in a BEOL interconnect structure in an IC, a first overlay metal line disposed in a first overlay metallization layer of the IC's BEOL interconnect structure contacts at least a portion of a second lower metal line in a second adjacent lower metallization layer of the BEOL interconnect structure. The overlay metallization layer and the lower metallization layer are respectively an overlay interconnect layer and a lower interconnect layer. The overlay metal line and the lower metal line extend longitudinally orthogonally to each other in their respective metallization layers in the horizontal direction. The direct contact between the overlay metal line and the lower metal line can be provided in a connection region at the intersection of the overlay metal line and the lower metal line in the vertical direction. In this way, it is not necessary to use vias in a separate via layer between adjacent first and second metallization layers in the BEOL interconnect structure to couple the overlay metal lines and lower metal lines in adjacent metallization layers to each other. For example, the overlay metal lines and lower metal lines formed to be in direct contact with each other can be positive power rails or negative / ground power rails as part of a PDN distributed in the overlay metal lines and lower metal lines. Direct contact between the overlay metal lines and the underlying metal lines in adjacent metallization layers that are part of a PDN can reduce contact resistance, which may be desirable for reducing IR drop in the PDN.

[0008] Because the overlay metal lines in the overlay metallization layer can extend vertically above other lower metal lines in the lower metallization layer that should not be directly coupled to each other, thin insulating layers of dielectric material (multiple layers) can be formed (e.g., patterned) in selected areas below the overlay metal lines in the overlay metallization layer to insulate and isolate the overlay metal lines from other lower metal lines in the lower metallization layer that also vertically intersect with the overlay metal lines. For example, two adjacent overlay metal lines in the lower metallization layer can be the positive and negative / ground metal lines of the PDN, respectively. It may be necessary to directly couple the positive overlay metal line to the positive lower metal line while ensuring that the positive overlay metal line does not make conductive contact with the negative / ground lower metal line. In this regard, insulating layers can be formed in recesses formed in the overlay metal lines in the overlay metallization layer, thereby eliminating the need for separate insulating layers between metallization layers to avoid increasing the height of the BEOL interconnect structure. Alternatively, a thin insulating layer can be formed by patterning openings in the insulating layer located in the contact region between the lower and upper metal wires, in which the metal wires will be directly coupled. The patterned openings are formed in the insulating layer, where the upper metal wire to be formed in the upper metallization layer will be directly coupled to the lower metal layer in the lower metallization layer. The metal material disposed in the upper metallization layer to form the upper metal wire is also disposed in the patterned openings extending through the insulating layer and in direct contact with the lower metal wire. In this way, the insulating layer is not patterned and remains present in regions where the lower and upper metal wires should not be electrically coupled to each other.

[0009] Note that not all metallization layers in a BEOL interconnect structure need to be provided between adjacent metallization layers without intermediate via layers. It may be desirable to provide only a subset of the metallization layers in the interconnect structure, which includes direct connections between adjacent metal lines within this subset of metallization layers.

[0010] In another exemplary aspect, the IC may include directly coupled metal lines in the vertical direction in adjacent interconnect layers on the back side of the IC's semiconductor structure. For example, the semiconductor structure includes an active semiconductor layer disposed on a semiconductor substrate. The semiconductor substrate may be a lower interconnect layer including buried metal lines as lower metal lines. For example, the buried metal lines may be part of the IC's PDN. The buried metal lines in the semiconductor substrate may be coupled to the back side of the source and / or drain contacts of a field-effect transistor (FET) to distribute power to such FET. One or more metallization layers as additional interconnect layers may be formed on the back side of the semiconductor substrate, including metal lines as overlay metal lines that are directly coupled to the buried metal lines in the semiconductor substrate. Other exemplary aspects of directly coupling overlay metal lines to lower metal lines for BEOL interconnect structures discussed above can also be applied to directly coupled metal lines in the vertical direction in adjacent interconnect layers on the back side of the IC's active semiconductor layer. Similarly, by eliminating the need for an intermediate via layer between the semiconductor substrate and adjacent interconnect layers, providing directly coupled metal lines between the semiconductor substrate and adjacent interconnect layers on the back side of the IC can reduce metal line contact resistance and also reduce the height of the IC.

[0011] In one exemplary aspect, a capacitor is provided. The capacitor includes an interconnect structure. The interconnect structure includes a lower interconnect layer comprising a first lower metal finger structure and a second lower metal finger structure. The first lower metal finger structure includes a plurality of first lower metal lines extending parallel to each other, and the second lower metal finger structure includes a plurality of second lower metal lines extending parallel to each other. The first lower metal finger structures and the second lower metal finger structures are interleaved. The interconnect structure also includes an upper interconnect layer configured to be vertically adjacent to the lower interconnect layer. The upper interconnect layer includes a first upper metal finger structure and a second upper metal finger structure. The first upper metal finger structure includes a plurality of first upper metal lines extending parallel to each other, and the second upper metal finger structure includes a plurality of second upper metal lines extending parallel to each other. The first upper metal finger structures and the second upper metal finger structures are interleaved. The first upper metal finger structure intersects the first lower metal finger structure in a vertical direction in a first connection region. The first upper metal finger structure is coupled to the first lower metal finger structure in the first connection region. The second upper metal finger structure and the second lower metal finger structure intersect in the vertical direction in the second connection region. The second upper metal finger structure is coupled to the second lower metal finger structure in the second connection region.

[0012] In another exemplary aspect, an inductor is provided. The inductor includes an interconnect structure comprising a lower interconnect layer including a lower metal coil structure comprising a plurality of lower metal segments coupled to each other in a coil-shaped pattern. The interconnect structure further includes an upper interconnect layer configured to be vertically adjacent to the lower interconnect layer, the upper interconnect layer including an upper metal coil structure comprising a plurality of upper metal segments coupled to each other in a coil-shaped pattern. The upper metal coil structure and the lower metal coil structure intersect vertically in a first connection region. The interconnect structure also includes an insulating layer disposed between the upper metal coil structure and the lower metal coil structure in a second connection region. The upper metal coil structure is coupled to the lower metal coil structure in the first connection region.

[0013] In another exemplary aspect, an IC is provided. The IC includes a lower interconnect layer comprising a first lower metal line extending in a first horizontal direction and a second lower metal line extending in a second horizontal direction parallel to the first horizontal direction. The IC also includes an upper interconnect layer configured to be vertically adjacent to the lower interconnect layer, the upper interconnect layer including a first upper metal line extending in a third horizontal direction orthogonal to the first horizontal direction. The first upper metal line intersects the first lower metal line in a vertical direction in a first connection region. The first upper metal line intersects the second lower metal line in a vertical direction in a second connection region. The first upper metal line is coupled to the first lower metal line in the first connection region. The IC also includes a first insulating layer disposed between the first upper metal line and the second lower metal line in the second connection region. Simple Explanation of the Diagram

[0014] Figure 1 is a side view of an integrated circuit (IC) including a semiconductor die (“die”) stack, the semiconductor die (“die”) stack including a back-end (BEOL) interconnect structure, the BEOL interconnect structure including a metallization layer separated by a vertical interconnect access (via) layer, the vertical interconnect access (via) layer containing vias interconnecting adjacent metal lines in adjacent metallization layers;

[0015] Figure 2A is a top view of an exemplary IC, which includes an overlay interconnect layer disposed on a lower interconnect layer, wherein a first overlay metal line and a second overlay metal line in the overlay interconnect layer are coupled to corresponding first lower metal lines and second lower metal lines in the lower interconnect layer through vias in a via layer;

[0016] Figure 2B is a cross-sectional side view of IC in Figure 2A;

[0017] Figure 3 is a side view of an exemplary IC including a die stack, the die stack including a BEOL interconnect structure, the BEOL interconnect structure including adjacent upper and lower interconnect layers without intermediate via layers as metallization layers, wherein the upper metal lines in the upper interconnect layer are directly coupled to the lower metal lines in the selected connection region;

[0018] Figure 4A is a top view of an IC, which includes an overlay interconnect layer disposed on a lower interconnect layer without an intermediate via layer. A first and a second overlay metal line in the overlay interconnect layer are coupled to corresponding first and second lower metal lines in a first and a second connection region at a first vertical intersection point and a second vertical intersection point of the metal lines. The IC also includes an insulating layer disposed in recesses in other connection regions to insulate and isolate the first and second overlay metal lines from their corresponding second and first lower metal lines.

[0019] Figure 4B is a cross-sectional side view of IC in Figure 4A;

[0020] Figure 5A is a top view of another IC, which includes an overlay interconnect layer disposed on a lower interconnect layer without an intermediate via layer, wherein a first overlay metal line and a second overlay metal line in the overlay interconnect layer are coupled to corresponding first lower metal lines and second lower metal lines in a first connection region and a second connection region at a first vertical intersection of the metal lines, and the IC also includes an insulating layer disposed in a recess outside the first connection region and the second connection region to insulate and isolate the first overlay metal line and the second overlay metal line from the corresponding second lower metal line and the first lower metal line;

[0021] Figure 5B is a cross-sectional side view of IC in Figure 5A;

[0022] Figure 6 is a flowchart illustrating an exemplary process for manufacturing an IC, which includes adjacent upper and lower interconnect layers without intermediate via layers, wherein upper metal lines in the upper interconnect layer are directly coupled to lower metal lines in selected connection regions, including but not limited to the ICs in Figures 4A-4B and 5A-5B;

[0023] Figures 7A and 7B-1 are flowcharts illustrating another exemplary process for manufacturing an IC, which includes adjacent overlay interconnect layers and lower interconnect layers without intermediate via layers, wherein overlay metal lines in the overlay interconnect layer are directly coupled to lower metal lines in selected connection regions, and the IC also includes an insulating layer disposed in recesses in other connection regions to insulate and isolate first and second overlay metal lines from corresponding second and first lower metal lines, including but not limited to the IC in Figures 4A-4B;

[0024] Figures 7A and 7B-2 are flowcharts illustrating another exemplary process for manufacturing an IC, which includes adjacent overlay interconnect layers and lower interconnect layers without intermediate via layers, wherein overlay metal lines in the overlay interconnect layer are directly coupled to lower metal lines in selected connection regions, and the IC also includes an insulating layer disposed in recesses outside the first and second connection regions to insulate and isolate the first and second overlay metal lines from the corresponding second and first lower metal lines, including but not limited to the IC in Figures 5A-5B;

[0025] Figures 8A-8E-1 illustrate exemplary manufacturing stages in the process shown in Figures 7A and 7B-1;

[0026] Figures 8A-8E-2 illustrate exemplary manufacturing stages in the process shown in Figures 7A and 7B-2;

[0027] Figure 9 is a top view of another exemplary IC, which includes an overlay interconnect layer disposed on a lower interconnect layer without an intermediate via layer, wherein a first overlay metal line and a second overlay metal line in the overlay interconnect layer are coupled to a corresponding first lower metal line and a corresponding lower lower metal line in a first connection region and a second connection region at a corresponding first vertical intersection and a second vertical intersection of the metal lines, wherein the overlay metal line also extends in both directions of its coupled lower metal line;

[0028] Figure 10 is a top view of another exemplary IC, which includes an overlay interconnect layer disposed on a lower interconnect layer without an intermediate via layer, wherein a first overlay metal line and a second overlay metal line in the overlay interconnect layer are coupled to corresponding first and second lower metal lines in a first connection region and a second connection region at a first vertical intersection point and a second vertical intersection point of the metal lines, wherein the overlay metal line also extends in the direction of its coupled lower metal line;

[0029] Figure 11 is a top view of another exemplary IC, which includes an overlay interconnect layer disposed on a lower interconnect layer without an intermediate via layer, wherein a first overlay metal line and a second overlay metal line in the overlay interconnect layer are coupled to corresponding first and second lower metal lines in a first connection region and a second connection region at a first vertical intersection point and a second vertical intersection point of the metal lines, wherein the overlay metal lines also extend in both directions of their coupled lower metal lines;

[0030] Figure 12A is a side view of an exemplary IC, which includes a field-effect transistor (FET) formed in an active semiconductor layer of an FEOL structure, a BEOL interconnect structure on the front side of the FEOL structure, and an adjacent interconnect layer on the back side of the FEOL structure. The interconnect layer includes buried metal lines in a semiconductor substrate, which are coupled to metal lines in connection regions of adjacent metallization layers without intermediate via layers. The IC also includes an insulating layer disposed in recesses in other connection regions to insulate and isolate a first overlay metal line and a second overlay metal line from corresponding second underlay metal lines and first underlay metal lines.

[0031] Figure 12B is another side view of the IC in Figure 12A;

[0032] Figures 13A and 13B are flowcharts illustrating another exemplary process for manufacturing an IC, which includes a FET formed in an active semiconductor layer of a FEOL structure, a BEOL interconnect structure on the front side of the FEOL structure, and an adjacent interconnect layer on the back side of the FEOL structure. The interconnect layer includes buried metal lines in a semiconductor substrate, which are coupled to metal lines in an adjacent metallization layer without intermediate via layers, including but not limited to the ICs in Figures 12A and 12B.

[0033] Figures 14A-14E illustrate exemplary manufacturing stages in the process shown in Figures 13A and 13B;

[0034] Figure 15 is a side view of another exemplary IC, which includes a FET formed in an active semiconductor layer of an FEOL structure, a BEOL interconnect structure on the front side of the FEOL structure, and an adjacent interconnect layer on the back side of the FEOL structure. The interconnect layer includes buried metal lines in a semiconductor substrate, which are coupled to metal lines in a connection region in an adjacent metallization layer without an intermediate via layer. The IC also includes an insulating layer disposed in a recess outside the connection region to insulate and isolate a first overlay metal line and a second overlay metal line from their respective second underlay metal lines and first underlay metal lines.

[0035] Figure 16A is a top view of an exemplary IC that includes a capacitor formed in an interconnect structure. The interconnect structure includes a lower interconnect layer and an upper interconnect layer. The lower interconnect layer includes interleaved first and second lower metal finger structures. The upper interconnect layer includes interleaved first and second upper metal finger structures extending orthogonally to the first and second lower metal fingers. The first upper metal finger structure is coupled to the first lower metal finger structure in a first connection region, coupled to the first lower metal finger structure in a first intersecting connection region, and coupled to the second lower metal finger structure in a second intersecting connection region, without an intermediate via layer.

[0036] Figure 16B is a cross-sectional side view of IC in Figure 16A;

[0037] Figure 17A is a top view of another exemplary IC, which includes a capacitor formed in an interconnect structure. The interconnect structure includes a lower interconnect layer and an upper interconnect layer. The lower interconnect layer includes interleaved first and second lower metal finger structures. The upper interconnect layer includes interleaved first and second upper metal finger structures extending orthogonally to the first and second lower metal fingers. The first upper metal finger structure is coupled to the first lower metal finger structure in a first connection region, coupled to the first lower metal finger structure in a first intersecting connection region, and coupled to the second lower metal finger structure in a second intersecting connection region, without an intermediate via layer.

[0038] Figure 17B is a cross-sectional side view of IC in Figure 17A;

[0039] Figure 18A is a top view of another exemplary IC, which includes a capacitor formed in an interconnect structure. The interconnect structure includes a lower interconnect layer and an upper interconnect layer. The lower interconnect layer includes interleaved first and second lower metal finger structures. The upper interconnect layer includes interleaved first and second upper metal finger structures extending in the same direction as the first and second lower metal fingers. The first upper metal finger structure is coupled to the first lower metal finger structure in a first connection region, coupled to the first lower metal finger structure in a first intersecting connection region, and coupled to the second lower metal finger structure in a second intersecting connection region, without an intermediate via layer.

[0040] Figure 18B is a cross-sectional side view of IC in Figure 18A;

[0041] Figure 19A is a top view of another exemplary IC, which includes an inductor formed in an interconnect structure. The interconnect structure includes a lower interconnect layer and an upper interconnect layer. The lower interconnect layer includes a lower metal coil structure, and the upper interconnect layer includes an upper metal coil structure. There is no intermediate via layer between the lower interconnect layer and the upper interconnect layer, and the upper metal coil structure is coupled to the lower metal coil structure to form a multi-interconnect-layer inductor.

[0042] Figure 19B is a cross-sectional side view of IC in Figure 19A;

[0043] Figure 20A is a top view of another exemplary IC, which includes an inductor formed in an interconnect structure. The interconnect structure includes a lower interconnect layer and a plurality of upper interconnect layers. The lower interconnect layer includes a lower metal coil structure, and the plurality of upper interconnect layers include corresponding upper metal coil structures. There are no intermediate via layers between the interconnect layers, and the upper metal coil structures are coupled to the lower metal coil structures to form a multi-interconnect-layer inductor.

[0044] Figure 20B is a cross-sectional side view of IC in Figure 20B;

[0045] Figure 21 is a block diagram of an exemplary processor-based system that can be disposed in one or more ICs. Each IC may include one or more interconnect structures, each interconnect structure comprising vertically adjacent lower interconnect layers and upper interconnect layers without intermediate via layers. The vertically adjacent lower and upper interconnect layers include corresponding lower and upper metal lines coupled to each other, including but not limited to the exemplary ICs in Figures 3-5B, 8A-12B, and 15-20B, and conforming to the exemplary manufacturing processes in Figures 6-7B-2 and 14A-14E; and

[0046] Figure 22 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components disposed in one or more ICs. Each IC may include one or more interconnect structures, which include vertically adjacent lower interconnect layers and upper interconnect layers without intermediate via layers. The vertically adjacent lower interconnect layers and upper interconnect layers include corresponding lower metal lines and upper metal lines coupled to each other, including but not limited to the exemplary ICs in Figures 3-5B, 8A-12B, and 15-20B and conforming to the exemplary manufacturing processes in Figures 6-7B-2 and 14A-14E. Implementation

[0047] Several exemplary aspects of this disclosure are now described with reference to the figures. The word “exemplary” is used herein to mean “as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as being better than or superior to the others.

[0048] Exemplary aspects disclosed in the detailed description include integrated circuits (ICs) employing directly coupled metal lines between vertically adjacent interconnect layers to reduce coupling resistance. Related manufacturing methods are also disclosed. The IC may include capacitors and / or inductors employing directly coupled metal lines between vertically adjacent interconnect layers. Direct coupling indicates the absence of intermediate vertical interconnect access (via) layers, where vias(multiple) interconnects the metal lines in the vertically adjacent interconnect layers. For example, the vertically adjacent interconnect layers in the IC may be provided as adjacent metallization layers in a back-end (BEOL) interconnect structure manufactured as part of a back-end (BEOL) manufacturing process. The BEOL interconnect structure is fabricated on the front side of the active semiconductor layer of the IC. For example, it may be necessary to provide coupling metal lines (e.g., metal traces) in the adjacent metallization layers of the BEOL interconnect structure as part of a distribution network (PDN) in the IC to reduce contact resistance and thereby reduce current (I) resistance (R) drop (IR). As another example, it may be necessary to electrically couple metal lines in adjacent metallization layers of a BEOL interconnect structure as part of a capacitor (e.g., a metal oxide metal (MoM) capacitor) or a coil inductor to reduce resistance and / or the area required to provide such components in the interconnect structure. In another example, vertically adjacent interconnect layers of an IC may be disposed in a semiconductor substrate, wherein buried metal lines are vertically adjacent to metallization layers formed on the back side of the semiconductor substrate.

[0049] Providing coupling metal lines between vertically adjacent interconnect layers in an IC avoids the need to fabricate separate via layers between adjacent interconnect layers, each with corresponding adjacent metal lines that are electrically coupled to each other to form an interconnect for the desired application. Therefore, separate via layer masks may not be required to form vias in separate via layers between adjacent interconnect layers designed to have metal lines directly coupled to each other. Providing direct coupling metal lines between adjacent interconnect layers in an IC can also reduce the overall height of the semiconductor die (“die”) stack in the IC. This height reduction can be achieved or consumed by additional metallization layers to support higher density components and interconnects within the die.

[0050] Before discussing examples of ICs including adjacent top interconnect layers and bottom interconnect layers (including capacitors and inductors) without intermediate via layers, where, starting from Figure 3, the top metal lines in the top interconnect layer are directly coupled to the bottom metal lines in the selected connection area, we will first describe ICs including top interconnect layers and bottom interconnect layers with respect to Figures 1-2B, where the corresponding top metal lines are coupled together through an intermediate via layer with vias.

[0051] In this regard, Figure 1 is a side view of an integrated circuit (IC) 100 including a semiconductor die (“die”) stack 102, which includes a back-end (BEOL) interconnect structure 104 disposed on a front-end (FEOL) structure 106. The FEOL structure 106 includes an active semiconductor layer 108 formed on a substrate 110. P-type field-effect transistors (FETs) 112P and N-type (FETs) 112N are formed in the active semiconductor layer 108. The BEOL interconnect structure 104 includes multiple interconnect layers 114(1)-114(4), each interconnect layer including one or more metal lines 116(1)-116(4) which can provide direct or indirect interconnects between FETs 112P, 112N and external interconnects 118 (e.g., solder bumps) adjacent to the overlay interconnect layer 114(4) of the BEOL interconnect structure 104. The interconnect layers 114(1)-114(4) in the BEOL interconnect structure 104 of IC 100 are also referred to as “metallization layers” in this example. The metal lines 116(1)-116(4) extend longitudinally in the horizontal X-axis or Y-axis direction in FIG. 1. The BEOL interconnect structure 104 also includes multiple vertical interconnect via (via) layers 120(1)-120(4) disposed adjacent to the respective interconnect layers 114(1)-114(4). Vias 122(1)-122(4) (e.g., metal pillars) are formed in via layers 120(1)-120(4) to provide interconnection between metal lines 116(1)-116(4) in adjacent interconnect layers 114(1)-114(4). Therefore, the total height H1 of IC 100 in FIG1 is a function of the height of FEOL structure 106 and BEOL interconnect structure 104. The height H2 of BEOL interconnect structure 104 is a function of the number and height of individual interconnect layers 114(1)-114(4) and via layers 120(1)-120(4).

[0052] Figures 2A and 2B are respectively a top view and a cross-sectional side view of the overlay interconnect layer 114O in the BEOL interconnect structure 104 of IC 100 in Figure 1, which is adjacent to the lower interconnect layer 114U. Figure 2B is a cross-sectional side view through the A1-A1' section line in Figure 2A. As shown in Figure 2B, the overlay interconnect layer 114O and the lower interconnect layer 114U are adjacent interconnect layers in interconnect layers 114(1)-114(4) in the BEOL interconnect structure 104. For example, the lower interconnect layer 114U can be interconnect layer 114(2) in Figure 1, and the overlay interconnect layer 114O can be interconnect layer 114(3) in Figure 1. In this example, "overlay" and "lower layer" mean that the overlay interconnect layer 114O is disposed above the lower interconnect layer 114U in the vertical direction (Z-axis direction) in Figures 2A and 2B. As shown in Figure 2A, a first lower metal line 116U(1) and a second lower metal line 116U(2) are disposed in a lower interconnect layer 114U. Each of the first lower metal line 116U(1) and the second lower metal line 116U(2) extends parallel to each other along the corresponding longitudinal axes LA1 and LA2 in the horizontal direction (Y-axis direction). Also as shown in Figure 2A, a first upper metal line 116O(1) and a second upper metal line 116O(2) are disposed in an upper interconnect layer 114O. Each of the first upper metal line 116O(1) and the second upper metal line 116O(2) extends parallel to each other and orthogonal to the longitudinal axes LA1 and LA2 in the horizontal direction (X-axis direction), wherein the first lower metal line 116U(1) and the second lower metal line 116U(2) extend in the longitudinal axes LA1 and LA2.

[0053] As shown in Figure 2B, in order to interconnect the first lower metal line 116U(1) to the first upper metal line 116O(1), a via layer 120 is disposed between the lower interconnect layer 114U and the upper interconnect layer 114O in the BEOL interconnect structure 104. One or more vias 122(1) are disposed in the via layer 120 in the first connection region 200(1), in which the first lower metal line 116U(1) and the first upper metal line 116O(1) intersect in the horizontal X-axis and Y-axis directions. The vias 122(1) contact the first lower metal line 116U(1) and the first upper metal line 116O(1) in the first connection region 200(1) to electrically couple the first lower metal line 116U(1) and the first upper metal line 116O(1) together. For example, the first lower metal line 116U(1) and the first upper metal line 116O(1) can be electrically coupled together as part of the positive power rail in the distribution network (PDN) of IC 100 in FIG. 1 for routing power supply voltage. Similarly, as shown in FIG. 2A, one or more vias 122(2) are also provided in the via layer 120 in the second connection region 200(2), in which the second lower metal line 116U(2) and the second upper metal line 116O(2) intersect in the horizontal X-axis and Y-axis directions. The vias 122(2) contact the second lower metal line 116U(2) and the second upper metal line 116O(2) in the second connection region 200(2) to electrically couple the second lower metal line 116U(2) and the second upper metal line 116O(2) together. For example, the second lower metal line 116U(2) and the second upper metal line 116O(2) can be electrically coupled together as part of the ground or negative power rail in the PDN of IC 100 in Figure 1.

[0054] Using the example of IC 100 in Figures 1 and 2A-2B, as the package size of IC 100 decreases, the spacing and width above the lower metal lines 116U(1), 116U(2) and the upper metal lines 116O(1), 116O(2) may also need to be reduced. This will result in increased contact resistance because the dimensions of the first connection region 200(1) and the second connection region 200(2) will also decrease. Therefore, the number and size of vias 122(1), 122(2) that can be formed in the first connection region 200(1) and the second connection region 200(2) will decrease, thereby increasing contact resistance. For example, if the lower metal lines 116U(1), 116U(2) and the upper metal lines 116O(1), 116O(2) are part of the PDN in IC 100, the increase in contact resistance will cause the current resistance (IR) drop to increase in an undesirable manner. As shown in Figure 2A, the presence of via layer 120 in BEOL interconnect structure 104 of IC 100 also contributes to the overall height of BEOL interconnect structure 104, as discussed above regarding Figure 1. As the package size of IC 100 decreases, the height budget of IC 100 can also be reduced.

[0055] Therefore, to reduce or lower the contact resistance between metal lines in the BEOL interconnect structure of the IC, IC 300 in FIG3 is provided. Similar to IC 100 in FIG1, IC 300 in FIG3 includes a die stack 302, which includes a BEOL interconnect structure 304 disposed on a FEOL structure 306. The FEOL structure 306 includes an active semiconductor layer 308 formed on a substrate 310. P-type field-effect transistors (FETs) (PFETs) and N-type (FETs) (NFETs) 312P, 312N are formed in the active semiconductor layer 308. The BEOL interconnect structure 304 includes a plurality of interconnect layers 314(1)-314(4), each interconnect layer including one or more metal lines 316(1)-316(4), which provide interconnection between FETs 312P, 312N and external interconnects 318 (e.g., solder bumps) formed adjacent to the upper interconnect layer 314(4) of the BEOL interconnect structure 304. Metal lines 316(1)-316(4) are made of a metallic material such as copper. Interconnect layers 314(1)-314(4) in the BEOL interconnect structure 304 of IC 300 are also referred to as “metallization layers” in this example. Metal lines 316(1)-316(4) extend longitudinally in the horizontal X-axis or Y-axis direction in FIG3. The BEOL interconnect structure 304 also includes via layers 320(1)-320(3) disposed adjacent to the respective interconnect layers 314(1)-314(3). Vias 322(1)-322(3) (e.g., metal pillars) are formed in via layers 320(1)-320(3) to provide interconnection between metal lines 316(1)-316(3) in adjacent interconnect layers 314(1)-314(3).

[0056] However, unlike the BEOL interconnect structure 104 in Figure 1, the BEOL interconnect structure 304 in Figure 3 does not include a via layer 320(4) between interconnect layers 314(3) and 314(4) in this example. Instead, interconnect layer 314(4) is configured to be adjacent to interconnect layer 314(3) in the vertical direction (Z-axis direction) without an intermediate via layer. As will be discussed in more detail below, the overlay metal line 316(4) in interconnect layer 314(4) is directly coupled to the lower metal line 316(3) in interconnect layer 314(3) in connection region 324(1), and the overlay metal line 316(4) and the lower metal line 316(3) intersect in the X-axis and Y-axis in connection region 324(1). In this way, the overlay metal line 316(4) is connected to the lower metal line 316(3) without the use of vias. The overlay metal line 316(4) is directly coupled to the underlay metal line 316(3) in the connection region 324(1). As a result, the larger surface areas of the overlay metal line 316(4) and the underlay metal line 316(3) can be coupled together to reduce contact resistance. In addition, the total height H3 of the IC 300 in FIG. 3 is reduced compared to the height H1 of the IC 100 in FIG. 1 because the elimination of the via layer between the interconnect layers 314(3) and 314(4) reduces the height H4 of the BEOL interconnect structure 304 compared to the height H2 of the BEOL interconnect structure 104 in FIG. 1.

[0057] To further illustrate the direct coupling between the lower metal line 316U and the upper metal line 316O in IC 300 of Figure 3, Figures 4A and 4B are provided. Figures 4A and 4B are respectively a top view and a cross-sectional side view of the upper interconnect layer 314O in the BEOL interconnect structure 304 of IC 300 of Figure 3, which is adjacent to the lower interconnect layer 314U. Figure 4B is a cross-sectional side view through the A2-A2' section line in Figure 4A. As shown in Figure 4B, the upper interconnect layer 314O and the lower interconnect layer 314U can be adjacent interconnect layers 314(3) and 314(4) in the BEOL interconnect structure 304 of Figure 3. In this example, "upper" and "lower" indicate that the upper interconnect layer 314O is positioned above the lower interconnect layer 314U in the Z-axis direction in Figures 4A and 4B. As shown in Figure 4A, a first lower metal line 316U(1) and a second lower metal line 316U(2) are disposed in a lower interconnect layer 314U. Each of the first lower metal line 316U(1) and the second lower metal line 316U(2) extends parallel to each other along the corresponding longitudinal axes LA5 and LA6 in the horizontal direction of the Y-axis. Also as shown in Figure 4A, a first upper metal line 316O(1) and a second upper metal line 316O(2) are disposed in an upper interconnect layer 314O. Each of the first upper metal line 316O(1) and the second upper metal line 316O(2) extends parallel to each other and orthogonal to the longitudinal axes LA5 and LA6 in the horizontal direction of the X-axis along the corresponding longitudinal axes LA7 and LA8. The first lower metal line 316U(1) and the second lower metal line 316U(2) extend in the longitudinal axes LA5 and LA6.

[0058] As shown in Figure 4B, in this example, to interconnect the first lower metal line 316U(1) to the first upper metal line 316O(1), the first upper metal line 316O(1) is configured to directly contact the first lower metal line 316U(1). This is because the upper interconnect layer 314O is disposed on the lower interconnect layer 314U in the BEOL interconnect structure 304 without using an intermediate via layer. The first upper metal line 316O(1) is directly coupled to the first lower metal line 316U(1) in the first connection region 400(1), where the first upper metal line 316O(1) and the first lower metal line 316U(1) intersect in the horizontal X-axis and Y-axis directions. For example, the first lower metal line 316U(1) and the first upper metal line 316O(1) can be electrically coupled together as part of the positive power rail in the PDN of IC 300 in Figure 3 for routing power supply voltage. Similarly, as shown in Figure 4A, the second overlay metal line 316O(2) is directly coupled to the second underlay metal line 316U(2) in the second connection region 400(2), where the second overlay metal line 316O(2) and the second underlay metal line 316U(2) intersect in the horizontal X-axis and Y-axis directions. For example, the second underlay metal line 316U(2) and the second overlay metal line 316O(2) can be electrically coupled together as part of the ground or negative power rail in the PDN of IC 300 in Figure 3.

[0059] As shown in Figure 4A, the first upper metal line 316O(1) also intersects with the second lower metal line 316U(2) in the third connection region 400(3). However, it may not be desirable to electrically couple (i.e., short-circuit) the first upper metal line 316O(1) to the second lower metal line 316U(2). For example, the first upper metal line 316O(1) may be a positive power rail, and the second lower metal line 316U(2) may be a ground or negative power rail that cannot be short-circuited. Similarly, as shown in Figure 4A, the second upper metal line 316O(2) also intersects with the first lower metal line 316U(1) in the fourth connection region 400(4). It may also not be desirable to electrically couple (i.e., short-circuit) the second upper metal line 316O(2) to the first lower metal line 316U(1). For example, the second overlay metal line 316O(2) can be a ground or negative power rail, and the first lower metal line 316U(1) can be a positive power rail that cannot be short-circuited. Because the intermediate via layer between the overlay interconnect layer 314O and the lower interconnect layer 314U is eliminated, if isolation is not provided, the first overlay metal line 316O(1) and the second lower metal line 316U(2), as well as the second overlay metal line 316O(2) and the first lower metal line 316U(1), will be in direct contact with each other, resulting in a short circuit.

[0060] In this respect, as shown in Figures 4A and 4B, the BEOL interconnect structure 304 includes a first insulating layer 402(1) disposed in the third connection region 400(3) between the first overlay metal line 316O(1) and the second lower layer metal line 316U(2). The first insulating layer 402(1) is formed of a dielectric material. As shown in Figure 4A, the BEOL interconnect structure 304 also includes a second insulating layer 402(2) disposed in the fourth connection region 400(4) between the second overlay metal line 316O(2) and the first lower layer metal line 316U(1). In this example, as shown in Figure 4B, the first insulating layer 402(1) is disposed in the third connection region 400(3) in a first recess 404(1) in the first overlay metal line 316O(1), adjacent to the third connection region 400(3). The first insulating layer 402(1) is a dielectric material. The first insulating layer 402(1) isolates and insulates the second lower metal line 316U(2) from the first upper metal line 316O(1) to avoid electrical connection between the second lower metal line 316U(2) and the first upper metal line 316O(1). By providing a first recess 404(1) in the first upper metal line 316O(1) in the third connection region 400(3), it is not necessary to provide an additional insulating material layer between the entire interface between the upper interconnect layer 314O and the lower interconnect layer 314U, which will contribute to the height H4 in the BEOL interconnect structure 304 in FIG3.

[0061] Similarly, as shown in Figure 4B, in this example, a first overlay metal line 316O(1) is disposed on a thin first metal barrier layer 406(1), which is disposed on a lower interconnect layer 314U. For example, the first metal barrier layer 406(1) may be, for example, tantalum nitride. The first metal barrier layer 406(1) provides a direct electrical connection between the first overlay metal line 316O(1) and the first lower metal line 316U(1), while also providing a barrier layer that can reduce or prevent the metal material 408 of the first overlay metal line 316O(1) from diffusing into the lower interconnect layer 314U during manufacturing processes where the temperature is sufficient to cause metal diffusion. For example, in this example, the lower interconnect layer 314U includes a dielectric material 410 in which the lower metal lines 316U(1) and 316U(2) are formed to insulate and isolate the lower metal lines 316U(1) and 316U(2). If the metal material 408 from the first overlay metal line 316O(1) diffuses into the dielectric material 410 of the lower interconnect layer 314U, the diffused metal may cause an unintended short circuit with the lower metal line 316U, such as between the first overlay metal line 316O(1) and the second lower metal line 316U(1) in this example.

[0062] Furthermore, although not directly shown in FIG4B, but shown in the top view of FIG4A, a second insulating layer 402(2) is also provided in a second recess 404(2) adjacent to the fourth connection region 400(4) in the second overlay metal wire 316O(2). The second insulating layer 402(2) is formed of a dielectric material. The second insulating layer 402(2) isolates and insulates the first lower metal wire 316U(1) from the second overlay metal wire 316O(2) to avoid electrical connection between the first lower metal wire 316U(1) and the second overlay metal wire 316O(2). The details of the first recess 404(1) in the first overlay metal wire 316O(1) discussed above with respect to FIG4B also apply to the second recess 404(2) provided in the second overlay metal wire 316O(2). Furthermore, although not directly shown in Figures 4A and 4B, in this example, the second overlay metal line 316O(2) is disposed on a thin metal barrier layer, such as the first metal barrier layer 406(1) disposed on the lower interconnect layer 314U. The thin metal barrier layer provides a direct electrical connection between the second overlay metal line 316O(2) and the second lower metal line 316U(2), while also providing a barrier layer that can reduce or prevent the metal material of the second overlay metal line 316O(2) from diffusing into the lower interconnect layer 314U during manufacturing processes in which the temperature is sufficient to cause metal diffusion. As described above, in this example, the lower interconnect layer 314U includes a dielectric material 410 in which the lower metal lines 316U(1) and 316U(2) are formed, to insulate and isolate the lower metal lines 316U(1) and 316U(2). If the metal material from the second overlay metal line 316O(2) diffuses into the dielectric material 410 of the lower interconnect layer 314U, the diffused metal may cause an unintended short circuit with the lower metal line 316U, such as between the second overlay metal line 316O(2) and the first lower metal line 316U(1) in this example.

[0063] As discussed above regarding the BEOL interconnect structure 304 in Figures 4A and 4B, a first insulating layer 402(1) and a second insulating layer 402(2) are disposed in the first recess 404(1) and the second recess 404(2) in the corresponding first overlay metal line 316O(1) and the second overlay metal line 316O(2). However, there is an alternative way to insulate the first overlay metal line 316O(1) and the second overlay metal line 316O(2) from the corresponding second underlay metal line 316U(2) and the first underlay metal line 316U(1). In this regard, Figures 5A and 5B show a top view and a cross-sectional side view of the BEOL interconnect structure 504, which can be provided as the BEOL interconnect structure 304 in the IC 300 in Figure 3. Figure 5B is a cross-sectional side view through the section line A3-A3' in Figure 5A. As shown in Figures 5A and 5B discussed below, insulation between the selected lower metal wire and the upper metal wire is provided by providing an extended recess in the upper metal wire that extends beyond the connection area where a connection is formed between the upper metal wire and the lower metal wire.

[0064] In this respect, Figures 5A and 5B are respectively a top view and a cross-sectional side view of the overlay interconnect layer 514O adjacent to the lower interconnect layer 514U in the Z-axis direction of the BEOL interconnect structure 504 in IC 500. IC 500 can be similar to IC 300 in Figure 3. Figure 5B is a cross-sectional side view through the section line A3-A3' in Figure 5A. For example, the overlay interconnect layer 514O and the lower interconnect layer 514U can be adjacent interconnect layers 314(3) and 314(4) in the BEOL interconnect structure 304 in IC 300 in Figure 3. In this example, "overlay" and "lower layer" mean that the overlay interconnect layer 514O is disposed above the lower interconnect layer 514U in the Z-axis direction in Figures 5A and 5B. As shown in Figure 5A, a first lower metal line 516U(1) and a second lower metal line 516U(2) are disposed in a lower interconnect layer 514U. Each of the first lower metal line 516U(1) and the second lower metal line 516U(2) extends parallel to each other along the corresponding longitudinal axes LA9 and LA10 in the horizontal direction of the Y-axis. Also as shown in Figure 5A, a first upper metal line 516O(1) and a second upper metal line 516O(2) are disposed in an upper interconnect layer 514O. Each of the first upper metal line 516O(1) and the second upper metal line 516O(2) extends parallel to each other and orthogonal to the longitudinal axes LA9 and LA10 in the horizontal direction of the X-axis along the corresponding longitudinal axes LA11 and LA12, wherein the first lower metal line 516U(1) and the second lower metal line 516U(2) extend in the longitudinal axes LA9 and LA10.

[0065] As shown in Figure 5B, in this example, to interconnect the first lower metal line 516U(1) to the first upper metal line 516O(1), the first upper metal line 516O(1) is configured to directly contact the first lower metal line 516U(1). This is because the upper interconnect layer 514O is disposed on the lower interconnect layer 514U in the BEOL interconnect structure 504 without using an intermediate via layer. The first upper metal line 516O(1) is directly coupled to the first lower metal line 516U(1) in the first connection region 526(1), in which the first upper metal line 516O(1) and the first lower metal line 516U(1) intersect in the horizontal X-axis and Y-axis directions. For example, the first lower metal line 516U(1) and the first upper metal line 516O(1) can be electrically coupled together as part of the positive power rail in the PDN of IC 500 for routing power supply voltage. Similarly, as shown in Figure 5A, the second overlay metal line 516O(2) is directly coupled to the second underlay metal line 516U(2) in the second connection region 526(2), where the second overlay metal line 516O(2) and the second underlay metal line 516U(2) intersect in the horizontal X-axis and Y-axis directions. For example, the second underlay metal line 516U(2) and the second overlay metal line 516O(2) can be electrically coupled together as part of the ground or negative power rail in the PDN of IC 500.

[0066] As shown in Figure 5A, the first overlay metal line 516O(1) also intersects with the second lower metal line 516U(2) in the third connection region 526(3). However, it may be undesirable to electrically couple (i.e., short-circuit) the first overlay metal line 516O(1) to the second lower metal line 516U(2). For example, the first overlay metal line 516O(1) may be a positive power rail, and the second lower metal line 516U(2) may be a ground or negative power rail that cannot be short-circuited. Similarly, as shown in Figure 5A, the second overlay metal line 516O(2) also intersects with the first lower metal line 516U(1) in the fourth connection region 526(4). It may also be undesirable to electrically couple (i.e., short-circuit) the second overlay metal line 516O(2) to the first lower metal line 516U(1). For example, the second overlay metal line 516O(1) can be a ground or negative power rail, and the first lower metal line 516U(1) can be a positive power rail that cannot be short-circuited. Because the intermediate via layer between the overlay interconnect layer 514O and the lower interconnect layer 514U is eliminated, if isolation is not provided, the first overlay metal line 516O(1) and the second lower metal line 516U(2), as well as the second overlay metal line 516O(2) and the first lower metal line 516U(1), will be in direct contact with each other, resulting in a short circuit.

[0067] In this respect, as shown in FIG5A, the BEOL interconnect structure 504 includes an insulating layer 530 disposed between and above the entire overlay interconnect layer 514O and the lower interconnect layer 514U. The insulating layer 530 is formed of a dielectric material. However, unlike the BEOL interconnect structure 304 in FIG4A and FIG4B, in the example BEOL interconnect structure 504 in FIG5A and FIG5B, the insulating layer 530 is patterned and removed (e.g., etched away) at the intersection between the first overlay metal line 516O (1) and the first lower metal line 516U (1) and the second overlay metal line 516O (2) and the second lower metal line 516U (2) in the first connection region 526 (1) and the second connection region 526 (2). This actually creates a first recess 532(1) in the first overlay metal line 516O(1) and the second overlay metal line 516O(2) outside the corresponding first connection region 526(1) and second connection region 526(2). As shown in FIG5B, for the first overlay metal line 516O(1), due to the patterning and removal of a portion of the insulating layer 530 in the first connection region 526(1), a first opening 534(1) (also referred to as a "groove") is created in the insulating layer 530, which extends to the first surface 536(1) of the first lower layer metal line 516U(1). The first opening 534(1) is filled with a metal material 538(1) which forms the first overlay metal line 516O(1) in the overlay interconnect layer 514O. In this way, the metal material 538(1) of the first overlay metal line 516O(1) is configured to contact the first lower metal line 516U(1), while the remainder of the insulating layer 530 remains in the third connection region 526(3) to insulate and isolate the first overlay metal line 516O(1) from the second lower metal line 516U(2). By providing a first recess 532(1) in the first connection region 526(1) in the first overlay metal line 516O(1), it is not necessary to have an additional insulating material layer on the entire interface between the overlay interconnect layer 514O and the lower interconnect layer 514U, which would contribute to the height of the BEOL interconnect structure 504 in Figures 5A and 5B.

[0068] Similarly, as shown in FIG5B, in this example, a first overlay metal line 516O(1) is disposed on a first thin metal barrier layer 540(1), which is disposed on a lower interconnect layer 514U. For example, the first thin metal barrier layer 540(1) may be, for example, tantalum nitride. The first thin metal barrier layer 540(1) provides a direct electrical connection between the first overlay metal line 516O(1) and the first lower metal line 516U(1), while also providing a barrier layer that can reduce or prevent the metal material 538(1) of the first overlay metal line 516O(1) from diffusing into the lower interconnect layer 514U during a manufacturing process in which the temperature is sufficient to cause metal diffusion. For example, in this example, the lower interconnect layer 514U includes a dielectric material 542 in which the lower metal lines 516U(1) and 516U(2) are formed to insulate and isolate the lower metal lines 516U(1) and 516U(2). If the metal material from the first overlay metal line 516O(1) diffuses into the dielectric material 542 of the lower interconnect layer 514U, the diffused metal may cause an unintended short circuit with the lower metal line 516U, such as between the first overlay metal line 516O(1) and the second lower metal line 516U(2) in this example.

[0069] Furthermore, although not directly shown in FIG5B, but shown in the top view of FIG5A, the insulating layer 530 is also patterned and removed (e.g., etched away) between the second overlay metal line 516O (2) and the second underlay metal line 516U (2) in the second connection region 526 (2). This effectively creates a second recess 532 (2) in the first overlay metal line 516O (1) and the second overlay metal line 516O (2) outside the second connection region 526 (2). Although not shown in FIG5B, the second opening 534 (2) extending to the first surface of the second underlay metal line 516U (2) created in the insulating layer 530 due to the patterning and removal of a portion of the insulating layer 530 in the second connection region 526 (2) is filled with a metallic material. The metallic material forms the second overlay metal line 516O (2) in the overlay interconnect layer 514O. In this way, the metal material of the second overlay metal line 516O(2) is configured to contact the second lower layer metal line 516U(2), while the remainder of the insulating layer 530 remains in the fourth connection region 526(4) to insulate and isolate the second overlay metal line 516O(2) from the first lower layer metal line 516U(1). By providing a second recess 532(2) in the second connection region 526(2) in the second overlay metal line 516O(2), it is not necessary to have an additional insulating material layer on the entire interface between the overlay interconnect layer 514O and the lower interconnect layer 514U, which would increase the height of the BEOL interconnect structure 504 in Figures 5A and 5B.

[0070] Furthermore, although not shown in Figure 5B, in this example, a second overlay metal line 516O(2) is disposed on a second thin metal barrier layer, such as a first thin metal barrier layer 540(1), which is disposed on a lower interconnect layer 514U. For example, the second metal barrier layer may be, for example, tantalum nitride. The second thin metal barrier layer provides a direct electrical connection between the second overlay metal line 516O(2) and the second lower metal line 516U(2), while also providing a barrier layer that can reduce or prevent the metal material of the second overlay metal line 516O(2) from diffusing into the lower interconnect layer 514U during a manufacturing process in which the temperature is sufficient to cause metal diffusion. For example, in this example, the lower interconnect layer 514U includes a dielectric material 542 in which the lower metal lines 516U(1), 516U(2) are formed to insulate and isolate the lower metal lines 516U(1), 516U(2). If the metal material from the second overlay metal line 516O(2) diffuses into the dielectric material 542 of the lower interconnect layer 514U, the diffused metal may cause an unintended short circuit with the lower metal line 516U, such as between the second overlay metal line 516O(2) and the first lower metal line 516U(1) in this example.

[0071] Figure 6 is a flowchart illustrating an exemplary manufacturing process 600 for an IC, which includes adjacent upper and lower interconnect layers without intermediate via layers, wherein upper metal lines in the upper interconnect layer are directly coupled to lower metal lines in selected connection regions, including but not limited to ICs 300 and 500 in Figures 4A-5B. The exemplary manufacturing process step 600 in Figure 6 will be described with respect to the exemplary ICs 300 and 500 in Figures 4A-5B.

[0072] In this respect, the first step in manufacturing process 600 may be the formation of lower interconnect layers 314U, 514U (block 602 in FIG. 6). This process of forming the lower interconnect layers 314U, 514U (block 602 in FIG. 6) may involve forming first lower metal lines 316U(1), 516U(1) extending in a first horizontal direction (X-axis direction) (block 604 in FIG. 6), and forming second lower metal lines 316U(2), 516U(2) extending in a second horizontal direction (X-axis direction) parallel to the first horizontal direction (X-axis direction) (block 606 in FIG. 6). The next step in manufacturing process 600 may include forming overlay interconnect layers 314O, 514O on the lower interconnect layers 314U, 514U in a vertical direction (Z-axis direction) (block 608 in FIG. 6). The process of forming overlay interconnect layers 314O and 514O on the lower interconnect layers 314U and 514U (block 608 in FIG. 6) may involve forming a first insulating layer 402(1) and 530 (block 610 in FIG. 6) between the first overlay metal lines 316O(1) and 516O(1) and the second lower metal lines 316U(2) and 516U(2) in the second connection regions 400(2) and 526(2). The process of forming overlay interconnect layers 314O and 514O on the lower interconnect layers 314U and 514U (block 608 in FIG. 6) may also involve forming first overlay metal lines 316O(1) and 516O(1) in the overlay interconnect layers 314O and 514O that extend in a third horizontal direction (Y-axis direction) orthogonal to the first horizontal direction (X-axis direction), intersecting with the first lower metal lines 316U(1) and 516U(1) in the vertical direction (Z-axis) in the first connection regions 400(1) and 526(1), and intersecting with the second lower metal lines 316U(2) and 516U(2) in the vertical direction (Z-axis direction) in the second connection regions 400(2) and 526(2) (block 612 in FIG. 6). The process of forming overlay interconnect layers 314O and 514O on the lower interconnect layers 314U and 514U (block 608 in FIG6) may also involve coupling the first overlay metal lines 316O (1) and 516O (1) to the first lower metal lines 316U (1) and 516U (1) in the first connection regions 400 (1) and 526 (1) (block 614 in FIG6).

[0073] Other manufacturing processes can also be used to manufacture ICs including adjacent top and bottom interconnect layers without intermediate via layers, wherein the top metal lines in the top interconnect layer are directly coupled to the bottom metal lines in selected connection regions, including but not limited to ICs 300 and 500 in Figures 4A-5B. For example, Figures 7A-7B-1 are flowcharts illustrating another exemplary manufacturing process 700-1 for manufacturing an IC, which includes adjacent top and bottom interconnect layers without intermediate via layers, wherein the top metal lines in the top interconnect layer are directly coupled to the bottom metal lines in selected connection regions, and the IC also includes an insulating layer disposed in recesses in other connection regions to insulate and isolate the first and second top metal lines from the corresponding second and first bottom metal lines, as shown in IC 300 in Figures 4A and 4B. Figures 8A-8E-1 illustrate exemplary manufacturing stages 800A-800E-1 in manufacturing process 700-1 in Figures 7A-7B-1. The exemplary manufacturing process 700(-1) step in Figure 7B-1 will be discussed in conjunction with the exemplary manufacturing stages 800A-800E-1 in Figures 8A-8E-1 of IC 300 in Figures 4A and 4B.

[0074] In this respect, as shown in manufacturing stage 800A of FIG8A, the first step in the manufacturing process 700 for manufacturing the BEOL interconnect structure 304 in FIG4A and FIG4B is to form a first dielectric layer 801 of dielectric material 410 (block 702 in FIG7A). Furthermore, as shown in manufacturing stage 800A of FIG8A, another step in the manufacturing process 700 for manufacturing the BEOL interconnect structure 304 is to form a first lower metal line 316U (1) in the first dielectric layer 801 in a first horizontal direction (Y-axis direction). The first dielectric layer 801 can be made of silicon nitride (SiN), for example. Similarly, as shown in manufacturing stage 800A of FIG8A, another step in the manufacturing process 700 for manufacturing the BEOL interconnect structure 304 is to form a second lower metal line 316U (2) in the first dielectric layer 801 in a second horizontal direction (Y-axis direction) parallel to the first horizontal direction (block 702 in FIG7A). Similarly, as shown in manufacturing stage 800A in Figure 8A, another step in the manufacturing process 700 of manufacturing the BEOL interconnect structure 304 is to polish the first surface 802 of the first dielectric layer 801 to expose the first surface 804(1) of the first lower metal line 316U(1) and the first surface 804(2) of the second lower metal line 316U(2) from the first dielectric layer 801.

[0075] Similarly, as shown in manufacturing stage 800B of FIG8B, another step in the manufacturing process 700 of manufacturing the BEOL interconnect structure 304 is to form a first insulating layer 402(1) (or insulating layer 530 with respect to the BEOL interconnect structure 504 in FIG5A and FIG5B) (block 704 in FIG7A) on the first surface 802 of the first dielectric layer 801, the first surface 804(1) of the first lower metal line 316U(1), and the first surface 804(2) of the second lower metal line 316U(2). The first lower interconnect layer 314U is formed as shown in manufacturing stage 800B of FIG8B.

[0076] The manufacturing stages 800C-1-800E-1 described in process 700-1 of Figures 8C-1-8E-1 and 7B-1 apply to the manufacturing of the BEOL interconnect structure 304 in Figures 3-4B. At this point, as shown in manufacturing stage 800C-1 of Figure 8C-1, another step in the manufacturing process 700 for manufacturing the BEOL interconnect structure 304 is to pattern the first insulating layer 402(1) to form an opening 806 (block 706 in Figure 7B) in the first insulating layer 402(1) outside the second connection region 400(2). A portion of the first insulating layer 402(1) in the opening 806 outside the second connection region 400(2) remains in the second connection region 400(2) of the second lower metal line 316U(2) to provide final isolation and insulation for the first overlay metal line to be disposed on the lower interconnect layer 314U (block 706-1 in Figure 7B-1). Then, as shown in manufacturing stage 800D-1 in Figure 8D-1, another step in the manufacturing process 700-1 of manufacturing the BEOL interconnect structure 304 is to set a first metal barrier layer 406(1) on the first dielectric layer 801, on the first surface 804(1) of the first lower metal line 316U(1), on the first surface 804(2) of the second lower metal line 316U(2) and on the first insulating layer 402(1) (block 708-1 in Figure 7B-1). Then, as shown in manufacturing stage 800E-1 in FIG8D-1, another step in the manufacturing process 700-1 of manufacturing BEOL interconnect structure 304 is to place metal material 808 on the lower interconnect layer 314U, on the first surfaces 804(1), 804(2) of the first lower metal line 316U(1) and the second lower metal line 316U(2), and on the surface 802 of the first insulating layer 402(1) to form the first overlay metal line 316O(1) (block 710-1 in FIG7B-1).

[0077] Process steps 702 and 704 in Figure 7A can be used as common steps in manufacturing any of ICs 300 and 500 in Figures 3-4B and 5A-5B. Process steps 706-2-710-2 shown in manufacturing stages 800C-2-800E-2 in Figures 7B-2 and 8C-2-8E-2 can be used to manufacture IC 500 in Figures 5A and 5B. Process steps 706-2-710-2 shown in manufacturing stages 800C-2-800E-2 in Figures 7B-2 and 8C-2-8E-2 will be discussed with respect to the BEOL interconnect structure 504 in IC 500 in Figures 5A and 5B.

[0078] In this respect, as shown in manufacturing stage 800C-2 of Figure 8C-2, the next step in the manufacturing process 700-2 of the BEOL interconnect structure 504 is to pattern the insulating layer 530 to form an opening 810 in the insulating layer 530 in the first connection region 526(1) (block 706-2 in Figure 7B-2). As shown in manufacturing stage 800C-2 of Figure 8C-2, another step in the manufacturing process 700-2 of the BEOL interconnect structure 504 is to etch a portion 526(1) of the insulating layer 530 in the opening 810 in the first connection region to remove a portion of the insulating layer 530 on the first lower metal line 516U(1) in the first connection region 526(1) (block 706-2 in Figure 7B-2). As shown in manufacturing stage 800D-2 of Figure 8D-2, the next step in the manufacturing process 700-2 of the BEOL interconnect structure 504 is to provide a metal barrier layer 812 on the first dielectric layer 801, on the first surface 804(1) of the first lower metal line 516U(1), and on the insulating layer 530 (block 708-2 in Figure 7B-2). As shown in manufacturing stage 800E-2 of Figure 8E-2, the next step in the manufacturing process 700-2 of the BEOL interconnect structure 504 is to provide a metal material 814 on the first dielectric layer 801 above the insulating layer 530 and in the opening 810 to contact the first lower metal line 516U(1) in the first connection area 526(1) to form a first overlay metal line 516O(1) (block 710-2 in Figure 7B-2). The first upper metal wire 516O(1) is insulated and isolated from the second lower metal wire 516U(2) through the insulation layer 530 outside the first connection area 526(1).

[0079] A top metal line can also be provided in the BEOL interconnect structure of the IC, extending orthogonally from the connection region in the longitudinal direction of the coupled lower metal line to increase the contact area and thus further reduce the contact resistance. This includes adjacent top and lower interconnect layers without intermediate via layers. This is illustrated by example in ICs 900, 1000, and 1100 in Figures 9-11, respectively. The example ICs 900-1100 in Figures 9-11 will be described using the common components of IC 300 in Figures 3-4B as an example; however, note that ICs 900-1100 in Figures 9-11 can also include common components and designs of IC 500 in Figures 5A-5B.

[0080] In this regard, Figure 9 is a top view of another exemplary IC 900, which includes a BEOL interconnect structure 904 similar to the BEOL interconnect structure 304 in Figures 3-4B. In the BEOL interconnect structure 904 in Figure 9, a first overlay interconnect 916O(1) and a second overlay interconnect 916O(2) in the overlay interconnect layer 914O are disposed above and intersect with the first lower layer metal line 916U(1) and the second lower layer metal line 916U(2) in the corresponding connection regions 901(1)-901(4) without intermediate via layers. The first overlay interconnect 916O(1) intersects with the first lower layer interconnect 916U(1) in the first connection region 901(1) and is directly coupled to the first lower layer interconnect 916U(1). The second overlay interconnect 916O(2) intersects with and is directly coupled to the second lower layer interconnect 916U(2) in the second connection region 901(2). The second overlay interconnect 916O(2) intersects with the first lower layer interconnect 916U(1) in the third connection region 901(3), but is isolated by the first insulating layer 902(1). The first overlay interconnect 916O(1) intersects with the second lower layer interconnect 916U(1) in the fourth connection region 901(4), but is isolated by the second insulating layer 902(2). In this example, the first overlay metal line 916O(1) and the second overlay metal line 916O(2) extend in the horizontal X-axis and Y-axis directions to form an enlarged first connection region 901(1) and second connection region 901(2) to increase the contact area between the first underlay metal line 916U(1) and the second underlay metal line 916U(2) beyond the connection regions 901(1) and 901(2) and the corresponding first overlay metal line 916O(1) and second overlay metal line 916O(2), thereby reducing the contact resistance.

[0081] Figure 10 is a top view of another exemplary IC 1000, which includes a BEOL interconnect structure 1004 similar to the BEOL interconnect structure 304 in Figures 3-4B. In the BEOL interconnect structure 1004 in Figure 10, a first overlay interconnect 1016O(1) and a second overlay interconnect 1016O(2) in the overlay interconnect layer 1014O are disposed above and intersect with the first lower layer metal line 1016U(1) and the second lower layer metal line 1016U(2) in the corresponding connection regions 1001(1)-1001(4) without intermediate via layers. The first overlay interconnect 1016O(1) intersects with the first lower layer interconnect 1016U(1) in the first connection region 1001(1) and is directly coupled to the first lower layer interconnect 1016U(1). The second overlay interconnect 1016O(2) intersects with and is directly coupled to the second lower layer interconnect 1016U(2) in the second connection region 1001(2). The second overlay interconnect 1016O(2) intersects with the first lower layer interconnect 1016U(1) in the third connection region 1001(3), but is isolated by the first insulating layer 1002(1). The first overlay interconnect 1016O(1) intersects with the second lower layer interconnect 1016U(1) in the fourth connection region 1001(4), but is isolated by the second insulating layer 1002(2). In this example, the first overlay metal line 1016O(1) and the second overlay metal line 1016O(2) extend in the horizontal X-axis and Y-axis directions and in the horizontal X-axis direction outward from the corresponding connection regions 1001(1) and 1001(2) to form enlarged first connection regions 1001(1) and second connection regions 1001(2) to increase the contact area between the first underlay metal line 1016U(1) and the second underlay metal line 1016U(2) beyond the connection regions 1001(1) and 1001(2) and the corresponding first overlay metal line 1016O(1) and second overlay metal line 1016O(2), thereby reducing the contact resistance.

[0082] Figure 11 is a top view of another exemplary IC 1100, which includes a BEOL interconnect structure 1104 similar to the BEOL interconnect structure 304 in Figures 3-4B. In the BEOL interconnect structure 1104 in Figure 11, a first overlay interconnect line 1116O(1) and a second overlay interconnect line 1116O(2) in the overlay interconnect layer 1114O are disposed above and intersect with the first lower layer metal line 1116U(1) and the second lower layer metal line 1116U(2) in the corresponding connection regions 1101(1)-1101(4) without intermediate via layers. The first overlay interconnect line 1116O(1) intersects with the first lower layer interconnect line 1116U(1) in the first connection region 1101(1) and is directly coupled to the first lower layer interconnect line 1116U(1). The second overlay interconnect 1116O(2) intersects with and is directly coupled to the second lower layer interconnect 1116U(2) in the second connection region 1101(2). The second overlay interconnect 1116O(2) intersects with the first lower layer interconnect 1116U(1) in the third connection region 1101(3), but is isolated by the first insulating layer 1102(1). The first overlay interconnect 1116O(1) intersects with the second lower layer interconnect 1116U(1) in the fourth connection region 1101(4), but is isolated by the second insulating layer 1102(2). In this example, the first overlay metal line 1116O(1) and the second overlay metal line 1116O(2) extend in the horizontal X-axis and Y-axis directions, and extend in the X-axis direction from the corresponding connection regions 1101(1), 1101(2) to form enlarged first connection regions 1101(1) and second connection regions 1101(2) to increase the contact area between the first lower layer metal line 1116U(1) and the second lower layer metal line 1116U(2) beyond the connection regions 1101(1), 1101(2) and the corresponding first overlay metal line 1116O(1) and second overlay metal line 1116O(2), thereby reducing the contact resistance. An example of the above IC is provided in the BEOL interconnect structure, comprising adjacent overlay interconnect layers and lower interconnect layers with direct coupling without intermediate via layers.

[0083] It may be necessary to provide an IC that includes adjacent overlay interconnect layers and underlay interconnect layers directly coupled to the back side of the IC without intermediate via layers. In this regard, FIG12A is a side view of an exemplary IC 1200, which includes an active semiconductor layer 1202 in a FEOL structure 1204 and a BEOL interconnect structure 1206 disposed on the front side 1208 of the FEOL structure 1204. The IC 1200 also includes a back interconnect structure 1210 having adjacent interconnect layers 1212(1)-1212(N) on the back side 1214 of the FEOL structure 1204. FIG12B is another side view of the IC 1200 in FIG12A, showing the back interconnect structure 1210, with the adjacent interconnect layers 1212(1)-1212(N) rotated 180 degrees in the Z-axis direction of the IC 1200 in FIG12A. As shown in FIG12A, a FET 1216 is formed in the active semiconductor layer 1202. As shown in Figures 12A and 12B, the first interconnect layer 1212(1) of the back interconnect structure 1210 is the substrate 1218 of the IC 1200. The substrate 1218 may be a silicon substrate. The back metal contact 1220 of the FET 1216 contacts the back metal line 1222 in the interconnect layer 1212(2) to allow signal routing in the Z-axis direction from the back 1214 of the FEOL structure 1204 below the substrate 1218, which serves as the first interconnect layer 1212(1). For example, the back metal line 1222 may be electrically coupled to a power rail configured to deliver power signals from a power source to the source S of the FET 1216 via the back metal line 1222 and the back metal contact 1220.

[0084] As shown in Figure 12B, the back interconnect structure 1210 includes back metal lines 1222(1) and 1222(2) as buried metal lines in the substrate 1218. As shown in Figure 12B, it is assumed that the back interconnect structure 1210 includes only three (3) interconnect layers 1212(1)-1212(3), with interconnect layer 1212(3) serving as the overlay interconnect layer 1224O. Interconnect layer 1212(2) serves as the lower interconnect layer 1224U adjacent to the overlay interconnect layer 1224O. The overlay interconnect layer 1224O and the lower interconnect layer 1224U serve as adjacent interconnect layers 1212(2) and 1213(3) in the back interconnect structure 1210 in Figure 12B. In this example, "overlay" and "lower layer" indicate that the overlay interconnect layer 1224O is disposed above the lower interconnect layer 1224U in the Z-axis direction in Figure 12B. As shown in Figure 12B, a first lower metal line 1222U(1) and a second lower metal line 1222U(2) are disposed in a lower interconnect layer 1224U. Each of the first lower metal line 1222U(1) and the second lower metal line 1222U(2) extends parallel to each other along the corresponding longitudinal axes LA13 and LA14 in the horizontal direction of the Y-axis. Also as shown in Figure 12B, a first overlay metal line 1222O(1) is disposed in the overlay interconnect layer 1224O, extending along the corresponding longitudinal axis LA15 in the horizontal direction of the X-axis and orthogonal to the longitudinal axes LA13 and LA14 in which the first lower metal line 1222U(1) and the second lower metal line 1222U(2) extend.

[0085] As further shown in Figure 12B, in this example, in order to interconnect the first lower metal line 1222U(1) to the first upper metal line 1222O(1), the first upper metal line 1222O(1) is configured to be in direct contact with the first lower metal line 1222U(1). This is because the upper interconnect layer 1224O is disposed on the lower interconnect layer 1224U in the back interconnect structure 1210 without using an intermediate via layer. The first upper metal line 1222O(1) intersects the first lower metal line 1222U(1) in the horizontal X-axis direction. The first upper metal line 1222O(1) is directly coupled to the first lower metal line 1222U(1) in the first connection region 1230(1), in which the first upper metal line 1222O(1) and the first lower metal line 1222U(1) intersect in the horizontal X-axis and Y-axis directions. For example, the first lower metal line 1222U(1) and the first upper metal line 1222O(1) can be electrically coupled together as part of a positive power rail in the PDN of IC 1200 in FIG. 12 for routing power supply voltage. As another example, the first lower metal line 1222U(1) and the first upper metal line 1222O(1) can be electrically coupled together as part of a ground or negative power rail in the PDN of IC 1200. Note that although not shown directly in FIG. 12B, the upper interconnect layer 1224O may also include a second upper metal line, which is not shown and is directly coupled to the second lower metal line 1222U(2) in a second connection region, in which the second upper metal line and the second lower metal line 1222U(2) intersect in the horizontal X-axis and Y-axis directions.

[0086] As shown in Figure 12B, the first overlay metal line 1222O(1) also intersects with the second lower metal line 1222U(2) in the third connection region 1230(3). However, it may be undesirable to electrically couple (i.e., short-circuit) the first overlay metal line 1222O(1) to the second lower metal line 1222U(2). For example, the first overlay metal line 1222O(1) may be a positive power rail, and the second lower metal line 1222U(2) may be a ground or negative power rail that cannot be short-circuited. Because the intermediate via layer between the overlay interconnect layer 1224O and the lower interconnect layer 1224U is eliminated, if isolation is not provided, the first overlay metal line 1222O(1) and the second lower metal line 1222U(2) will be set to be in direct contact with each other, resulting in a short circuit. In this respect, as shown in FIG12B, the back-side interconnect structure 1210 includes a first insulating layer 1232(1) disposed in the third connection region 1230(3) between the overlying metal line 1222O(1) and the second lower metal line 1222U(2). The first insulating layer 1232(1) is formed of a dielectric material. In this example, the first insulating layer 1232(1) is disposed in a first recess 1234(1) adjacent to the third connection region 1230(3) in the first overlying metal line 1222O(1). The first insulating layer 1232(1) isolates and insulates the second lower metal line 1222U(2) from the first overlying metal line 1222O(1) to avoid electrical connection between the second lower metal line 1222U(2) and the first overlying metal line 1222O(1). By providing a first recess 1234(1) in the second lower metal line 1222U(2) in the third connection region 1230(3), it is not necessary to have an additional insulating material layer on the entire interface between the overlay interconnect layer 1224O and the lower interconnect layer 1224U. An additional insulating material layer would increase the height (in the Z-axis direction) of the back interconnect structure 1210 in FIG12B, and thus contribute to the total height (in the Z-axis direction) of IC 1200.

[0087] Similarly, as shown in Figure 12B, in this example, a first overlay metal line 1222O(1) is disposed on a thin metal barrier layer 1236(1), which is disposed on a lower interconnect layer 1224U. For example, the thin metal barrier layer 1236(1) may be tantalum nitride. The thin metal barrier layer 1236(1) provides a direct electrical connection between the first overlay metal line 1222O(1) and the first lower metal line 1222U(1), while also providing a barrier layer that can reduce or prevent the metal material of the first overlay metal line 1222O(1) from diffusing into the lower interconnect layer 1224U during manufacturing processes in which the temperature is sufficient to cause metal diffusion. For example, in this example, the lower interconnect layer 1224U includes a dielectric material 1238 in which the lower metal lines 1222U(1) and 1222U(2) are formed to insulate and isolate the lower metal lines 1222U(1) and 1222U(2). If the metal material from the first overlay metal line 1222O(1) diffuses into the dielectric material 1238 of the lower interconnect layer 1224U, the diffused metal may cause an unintended short circuit with the lower metal line 1222U, such as between the first overlay metal line 1222O(1) and the second lower metal line 1222U(2) in this example.

[0088] Furthermore, although not shown directly in FIG12B, note that a second insulating layer is also disposed in a second recess in the first lower metal wire 1222U(1) adjacent to another fourth connection region (similar to the first insulating layer 402(1) in the first recess 404(1)). The second insulating layer is formed of a dielectric material. The second insulating layer isolates and insulates the first lower metal wire 1222U(1) from the second upper metal wire formed in the upper interconnect layer 1224O to avoid electrical connection between the first lower metal wire 1222U(1) and the second upper metal wire. The details regarding the first recess 1234(1) in the first upper metal wire 1222O(1) shown in FIG12B also apply to the second recess in the second upper metal wire. Furthermore, although not shown directly in FIG12B, in this example, the second upper metal wire is disposed on a thin metal barrier layer, such as the first metal barrier layer 406(1) disposed on the lower interconnect layer 1224U. The thin metal barrier layer provides a direct electrical connection between the second overlay metal line 1222O(2) and the second lower metal line 1222U(2), while also providing a barrier layer that can reduce or prevent the metal material of the second overlay metal line from diffusing into the lower interconnect layer 1224U during manufacturing processes where the temperature is sufficient to cause metal diffusion.

[0089] The IC 1200 in Figures 12A and 12B can be manufactured according to the exemplary manufacturing process 600 described above with respect to Figure 6. Other manufacturing processes can also be used to manufacture the IC 1200, which includes adjacent overlay interconnect layers and lower interconnect layers without intermediate via layers in a back-side interconnect structure, wherein overlay metal lines in the overlay interconnect layer are directly coupled to lower metal lines in selected connection regions. For example, Figures 13A and 13B are flowcharts illustrating another exemplary manufacturing process 1300 for manufacturing the IC 1200 in Figures 12A and 12B. Figures 14A-14E illustrate exemplary manufacturing stages 1400A-1400E in the manufacturing process 1300 in Figures 13A and 13B. The exemplary manufacturing process 1300 in Figures 13A and 13B will be discussed with reference to the IC 1200 in Figures 12A and 12B in conjunction with the exemplary manufacturing stages 1400A-1400E in Figures 14A-14E.

[0090] In this respect, as shown in manufacturing stage 1400A of FIG14A, the first step in manufacturing process 1300 for manufacturing the back interconnect structure 1210 in FIG12A and FIG12B is to form a first lower metal line 1222U(1) extending in a first horizontal direction (Y-axis direction) in the substrate 1218 of the FEOL structure 1204 as the lower interconnect layer 1224U(1) ​​in the back interconnect structure 1210 (block 1302 in FIG13A). Similarly, as shown in manufacturing stage 1400A of FIG14A, manufacturing process 1300 includes forming a second lower metal line 1222U(2) in the substrate 1218, which extends in a second horizontal direction (Y-axis direction) parallel to the first horizontal direction (Y-axis direction) in the lower interconnect layer 1224U(1) ​​of the back interconnect structure 1210 (block 1302 in FIG13A). As shown in manufacturing stage 1400B in FIG14B, manufacturing process 1300 includes: grinding the top surface 1402 of substrate 1218 in FIG14A to a second surface 1403 (FIG14B) from the top surface 1402 of substrate 1218 to expose the first surface 1404(1) of the first lower metal line 1222U(1) and the first surface 1404(2) of the second lower metal line 1222U(2) (block 1304 in FIG13A).

[0091] As shown in manufacturing stage 1400C in FIG14C, manufacturing process 1300 further includes recessing the second surface 1403 of the substrate 1218 of the lower interconnect layer 1224U downward into the third surface 1406 of the substrate 1218 to prepare for the deposition of a dielectric layer to isolate the first overlay metal line 1222O(1) to be disposed on the substrate 1218 from the substrate 1218 (block 1306 in FIG13A). Similarly, as shown in manufacturing stage 1400D in FIG14D, manufacturing process 1300 further includes disposing a dielectric layer 1408 on the third surface 1406 of the substrate 1218 and adjacent to the first lower metal line 1222U(1) and the second lower metal line 1222U(2) (block 1308 in FIG13B). Similarly, as shown in manufacturing stage 1400D in FIG14D, manufacturing process 1300 also includes forming the first overlay metal line 1222O(1) (block 1310 in FIG13B) in the overlay metal layer 1224O on the first surfaces 1404(1) and 1404(2) of the dielectric layer 1408 and the first underlay metal line 1222U(1) and the second underlay metal line 1222U(2). The first upper metal line 1222O(1) is configured to extend in a horizontal direction (X-axis direction) orthogonal to the horizontal direction (Y-axis direction) of the first lower metal line 1222U(1) and the second lower metal line 1222U(2), such that the first upper metal line 1222O(1) intersects the first lower metal line 1222U(1) and the second lower metal line 1222U(2) in the vertical direction (Z-axis direction) in the corresponding first connection region 1230(1) and third connection region 1230(3). After the dielectric layer 1408 is patterned to form a first insulating layer 1232(1) on the second lower metal line 1222U(2) in the third connection region 1230(3), the first lower metal line 1222U(1) is disposed on the dielectric layer 1408. This therefore provides a first recess 1234(1) in the first overlay metal wire 1222O(1) such that the first insulating layer 1232(1) insulates and isolates the first overlay metal wire 1222O(1) from the second underlay metal wire 1222U(2).

[0092] As discussed above regarding the back interconnect structure 1210 in IC 1200 in Figures 12A and 12B, a first insulating layer 1232(1) is disposed in a first recess 1234(1) in the corresponding first overlay metal line 1222O(1). However, there are alternatives that provide insulation between the first overlay metal line 1222O(1) and the corresponding second lower metal line 1222U(2) and the first lower metal line 1222U(1). In this regard, Figure 15 is a side view of an alternative back interconnect structure 1510 that can be provided in IC 1500, similar to the back interconnect structure 1210 in IC 1200 in Figures 12A and 12B. As shown in Figure 15, in the back interconnect structure 1510 of IC 1500, the overlay interconnect layer 1524O and the lower interconnect layer 1524U are adjacent in the Z-axis direction. IC 1500 can be similar to IC 300 in Figure 3. A first lower metal line 1522U(1) and a second lower metal line 1522U(2) are disposed in a lower interconnect layer 1524U. Each of the first lower metal line 1522U(1) and the second lower metal line 1522U(2) extends parallel to each other in the horizontal direction of the Y-axis along the corresponding longitudinal axes LA16 and LA17. The first lower metal line 1522U(1) and the second lower metal line 1522U(2) may be metal lines buried in the substrate 1518 as part of the lower interconnect layer 1524U. Also as shown in FIG15, a first upper metal line 1522O(1) is disposed in the upper interconnect layer 1524O. The first upper metal line 1522O(1) extends along the longitudinal axis LA18 in the horizontal direction of the X-axis, which is orthogonal to the longitudinal axes LA16 and LA17 extending from the first lower metal line 1522U(1) and the second lower metal line 1522U(2).

[0093] In this example, in order to interconnect the first lower metal line 1522U(1) to the first upper metal line 1522O(1), the first upper metal line 1522O(1) is configured to directly contact the first lower metal line 1522U(1). This is because the upper interconnect layer 1524O is disposed on the lower interconnect layer 1524U in the back interconnect structure 1510 without using an intermediate via layer. The first upper metal line 1522O(1) is directly coupled to the first lower metal line 1522U(1) in the first connection region 1528(1), in which the first upper metal line 1522O(1) and the first lower metal line 1522U(1) intersect in the horizontal X-axis and Y-axis directions. As shown in FIG15, the first upper metal line 1522O(1) also intersects with the second lower metal line 1522U(2) in the third connection region 1528(3). However, it may be undesirable to electrically couple (i.e., short-circuit) the first overlay metal line 1522O(1) to the second underlay metal line 1522U(2). For example, the first overlay metal line 1522O(1) could be a positive power rail, and the second underlay metal line 1522U(2) could be a ground or negative power rail that cannot be short-circuited. Because the intermediate via layer between the overlay interconnect layer 1524O and the underlay interconnect layer 1524U is eliminated, if isolation is not provided, the first overlay metal line 1522O(1) and the second underlay metal line 1522U(2) would be set to be in direct contact with each other, resulting in a short circuit.

[0094] In this respect, as shown in FIG15, the back-side interconnect structure 1510 includes an insulating layer 1530(1) disposed between and above the entire overlay interconnect layer 1524O and the lower interconnect layer 1524U. The insulating layer 1530(1) is formed of a dielectric material. However, unlike the back-side interconnect structure 1210 in FIG12A and FIG12B, in the exemplary back-side interconnect structure 1510 in FIG15, the insulating layer 1530(1) is patterned and removed (e.g., etched away) in the first connection region 1528(1) between the first overlay metal line 1522O(1) and the first lower metal line 1522U(1). This effectively creates a first recess 1532(1) in the first overlay metal line 1522O(1) outside the corresponding first connection region 1528(1). As shown in Figure 15, for the first overlay metal line 1522O(1), a first opening 1534(1) (also referred to as a “groove”) extending to the first surface 1536(1) of the first lower metal line 1522U(1) is filled with metal material 1538(1) due to the patterning and removal of a portion of the insulating layer 1530(1) in the first connection region 1528(1). This metal material 1538(1) forms the first overlay metal line 1522O(1) in the overlay interconnect layer 1524O. In this way, the metal material 1538(1) of the first overlay metal line 1522O(1) is configured to contact the first lower metal line 1522U(1), while the remainder of the insulating layer 1530(1) remains in the third connection region 1528(3) to insulate and isolate the first overlay metal line 1522O(1) from the second lower metal line 1522U(2). By providing a first recess 1532(1) in the first overlay metal line 1522O(1) in the first connection region 1528(1), it is not necessary to have an additional insulating material layer between the overlay interconnect layer 1524O and the lower interconnect layer 1524U. Providing an additional insulating material layer would contribute to the height of the back-side interconnect structure 1510.

[0095] Similarly, as shown in Figure 15, in this example, a first overlay metal line 1522O(1) is disposed on a first thin metal barrier layer 1540(1), which is disposed on a lower interconnect layer 1524U. For example, the first thin metal barrier layer 1540(1) may be, for example, tantalum nitride. The first thin metal barrier layer 1540(1) provides a direct electrical connection between the first overlay metal line 1522O(1) and the first lower metal line 1522U(1), while also providing a barrier layer that can reduce or prevent the metal material 1538(1) of the first overlay metal line 1522O(1) from diffusing into the lower interconnect layer 1524U during a manufacturing process in which the temperature is sufficient to cause metal diffusion. For example, in this example, the lower interconnect layer 1524U includes a dielectric material 1542 in which lower metal lines 1522U(1), 1522U(2) are formed to insulate and isolate the lower metal lines 1522U(1), 1522U(2). If metal material from the first overlay metal line 1522O(1) diffuses into the dielectric material 1542 of the lower interconnect layer 1524U, the diffused metal may cause an unintended short circuit with the lower metal line 1522U, such as between the first overlay metal line 1522O(1) and the second lower metal line 1522U(1) in this example.

[0096] Other structures besides metal lines carrying signals (such as power signals) can be formed in the interconnect structure of an IC that includes directly coupled metal lines in adjacent interconnect layers without intermediate via layers. For example, metal oxide (MoM) capacitors can be formed in interconnect structures, such as BEOL interconnect structures, where directly coupled metal lines are present in adjacent interconnect layers (e.g., metallization layers) without intermediate via layers. Forming capacitors (e.g., metal oxide (MoM) capacitors) from directly coupled metal lines in adjacent interconnect layers without intermediate via layers can advantageously reduce the size (e.g., in the vertical direction) of the interconnect structure in which capacitors are formed. Similarly, as mentioned above, directly coupled metal lines in adjacent interconnect layers can reduce the contact resistance between coupled metal lines.

[0097] In this regard, FIG16A is a top view of an exemplary IC 1600 including capacitor 1602. For example, capacitor 1602 may be a MoM capacitor. FIG16B is a cross-sectional side view through section line A4-A4' in FIG16A. As discussed in more detail below, capacitor 1602 is formed in interconnect structure 1604, which includes directly coupled metal lines in adjacent interconnect layers 1606(1), 1606(2). For example, interconnect structure 1604 may be a BEOL interconnect structure, such as BEOL interconnect structure 304 in IC 300 of FIG3. There is no via layer between adjacent interconnect layers 1606(1), 1606(2). As shown in FIG16A and FIG16B, the first interconnect layer 1606(1) is a lower interconnect layer 1606U disposed in the Z-axis direction below the second interconnect layer 1606(2) which is an overlay interconnect layer 1606O. The lower interconnect layer 1606U includes a first lower metal finger structure 1608U(1), which includes a first lower metal line 1610U(1) and a second lower metal line 1610U(2) extending parallel to each other in the horizontal Y-axis direction. The first lower metal line 1610U(1) and the second lower metal line 1610U(2) are coupled together by a first lower metal line 1612U(1) disposed in the horizontal X-axis direction. The lower interconnect layer 1606U also includes a second lower metal finger structure 1608U(2), which includes a third lower metal line 1610U(3) and a fourth lower metal line 1610U(4) extending parallel to each other in the horizontal Y-axis direction. The third lower metal line 1610U(3) and the fourth lower metal line 1610U(4) are coupled together by a second lower metal line 1612U(2) disposed in the horizontal X-axis direction.

[0098] Referring again to Figure 16A, the first lower metal finger structure 1608U(1) and the second lower metal finger structure 1608U(2) are interleaved. At this point, the first lower metal wire 1610U(1) and the second lower metal wire 1610U(2) of the first lower metal finger structure 1608U(1) are interleaved with the third lower metal wire 1610U(3) and the fourth lower metal wire 1610U(4) of the second lower metal finger structure 1608U(2), respectively. The first lower metal wire 1610U(1) is adjacent to and located between the third lower metal wire 1610U(3) and the fourth lower metal wire 1610U(4). The second lower metal wire 1610U(2) is adjacent to the fourth lower metal wire 1610U(4). The fourth lower metal line 1610U(4) is disposed adjacent to and between the first lower metal line 1610U(1) and the second lower metal line 1610U(2).

[0099] Furthermore, as shown in Figure 16A, the overlay interconnect layer 1606O includes a first overlay metal finger structure 1608O(1), which includes a first overlay metal line 1610O(1) and a second overlay metal line 1610O(2) extending parallel to each other in the horizontal Y-axis direction. The first overlay metal line 1610O(1) and the second overlay metal line 1610O(2) are coupled together by a first overlay metal line 1612O(1) disposed in the horizontal X-axis direction. The overlay interconnect layer 1606O also includes a second overlay metal finger structure 1608O(2), which includes a third overlay metal line 1610O(3) and a fourth overlay metal line 1610O(4) extending parallel to each other in the horizontal Y-axis direction. The third and fourth top metal wires 1610O(3) and 1610O(4) are coupled together by the second top metal wire 1612O(2) disposed in the horizontal X-axis direction. The first and second top metal finger structures 1608O(1) and 1608O(2) are interleaved. At this point, the first lower metal finger structure 1608O(1) and the first and second top metal wires 1610O(1) and 1610O(2) are interleaved with the third and fourth top metal wires 1610O(3) and 1610O(4) of the second top metal finger structure 1608O(2), respectively. The third top metal wire 1610O(3) is disposed adjacent to and between the first and second top metal wires 1610O(1) and 1610O(2). The fourth upper metal wire 1610O(4) is disposed adjacent to the second lower metal wire 1610U(2). The second upper metal wire 1610O(2) is disposed adjacent to and between the third upper metal wire 1610O(3) and the fourth upper metal wire 1610O(4). For example, the first lower metal finger structure 1608U(1) and the second upper metal finger structure 1608O(2) may have the same polarity (+), and the second lower metal finger structure 1608U(2) and the first upper metal finger structure 1608O(1) may have different second polarities (-).

[0100] Referring again to Figure 16A, the first upper metal finger structure 1608O(1) and the first lower metal finger structure 1608U(1) intersect in the first connecting region 1614(1) in the horizontal X-axis and Y-axis directions. The first upper metal finger structure 1608O(1) is coupled to the first lower metal finger structure 1608U(1) in the first connecting region 1614(1) without an intermediate via layer. In this example, the third upper metal line 1610O(3) intersects and is directly coupled to the first lower metal line 1610U(1) and the second lower metal line 1610U(2) in the horizontal X-axis and Y-axis directions. The second upper metal finger structure 1608O(2) and the second lower metal finger structure 1608U(2) intersect in the second connecting region 1614(2) in the horizontal X-axis and Y-axis directions. The second overlay metal finger structure 1608O(2) is directly coupled to the second lower layer metal finger structure 1608U(2) in the second connection region 1614(2) without an intermediate via layer. In this example, the first overlay metal line 1610O(1) and the second overlay metal line 1610O(2) intersect and are directly coupled to the third lower layer metal line 1610U(3) and the fourth lower layer metal line 1610U(4) in the horizontal X-axis and Y-axis directions.

[0101] As shown in Figure 16B, capacitor 1602 includes an insulating layer 1616 disposed on the lower interconnect layer 1606U between the overlying interconnect layer 1606O and the lower interconnect layer 1606U to insulate the first overlying metal line 1610O(1) from the third lower metal line 1610U(3) and the fourth lower metal line 1610U(4). The insulating layer 1616 is formed of a dielectric material. In this example, the insulating layer 1616 is patterned and removed (e.g., etched away) in the first connection region 1614(1) between the first overlying metal line 1610O(1) and the first lower metal line 1610U(1) and the second lower metal line 1610U(2). Similar to IC 500 in Figures 5A and 5B, this actually creates a recess 1618 in the first overlying metal line 1610O(1) outside the first connection region 1614(1). As shown in Figure 16B, for the first overlay metal line 1610O(1), the opening 1620 (also referred to as "groove") in the insulating layer 1616, which is formed by the patterning and removal of a portion of the insulating layer 1616 in the first connection region 1614(1) and extends to the first lower metal lines 1610U(1) and 1610U(2), is filled with metal material 1624, which forms the first overlay metal line 1610O(1) in the overlay interconnect layer 1606O. In this way, the metal material 1624 of the first overlay metal line 1610O(1) is configured to contact the first lower metal line 1610U(1) and the second lower metal line 1610U(2), while the remainder of the insulating layer 1616 remains in the second connection region 1614(2) to insulate and isolate the first overlay metal line 1610O(1) from the third lower metal line 1610U(3) and the fourth lower metal line 161U(4). By providing a first recess 1618 in the first connection region 1614(1) in the first overlay metal line 1610O(1), it is not necessary to have an additional insulating material layer on the entire interface between the overlay interconnect layer 1606O and the lower interconnect layer 1606U, which would otherwise contribute to the height of the interconnect structure 1604.

[0102] Note that, similar to IC 300 in Figures 4A and 4B, recesses can be formed in the second connection region 1614(2) instead of in the first connection region 1614(1). In this way, these recesses can contain an insulating layer 1616 that remains stationary without being patterned and etched, so that the third lower metal line 1610U(3) and the fourth lower metal line 1610U(4) in the second connection region 1614(2) are insulated and isolated from the first overlay metal line 1610O(1). As described above, a thin barrier metal layer can also be disposed between the overlay metal lines 1610O coupled to the lower metal lines 1610U.

[0103] Figure 17A is a top view of another exemplary IC 1700 including capacitor 1702. For example, capacitor 1702 may be a MoM capacitor. Figure 17B is a cross-sectional side view through section line A5-A5' in Figure 17A. As discussed in more detail below, capacitor 1702 is formed in interconnect structure 1704, which includes directly coupled metal lines in adjacent interconnect layers 1706(1), 1706(2). For example, interconnect structure 1704 may be a BEOL interconnect structure, such as BEOL interconnect structure 304 in IC 300 of Figure 3. There are no via layers between adjacent interconnect layers 1706(1), 1706(2). As shown in Figures 17A and 17B, the first interconnect layer 1706(1) is a lower interconnect layer 1706U disposed in the Z-axis direction below the second interconnect layer 1706(2) which is an overlay interconnect layer 1706O. The lower interconnect layer 1706U includes a first lower metal finger structure 1708U(1), which includes a first lower metal line 1710U(1) and a second lower metal line 1710U(2) extending parallel to each other in the horizontal Y-axis direction. The lower interconnect layer 1706U also includes a second lower metal finger structure 1708U(2), which includes a third lower metal line 1710U(3) and a fourth lower metal line 1710U(4) extending parallel to each other in the horizontal Y-axis direction.

[0104] Referring again to Figure 17A, the first lower metal finger structure 1708U(1) and the second lower metal finger structure 1708U(2) are interleaved. At this point, the first lower metal wire 1710U(1) and the second lower metal wire 1710U(2) of the first lower metal finger structure 1708U(2) are interleaved with the third lower metal wire 1710U(3) and the fourth lower metal wire 1710U(4) of the second lower metal finger structure 1708U(2), respectively. The first lower metal wire 1710U(1) is adjacent to and located between the third lower metal wire 1710U(3) and the fourth lower metal wire 1710U(4). The second lower metal wire 1710U(2) is adjacent to the fourth lower metal wire 1710U(4). The fourth lower metal line 1710U(4) is disposed adjacent to and between the first lower metal line 1710U(1) and the second lower metal line 1710U(2).

[0105] Furthermore, as shown in Figure 17A, the overlay interconnect layer 1706O includes a first overlay metal finger structure 1708O(1), which includes a first overlay metal line 1710O(1) and a second overlay metal line 1710O(2) extending parallel to each other in the horizontal X-axis direction. The overlay interconnect layer 1706O also includes a second overlay metal finger structure 1708O(2), which includes a third overlay metal line 1710O(3) and a fourth overlay metal line 1710O(4) extending parallel to each other in the horizontal X-axis direction. The first overlay metal finger structure 1708O(1) and the second overlay metal finger structure 1708O(2) are interleaved. In this respect, the first top metal wire 1710O(1) and the second top metal wire 1710O(2) of the first top metal finger structure 1708O(1) are interleaved with the third top metal wire 1710O(3) and the fourth top metal wire 1710O(4) of the second top metal finger structure 1708O(2). The fourth top metal wire 1710O(4) is arranged adjacent to and between the first top metal wire 1710O(1) and the second top metal wire 1710O(2). The third top metal wire 1710O(3) is arranged adjacent to the first bottom metal wire 1710U(1). The first top metal wire 1710O(1) is arranged adjacent to and between the third top metal wire 1710O(3) and the fourth top metal wire 1710O(4). For example, the first lower metal finger structure 1708U(1) and the first upper metal finger structure 1708O(1) may have the same polarity (+), and the second lower metal finger structure 1708U(2) and the second upper metal finger structure 1708O(2) may have different second polarities (-).

[0106] Referring again to Figure 17A, the first upper metal finger structure 1708O(1) and the first lower metal finger structure 1708U(1) intersect in the first connecting region 1714(1) in the horizontal X-axis and Y-axis directions. The first upper metal finger structure 1708O(1) is coupled to the first lower metal finger structure 1708U(1) in the first connecting region 1714(1) without an intermediate via layer. In this example, the first upper metal line 1710O(1) and the second upper metal line 1710O(2) intersect and are directly coupled to the first lower metal line 1710U(1) and the second lower metal line 1710U(2) in the horizontal X-axis and Y-axis directions. The second upper metal finger structure 1708O(2) and the second lower metal finger structure 1708U(2) intersect in the second connecting region 1714(2) in the horizontal X-axis and Y-axis directions. The second overlay metal finger structure 1708O(2) is directly coupled to the second lower metal finger structure 1708U(2) in the second connection region 1714(2) without an intermediate via layer. In this example, the third overlay metal line 1710O(3) and the fourth overlay metal line 1710O(4) intersect and are directly coupled to the third lower metal line 1710U(3) and the fourth lower metal line 1710U(4) in the horizontal X-axis and Y-axis directions.

[0107] As shown in Figure 17B, capacitor 1702 includes an insulating layer 1716 disposed on the lower interconnect layer 1706U between the overlying interconnect layer 1706O and the lower interconnect layer 1706U to insulate the first overlying metal line 1710O(1) from the first lower metal line 1710U(1) and the second lower metal line 1710U(2). The insulating layer 1716 is formed of a dielectric material. In this example, the insulating layer 1716 is patterned and removed (e.g., etched away) in the first connection region 1714(1) between the first overlying metal line 1710O(1) and the first lower metal line 1710U(1) and the second lower metal line 1710U(2). Similar to IC 500 in Figures 5A and 5B, this actually creates a recess 1718 in the first overlying metal line 1710O(1) outside the first connection region 1714(1). As shown in Figure 17B, for the first overlay metal line 1710O(1), the opening 1720 (also referred to as a “groove”) in the insulating layer 1716, which is formed by the patterning and removal of a portion of the insulating layer 1716 in the first connection region 1714(1) and extends to the first lower layer metal lines 1710U(1) and 1710U(2), is filled with metal material 1724, which forms the first overlay metal line 1710O(1) in the overlay interconnect layer 1706O. In this way, the metal material 1724 of the first overlay metal wire 1710O(1) is configured to contact the first lower metal wire 1710U(1) and the second lower metal wire 1710U(2), while the remainder of the insulating layer 1716 remains in the second connection region 1714(2) to insulate and isolate the first overlay metal wire 1710O(1) from the third lower metal wire 1710U(3) and the fourth lower metal wire 171U(4). By providing a first recess 1718 in the first connection region 1714(1) in the first overlay metal wire 1710O(1), it is not necessary to have an additional insulating material layer on the entire interface between the overlay interconnect layer 1706O and the lower interconnect layer 1706U, which would contribute to the height of the interconnect structure 1704.

[0108] Note that, similar to IC 300 in Figures 4A and 4B, recesses can be formed in the second connection region 1714(2) instead of in the first connection region 1714(1). In this way, these recesses can contain an insulating layer 1716 that remains stationary without being patterned and etched, so that the third lower metal line 1710U(3) and the fourth lower metal line 1710U(4) in the second connection region 1714(2) are insulated and isolated from the first overlay metal line 1710O(1). As described above, a thin barrier metal layer can also be disposed between the overlay metal lines 1710O coupled to the lower metal lines 1710U.

[0109] Figure 18A is a top view of another exemplary IC 1800 including capacitor 1802. For example, capacitor 1802 may be a MoM capacitor. Figure 18B is a cross-sectional side view through section line A6-A6' in Figure 18A. As discussed in more detail below, capacitor 1802 is formed in interconnect structure 1804, which includes directly coupled metal lines in adjacent interconnect layers 1806(1), 1806(2). For example, interconnect structure 1804 may be a BEOL interconnect structure, such as BEOL interconnect structure 304 in IC 300 of Figure 3. There is no via layer between adjacent first interconnect layer 1806(1) and second interconnect layer 1806(2). As shown in Figures 18A and 18B, first interconnect layer 1806(1) is a lower interconnect layer 1806U disposed in the Z-axis direction below second interconnect layer 1806(2) which is an overlying interconnect layer 1806O. The lower interconnect layer 1806U includes a first lower metal finger structure 1808U(1), which includes a first lower metal line 1810U(1) and a second lower metal line 1810U(2) extending parallel to each other in the horizontal Y-axis direction. The first lower metal line 1810U(1) and the second lower metal line 1810U(2) are coupled to each other through a first lower metal line 1812U(1) extending in the horizontal X-axis direction. The lower interconnect layer 1806U also includes a second lower metal finger structure 1808U(2), which includes a third lower metal line 1810U(3) and a fourth lower metal line 1810U(4) extending parallel to each other in the horizontal Y-axis direction. The third lower metal line 1810U(3) and the fourth lower metal line 1810U(4) are coupled to each other through the second lower metal line 1812U(1) extending in the horizontal X-axis direction.

[0110] Referring again to Figure 18A, the first lower metal finger structure 1808U(1) and the second lower metal finger structure 1808U(2) are interleaved. At this point, the first lower metal wire 1810U(1) and the second lower metal wire 1810U(2) of the first lower metal finger structure 1808U(2) are interleaved with the third lower metal wire 1810U(3) and the fourth lower metal wire 1810U(4) of the second lower metal finger structure 1808U(2), respectively. The first lower metal wire 1810U(1) is arranged adjacent to and between the third lower metal wire 1810U(3) and the fourth lower metal wire 1810U(4). The second lower metal wire 1810U(2) is arranged adjacent to the fourth lower metal wire 1810U(4). The fourth lower metal line 1810U(4) is disposed adjacent to and between the first lower metal line 1810U(1) and the second lower metal line 1810U(2).

[0111] Furthermore, as shown in Figure 18A, the overlay interconnect layer 1806O includes a first overlay metal finger structure 1808O(1), which includes a first overlay metal line 1810O(1) and a second overlay metal line 1810O(2) extending parallel to each other in the horizontal X-axis direction. The first overlay metal line 1810O(1) and the second overlay metal line 1810O(2) are coupled to each other through a first overlay metal line 1812O(1) extending in the horizontal X-axis direction. The overlay interconnect layer 1806O also includes a second overlay metal finger structure 1808O(2), which includes a third overlay metal line 1810O(3) and a fourth overlay metal line 1810O(4) extending parallel to each other in the horizontal X-axis direction. The third overcoating metal line 1810O(3) and the fourth overcoating metal line 1810O(4) are coupled to each other by the second overcoating metal line 1812O(2) extending in the horizontal X-axis direction. The first overcoating metal finger structure 1808O(1) and the second overcoating metal finger structure 1808O(2) are interleaved. At this point, the first overcoating metal line 1810O(1) and the second overcoating metal line 1810O(2) of the first overcoating metal finger structure 1808O(1) are interleaved with the third overcoating metal line 1810O(3) and the fourth overcoating metal line 1810O(4) of the second overcoating metal finger structure 1808O(2), respectively. The third overcoating metal line 1810O(3) is disposed adjacent to the first overcoating metal line 1810O(1) and the second overcoating metal line 1810O(2) and is located therebetween. The fourth overlay metal line 1810O(4) is disposed adjacent to the second underlay metal line 1810U(2). The third overlay metal line 1810O(3) is disposed adjacent to and between the first overlay metal line 1810O(1) and the second overlay metal line 1810O(2). For example, the first underlay metal finger structure 1808U(1) and the first overlay metal finger structure 1808O(1) may have the same polarity (+), and the second underlay metal finger structure 1808U(2) and the second overlay metal finger structure 1808O(2) may have different second polarities (-).

[0112] Referring again to Figure 18A, the first upper metal finger structure 1808O(1) and the first lower metal finger structure 1808U(1) intersect in the horizontal X-axis and Y-axis directions. The first upper metal finger structure 1808O(1) and the first lower metal finger structure 1808U(1) are coupled to each other in the first connection region 1814(1) without an intermediate via layer. In this example, the first upper metal line 1812O(1) and the first lower metal line 1812U(1) intersect in the horizontal X-axis and Y-axis directions and are directly coupled. The second upper metal finger structure 1808O(2) and the second lower metal finger structure 1808U(2) intersect in the horizontal X-axis and Y-axis directions. The second upper metal finger structure 1808O(2) is directly coupled to the second lower metal finger structure 1808U(2) in the second connection region 1814(2) without an intermediate via layer. In this example, the second upper metal line 1810O(2) intersects and is directly coupled to the second lower metal line 1810U(2) in the horizontal X-axis and Y-axis directions.

[0113] As shown in Figure 18B, capacitor 1802 includes an insulating layer 1816 disposed on the lower interconnect layer 1806U between the upper interconnect layer 1806O and the lower interconnect layer 1806U to insulate and isolate the first upper metal line 1810O(1) and the second upper metal line 1810O(2) from the third lower metal line 1810U(3) and the fourth lower metal line 1810U(4). The insulating layer 1816 also insulates and isolates the third upper metal line 1810O(3) and the fourth upper metal line 1810O(4) from the first lower metal line 1810U(1) and the second lower metal line 1810U(2). The insulating layer 1816 is formed of a dielectric material. In this example, the insulating layer 1816 can be patterned to provide recesses in the first connection region 1814(1) and / or the second connection region 1814(2), as shown in the examples of IC 300, 500 in Figures 3-4B and 5A-5B. As described above, a thin barrier metal layer can also be disposed between the overlying metal lines 1810O coupled to the lower metal line 1810U.

[0114] Other structures besides metal lines carrying signals (such as power signals) can be formed in the interconnect structure of an IC, including directly coupled metal lines in adjacent interconnect layers without intermediate via layers. For example, inductors can be formed in interconnect structures such as BEOL interconnect structures, where directly coupled coil-shaped metal lines are present in adjacent interconnect layers (e.g., metallization layers) without intermediate via layers. Forming inductors from directly coupled metal lines in adjacent interconnect layers without intermediate via layers can advantageously reduce the size (e.g., in the vertical direction) of the interconnect structure in which inductors are formed. Similarly, as mentioned above, directly coupled metal lines in adjacent interconnect layers can reduce the contact resistance between coupled metal lines.

[0115] In this regard, Figure 19A is a top view of an exemplary IC 1900 including inductor 1902. Figure 19B is a cross-sectional side view through section line A7-A7' in Figure 19A. As discussed in more detail below, inductor 1902 is formed in interconnect structure 1904, which includes an overlying metal coil structure of metal segments in a coil-shaped pattern that is directly coupled to a lower metal coil structure of metal segments in a coil-shaped pattern in adjacent interconnect layers 1906(1), 1906(2). For example, interconnect structure 1904 may be a BEOL interconnect structure, such as BEOL interconnect structure 304 in IC 300 of Figure 3. There are no via layers between adjacent interconnect layers 1906(1), 1906(2).

[0116] As shown in Figures 19A and 19B, the first interconnect layer 1906(1) is a lower interconnect layer 1906U disposed in the Z-axis direction below the second interconnect layer 1906(2), which serves as the overlay interconnect layer 1906O. The lower interconnect layer 1906U includes a first lower metal coil structure 1908U, which includes a plurality of lower metal segments 1910U(1)-1910U(8) coupled to each other in an end-to-end configuration. The overlay interconnect layer 1906O includes a first overlay metal coil structure 1908O, which includes a plurality of overlay metal segments 1910O(1)-1910O(8) coupled to each other in an end-to-end configuration. Each corresponding upper metal segment 1910O(1)-1910O(8) in the upper metal coil structure 1908O of the upper interconnect layer 1906O is arranged vertically (Z-axis direction) above each corresponding upper metal segment 1910O(1)-1910O(8) in the lower metal coil structure 1908U of the lower interconnect layer 1906U and directly coupled to each corresponding upper metal segment 1910O(1)-1910O(8) in the lower metal coil structure 1908U of the lower interconnect layer 1906U. This is also shown in the cross-section of the inductor 1902 in FIG19B, wherein the upper metal segments 1910O(2), 1910O(6) are arranged and directly coupled to the corresponding lower metal segments 1910U(2), 1910U(6).

[0117] Referring again to Figure 19A, the lower metal segments 1910U(1)-1910U(8) of the lower metal coil structure 1908U are coupled to each other to form a coil pattern. The lower metal segment 1910U(1) includes a first end 1912(1) of the lower metal coil structure 1908U. The lower metal segment 1910U(8) includes a second end 1912(2) of the lower metal coil structure 1908U. The upper metal segment 1910O(8) includes a first end 1912(1) of the lower metal coil structure 1908U. The lower metal segment 1910U(8) includes a second end 1912(2) of the lower metal coil structure 1908U. The upper metal segment 1910O(1) includes a third end 1912(3) of the upper metal coil structure 1908O. The overlying metal segment 1910O(8) includes the fourth end 1912(4) of the overlying metal coil structure 1908O. The overlying metal coil structure 1908O between its third end 1912(3) and fourth end 1912(4) intersects the lower metal coil structure 1908U between its first end 1912(1) and second end 1912(2) in the vertical direction (Z-axis direction).

[0118] As shown in Figures 19A and 19B, the third end 1912(3) of the upper metal coil structure 1908O is coupled to the second end 1912(2) of the lower metal coil structure 1908U in the first connection region 1916(1). As shown in Figure 19B, an insulating layer 1914 is disposed in the first connection region 1916(1) between the upper metal coil structure 1908O and the lower metal coil structure 1908U to prevent accidental short circuits between the upper metal coil structure 1908O and the lower metal coil structure 1908U at locations other than where the upper metal coil structure 1908O and the lower metal coil structure 1908U intersect with the first connection region 1916(1) and the second connection region 1916(2). The insulating layer 1914 is formed of a dielectric material. In this example, the insulating layer 1914 is patterned and removed (e.g., etched away) between the overlying metal coil structure 1908O and the lower metal coil structure 1908U in the first connection region 1916(1) and the second connection region 1916(2). Similar to IC 500 in Figures 5A and 5B, this actually creates a recess in the overlying metal coil structure 1908O outside the first connection region 1916(1). In this way, the metal material 1924 of the overlying metal coil structure 1908O is positioned to contact the lower metal coil structure 1908U in the first connection region 1916(1) and the second connection region 1916(2), while the remaining portion of the insulating layer 1914 is left to insulate and isolate the overlying metal coil structure 1908O and the lower metal coil structure 1908U. Note that a recess is formed in the second connection region 1916(2), rather than in the first connection region 1916(1), similar to IC 300 in Figures 4A and 4B. In this way, these recesses may contain an insulating layer 1914 that remains in place without being patterned and etched, so as to insulate and isolate the overlying metal coil structure 1908O and the underlying metal coil structure 1908U.

[0119] Figure 20A is a top view of another exemplary IC 2000 including two (2) inductors 2002(1) and 2002(2). Figure 20B is a cross-sectional side view through section line A8-A8' in Figure 20A. As discussed in more detail below, the inductors 2002(1) and 2002(2) are formed in an interconnect structure 2004, which includes a plurality of overlying metal coil structures of metal segments of coil-shaped patterns coupled to a lower metal coil structure of coil-shaped patterns in adjacent interconnect layers 2006(1)-2006(4). For example, interconnect structure 2004 may be a BEOL interconnect structure, such as BEOL interconnect structure 304 in IC 300 of Figure 3. In this example, there is no via layer between adjacent interconnect layers 2006(1)-2006(4). As shown in Figures 20A and 20B, the first interconnect layer 2006(1) is a lower interconnect layer disposed below the second interconnect layer 2006(2), which serves as an overlay interconnect layer, in the Z-axis direction. The second interconnect layer 2006(2), which serves as a lower interconnect layer, is disposed below the third interconnect layer 2006(3), which serves as an overlay interconnect layer, in the Z-axis direction. The third interconnect layer 2006(3), which serves as a lower interconnect layer, is disposed below the fourth interconnect layer 2006(4), which serves as an overlay interconnect layer, in the Z-axis direction.

[0120] The lower interconnect layer 2006(1) includes a first lower metal coil structure 2008U(1), which includes a plurality of lower metal segments 2010U(1)-2010U(8) coupled to each other in an end-to-end configuration. The upper interconnect layer 2006(2) includes a second lower metal coil structure 2008U(2), which includes a plurality of lower metal segments 2012U(1)-2012U(8) coupled to each other in an end-to-end configuration. The upper interconnect layer 2006(3) includes a third lower metal coil structure 2008U(3), which includes a plurality of lower metal segments 2014U(1)-2014U(8) coupled to each other in an end-to-end configuration. The overlay interconnect layer 2006(4) includes an overlay metal coil structure 2008O(4), which includes a plurality of lower metal segments 2016U(1)-2016U(8) coupled to each other in an end-to-end configuration. Each corresponding overlay metal segment 2016O(1)-2016O(8) in the overlay metal coil structure 2008O(4) of the overlay interconnect layer 2006(4) is disposed in the vertical direction (Z-axis direction) above each corresponding lower metal segment 2014U(1)-2014U(8) in the lower metal coil structure 2008U(3) of the lower interconnect layer 2006(3) to form a second inductor 2002(2). Each corresponding upper metal segment 2012O(1)-2012O(8) in the upper metal coil structure 2008U(2) is arranged in the vertical direction (Z-axis direction) above each corresponding lower metal segment 2010U(1)-2010U(8) in the lower metal coil structure 2008U(1) to form a first inductor 2002(1). This is also shown in the cross-section of inductors 2002(1) and 2002(2) in FIG20B.

[0121] Referring again to Figure 20A, the lower metal segments 2010U(1)-2010U(8) of the lower metal coil structure 2008U(1) are coupled to each other to form a coil-shaped pattern. The lower metal segment 2010U(1) includes the first end 2022(1) of the lower metal coil structure 2008U(1). The lower metal segment 2010U(8) includes the second end 2024(1) of the lower metal coil structure 2008U(1). The lower metal segment 2012U(1) includes the first end 2022(2) of the lower metal coil structure 2008(2). The lower metal segment 2012U(8) includes the second end 2024(2) of the lower metal coil structure 2008U(2). The lower metal segment 2014U(1) ​​includes the first end 2022(3) of the lower metal coil structure 2008(3). The lower metal segment 2014U(8) includes the second end 2024(3) of the lower metal coil structure 2008(3). The upper metal segment 2016O(1) includes the first end 2022(4) of the lower metal coil structure 2008(4). The upper metal segment 2016O(8) includes the second end 2024(4) of the lower metal coil structure 2008U(4).

[0122] As shown in Figure 20B, the upper metal coil structure 2008O(4) intersects the lower metal coil structure 2008U(3) in the vertical direction (Z-axis direction) at the connection region 2026(3). The upper metal coil structure 2008O(4) is coupled to the lower metal coil structure 2008U(3) at the connection region 2026(3). The lower metal coil structure 2008U(2) intersects the lower metal coil structure 2008U(1) in the vertical direction (Z-axis direction) at the connection region 2026(1). The lower metal coil structure 2008U(2) is coupled to the lower metal coil structure 2008U(1) at the connection region 2026(1). Insulating layers 2028(1)-2028(3) are disposed between the corresponding metal coil structures 2008(1)-2008(4) to prevent accidental short circuits in the metal coil structures 2008(1)-2008(4) that form the discrete inductors 2002(2), 2002(1). The insulating layers 2028(1)-2028(3) are formed of a dielectric material. In this example, the insulating layers 2028(1)-2028(3) are patterned and removed (e.g., etched away) in the connection regions 2026(1), 2026(3). Similar to IC 500 in Figures 5A and 5B, this actually creates recesses in the metal coil structures 2008(1)-2008(4) outside the connection regions 2026(1), 2026(3). In this way, the metal material of the corresponding metal coil structures 2008O(4) and 2008U(2) is set to contact the corresponding lower metal coil structures 2008U(3) and 2008U(1), while the remainder of the insulating layers 2028(1)-2028(3) is left to insulate and isolate the metal coil structures 2008(1)-2008(4). Note that the insulating layer 2028(2) between the metal segment 2014U(6) and the metal segment 2012U(6) is not removed to provide discontinuity between the metal coil structures 2008(2) and 2008(3) to form two (2) separate inductors 2002(1) and 2002(2). Note that the recess is formed outside the connection regions 2026(1) and 2026(3), rather than in the connection regions 2026(1) and 2026(3), similar to IC 300 and 4B in FIG4A.

[0123] Note that the terms “overlapping” and “underlapping” as used in this document are relative terms and do not imply a restriction or implication that a “top” referenced element must always be strictly oriented above a “bottom” referenced element relative to the ground, or vice versa. In one example, “underlapping” refers to something located below something that is “overlapping”, but if the orientation is reversed, something that is “underlapping” can be above something that is “overlapping.” Also note that the terms “top” and “bottom” as used in this document are relative terms and do not imply a restriction or implication that an element referenced “above” another referenced element must always be strictly oriented above another referenced element relative to the ground, or that an element referenced “below” another referenced element must always be below another referenced element relative to the ground.

[0124] Each IC may include one or more interconnect structures, which include vertically adjacent lower interconnect layers and upper interconnect layers without intermediate via layers, wherein the vertically adjacent lower interconnect layers and upper interconnect layers include corresponding lower metal lines and upper metal lines coupled to each other, including but not limited to the exemplary ICs in Figures 3-5B, 8A-12B, and 15-20B and conforming to the exemplary manufacturing processes in Figures 6-7B-2 and 14A-14E, such ICs can be disposed in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, laptops, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), displays, computer monitors, televisions, tuners, radios, satellite broadcasting, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0125] In this regard, Figure 21 illustrates an example of a processor-based system 1400 including circuitry that can be disposed in one or more ICs 2102(1)-2102(5), each IC including one or more interconnect structures comprising vertically adjacent lower interconnect layers and overlay interconnect layers without intermediate via layers, wherein the vertically adjacent lower interconnect layers and overlay interconnect layers include corresponding lower metal lines and overlay metal lines coupled to each other, including but not limited to the exemplary ICs in Figures 3-5B, 8A-12B, 15-20B and conforming to the exemplary manufacturing processes in Figures 6-7B-2 and 14A-14E. In this example, the processor-based system 2100 can be formed as IC 2104 in IC package 2102 as a system-on-a-chip (SoC) 2106. The processor-based system 2100 includes a central processing unit (CPU) 2108, which includes one or more processors 2110, also referred to as CPU cores or processor cores. The CPU 2108 may have cache memory 2112 coupled to the CPU 2108 for fast access to temporarily stored data. The CPU 2108 is coupled to system buses 2114 and may be coupled to master and slave devices included in the processor-based system 2100. It is known that the CPU 2108 communicates with these other devices by exchanging address, control, and data information via system buses 2114. For example, the CPU 2108 may transmit bus transaction requests to a memory controller 2116, an example of a slave device. Although not shown in Figure 21, multiple system buses 2114 may be provided, each forming a different architecture.

[0126] Other master and slave devices can be connected to system bus 2114. As shown in FIG21, for example, these devices may include: a memory system 2120 including a memory controller 2116 and multiple memory arrays 2118, one or more input devices 2122, one or more output devices 2124, one or more network interface devices 2126, and one or more display controllers 2128. Each of the memory system 2120, one or more input devices 2122, one or more output devices 2124, one or more network interface devices 2126, and one or more display controllers 2128 may be disposed in the same IC package 2102 or different IC packages 2102(3), 2102(4). The multiple input devices 2122 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The multiple output devices 2124 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Multiple network interface devices 2126 can be any device configured to allow data exchange with network 2130. Network 2130 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. Multiple network interface devices 2126 can be configured to support any desired type of communication protocol.

[0127] CPU 2108 can also be configured to access (multiple) display controllers 2128 via system bus 2114 to control information sent to one or more displays 2132. The (multiple) display controllers 2128 send information to the (multiple) displays 2132 for display via one or more video processors 2134, which process the information to be displayed into a format suitable for the (multiple) displays 2132. For example, the (multiple) display controllers 2128 and the (multiple) video processors 2134 can be included in the same IC package 2102 (5) and in the same or different IC packages 2102, 2102 (1) containing CPU 2108. The (multiple) displays 2132 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light emitting diode (LED) display, etc.

[0128] Figure 22 illustrates an exemplary wireless communication device 2200 including radio frequency (RF) components formed by one or more ICs 2202, wherein any of the ICs 2202 may include one or more interconnect structures comprising vertically adjacent lower interconnect layers and upper interconnect layers without intermediate via layers, wherein the vertically adjacent lower interconnect layers and upper interconnect layers include corresponding lower metal lines and upper metal lines coupled to each other, including but not limited to the exemplary ICs in Figures 3-5B, 8A-12B, and 15-20B and conforming to the exemplary manufacturing processes in Figures 6-7B-2 and 14A-14E. For example, the wireless communication device 2200 may include any of the devices or settings referenced above. As shown in Figure 22, the wireless communication device 2200 includes a transceiver 2204 and a data processor 2206. The data processor 2206 may include memory for storing data and program code. The transceiver 2204 includes a transmitter 2208 and a receiver 2210 supporting bidirectional communication. Typically, wireless communication device 2200 may include any number of transmitters 2208 and / or receivers 2210 for any number of communication systems and frequency bands. All or part of transceiver 2204 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0129] Transmitter 2208 or receiver 2210 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, for receiver 2210, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 2200 in Figure 22, transmitter 2208 and receiver 2210 are implemented using a direct conversion architecture.

[0130] In the transmission path, data processor 2206 processes the data to be transmitted and provides I and Q analog output signals to transmitter 2208. In the exemplary wireless communication device 2200, data processor 2206 includes digital-to-analog (DAC) converters 2212(1) and 2212(2) to convert the digital signals generated by data processor 2206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0131] Within transmitter 2208, low-pass filters 2214(1) and 2214(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers AMP 2216(1) and 2216(2) amplify the signals from low-pass filters 2214(1) and 2214(2), respectively, and provide I and Q baseband signals. Upconverter 2218 uses the I and Q transmit (TX) local oscillator (LO) signals from mixers 2220(1) and 2220(2) from TX LO signal generator 2222 to upconvert the I and Q baseband signals to provide upconverted signal 2224. Filter 2226 filters the upconverted signal 2224 to remove unwanted signals caused by upconversion and noise in the receive band. The power amplifier (PA) 2228 amplifies the up-converted signal 2224 from the filter 2226 to obtain the desired output power level and provides a transmitted RF signal. The transmitted RF signal is routed via a duplexer or switch 2230 and transmitted via an antenna 2232.

[0132] In the receiving path, antenna 2232 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 2230 and provided to low noise amplifier (LNA) 2234. Duplexer or switch 2230 is designed to operate with a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 2234 and filtered by filter 2236 to obtain the desired RF input signal. Downconversion mixers 2238(1) and 2238(2) mix the output of filter 2236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 2240 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 2242(1) and 2242(2) and further filtered by low-pass filters 2244(1) and 2244(2) to obtain I and Q analog input signals, which are provided to data processor 2206. In this example, data processor 2206 includes analog-to-digital converters (ADCs) 2246(1) and 2246(2) to convert the analog input signals into digital signals for further processing by data processor 2206.

[0133] In the wireless communication device 2200 of Figure 22, the TX LO signal generator 2222 generates I and Q TX LO signals for up-conversion, while the RX LO signal generator 2240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 2248 receives timing information from the data processor 2206 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 2222. The RX PLL circuit 2250 receives timing information from the data processor 2206 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 2240.

[0134] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. For example, the master and slave devices described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0135] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic elements, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0136] The aspects disclosed herein can be implemented as hardware and instructions stored in hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable magnetic disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0137] It should also be noted that the operational steps described in any exemplary aspect of this document are described to provide examples and discussion. The described operations can be performed in many different orders besides the order shown. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0138] The prior description of this disclosure is provided to enable those skilled in the art to make or use the invention. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, the invention is not intended to be limited to the examples and designs described herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0139] An implementation example is described in the following numbered clauses: 1. A capacitor, comprising: Interconnection structure, including: The lower interconnect layer includes: The first lower metal finger structure includes a plurality of first lower metal lines extending parallel to each other; and The second lower metal finger structure includes multiple second lower metal lines extending parallel to each other; The first lower metal finger structure and the second lower metal finger structure are interleaved; and An overlay interconnect layer is disposed vertically adjacent to the lower interconnect layer, the overlay interconnect layer comprising: The first overlay metal finger structure includes a plurality of first overlay metal lines extending parallel to each other; and The second overlay metal finger structure includes a plurality of second overlay metal lines extending parallel to each other; The first upper metal finger structure and the second upper metal finger structure are interleaved, wherein the first upper metal finger structure and the first lower metal finger structure intersect in the vertical direction in the first connecting region; The first upper metal finger structure is coupled to the first lower metal finger structure in the first connection region; The second upper metal finger structure and the second lower metal finger structure intersect in the vertical direction in the second connection region; and The second upper metal finger structure is coupled to the second lower metal finger structure in the second connection region. 2. The capacitors described in Clause 1, excluding: A through-hole layer disposed between the first upper metal finger structure and the first lower metal finger structure; and A through-hole layer is disposed between the second upper metal finger structure and the second lower metal finger structure. 3. The capacitor according to any one of clauses 1 to 2 further includes: A first metal barrier layer is disposed in the first connection region between the first upper metal finger structure and the first lower metal finger structure, wherein the first metal barrier layer electrically couples the first upper metal finger structure to the first lower metal finger structure in the first connection region; and A second metal barrier layer is disposed in the second connection region between the second upper metal finger structure and the second lower metal finger structure, wherein the second metal barrier layer electrically couples the second upper metal finger structure to the second lower metal finger structure in the second connection region. 4. The capacitor according to any one of clauses 1 to 3, wherein: The first upper metal finger structure and the second lower metal finger structure intersect in the vertical direction in the third connecting region; and The second upper metal finger structure intersects the first lower metal finger structure in the vertical direction in the fourth connection region; and The capacitor further includes: A first insulating layer is disposed in the third connection region between the first upper metal finger structure and the second lower metal finger structure; and The second insulating layer is disposed in the fourth connection region between the second upper metal finger structure and the first lower metal finger structure. 5. The capacitor as described in Clause 4, wherein: The first overlying metal finger structure includes a first recess adjacent to the third connecting region; The first insulating layer is disposed in the first recess of the first upper metal finger structure to insulate the first upper metal finger structure from the second lower metal finger structure. The second overlying metal finger structure includes a second recess adjacent to the fourth connecting region; and The second insulating layer is disposed in the second recess of the second upper metal finger structure to insulate the second upper metal finger structure from the first lower metal finger structure. 6. The capacitor as described in Clause 4, wherein: The first overlying metal finger structure includes a first recess located outside the first connecting region; The first insulating layer is disposed in the first recess of the first upper metal finger structure to insulate the first upper metal finger structure from the second lower metal finger structure. The second overlying metal finger structure includes a second recess located outside the second connecting region; and The second insulating layer is disposed in the second recess of the second upper metal finger structure to insulate the second upper metal finger structure from the first lower metal finger structure. 7. The capacitor according to any one of clauses 1 to 6 further includes a back-end interconnect (BEOL) structure, said BEOL interconnect structure comprising: The lower metallization layer includes the lower interconnect layer; and The overlying metallization layer includes the overlying interconnect layer; The upper metallization layer is disposed adjacent to the lower metallization layer in the vertical direction. 8. The capacitor according to any one of clauses 1 to 7, wherein: The plurality of first lower layer metal lines have a first polarity; The plurality of second lower-layer metal lines have a second polarity; The plurality of first overlying metal lines have the first polarity; and The plurality of second overlay metal lines have the second polarity. 9. The capacitor according to any one of clauses 1 to 8, wherein: The plurality of first lower metal lines and the plurality of second lower metal lines each extend parallel to each other in a first horizontal direction; and The plurality of first and second top metal lines extend parallel to each other in a second horizontal direction, which is orthogonal to the first horizontal direction. 10. The capacitor according to any one of clauses 1 to 3 and 7 to 8, wherein: The plurality of first lower metal lines and the plurality of second lower metal lines each extend parallel to each other in a first horizontal direction; and The plurality of first overlay metal lines and the plurality of second overlay metal lines each extend parallel to each other in the first horizontal direction. 11. The capacitor as described in Clause 10, wherein: Each of the plurality of first lower metal wires is positioned vertically directly below a corresponding second upper metal wire among the plurality of second upper metal wires; and Each of the plurality of second lower metal wires is positioned vertically directly below the corresponding first upper metal wire among the plurality of first upper metal wires. 12. The capacitor according to any one of Clauses 1 to 11, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; conversation initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); displays; computer monitors; televisions; tuners; radios; satellite broadcasting; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft. 13. An inductor, comprising: Interconnection structure, including: The lower interconnect layer includes: The lower metal coil structure includes multiple lower metal segments coupled to each other in a coil-shaped pattern; An upper interconnect layer is disposed adjacent to the lower interconnect layer in the vertical direction, and the upper interconnect layer includes: An upper metal coil structure includes a plurality of upper metal segments coupled to each other in a coil-shaped pattern, wherein the upper metal coil structure intersects the lower metal coil structure in the vertical direction in a first connection region; and An insulating layer is disposed in the second connection region between the upper metal coil structure and the lower metal coil structure; The upper metal coil structure is coupled to the lower metal coil structure in the first connection region. 14. The inductor according to Clause 13, wherein the interconnection structure further comprises: A second overlay interconnect layer, disposed adjacent to the overlay interconnect layer in the vertical direction, includes: The second overlying metal coil structure includes a plurality of second overlying metal segments coupled to each other in a coil-shaped pattern. The second overlying metal coil structure intersects the overlying metal coil structure in the vertical direction in the third connection region; and A second insulating layer is disposed in the fourth connection region between the second overlying metal coil structure and the overlying metal coil structure; The second overlying metal coil structure is coupled to the overlying metal coil structure in the third connection region. 15. The inductor according to any one of Clauses 13 to 14, excluding the through-hole layer disposed between the upper metal coil structure and the lower metal coil structure. 16. The inductor according to any one of clauses 13 to 15, further comprising a metal barrier layer disposed in the first connection region between the upper metal coil structure and the lower metal coil structure, the metal barrier layer electrically coupling the upper metal coil structure to the lower metal coil structure. 17. The inductor according to any one of Clauses 13 to 16, wherein: The overlying metal coil structure includes a first recess adjacent to the second connection region; and The insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure. 18. The inductor according to any one of clauses 14 to 16, wherein: The overlying metal coil structure includes a first recess adjacent to the second connection region; The insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure. The second overlying metal coil structure includes a second recess adjacent to the fourth connection region; and The second insulating layer is disposed in the second recess of the second overlying metal coil structure to insulate the second overlying metal coil structure from the overlying metal coil structure. 19. An inductor according to any one of clauses 13 to 16, wherein: The overlying metal coil structure includes a first recess located outside the first connection region; and The insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure. 20. The inductor according to any one of clauses 14 to 16, wherein: The overlying metal coil structure includes a first recess located outside the first connection region; The insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure. The second overlying metal coil structure includes a second recess located outside the third connection region; and The second insulating layer is disposed in the second recess of the second overlying metal coil structure to insulate the second overlying metal coil structure from the overlying metal coil structure. 21. The inductor according to any one of clauses 13 to 20 further includes a back-end interconnect (BEOL) structure, said BEOL interconnect structure comprising: The lower metallization layer includes the lower interconnect layer; and The overlying metallization layer includes the overlying interconnect layer; The upper metallization layer is disposed adjacent to the lower metallization layer in the vertical direction. 22. An inductor according to any one of Clauses 13 to 21, integrated into a device selected from: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular phone; a smartphone; a conversation initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a display; a computer monitor; a television; a tuner; a radio; a satellite broadcasting system; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multi-rotor aircraft.

[0140] 100: Integrated circuits 102: Grain stacking H1: Total height 104: Back-end interconnect structure 114(1), 114(2), 114(3), 114(4): Interconnection layer 116(1), 116(2), 116(3), 116(4): Metal wire 120(1), 120(2), 120(3), 120(4): Through-hole layer 122(1), 122(2), 122(3), 122(4): Through holes H2: Height 106: Front-end structure 108: Active semiconductor layer 110:Substrate 112N: N-type field-effect transistor 112P: P-type field-effect transistor 118: External Interconnection 114O: Overlay interconnect layer 116O(1): First overlay metal wire 116O(2): Second overlay metal wire 200(2): Second Connecting Region LA3, LA4: Longitudinal axes 114U: Lower interconnect layer 116U(1): First lower layer metal wire 116U(2): Second lower layer metal wire 200(1): First Connecting Region LA1, LA2: Longitudinal axes 300: Integrated Circuits 302: Grain stacking H3: Total Height 304: Back-end interconnect structure 314(1), 314(2), 314(3), 314(4): Interconnection layer 316(1), 316(2), 316(3), 316(4): Metal wire 320(1), 320(2), 320(3): Through-hole layer 322(1), 322(2), 322(3): Through holes 324(1): Connecting regions H4: Height 306: Front-end structure 308: Active Semiconductor Layer 310:Substrate 312N: N-type field-effect transistor 312P: P-type field-effect transistor 314O: Overlay interconnect layer 316O(1): First overlay metal wire 316O(2): Second overlay metal wire 400(2): Second Connecting Region 400(4): Fourth Connecting Region 402(2): Second insulating layer 404(2):Second recess LA7, LA8: Longitudinal axes 314U: Lower interconnect layer 316U(1): First lower layer metal wire 316U(2): Second lower layer metal wire 400(1): First Connecting Region 400(3): Third Connecting Region 402(1): First insulating layer 404(1): First concave part 406(1): First metal barrier layer 408: Metallic Materials 410: Dielectric materials LA5, LA6: Longitudinal axes 500: Integrated Circuits 504: Back-end interconnect structure 530: Insulation layer 514O: Overlay interconnect layer 516O(1): First overlay metal wire 516O(2): Second overlay metal wire 526(2): Second Connecting Region 526(4): Fourth Connecting Region 532(2):Second recess 534(2): Second opening LA11, LA12: Longitudinal axes 514U: Lower interconnect layer 516U(1): First lower layer metal wire 516U(2): Second lower layer metal wire 526(1): First Connecting Region 526(3): Third Connecting Region 532(1):First concave part 534(1): First opening 536(1): First surface 538(1): Metallic Materials 540(1): First thin metal barrier layer LA9, LA10: Longitudinal axes 600: Process 602, 604, 606, 608, 610, 612, 614: Squares 700: Process 702, 704: Steps 700-1: Process 706-1, 708-1, 710-1: Square 700-2: Process 706-2, 708-2, 710-2: Steps 800A: Manufacturing Stage 801: First dielectric layer 802, 804(1), 804(2): First surface 800B: Manufacturing Stage 800C-1: Manufacturing Stage 806: Opening 800D-1: Manufacturing Stage 800E-1: Manufacturing Stage 808: Metallic Materials 800C-2: Manufacturing Stage 810: Opening 800D-2: Manufacturing Stage 812: Metal Barrier Layer 814: Metallic Materials 900: Integrated Circuits 904: Back-end interconnect structure 914O: Overlay interconnect layer 901(2): Second Connecting Region 901(4): Fourth Connecting Region 902(2): Second insulating layer 916O(1): First overlay metal wire 916O(2): Second overlay metal wire 914U: Lower interconnect layer 901(1): First Connecting Region 901(3): Third Connecting Region 902(1): First insulating layer 916U(1): First lower layer metal wire 916U(2): Second lower layer metal wire 1000: Integrated Circuits 1004: Back-end interconnect structure 1014O: Overlay interconnect layer 1001(2): Second Connecting Region 1001(4): Fourth Connecting Region 1002(2): Second insulating layer 1016O(1): First overlay metal wire 1016O(2): Second overlay metal wire 1014U: Lower interconnect layer 1001(1): First Connecting Region 1001(3): Third Connecting Region 1002(1): First insulating layer 1016U(1): First lower layer metal wire 1016U(2): Second lower layer metal wire 1100: Integrated Circuits 1104: Back-end interconnect structure 1101(1): First Connecting Region 1101(2): Second Connecting Region 1101(3): Third Connecting Region 1101(4): Fourth Connecting Region 1102(1): First insulating layer 1102(2): Second insulating layer 1116O(1): First overlay metal wire 1116O(2): Second overlay metal wire 1116U(1): First lower layer metal wire 1116U(2): Second lower layer metal wire 1200: Integrated Circuits 1204: Front-end structure 1202: Active semiconductor layer 1216: Field-Effect Transistor 1210: Backside interconnect structure 1212(1)~1212(N): Interconnection layer 1218:Substrate 1220: Metal Contact 1222: Metal wire on the back 1222O(1): First overlay metal wire 1222U(1): First lower layer metal wire 1222U(2): Second lower layer metal wire 1224O: Overlay interconnect layer 1224U: Lower interconnect layer 1230(1): First Connecting Region 1230(3): Third Connecting Region 1232(1): First insulating layer 1234(1):First concave part 1236(1): Thin metal barrier layer 1238: Dielectric Materials 1208: Front 1214: Back 1206: Back-end interconnect structure LA13, LA14, LA15: Longitudinal axes 1300: Process 1302, 1304, 1306, 1308, 1310: Squares 1400A: Manufacturing Stage 1402: Top surface 1400B: Manufacturing Stage 1403: Second Surface 1404(1), 1404(2): First surface 1400C: Manufacturing Stage 1406: Third Surface 1400D: Manufacturing Stage 1408: Dielectric layer 1400E: Manufacturing Stage 1500: Integrated Circuits 1510: Backside interconnect structure 1524O: Overlay interconnect layer 1522O(1): First overlay metal wire 1530(1): Insulation layer 1532(1):First concave part 1534(1): First opening 1536(1): First surface 1540(1): First thin metal barrier layer 1524U: Lower interconnect layer 1518:Substrate 1522U(1): First lower layer metal wire 1522U(2): Second lower layer metal wire 1528(1): First Connecting Region 1528(3): Third Connecting Region 1542: Dielectric Materials LA16, LA17, LA18: Longitudinal axes 1600: Integrated Circuits 1602: Capacitor 1604: Interconnection Structure 1606(2): Second Interconnect Layer 1606O: Overlay interconnect layer 1608O(1): First overlying metal finger structure 1608O(2): Second overlying metal finger structure 1610O(1): First overlay metal wire 1610O(2): Second overlay metal wire 1610O(3): Third overlay metal wire 1610O(4): Fourth overlay metal wire 1612O(1): First overlay metal wire 1612O(2): Second overlay metal wire 1614(1): First Connecting Region 1616: Insulation layer 1618: concave part 1620: Opening 1624: Metallic Materials 1606(1): First interconnect layer 1606U: Lower Interconnect Layer 1608U(1): First lower metal finger structure 1608U(2): Second lower metal finger structure 1610U(1): First lower layer metal wire 1610U(2): Second lower layer metal wire 1610U(3): Third lower layer metal wire 1610U(4): Fourth lower layer metal wire 1612U(1): First lower layer metal wire 1612U(2): Second lower layer metal wire 1614(2): Second Connecting Region 1700: Integrated Circuits 1702: Capacitor 1704: Interconnection Structure 1706(2): Second Interconnect Layer 1706O: Overlay interconnect layer 1708O(1): First overlying metal finger structure 1708O(2): Second overlying metal finger structure 1710O(1): First overlay metal wire 1710O(2): Second overlay metal wire 1710O(3): Third overlay metal wire 1710O(4): Fourth overlay metal wire 1714(1): First Connecting Region 1714(2): Second Connecting Region 1716: Insulation layer 1718: concave part 1720: Opening 1706(1): First interconnect layer 1706U: Lower Interconnect Layer 1708U(1): First lower metal finger structure 1708U(2): Second lower metal finger structure 1710U(1): First lower layer metal wire 1710U(2): Second lower layer metal wire 1710U(3): Third lower layer metal wire 1710U(4): Fourth lower layer metal wire 1800: Integrated Circuits 1802: Capacitor 1804: Interconnection Structure 1806(2): Second Interconnect Layer 1806O: Overlay interconnect layer 1808O(1): First overlying metallic finger structure 1808O(2): Second overlying metal finger structure 1810O(1): First overlay metal wire 1810O(2): Second overlay metal wire 1810O(3): Third overlay metal wire 1810O(4): Fourth overlay metal wire 1814(1): First Connecting Region 1814(2): Second Connecting Region 1816: Insulation layer 1806(1): First interconnect layer 1806U: Lower Interconnect Layer 1808U(1): First lower metal finger structure 1808U(2): Second lower metal finger structure 1810U(1): First lower layer metal wire 1810U(2): Second lower layer metal wire 1810U(3): Third lower layer metal wire 1810U(4): Fourth lower layer metal wire 1900: Integrated Circuits 1902: Inductor 1904: Interconnection Structure 1906(2): Second Interconnect Layer 1906O: Overlay interconnect layer 1908O: Overlapping metal coil structure 1910O(1), 1910O(2), 1910O(3), 1910O(4), 1910O(5), 1910O(6), 1910O(7), 1910O(8): Overlapping metal segments 1912(1): First end 1912(3): Third end 1906(1): First interconnect layer 1906U: Lower Interconnect Layer 1908U: Lower layer metal coil structure 1910U(1), 1910U(2), 1910U(3), 1910U(4), 1910U(5), 1910U(6), 1910U(7), 1910U(8): Lower metal segments 1912(2): Second end 1912(4): Fourth end 1914: Insulation layer 1916(1): First Connecting Region 1916(2): Second Connecting Region 1924: Metallic Materials 2000: Integrated Circuits 2004: Interconnection Structure 2002(1): First Inductor 2006(1): First Interconnect Layer 2008(1)-2008(4): Metal coil structure 2008U(1): First lower layer metal coil structure 2010U(1)-2010U(8): Lower metal segments 2006(2): Second Interconnect Layer 2008U(2): Second Lower Layer Metal Coil Structure 2012U(1)-2012U(8): Lower metal segments 2024(1), 2024(2), 2024(3), 2024(4): Second end 2026(1): Connecting Regions 2028(1): Insulation layer 2028(2): Insulation layer 2002(2): Second Inductor 2006(3): Third Interconnect Layer 2008U(3): Third Lower Layer Metal Coil Structure 2014U(1)-2014U(8): Lower metal segments 2006(4): Fourth Interconnect Layer 2008O(4): Overlapping metal coil structure 2016O(1)-2016O(8): Overlapping metal segments 2022(1), 2022(2), 2022(3), 2022(4): First end 2026(3): Connecting Regions 2028(3): Insulation layer 2100: Processor-based system 2102(1): Integrated circuit package 2108: Central Processing Unit 2110: Processor 2112: Cache memory 2102(2): Integrated circuit package 2120: Memory System 2116: Memory controller 2118: Memory Array 2102(3): Integrated circuit package 2122: Input device 2102(4): Integrated circuit package 2124: Output device 2102(5): Integrated circuit package 2128: Display Controller 2134: Video Processor 2104: Integrated Circuits 2106: Single-chip system 2114: Busbar 2126: Interface Devices 2130: Internet 2132: Monitor 2200: Wireless communication equipment 2202: Integrated Circuits 2204: Transceiver 2208: Transmitter 2214(1), 2214(2): Low-pass filter 2216(1), 2216(2): Amplifier 2218: Upgraded frequency converter 2220(1), 2220(2): Mixer 2224: Up-converter signal 2222: TX LO signal generator 2248: TX Phase-Locked Loop Circuit 2226: Filter 2228: Power Amplifier 2230: Duplexer or switch 2232: Antenna 2210: Receiver 2234: Low-noise amplifier 2236: Filter 2238(1), 2238(2): Downconverter mixer 2240:RX LO Signal Generator 2250:RX Phase-Locked Loop Circuit 2242(1), 2242(2): Amplifier 2244(1), 2244(2): Low-pass filters 2206: Data Processor 2212(1), 2212(2): Digital-to-Analog Converter 2246(1), 2246(2): Analog-to-digital converter

Claims

1. An integrated circuit for a capacitor, comprising: An interconnect structure includes: a lower interconnect layer, including: a first lower metal finger structure including a plurality of first lower metal lines extending parallel to each other; and a second lower metal finger structure including a plurality of second lower metal lines extending parallel to each other; the first lower metal finger structure and the second lower metal finger structure intersect each other; and an upper interconnect layer disposed adjacent to the lower interconnect layer in a vertical direction, the upper interconnect layer including: a first upper metal finger structure including a plurality of first upper metal lines extending parallel to each other; and a second upper metal finger structure including a plurality of second upper metal lines extending parallel to each other; the first upper metal finger structure and the second upper metal finger structure intersect each other, wherein the first upper metal finger structure and the first lower metal finger structure intersect in a first connection region in the vertical direction; the first upper metal finger structure is directly coupled to the first lower metal finger structure in the first connection region; the second upper metal finger structure and the second lower metal finger structure intersect in a second connection region in the vertical direction; and the second upper metal finger structure is directly coupled to the second lower metal finger structure in the second connection region.

2. The integrated circuit as described in claim 1, excluding: A through-hole layer is disposed between the first upper metal finger structure and the first lower metal finger structure; And a through-hole layer disposed between the second upper metal finger structure and the second lower metal finger structure.

3. The integrated circuit as described in claim 1 further includes: A first metal barrier layer is disposed in the first connection region between the first upper metal finger structure and the first lower metal finger structure, wherein the first metal barrier layer electrically couples the first upper metal finger structure to the first lower metal finger structure in the first connection region; and a second metal barrier layer is disposed in the second connection region between the second upper metal finger structure and the second lower metal finger structure, wherein the second metal barrier layer electrically couples the second upper metal finger structure to the second lower metal finger structure in the second connection region.

4. The integrated circuit as claimed in claim 1, wherein: The first upper metal finger structure and the second lower metal finger structure intersect in the vertical direction in the third connecting region; And the second upper metal finger structure intersects the first lower metal finger structure in the vertical direction in the fourth connection region; The capacitor further includes: a first insulating layer disposed in the third connection region between the first upper metal finger structure and the second lower metal finger structure; And a second insulating layer, disposed in the fourth connection region between the second upper metal finger structure and the first lower metal finger structure.

5. The integrated circuit as described in claim 4, wherein: The first upper metal finger structure includes a first recess adjacent to the third connection region; the first insulating layer is disposed in the first recess of the first upper metal finger structure to insulate the first upper metal finger structure from the second lower metal finger structure; the second upper metal finger structure includes a second recess adjacent to the fourth connection region; and the second insulating layer is disposed in the second recess of the second upper metal finger structure to insulate the second upper metal finger structure from the first lower metal finger structure.

6. The integrated circuit as described in claim 4, wherein: The first overlying metal finger structure includes a first recess located outside the first connection region; the first insulating layer is disposed in the first recess of the first overlying metal finger structure to insulate the first overlying metal finger structure from the second lower metal finger structure; the second overlying metal finger structure includes a second recess located outside the second connection region; and the second insulating layer is disposed in the second recess of the second overlying metal finger structure to insulate the second overlying metal finger structure from the first lower metal finger structure.

7. The integrated circuit as claimed in claim 1 further includes a back-end-of-line (BEOL) interconnect structure, the BEOL interconnect structure comprising: The lower metallization layer includes the lower interconnect layer; And an overlay metallization layer, including the overlay interconnect layer; The upper metallization layer is disposed adjacent to the lower metallization layer in the vertical direction.

8. The integrated circuit as claimed in claim 1, wherein: The plurality of first lower metal lines have a first polarity; the plurality of second lower metal lines have a second polarity; the plurality of first upper metal lines have the first polarity; and the plurality of second upper metal lines have the second polarity.

9. The integrated circuit as claimed in claim 1, wherein: The plurality of first lower metal lines and the plurality of second lower metal lines each extend parallel to each other in a first horizontal direction; The plurality of first and second top metal lines extend parallel to each other in a second horizontal direction, which is orthogonal to the first horizontal direction.

10. The integrated circuit as claimed in claim 1, wherein: The plurality of first lower metal lines and the plurality of second lower metal lines each extend parallel to each other in a first horizontal direction; The plurality of first overlay metal lines and the plurality of second overlay metal lines each extend parallel to each other in the first horizontal direction.

11. The integrated circuit as claimed in claim 10, wherein: Each of the plurality of first lower metal wires is disposed directly below a corresponding second upper metal wire in the plurality of second upper metal wires in the vertical direction; and each of the plurality of second lower metal wires is disposed directly below a corresponding first upper metal wire in the plurality of first upper metal wires in the vertical direction.

12. The integrated circuitry as described in claim 1, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); displays; computer monitors; televisions; tuners; radios; satellite broadcasting; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

13. The integrated circuit as claimed in claim 1, wherein a first surface of the overlay interconnect layer adjacent to the lower interconnect layer is configured to directly contact the first surface of the lower interconnect layer adjacent to the overlay interconnect layer.

14. The integrated circuit as claimed in claim 1, excluding the via layer disposed between the upper interconnect layer and the lower interconnect layer.

15. The integrated circuit as claimed in claim 1, wherein the first overlying metal finger structure further extends horizontally from the first connection region in a first horizontal direction of the first lower metal finger structure.

16. An integrated circuit for an inductor, comprising: An interconnect structure includes: a lower interconnect layer, including: a lower metal coil structure comprising a plurality of lower metal segments coupled to each other in a coil-shaped pattern; an upper interconnect layer disposed adjacent to the lower interconnect layer in a vertical direction, the upper interconnect layer comprising: an upper metal coil structure comprising a plurality of upper metal segments coupled to each other in a coil-shaped pattern, wherein the upper metal coil structure intersects the lower metal coil structure in the vertical direction in a first connection region; and an insulating layer disposed between the upper metal coil structure and the lower metal coil structure in a second connection region; the upper metal coil structure is coupled to the lower metal coil structure in the first connection region.

17. The integrated circuit as claimed in claim 16, wherein the interconnection structure further comprises: A second overlay interconnect layer, disposed adjacent to the overlay interconnect layer in the vertical direction, includes: a second overlay metal coil structure comprising a plurality of second overlay metal segments coupled to each other in a coil-shaped pattern, wherein the second overlay metal coil structure intersects the overlay metal coil structure in the vertical direction in a third connection region; and a second insulating layer disposed between the second overlay metal coil structure and the overlay metal coil structure in a fourth connection region; the second overlay metal coil structure is coupled to the overlay metal coil structure in the third connection region.

18. The integrated circuit as claimed in claim 16, excluding the via layer disposed between the upper metal coil structure and the lower metal coil structure.

19. The integrated circuit as claimed in claim 16, further comprising: A metal barrier layer is disposed in the first connection region between the upper metal coil structure and the lower metal coil structure, the metal barrier layer electrically coupling the upper metal coil structure to the lower metal coil structure.

20. The integrated circuit as claimed in claim 16, wherein: The upper metal coil structure includes a first recess adjacent to the second connection region; and the insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure.

21. The integrated circuit as claimed in claim 17, wherein: The upper metal coil structure includes a first recess adjacent to the second connection region; the insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure; the second upper metal coil structure includes a second recess adjacent to the fourth connection region; and the second insulating layer is disposed in the second recess of the second upper metal coil structure to insulate the second upper metal coil structure from the upper metal coil structure.

22. The integrated circuit as claimed in claim 16, wherein: The upper metal coil structure includes a first recess located outside the first connection area; and the insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure.

23. The integrated circuit as claimed in claim 17, wherein: The upper metal coil structure includes a first recess located outside the first connection region; the insulating layer is disposed in the first recess of the upper metal coil structure to insulate the upper metal coil structure from the lower metal coil structure; the second upper metal coil structure includes a second recess located outside the third connection region; and the second insulating layer is disposed in the second recess of the second upper metal coil structure to insulate the second upper metal coil structure from the upper metal coil structure.

24. The integrated circuit as claimed in claim 16, further comprising a back-end interconnect (BEOL) structure, the BEOL interconnect structure comprising: The lower metallization layer includes the lower interconnect layer; And an overlay metallization layer, including the overlay interconnect layer; The upper metallization layer is disposed adjacent to the lower metallization layer in the vertical direction.

25. The integrated circuitry as described in claim 16, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; Global Positioning System (GPS) devices; mobile phones; cellular phones; smartphones; SIP phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); displays; computer monitors; televisions; tuners; radios; satellite broadcasting; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

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